Amplifier circuit, differential amplifier circuit, reception circuit, and semiconductor integrated circuit

Abstract

An amplification circuit according to an embodiment of the present invention includes a first circuit, a second circuit, and a third circuit. The first circuit includes a first transistor connected between an input node through which an input current flows and a reference potential node, and having a gate electrode connected to the input node. The second circuit includes a low-pass filter circuit, and includes a second transistor connected in parallel with the first transistor between the input node and the reference potential node, and having a gate electrode connected to the gate electrode of the first transistor via the low-pass filter circuit. The third circuit includes a third transistor connected between an output node through which an output current flows and the reference potential node, and having a gate electrode connected to the gate electrode of the first transistor.

Description

Technical Field

[0001] One embodiment disclosed in this specification relates, for example, to an amplifier circuit, a differential amplifier circuit, a receiver circuit, and a semiconductor integrated circuit for a CTLE (Continuous Time Linear Equalizer). Background Technology

[0002] CTLE is an input amplifier circuit used in high-speed interfaces for networks, data centers, etc., for SerDes (serializer and deserializer) receiver circuits, serving as a loss compensation circuit in the transmission path. Previous CTLEs used source-degraded equalizers.

[0003] Patent Document 1: Japanese Patent Application Publication No. 9-74340

[0004] Patent Document 2: U.S. Patent Application Publication No. 2008 / 24228

[0005] Patent Document 3: US Patent No. 5,363,065

[0006] However, conventional CTLEs using source-degraded equalizers employ inductors (coils) to achieve gain amplification. This results in a larger circuit size (area). Furthermore, the gain becomes nonlinear due to variations in resistance, transconductance, and other biases within the circuit.

[0007] In recent years, the miniaturization of CMOS technology has necessitated further reductions in power and area for CTLEs. Additionally, the multi-leveling of signal amplitudes has created a need for higher linearity. Summary of the Invention

[0008] One of the problems that the embodiments disclosed in this specification and the like are intended to solve is to provide amplifier circuits, differential amplifier circuits, receiver circuits and semiconductor integrated circuits that can improve gain amplification while maintaining gain linearity and miniaturize the area.

[0009] The amplifier circuit according to the embodiment includes: a first circuit including a first transistor connected between a reference potential node and an input node through which the input current flows, and the gate electrode of the first transistor being connected to the input node; a second circuit including a low-pass filter circuit and including a second transistor connected in parallel with the first transistor between the input node and the reference potential node, and the gate electrode of the second transistor being connected to the gate of the first transistor via the low-pass filter circuit; and a third circuit including a third transistor connected between an output node through which the output current flows and the reference potential node, and the gate electrode of the third transistor being connected to the gate of the first transistor.

[0010] According to one embodiment disclosed in this specification, it is possible to realize an amplifier circuit, a differential amplifier circuit, a receiver circuit, and a semiconductor integrated circuit that can improve gain amplification while maintaining gain linearity and achieve miniaturization. Attached Figure Description

[0011] Figure 1 This is a diagram showing the structure of the amplifier circuit according to the first embodiment.

[0012] Figure 2 It is a graph showing the relationship between the DC gain, boost gain, peak gain and frequency of the amplifier circuit involved in the first embodiment.

[0013] Figure 3 This is a diagram showing the structure of the amplifier circuit according to the second embodiment.

[0014] Figure 4 This is a graph showing the relationship between the DC gain, boost gain, peak gain, and frequency of the amplifier circuit involved in the second embodiment.

[0015] Figure 5 This is a diagram showing the structure of the amplifier circuit involved in the third embodiment.

[0016] Figure 6 This is a graph showing the relationship between the DC gain, boost gain, peak gain, and frequency of the amplifier circuit involved in the third embodiment.

[0017] Figure 7 This is a diagram showing the structure of the amplifier circuit according to the fourth embodiment.

[0018] Figure 8 This is a diagram showing the structure of the amplifier circuit according to the fifth embodiment.

[0019] Figure 9 (a), (b), and (c) are checklists used to determine size parameters based on DC gain and boost gain, respectively.

[0020] Figure 10 This is a diagram showing the structure of the amplifier circuit according to the sixth embodiment.

[0021] Figure 11 This is a diagram showing the structure of the receiving circuit according to the seventh embodiment.

[0022] Figure 12 This is a diagram showing the structure of the semiconductor integrated circuit according to the eighth embodiment. Detailed Implementation

[0023] Hereinafter, with reference to the accompanying drawings, the amplifier circuit, differential amplifier circuit, receiver circuit, and semiconductor integrated circuit involved in the embodiments will be described in detail. However, the present invention is not limited to these embodiments. Furthermore, in the following description, parts common to all figures will be labeled with the same reference numerals, and detailed descriptions will be omitted.

[0024] (First Implementation)

[0025] Figure 1 This diagram illustrates the structure of the amplifier circuit D1 according to the first embodiment. Furthermore, the amplifier circuit D1 is a single-ended amplifier.

[0026] like Figure 1 As shown, amplifier circuit D1 includes a first circuit 11, a second circuit 12, a third circuit 13, a reference potential node 31, an input terminal 50, an input node 51, an output terminal 60, and an output node 61. Furthermore, in Figure 1 In this context, a and b are parameters representing the magnitude of the current flowing through the transistors in the first circuit 11 and the second circuit 12, respectively, and are parameters representing the size of the transistor (hereinafter referred to as "size parameters"). Size parameters a and b, for example, correspond to the number of fins in a FinFET (Fin Field Effect Transistor) and the gate width of a planar transistor.

[0027] Input node 51 contains input current I I The wiring flows through it. Output node 61 contains the output current I. O The wiring flows through. Reference potential node 31 contains wiring supplied with a reference potential Vbasis (e.g., ground potential). Furthermore, the potential Vin of input node 51 and the reference potential Vbasis are in a Vin > Vbasis relationship.

[0028] The first circuit 11 has a first transistor 111. The first transistor 111 is, for example, an n-channel transistor, connected to the input current I. IThe current flows between input node 51 and reference potential node 31. The gate electrode of the first transistor 111 is connected to input node 51. Furthermore, the drain and source electrodes of the first transistor 111 are connected to input node 51 and reference potential node 31, respectively. The dimensional parameter of the first transistor 111 is 'a'. Moreover, the first transistor 111 is an example of a first transistor.

[0029] The second circuit 12 includes a second transistor 121 and a low-pass filter circuit 127. The second transistor 121 is, for example, an n-channel transistor, which, when the input current I... I The input node 51 and the reference potential node 31 are connected in parallel with the first transistor 111. The gate electrode of the second transistor 121 is connected to the gate electrode of the first transistor 111 via a low-pass filter circuit 127. Furthermore, the drain and source electrodes of the second transistor 121 are connected to the input node 51 and the reference potential node 31, respectively. The dimensional parameter of the second transistor 121 is b. Furthermore, the second transistor 121 is an example of a second transistor.

[0030] The low-pass filter circuit 127 is a low-pass filter composed of capacitor 1271 and resistor 1272. The low-pass filter circuit 127 filters the signal to the gate electrode of the second transistor 121 in the high-frequency band.

[0031] Furthermore, the low-pass filter circuit 127 allows the passed frequency band, i.e., the cutoff frequency ω of the low-pass filter circuit 127, to pass through. z The capacitance C of capacitor 1271 and the resistance R of resistor 1272 can be adjusted (ω). z =1 / RC). Additionally, in Figure 1 The diagram illustrates a low-pass filter circuit 127 with one capacitor 1271 and one resistor 1272. However, the number of capacitors 1271 and resistors 1272 can be arbitrarily selected according to the purpose.

[0032] The third circuit 13 has a third transistor 131. The third transistor 131 is, for example, an n-channel transistor, connected to the output current I. O The current flows between the output node 61 and the reference potential node 31. The gate electrode of the third transistor 131 is connected to the gate electrode of the first transistor 111. Furthermore, the dimensional parameter of the third transistor 131 is a+b. That is, the dimensional parameter a+b of the third transistor 131 is equal to the sum of the dimensional parameter a of the first transistor 111 and the dimensional parameter b of the second transistor 121. Moreover, the third transistor 131 is an example of a third transistor.

[0033] The first circuit 11, the second circuit 12, and the third circuit 13 constitute a current mirror circuit. When the input current I... IWhen the current flows through input node 51, a current I flows through the third circuit 13 of the mirror target at a ratio corresponding to the size parameter a+b of the third transistor 131. a+b .

[0034] Next, refer to Figure 1 , Figure 2 The operation of amplifier circuit D1 will be explained. Figure 2 This is a graph showing the relationship between the DC gain, boost gain, peak gain, and frequency of the amplifier circuit D1 according to the first embodiment. Here, the DC gain corresponds to the gain that does not reflect the filtering operation of the low-pass filter circuit 127, and corresponds to the input current I. I The gain when the frequency is lower than the cutoff frequency of the low-pass filter circuit 127. The peak gain is equivalent to the gain reflecting the filtering operation of the low-pass filter circuit 127, and is equivalent to the input current I. I The gain when the frequency is higher than the cutoff frequency of the low-pass filter circuit 127. The boost gain corresponds to the difference between the peak gain and the DC gain, and is defined by boost gain = peak gain - DC gain.

[0035] In amplifier circuit D1, the input current I I When the frequency is higher than the cutoff frequency of the low-pass filter circuit 127, the gain (peak gain) is greater than the input current I. I The gain (DC gain) when the frequency is lower than the cutoff frequency of the low-pass filter circuit 127.

[0036] More specifically, firstly, assume that the input current I is the input signal. I The frequency ω is ω≦ω z =1 / RC (i.e., equal to the cutoff frequency ω of the low-pass filter circuit 127) z (or a lower frequency case compared to this). In this case, the input signal passes through the low-pass filter circuit 127. Therefore, when the input current I... I When input is applied to input node 51, a current I flows through the first circuit 11 at a ratio corresponding to the size parameter a of the first transistor 111. a A current I flows through the second circuit 12 at a ratio corresponding to the size parameter b of the second transistor 121. b .

[0037] In the third transistor 131, the first transistor 111, and the second transistor 121, the gate-source voltages are equal. Therefore, based on the current mirror operation, the same overdrive voltage V... od Current conversion is performed, and the drain current I flows through the third transistor 131. a+b As a mirror current. Therefore, as Figure 2 As shown, the DC gain when the input signal is low frequency is A1 = I.a+b / (I a +I b )=(a+b) / (a+b)=1.

[0038] Furthermore, assume that the input current I is the input signal. I The frequency ω is ω > ω z =1 / RC (i.e., the cutoff frequency ω of the low-pass filter circuit 127) z (Compared to the high-frequency case). In this case, when the input current I... I When the input is applied to input node 51, based on the current mirror operation, a drain current I flows through the third transistor 131. a+b As a mirror current, a current I flows through the first circuit 11 at a ratio corresponding to the size parameter a of the first transistor 111. a On the other hand, the gate electrode of the second transistor 121 is connected to the gate electrode of the first transistor 111 via a low-pass filter circuit 127. Therefore, since the input signal to the gate electrode of the second transistor 121 is filtered by the low-pass filter circuit 127, no current I flows through the second transistor 121. b Therefore, as Figure 2 As shown, when the frequency of the input signal ω > ω z When ω = 1 / RC, the frequency ω of the input signal satisfies ω z For a certain high-frequency range > 1 / RC, the increase in DC gain corresponds to the increase in gain A2. The result is that A3 = I a+b / I a = (a+b) / a.

[0039] Furthermore, in amplifier circuit D1, the input current I I The gain (peak gain) and input current I when the frequency is higher than the cutoff frequency of the low-pass filter circuit 127. I The difference in gain (DC gain) when the frequency is lower than the cutoff frequency of the low-pass filter circuit 127 can be determined based on the size parameter b of the second transistor 121.

[0040] Additionally, the boundary point ω between DC gain A1 and boost gain A2 can be adjusted by changing the resistance value R and capacitor C of the low-pass filter circuit 127. z =1 / RC is set to the desired position. Additionally, line B represents the frequency response of the reduced gain portion, and A = g m / sC TOT Here, gm is the transconductance, s is the variable of the Laplace transform, and C... TOT This represents the total capacitance of the gate terminal.

[0041] As described above, the amplifier circuit D1 according to this embodiment includes a first circuit 11, a second circuit 12, and a third circuit 13. The first circuit 11 includes a first transistor 111 connected between an input node 51 through which the input current flows and a reference potential node 31, with its gate electrode connected to the input node 51. The second circuit 12 includes a low-pass filter circuit 127. The second circuit 12 includes a second transistor 121 connected in parallel with the first transistor 111 between the input node 51 and the reference potential node 31, with its gate electrode connected to the gate electrode of the first transistor 111 via the low-pass filter circuit 127. The third circuit 13 includes a third transistor 131 connected between an output node 61 through which the output current flows and the reference potential node 31, with its gate electrode connected to the first transistor 111.

[0042] The input current I, which serves as the input signal I When the frequency is high, the input signal to the gate electrode of the second transistor 121 is filtered by the low-pass filter circuit 127. Therefore, in the high-frequency band, the current I can be suppressed. b The current flows through the second transistor 121, which can increase the amplification from DC gain to peak gain.

[0043] Furthermore, amplifier circuit D1 does not require an inductor (coil). Therefore, compared to conventional amplifier circuits that use inductors (coils), the circuit area can be reduced, and power consumption can be decreased.

[0044] Furthermore, amplifier circuit D1 is based on a current mirror circuit manufactured through the same process. Generally, the input and output deviation factors in integrated circuits (e.g., transistor threshold voltage Vth, gain coefficient β, etc.) change identically within the same process. Therefore, even if deviation changes occur, these deviation factors cancel each other out through identical changes, ultimately enabling the realization of an amplifier circuit with minimal gain error.

[0045] Additionally, for example, when using a resistor (resistance value R) S ), capacitor (capacitance C) S Parasitic resistance of the inductor (resistance value R) P and load resistance (resistance value R) L In the case of conventional source-degradable equalizers where DC gain and boost gain are variable, DC gain A V Able to use transconductance g m R S R P R L Represented as A V =(R L +R P ) / (1 / g m +R SThat is, because g m Because it is nonlinear, the DC gain A of previous source-degraded equalizers... V It is not linear.

[0046] In contrast, as shown below, the amplification A of amplifier circuit D1 based on the current mirror circuit is... I It can achieve linearity.

[0047] That is, in the current I of the input signal in With overdrive voltage V od Between them, there exists a relationship as in equation (1).

[0048] I in =(2I in / β in ) 1 / 2 =V od (1)

[0049] Here, β in It is the gain coefficient of the transistor in the mirror source. The gain coefficient β of the transistor is defined by the following equation (2).

[0050] β=μC OX {W(or nfin) / L}~{W(or nfin) / L} (2)

[0051] It should be noted that μ represents the carrier mobility, and C OX The capacitance of the gate oxide film is represented by W, the gate width of the planar transistor is represented by L, the gate length is represented by nfin, and the number of fins of the FinFET is represented by nfin.

[0052] In the current I of the output signal out With overdrive voltage V od There exists a relationship as shown in equation (3).

[0053] I out =(β) out / 2)V od 2 (3)

[0054] Here, β out It is the gain coefficient of the transistor of the mirror target.

[0055] According to equations (3) and (1), equation (4) holds.

[0056] I out =(β) out / 2)·{(2I in / β in ) 1 / 2} 2

[0057] =(β) out / β in )I in (4)

[0058] Therefore, the amplification A of amplifier circuit D1 i It is represented by the following equation (5), becoming a linear shape.

[0059] A i =(β) out / β in (5)

[0060] (Second Implementation)

[0061] Figure 3 This is a diagram showing the structure of the amplifier circuit D2 according to the second embodiment. (As shown...) Figure 3 As shown, amplifier circuit D2, besides Figure 1 In addition to the structure of the amplifier circuit D1 shown, it also has an output current I at the input node 51 that corresponds to the ratio of the size parameter c. c A constant current source 40 is provided. The constant current source 40 is connected in parallel with the first transistor 111 and the second transistor 121 between the input node 51 and the reference potential node 31. In addition, in the amplifier circuit D2, corresponding to the addition of the constant current source 40, the size parameters of the third transistor 131 on the output node 61 side are a+b+c.

[0062] Figure 4 This is a graph showing the relationship between the DC gain, boost gain, peak gain, and frequency of the amplifier circuit D2 according to the second embodiment. (Refer to...) Figure 3 , Figure 4 The operation of amplifier circuit D2 will be explained.

[0063] The third circuit 13, the first circuit 11, the second circuit 12, and the constant current source 40 function as a current mirror circuit. When the input current I... I When flowing through input node 51, a current I flows through the third circuit 13 of the mirror target in a ratio corresponding to the size parameters a+b+c of the third transistor 131. a+b+c .

[0064] First, assume that the input current I is the input signal. I The frequency ω is ω≦ω z =1 / RC (i.e., equal to the cutoff frequency ω of the low-pass filter circuit 127) z (or a lower frequency case compared to it). In this case, since the input signal passes through the low-pass filter circuit 127, when the input current I... I When input is applied to input node 51, a current I flows through the first transistor 111 at a ratio corresponding to the size parameter a.a A current I flows through the second transistor 121 at a ratio corresponding to the size parameter b. b Additionally, based on the current mirror operation, a drain current I flows through the third transistor 131 of the mirrored target. a+b+c Therefore, as Figure 4 As shown, the frequency of the input signal ω≦ω z The DC gain when 1 / RC is given is A4 = I. a+b+c / (I a +I b ) = (a+b+c) / (a+b).

[0065] Furthermore, assume that the input current I is the input signal. I The frequency ω is ω > ω z =1 / RC (i.e., the cutoff frequency ω of the low-pass filter circuit 127) z (Compared to the high-frequency case). In this case, when the input current I... I When input is applied to input node 51, based on the current mirror operation, a drain current I flows through the third transistor 131 of the mirror target. a+b+c At this time, a current I flows through the first circuit 11 at a ratio corresponding to the size parameter a of the first transistor 111. a On the other hand, since the input signal to the gate electrode of the second transistor 121 is filtered by the low-pass filter circuit 127, no current I flows through the second transistor 121. b Therefore, as Figure 4 As shown, when the frequency of the input signal ω > ω z When ω = 1 / RC, the frequency ω of the input signal satisfies ω z For a certain high-frequency range >1 / RC, the increase in DC gain corresponds to the boost gain A5. The result is that the peak gain is A6 = I. a+b+c / I a = (a+b+c) / a.

[0066] That is, according to the amplifier circuit D2 of the second embodiment, not only can the boost gain be amplified, but the DC gain can also be amplified. Furthermore, by adjusting the current I output from the constant current source 40... c It can variably amplify both the boost gain and the DC gain. Furthermore, compared to the amplifier circuit D1 according to the first embodiment, it can further amplify the boost gain.

[0067] (Third Implementation)

[0068] Figure 5 This is a diagram showing the structure of the amplifier circuit D3 according to the third embodiment. For example... Figure 5As shown, amplifier circuit D3 receives input current I from input terminals 50 and 52. IP I IN And output current I from output terminals 60 and 62 OP I ON The output differential amplifier.

[0069] The amplifier circuit D3 has a first circuit 11, a second circuit 12, a third circuit 13, a fourth circuit 14, a fifth circuit 15, a sixth circuit 16, a seventh circuit 17, an eighth circuit 18, an input node 51, a reference potential node 31, and an output node 61.

[0070] Regarding the first circuit 11 and the second circuit 12, as described in the first embodiment. Furthermore, the size parameter of the third transistor 131 in the third circuit 13 is equal to the sum of the size parameter a of the first transistor 111, the size parameter b of the second transistor 121, and the size parameter c of the seventh transistor 171 in the seventh circuit 17. That is, the size parameter of the third transistor 131 is a + b + c.

[0071] The fourth circuit 14 has a fourth transistor 141. The fourth transistor 141 is, for example, an n-channel transistor, connected to the input current I. IN The current flows between input node 32 and reference potential node 31. The gate electrode of the fourth transistor 141 is connected to input node 32. Additionally, the drain and source electrodes of the fourth transistor 141 are connected to input node 32 and reference potential node 31, respectively. The dimensional parameter of the fourth transistor 141 is a.

[0072] The fifth circuit 15 includes a fifth transistor 151 and a low-pass filter circuit 157. The fifth transistor 151 is, for example, an n-channel transistor, which, when the input current I... IN The input node 32 and the reference potential node 31 are connected in parallel with the fourth transistor 141. The gate electrode of the fifth transistor 151 is connected to the fourth transistor 141 via a low-pass filter circuit 157. Furthermore, the drain and source electrodes of the fifth transistor 151 are connected to the input node 32 and the reference potential node 31, respectively. The dimensional parameter of the fifth transistor 151 is b.

[0073] The low-pass filter circuit 157 includes a capacitor 1571 and a resistor 1572. The function of the low-pass filter circuit 157 is the same as that of the low-pass filter circuit 127.

[0074] The sixth circuit 16 has a sixth transistor 161. The sixth transistor 161 is, for example, an n-channel transistor, connected to the output current I. ONThe current flows between output node 63 and reference potential node 31. The gate electrode of the sixth transistor 161 is connected to the gate electrode of the fourth transistor 141. Furthermore, the drain and source electrodes of the sixth transistor 161 are connected to output node 63 and reference potential node 31, respectively. The dimensional parameters of the sixth transistor 161 are equal to the sum of the dimensional parameter a of the fourth transistor 141, the dimensional parameter b of the fifth transistor 151, and the dimensional parameter c of the eighth transistor 181 in the eighth circuit 18. That is, the dimensional parameters of the sixth transistor 161 are a + b + c.

[0075] The seventh circuit 17 has a seventh transistor 171. The seventh transistor 171 is, for example, an n-channel transistor, connected to the input current I. IN The current flows between input node 53 and reference potential node 31. Additionally, the gate electrode of the seventh transistor 171 is connected to the gate electrode of the first transistor 111. The dimensional parameter of the seventh transistor 171 is c.

[0076] The eighth circuit 18 has an eighth transistor 181. The eighth transistor 181 is, for example, an n-channel transistor, connected to the input current I. IP The current flows between input node 51 and reference potential node 31. Additionally, the gate electrode of the eighth transistor 181 is connected to the gate electrode of the fourth transistor 141. The dimensional parameter of the eighth transistor 181 is c.

[0077] The first circuit 11, the second circuit 12, the third circuit 13, and the seventh circuit 17 serve as input current I from input terminals 50 and 52. IP I IN The output current I is generated from the output terminal 60. OP The first current mirror circuit CM1 operates. Additionally, the fourth circuit 14, fifth circuit 15, sixth circuit 16, and eighth circuit 18 receive the input current I from input terminals 50 and 52. IP I IN The output current I is generated from the output terminal 62. ON The output second current mirror circuit CM2 is activated.

[0078] The first current mirror circuit CM1 and the second current mirror circuit CM2 are connected by an input current I. IN The seventh transistor 171 of the seventh circuit 17 and the input current I IP The eighth transistor 181 of the eighth circuit 18 is cross-coupled.

[0079] Figure 6 This is a graph showing the frequency response related to the gain of the amplifier circuit D3 according to the third embodiment. (Refer to...) Figure 5 , Figure 6The operation of amplifier circuit D3 will be explained.

[0080] First, in the first current mirror circuit CM1, assume that the input current I is the input signal. IP I IN The frequency ω is ω≦ω z =1 / RC (i.e., equal to the cutoff frequency ω of the low-pass filter circuit 127) z (or a lower frequency case compared to this). In this case, the input signal passes through the low-pass filter circuit 127. Therefore, when the input current I... IP When input is applied to input node 51, a current I flows through the first circuit 11 at a ratio corresponding to the size parameter a of the first transistor 111. a A current I flows through the second circuit 12 at a ratio corresponding to the size parameter b of the second transistor 121. b .

[0081] Additionally, when the input current I IN When the input is fed to input node 53, due to the input current I IN The polarity of the input current I IP The polarity is reversed, therefore a current -I flows through the seventh circuit 17 at a ratio corresponding to the size parameter c of the seventh transistor 171. c .

[0082] Furthermore, the gate-source voltages are equal between the third transistor 131 and the first transistor 111, the second transistor 121, and the seventh transistor 171. Therefore, the drain current I flows through the third transistor 131. a+b+c .

[0083] Regarding the operation of the second current mirror circuit CM2, besides the input current I with reversed polarity... IP I IN Apart from this point, they are essentially the same.

[0084] Therefore, as Figure 6 As shown, the DC gain when the input signal is low frequency is A10 = I. a+b+c / (I a +I b -I c ) = (a+b+c) / (a+b-c).

[0085] Furthermore, assume that the input current I is the input signal. IP I IN The frequency ω is ω > ω z =1 / RC (i.e., the cutoff frequency ω of the low-pass filter circuit 127) z (Compared to the high-frequency case). In this case, when the input current I... IPWhen input is applied to input node 51, based on the current mirror operation, a drain current I flows through the third transistor 131 of the mirror target. a+b+c At this time, a current I flows through the first circuit 11 at a ratio corresponding to the size parameter a of the first transistor 111. a A current – ​​I – flows through the seventh circuit 17 at a ratio corresponding to the size parameter c of the seventh transistor 171. c .

[0086] On the other hand, the gate electrode of the second transistor 121 is connected to the gate electrode of the first transistor 111 via a low-pass filter circuit 127. Therefore, since the input signal to the gate electrode of the second transistor 121 is filtered by the low-pass filter circuit 127, no current I flows through the second transistor 121. b .

[0087] Regarding the operation of the second current mirror circuit CM2, besides the input current I with reversed polarity... IP I IN Apart from this point, they are essentially the same.

[0088] Therefore, as Figure 6 As shown, when the frequency of the input signal ω > ω z When ω = 1 / RC, the frequency ω of the input signal satisfies ω z Within a certain high-frequency range >1 / RC, the increase in DC gain corresponds to the increase in gain A11. The result is, as... Figure 6 As shown, the peak gain is A12 = I a+b+c / (I a -I c ) = (a+b+c) / (a-c).

[0089] As described above, the amplifier circuit D3 according to this embodiment includes a first circuit 11, a second circuit 12, a third circuit 13, a fourth circuit 14, a fifth circuit 15, a sixth circuit 16, a seventh circuit 17, and an eighth circuit 18. The first circuit 11 includes circuits connected to the input current I. IP A first transistor 111 flows between input node 51 and reference potential node 31, and its gate electrode is connected to input node 51. A second circuit 12 includes a low-pass filter circuit 127. The second circuit 12 also includes a second transistor 121 connected in parallel with the first transistor 111 between input node 51 and reference potential node 31, and whose gate electrode is connected to the gate electrode of the first transistor 111 via the low-pass filter circuit 127. A third circuit 13 includes a third transistor 131 connected between output node 61 through which the output current flows and reference potential node 31, and whose gate electrode is connected to the first transistor 111.

[0090] The fourth circuit 14 includes circuits connected to the input current I.IN A fourth transistor 141 flows between input node 53 and reference potential node 31, and its gate electrode is connected to input node 53. A fifth circuit 15 includes a low-pass filter circuit 157. The fifth circuit 15 includes a fifth transistor 151 connected in parallel with the fourth transistor 141 between input node 53 and reference potential node 31, and whose gate electrode is connected to the gate electrode of the fourth transistor 141 via the low-pass filter circuit 157. A sixth circuit 16 includes a sixth transistor 161 connected between output node 63 through which the output current flows and reference potential node 31, and whose gate electrode is connected to the fourth transistor 141.

[0091] The seventh circuit 17 includes circuits connected to the input current I. IN A seventh transistor 171 flows between input node 53 and reference potential node 31, and its gate electrode is connected to the gate electrode of the first transistor 111. The eighth circuit 18 includes a transistor connected to the input current I... IP The eighth transistor 181 flows between the input node 51 and the reference potential node 31, and its gate electrode is connected to the gate electrode of the fourth transistor 141.

[0092] The first circuit 11, the second circuit 12, the third circuit 13, and the seventh circuit 17 operate as the first current mirror circuit CM1, while the fourth circuit 14, the fifth circuit 15, the sixth circuit 16, and the eighth circuit 18 operate as the second current mirror circuit CM2. The first current mirror circuit CM1 and the second current mirror circuit CM2 are cross-coupled by the seventh transistor 171 of the seventh circuit 17 and the eighth transistor 181 of the eighth circuit 18.

[0093] Through the seventh transistor 171 of the seventh circuit 17 and the eighth transistor 181 of the eighth circuit 18, the input current I is obtained in the first current mirror circuit CM1 and the second current mirror circuit CM2. IN Relative to input current I IP Cross-coupling. Thus, in addition to the gain amplification function described in the first embodiment, amplifier circuit D3 can also amplify the DC gain.

[0094] (Fourth Implementation)

[0095] Figure 7 This is a diagram showing the structure of the amplifier circuit D4 according to the fourth embodiment. (As shown...) Figure 7 As shown, amplifier circuit D4, besides Figure 5In addition to the structure of amplifier circuit D3 shown, constant current sources 40 and 41 corresponding to the size parameter d are also provided on the input nodes 51 and 53, respectively. Constant current source 40 is connected in parallel with the first transistor 111 and the second transistor 121 between input node 51 and reference potential node 31. Constant current source 41 is connected in parallel with the fourth transistor 141 and the fifth transistor 151 between input node 53 and reference potential node 31. Furthermore, in amplifier circuit D4, corresponding to the addition of constant current sources 40 and 41, the size parameters of the third transistor 131 and the sixth transistor 161 on the output nodes 61 and 63 are a+b+c+d.

[0096] Therefore, according to the fourth embodiment, the amplifier circuit D4, similar to the amplifier circuit D2 in the second embodiment, can further amplify the DC gain compared to the amplifier circuit D3. Furthermore, by adjusting the current I output from the constant current sources 40 and 41... d It can variably amplify both boost gain and DC gain.

[0097] (Fifth Implementation)

[0098] Figure 8 This is a diagram showing the structure of the amplifier circuit D5 according to the fifth embodiment. The amplifier circuit D5 according to the fifth embodiment is a circuit that uses transistors inserted into the source side of each transistor in the first current mirror circuit CM1 and the second current mirror circuit CM2 for turn-on / turn-off control to independently control the size parameters a, b, and c, thereby variably amplifying the DC gain and boost gain.

[0099] like Figure 8 As shown, amplifier circuit D5 is the input current I. IP I IN And output current I OP I ON The output differential amplifier.

[0100] The amplifier circuit D5 has A first circuits 11 (hereinafter referred to as the "first circuit group") connected in parallel.

[0101] Amplifier circuit D5 has B second circuits 12 connected in parallel (hereinafter referred to as the "second circuit group").

[0102] The amplifier circuit D5 has C seventh circuits 17 (hereinafter referred to as the "seventh circuit group") connected in parallel.

[0103] Amplifier circuit D5 has A+B+C third circuits 13 connected in parallel (hereinafter referred to as "third circuit group"). Furthermore, the number of third circuits 13 included in the third circuit group is equal to the total number of first circuits 11 included in the first circuit group, the number of second circuits 12 included in the second circuit group, and the number of seventh circuits 17 included in the seventh circuit group.

[0104] The amplifier circuit D5 has A fourth circuits 14 connected in parallel (hereinafter referred to as the "fourth circuit group").

[0105] The amplifier circuit D5 has B fifth circuits 15 connected in parallel (hereinafter referred to as the "fifth circuit group").

[0106] The amplifier circuit D5 has C eighth circuits 18 (hereinafter referred to as the "eighth circuit group") connected in parallel.

[0107] Amplifier circuit D5 has A+B+C sixth circuits 16 connected in parallel (hereinafter referred to as the "sixth circuit group"). Furthermore, the number of sixth circuits contained in the sixth circuit group is equal to the total number of fourth circuits 14 contained in the fourth circuit group, the total number of fifth circuits 15 contained in the fifth circuit group, and the total number of eighth circuits 18 contained in the eighth circuit group.

[0108] The first, second, seventh, and third circuit groups constitute the first current mirror circuit CM1. Furthermore, the fourth, fifth, sixth, and eighth circuit groups constitute the second current mirror circuit CM2. Additionally, the amplifier circuit D5 includes a controller 25.

[0109] Each first circuit 11 has a ninth transistor 112 connected in series with a first transistor 111. The ninth transistor 112 is, for example, an n-channel transistor, and its drain electrode is connected to the source electrode of the first transistor 111. The source electrode of the ninth transistor 112 is connected to a reference potential node 31. The gate electrode of the ninth transistor 112 is connected to a predetermined fixed potential node, such as a power supply potential node. Furthermore, the size parameter of the first transistor 111 is "1". The A first transistors 111 connected in parallel in the first circuit group constitute a current I flowing through a ratio corresponding to the size parameter a. a It is part of a group of transistors.

[0110] In addition to the second transistor 121 and the low-pass filter circuit 127, each of the second circuits 12 also has a tenth transistor 122, an eleventh transistor 123 for turn-on / turn-off control, a twelfth transistor 124 for turn-on / turn-off control, and a first converter 128.

[0111] The tenth transistor 122, for example, is an n-channel transistor, connected between the second transistor 121 and the reference potential node 31. The drain electrode of the tenth transistor 122 is connected to the source electrode of the second transistor 121. The source electrode of the tenth transistor 122 is connected to the reference potential node 31. The gate electrode of the tenth transistor 122 is connected to the first control node 33. Furthermore, the size parameter of the second transistor 121 is "1". The B second transistors 121 connected in parallel in the second circuit group constitute a current I flowing through them in a ratio corresponding to the size parameter b when they are turned on. b It is part of a group of transistors.

[0112] The eleventh transistor 123, for example, is an n-channel transistor, connected in parallel with the first transistor 111 and the second transistor 121 between the input node 51 and the reference potential node 31. The drain of the eleventh transistor 123 is connected to the input node 51. The source of the eleventh transistor 123 is connected to the drain of the twelfth transistor 124. The gate of the eleventh transistor 123 is connected to the gate of the first transistor 111 without passing through the low-pass filter circuit 127. Furthermore, the size parameter of the eleventh transistor 123 is "1". The B parallel-connected eleventh transistors 123 in the second circuit group constitute a current I flowing in a ratio corresponding to the size parameter a when turned on. a It is part of a group of transistors.

[0113] The twelfth transistor 124, for example, is an n-channel transistor, connected between the eleventh transistor 123 and the reference potential node 31. The source electrode of the twelfth transistor 124 is connected to the reference potential node 31.

[0114] The input side of the first converter 128 is connected to the gate electrode of the tenth transistor 122, i.e., the first control node 33. The output side of the first converter 128 is connected to the gate electrode of the twelfth transistor 124. The first converter 128 selectively turns on either the tenth transistor 122 or the twelfth transistor 124 according to the input control signal.

[0115] In the second circuit 12, it is assumed that the controller 25 supplies a control signal (e.g., a high-level signal) to the first control node 33 to turn on the tenth transistor 122 and allow current to flow through the second transistor 121. In this case, the tenth transistor 122 is turned on by the high-level signal, and a current I1 corresponding to the ratio of the size parameter "1" flows through the second transistor 121.

[0116] On the other hand, a high-level signal is also supplied to the first converter 128. The first converter 128 inverts the supplied high-level signal into a low-level signal and supplies it to the gate electrode of the twelfth transistor 124. The twelfth transistor 124 is not turned on because the control signal supplied to its gate electrode is a low-level signal.

[0117] Alternatively, assume that the controller 25 supplies a control signal (e.g., a low-level signal) to the first control node 33 to turn off the tenth transistor 122. In this case, the tenth transistor 122 is turned off by the low-level signal, and no current I1 flows through the second transistor 121.

[0118] On the other hand, a low-level signal is also supplied to the first converter 128. The first converter 128 supplies a high-level signal, which inverts the supplied low-level signal, to the gate electrode of the twelfth transistor 124. The twelfth transistor 124 is turned on because the control signal supplied to its gate electrode is a high-level signal, and a current I1 corresponding to the ratio of the size parameter "1" flows through the eleventh transistor 123.

[0119] Each seventh circuit 17 has a seventh transistor 171, a thirteenth transistor 172, a fourteenth transistor 173, a fifteenth transistor 174, and a second converter 175.

[0120] The seventh transistor 171, for example, is an n-channel transistor, connected in parallel with the fourth transistor 141 and the fifth transistor 151 between the input node 53 and the reference potential node 31. The drain of the seventh transistor 171 is connected to the input node 53. The source of the seventh transistor 171 is connected to the drain of the thirteenth transistor 172. The gate of the seventh transistor 171 is connected to the gate of the first transistor 111. Furthermore, the size parameter of the seventh transistor 171 is "1". The C parallel-connected seventh transistors 171 in the seventh circuit group constitute a current -I flowing in a ratio corresponding to the size parameter c when turned on. c It is part of a group of transistors.

[0121] The thirteenth transistor 172, for example, is an n-channel transistor connected between the seventh transistor 171 and the reference potential node 31. The source electrode of the thirteenth transistor 172 is connected to the reference potential node 31.

[0122] The fourteenth transistor 173, for example, is an n-channel transistor, connected in parallel with the first transistor 111 and the second transistor 121 between the input node 51 and the reference potential node 31. The drain of the fourteenth transistor 173 is connected to the input node 51. The source of the fourteenth transistor 173 is connected to the drain of the fifteenth transistor 174. The gate of the fourteenth transistor 173 is connected to the gate of the first transistor 111. Furthermore, the size parameter of the fourteenth transistor 173 is "1". The C parallel-connected fourteenth transistors 173 in the seventh circuit group constitute a current I flowing in a ratio corresponding to the size parameter a when turned on. a It is part of a group of transistors.

[0123] The fifteenth transistor 174, for example, is an n-channel transistor, connected between the fourteenth transistor 173 and the reference potential node 31. The source electrode of the fifteenth transistor 174 is connected to the reference potential node 31. The gate electrode of the fifteenth transistor 174 is connected to the second control node 34.

[0124] The input side of the second converter 175 is connected to the gate electrode of the fifteenth transistor 174, i.e., the second control node 34. The output side of the second converter 175 is connected to the gate electrode of the thirteenth transistor 172. The second converter 175 selectively turns on either the thirteenth transistor 172 or the fifteenth transistor 174 according to the input control signal.

[0125] In the seventh circuit 17, it is assumed that the controller 25 supplies a high-level signal to the second control node 34 to turn on the fifteenth transistor 174 and allow current to flow through the fourteenth transistor 173. In this case, the fifteenth transistor 174 is turned on by the high-level signal, and a current I1 corresponding to the size parameter "1" flows through the fourteenth transistor 173.

[0126] On the other hand, a high-level signal is also supplied to the second converter 175. The second converter 175 inverts the supplied high-level signal into a low-level signal and supplies it to the gate electrode of the thirteenth transistor 172. The thirteenth transistor 172 does not conduct because the control signal supplied to its gate electrode is a low-level signal.

[0127] Alternatively, consider the case where the controller 25 supplies a low-level signal to the second control node 34 to turn off the fourteenth transistor 173. In this case, the fifteenth transistor 174 is turned off by this low-level signal, and no current I1 flows through the fourteenth transistor 173.

[0128] On the other hand, a low-level signal is also supplied to the second converter 175. The second converter 175 inverts the supplied low-level signal into a high-level signal and supplies it to the gate electrode of the thirteenth transistor 172. The thirteenth transistor 172 is turned on because the control signal supplied to its gate electrode is a high-level signal, and a current -I1 corresponding to the size parameter "1" flows through the seventh transistor 171.

[0129] Each third circuit 13 has a sixteenth transistor 132 connected between the third transistor 131 and the reference potential node 31. The sixteenth transistor 132 is, for example, an n-channel transistor, and its drain electrode is connected to the source electrode of the third transistor 131. The source electrode of the sixteenth transistor 132 is connected to the reference potential node 31. The gate electrode of the sixteenth transistor 132 is connected to a predetermined fixed potential node, such as a power supply potential node. Furthermore, the size parameter of the third transistor 131 is "1". The A+B+C third transistors 131 connected in parallel in the third circuit group constitute a current I flowing through a ratio corresponding to the size parameter a+b+c. a+b+c A group of transistors.

[0130] As explained above, in Figure 8 In the amplifier circuit D5 shown, the size parameters of the first transistor 111, the second transistor 121, the third transistor 131, the seventh transistor 171, the eleventh transistor 123, and the fourteenth transistor 173 are all "1", and their sizes are equal.

[0131] Each fourth circuit 14 has a seventeenth transistor 142 connected between the fourth transistor 141 and the reference potential node 31. The seventeenth transistor 142 is, for example, an n-channel transistor, and its drain electrode is connected to the source electrode of the fourth transistor 141. The source electrode of the seventeenth transistor 142 is connected to the reference potential node 31. The gate electrode of the seventeenth transistor 142 is connected to a predetermined fixed potential node, such as a power supply potential node. Furthermore, the size parameter of the fourth transistor 141 is "1". The A fourth transistors 141 connected in parallel in the fourth circuit group constitute a current -I flowing through a ratio corresponding to the size parameter a. a It is part of a group of transistors.

[0132] In addition to the fifth transistor 151 and the low-pass filter circuit 157, each of the fifth circuits 15 also has an eighteenth transistor 152, a nineteenth transistor 153, a twentieth transistor 154, and a third converter 158.

[0133] The eighteenth transistor 152, for example, is an n-channel transistor, connected between the fifth transistor 151 and the reference potential node 31. The drain electrode of the eighteenth transistor 152 is connected to the source electrode of the fifth transistor 151. The source electrode of the eighteenth transistor 152 is connected to the reference potential node 31. The gate electrode of the eighteenth transistor 152 is connected to the third control node 35. Furthermore, the size parameter of the fifth transistor 151 is "1". The B fifth transistors 151 connected in parallel in the fifth circuit group constitute a current -I flowing in a ratio corresponding to the size parameter b when turned on. b It is part of a group of transistors.

[0134] The nineteenth transistor 153, for example, is an n-channel transistor, connected in parallel with the fourth transistor 141 and the fifth transistor 151 between the input node 53 and the reference potential node 31. The drain of the nineteenth transistor 153 is connected to the input node 53. The source of the nineteenth transistor 153 is connected to the drain of the twentieth transistor 154. The gate of the nineteenth transistor 153 is connected to the gate of the fourth transistor 141 without passing through the low-pass filter circuit 157. Furthermore, the size parameter of the nineteenth transistor 153 is "1". The B nineteenth transistors 153 connected in parallel in the fifth circuit group constitute a current -I flowing in a ratio corresponding to the size parameter a when turned on. a It is part of a group of transistors.

[0135] The twentieth transistor 154 is, for example, an n-channel transistor, connected between the nineteenth transistor 153 and the reference potential node 31. The source electrode of the twentieth transistor 154 is connected to the reference potential node 31.

[0136] The input side of the third converter 158 is connected to the gate electrode of the eighteenth transistor 152, i.e., the third control node 35. The output side of the third converter 158 is connected to the gate electrode of the twentieth transistor 154. The third converter 158 selectively turns on either the eighteenth transistor 152 or the twentieth transistor 154 according to the input control signal.

[0137] The switch control in the fifth circuit 15 is the same as that in the second circuit 12, so its description is omitted.

[0138] Each of the eighth circuits 18 has an eighth transistor 181, a twenty-first transistor 182, a twenty-second transistor 183, a twenty-third transistor 184, and a fourth converter 185.

[0139] The eighth transistor 181, for example, is an n-channel transistor, connected in parallel with the first transistor 111 and the second transistor 121 between the input node 51 and the reference potential node 31. The drain of the eighth transistor 181 is connected to the input node 51. The source of the eighth transistor 181 is connected to the drain of the twenty-first transistor 182. The gate of the eighth transistor 181 is connected to the gate of the fourth transistor 141. Furthermore, the size parameter of the eighth transistor 181 is "1". The C parallel-connected eighth transistors 181 in the eighth circuit group constitute a current I flowing in a ratio corresponding to the size parameter c when turned on. c It is part of a group of transistors.

[0140] The twenty-first transistor 182 is, for example, an n-channel transistor, connected between the eighth transistor 181 and the reference potential node 31. The source electrode of the twenty-first transistor 182 is connected to the reference potential node 31.

[0141] The 22nd transistor 183 is, for example, an n-channel transistor, connected in parallel with the fourth transistor 141 and the fifth transistor 151 between the input node 53 and the reference potential node 31. The drain of the 22nd transistor 183 is connected to the input node 53. The source of the 22nd transistor 183 is connected to the drain of the 23rd transistor 184. The gate of the 22nd transistor 183 is connected to the gate of the fourth transistor 141. Furthermore, the size parameter of the 22nd transistor 183 is "1". The C parallel-connected 22nd transistors 183 in the eighth circuit group constitute a current -I flowing in a ratio corresponding to the size parameter a when turned on. a It is part of a group of transistors.

[0142] The twenty-third transistor 184, for example, is an n-channel transistor, connected between the twenty-second transistor 183 and the reference potential node 31. The source electrode of the twenty-third transistor 184 is connected to the reference potential node 31. The gate electrode of the twenty-third transistor 184 is connected to the fourth control node 36.

[0143] The input side of the fourth converter 185 is connected to the gate electrode of the twenty-third transistor 184, i.e., the fourth control node 36. The output side of the fourth converter 185 is connected to the gate electrode of the twenty-first transistor 182. The fourth converter 185 selectively turns on either the twenty-first transistor 182 or the twenty-third transistor 184 according to the input control signal.

[0144] The switch control in the eighth circuit 18 is the same as that in the seventh circuit 17, so its description is omitted.

[0145] Each sixth circuit 16 has a twenty-fourth transistor 162 connected between the sixth transistor 161 and the reference potential node 31. The twenty-fourth transistor 162 is, for example, an n-channel transistor, and its drain electrode is connected to the source electrode of the sixth transistor 161. The source electrode of the twenty-fourth transistor 162 is connected to the reference potential node 31. The gate electrode of the twenty-fourth transistor 162 is connected to a predetermined fixed potential node, such as a power supply potential node. Furthermore, the size parameter of the sixth transistor 161 is "1". The A+B+C sixth transistors 161 connected in parallel in the sixth circuit group constitute a current -I flowing through a ratio corresponding to the size parameter a+b+c. a+b+c It is part of a group of transistors.

[0146] As mentioned above, in Figure 8 In the amplifier circuit D5 shown, the size parameters of the fourth transistor 141, the fifth transistor 151, the sixth transistor 161, the eighth transistor 181, the nineteenth transistor 153, and the twenty-second transistor 183 are all "1", and their sizes are equal.

[0147] The controller 25 is a control circuit that, based on the set DC gain and boost gain, can selectively input multiple first control signals to the second circuit group, multiple second control signals to the seventh circuit group, multiple third control signals to the fifth circuit group, and multiple fourth control signals to the eighth circuit group.

[0148] Furthermore, in amplifier circuit D5, the input current I IP I IN The frequency ω is higher than the cutoff frequency ω of low-pass filter circuit 127 and low-pass filter circuit 157. z The gain difference between the large and small cases is determined by the number of second transistors 121 turned on by the first control signal and the number of fifth transistors 151 turned on by the third control signal.

[0149] Additionally, in amplifier circuit D5, the input current I... IP I IN The frequency ω is higher than the cutoff frequency ω of low-pass filter circuit 127 and low-pass filter circuit 157. z In the case of small gain, the number of seventh transistors 171 turned on by the second control signal and the number of eighth transistors 181 turned on by the fourth control signal are determined.

[0150] Additionally, in amplifier circuit D5, the input current I... IP I IN The frequency ω is higher than the cutoff frequency ω of low-pass filter circuit 127 and low-pass filter circuit 157.z The gain is greater than the input current I under large conditions. IP I IN The frequency ω is higher than the cutoff frequency ω of low-pass filter circuit 127 and low-pass filter circuit 157. z Gain in small cases.

[0151] More specifically, the controller 25 supplies corresponding control signals to multiple first control nodes 33, multiple second control nodes 34, multiple third control nodes 35, and multiple fourth control nodes 36 according to the set DC gain and boost gain. The controller 25 stores a checklist for determining the size parameters a, b, and c based on the set DC gain and boost gain. The controller 25 determines the values ​​of size parameters a, b, and c based on the set DC gain, boost gain, and checklist. The controller 25 supplies the corresponding control signals used to set the determined values ​​of size parameters a, b, and c to the multiple first control nodes 33, multiple second control nodes 34, multiple third control nodes 35, and multiple fourth control nodes 36.

[0152] Next, the switching control of the first circuit 11 and the second circuit 12 in the first current mirror circuit CM1 will be described. This switching control is performed using size parameters a, b, and c, which are determined based on the DC gain level and the boost gain level.

[0153] First, the determination of size parameters a, b, and c will be explained. The DC gain and boost gain are set as input information, and the values ​​of each of the size parameters a, b, and c (i.e., the number of transistors that should be driven in the first current mirror circuit CM1 to flow with current corresponding to each size parameter) are set as output information. A checklist is used to determine the size parameters a, b, and c.

[0154] Figure 9 (a), (b), and (c) are checklists used to determine the size parameters a, b, and c based on the set DC gain and the boost gain. In each checklist, EQ represents the boost gain level, and VGA represents the DC gain level. Figure 9 The checklists shown in (a), (b), and (c) are examples of cases where A = 8, B = 14, C = 10, and A + B + C = 32.

[0155] For example, suppose the boost gain level (EQ) is set to 3 and the DC gain level (VGA) is set to 8. In this case, according to Figure 9 The checklists for (a), (b), and (c) are as follows: (a, b, c) = (19, 3, 10).

[0156] At this time, according to b=3, the controller 25 supplies a control signal (e.g., a high-level signal) to the first control node 33 in three of the B parallel-connected second circuits 12 constituting the second circuit group, for turning on the tenth transistor 122 and allowing current to flow through the second transistor 121. According to b=3, the controller 25 also supplies a control signal (e.g., a low-level signal) to the first control node 33 in the remaining 11 (B-b=11) of the B parallel-connected second circuits 12 constituting the second circuit group, for turning on the twelfth transistor 124 and allowing current to flow through the eleventh transistor 123.

[0157] Furthermore, according to c=10, controller 25 supplies a control signal (e.g., a low-level signal) to the second control node 34 in all 10 of the C parallel-connected seventh circuits 17 constituting the seventh circuit group, for turning on the thirteenth transistor 172 and allowing current to flow through the seventh transistor 171. On the other hand, in any of the seventh circuits 17, no control signal (e.g., a high-level signal) is supplied for turning on the fifteenth transistor 174 and allowing current to flow through the fourteenth transistor 173.

[0158] That is, when the boost gain level (EQ) is set to 3 and the DC gain level (VGA) is set to 8, it is necessary to set (a, b, c) = (19, 3, 10) according to the checklist. This corresponds to the following three controls, for example. First, in the mirror source of the first current mirror circuit CM1, it is necessary to generate a current I corresponding to the size parameter a (=19) by turning on 19 transistors with a size parameter of "1" in parallel, whose gate electrodes are connected to the gate electrodes of the transistors of the mirror target without passing through the low-pass filter circuit. a Additionally, it is necessary to generate a current I corresponding to the size parameter b (=3) by connecting three transistors with their gate electrodes connected to the gate electrodes of the mirror target transistor via a low-pass filter circuit and having a size parameter of "1" in parallel. b Furthermore, it is necessary to generate a current -I corresponding to the size parameter c (=10) by conducting 10 transistors with their drain electrodes connected in parallel to an input node different from the drain electrode of the transistor in the mirror target. c .

[0159] Therefore, the controller 25 controls as follows: for three of the 14 second circuits 12, the second transistor 121 with a size parameter of "1" is turned on, and for the remaining 11 second circuits 12, the eleventh transistor 123 with a size parameter of "1" is turned on.

[0160] In addition, the controller 25 controls the following: for the ten seventh circuits 17 that exist, the seventh transistor 171 with a size parameter of "1" is turned on, and none of the fourteenth transistors 173 with a size parameter of "1" in the ten seventh circuits 17 exist.

[0161] The first circuit 11 has 8 first transistors 111 with a size parameter of "1" that are always on. In addition, since the eleventh transistor 123 with a size parameter of "1" is turned on in the 11 second circuits 12, a total of 19 (=8+11) transistors with a size parameter of a=19 can be turned on.

[0162] Therefore, in the mirror source of the first current mirror circuit CM1, currents I with ratios corresponding to the size parameter a = 19 can flow respectively. a The current I corresponding to the size parameter b = 3 b And the current I for a size parameter c=10. c .

[0163] The determination of dimensional parameters a, b, and c can also be performed at any time. For example, it can be done during the startup of the device that houses the amplifier circuit D5.

[0164] Furthermore, the determination of the dimensional parameters a, b, and c in the second current mirror circuit CM2, and the switching control based on the determined dimensional parameters a, b, and c, are the same, so their description is omitted.

[0165] As described above, according to the amplifier circuit D5 of this embodiment, by setting a desired DC gain and boost gain (peak gain), the size parameters a, b, and c used to achieve the setting can be automatically determined by a check table. The amplifier circuit D5 can perform switching control according to the determined size parameters a, b, and c to amplify the DC gain and boost gain.

[0166] That is, users can independently and variably set the DC gain and boost gain. This allows for further handling of multi-level signal amplitude.

[0167] (Sixth Implementation Method)

[0168] The amplifier circuit D6 in the sixth embodiment is a circuit that achieves greater DC gain and improves gain by connecting any one of the amplifier circuits D1 or even D5 in multiple stages.

[0169] Figure 10 This diagram illustrates the structure of the amplifier circuit D6 according to the sixth embodiment, showing an example of connecting two stages of amplifier circuit D3. Figure 10In this circuit, a two-stage connection is achieved by connecting the output node of the amplifier circuit D3, which is composed of an n-channel transistor, to the input node of the amplifier circuit D3', which is composed of a p-channel transistor instead of an n-channel transistor.

[0170] like Figure 10 As shown, by reversing the polarity of the circuit and connecting multiple stages of amplifier circuit D3, a larger DC gain and improved gain can be achieved.

[0171] (Seventh Implementation)

[0172] Figure 11 This is a diagram showing the structure of the receiving circuit D7 according to the seventh embodiment. For example... Figure 11 As shown, the receiving circuit D7 has CTLE81, DFE (Decision feedback Equalizer)82, and DEMUX (Demultiplexer)83.

[0173] CTLE81 is an input amplifier circuit that internally incorporates the amplifier circuits described in the first to sixth embodiments, continuously amplifying and equalizing the differential input signal (serial input signal) received at the differential input terminals 84 and 85 along the time axis. DFE82 is an equalization circuit that receives the output signal of CTLE81 and performs equalization processing and signal level determination on the output signal of CTLE81 based on a feedback loop. Furthermore, CTLE81 and DFE82 are examples of input circuits. DEMUX83 is a conversion circuit that receives the output signal of DFE82 and performs conversion processing to convert the output signal of DFE82 from serial to parallel.

[0174] Based on such a receiving circuit D7, a receiving circuit that has the effects of each amplification circuit involved in the first to sixth embodiments can be realized.

[0175] (Eighth Implementation Method)

[0176] Figure 12 This is a diagram showing the structure of the semiconductor integrated circuit D8 according to the eighth embodiment. (As shown...) Figure 12 As shown, the semiconductor integrated circuit D8 has a receiving circuit 80 and a processing circuit 7 that performs prescribed signal processing on the output signal of the receiving circuit 80.

[0177] The receiving circuit 80 is, for example, Figure 11 The receiving circuit D7 shown, and the CTLE81 within the receiving circuit 80, have the amplification circuits involved in the first to sixth embodiments.

[0178] According to such a receiving circuit, a receiving circuit that has the effects of each amplification circuit involved in the first to sixth embodiments can be realized.

[0179] (Variation Example 1)

[0180] In the first and second embodiments, single-ended amplifier circuits D1 and D2 were described. In contrast, two amplifier circuits D1 and D2 can also be used to form a differential amplifier circuit.

[0181] (Variation Example 2)

[0182] In the above embodiments, amplifier circuits using n-channel transistors are illustrated. Of course, the amplifier circuits described in these embodiments can also be implemented using p-channel transistors.

[0183] In addition to the embodiments described above, the following notes are disclosed.

[0184] (Postscript 1)

[0185] An amplifier circuit, wherein:

[0186] A first circuit includes a first transistor connected between an input node through which the input current flows and a reference potential node, and the gate electrode of the first transistor is connected to the input node.

[0187] The second circuit includes a low-pass filter circuit and a second transistor connected in parallel with the first transistor between the input node and the reference potential node, and the gate electrode of the second transistor is connected to the gate electrode of the first transistor via the low-pass filter circuit; and

[0188] The third circuit includes a third transistor connected between the output node through which the output current flows and the aforementioned reference potential node, and the gate electrode of the third transistor is connected to the gate electrode of the aforementioned first transistor.

[0189] (Postscript 2)

[0190] According to the amplifier circuit described in Appendix 1, the first circuit, the second circuit, and the third circuit constitute a current mirror circuit.

[0191] (Note 3)

[0192] According to the amplifier circuit described in Appendix 1 or 2, the aforementioned low-pass filter circuit includes:

[0193] A capacitor is connected between the gate electrode of the second transistor and the reference potential node; and

[0194] A resistor is connected between the gate electrode of the second transistor and the gate electrode of the first transistor.

[0195] (Note 4)

[0196] According to any one of Appendices 1 to 3, the size of the third transistor is equal to the sum of the sizes of the first transistor and the second transistor.

[0197] (Note 5)

[0198] According to the amplifier circuit described in Appendix 4, the first transistor, the second transistor, and the third transistor are all planar transistors, and the dimensions correspond to the gate width of the planar transistors.

[0199] (Note 6)

[0200] According to the amplifier circuit described in Appendix 4, the first transistor, the second transistor, and the third transistor are all FinFETs, and the dimensions correspond to the number of fins of the FinFET.

[0201] (Note 7)

[0202] The amplifier circuit according to any one of Appendices 1 to 3 further comprises: a current source connected in parallel with the first transistor and the second transistor between the input node and the reference potential node.

[0203] (Postscript 8)

[0204] According to the amplifier circuit described in Appendix 7, when the frequency of the input current is lower than the cutoff frequency of the low-pass filter circuit, the gain of the amplifier circuit is determined by the size of the current source.

[0205] (Note 9)

[0206] According to any one of Appendices 1 to 8, the gain of the amplifier circuit is greater when the frequency of the input current is greater than the cutoff frequency of the low-pass filter circuit than when the frequency of the input current is less than the cutoff frequency of the low-pass filter circuit.

[0207] (Postscript 10)

[0208] According to the amplifier circuit described in Appendix 9, the difference in gain of the amplifier circuit between the case where the frequency of the input current is greater than the cutoff frequency of the low-pass filter circuit and the case where the frequency of the input current is less than the cutoff frequency of the low-pass filter circuit is determined by the size of the second transistor.

[0209] (Postscript 11)

[0210] A differential amplifier circuit, wherein:

[0211] A first circuit includes a first transistor connected between a first input node through which a first input current flows and a reference potential node, and the gate electrode of the first transistor is connected to the first input node.

[0212] The second circuit includes a first low-pass filter circuit and a second transistor, which is connected in parallel with the first transistor between the first input node and the reference potential node, and the gate electrode of the second transistor is connected to the gate electrode of the first transistor via the first low-pass filter circuit.

[0213] The third circuit includes a third transistor connected between the first output node through which the first output current flows and the aforementioned reference potential node, and the gate electrode of the third transistor is connected to the gate electrode of the aforementioned first transistor.

[0214] The fourth circuit includes a fourth transistor connected between the second input node through which the second input current flows and the aforementioned reference potential node, and the gate electrode of the fourth transistor is connected to the aforementioned second input node.

[0215] The fifth circuit includes a second low-pass filter circuit and a fifth transistor, which is connected in parallel with the fourth transistor between the second input node and the reference potential node, and the gate electrode of the fifth transistor is connected to the gate electrode of the fourth transistor via the second low-pass filter circuit.

[0216] The sixth circuit includes a sixth transistor connected between the second output node through which the second output current flows and the aforementioned reference potential node, and the gate electrode of the sixth transistor is connected to the gate electrode of the aforementioned fourth transistor.

[0217] A seventh circuit includes a seventh transistor connected between the second input node and the reference potential node, and the gate electrode of the seventh transistor is connected to the gate electrode of the first transistor; and

[0218] The eighth circuit includes an eighth transistor connected between the first input node and the reference potential node, and the gate electrode of the eighth transistor is connected to the gate electrode of the fourth transistor.

[0219] (Postscript 12)

[0220] According to the differential amplifier circuit described in Appendix 11, the first circuit, the second circuit, the seventh circuit, and the third circuit constitute a first current mirror circuit.

[0221] The fourth circuit, the fifth circuit, the eighth circuit, and the sixth circuit constitute the second current mirror circuit.

[0222] (Postscript 13)

[0223] According to the differential amplifier circuit described in Appendix 11 or 12, the aforementioned first low-pass filter circuit includes:

[0224] A first capacitor is connected between the gate electrode of the second transistor and the reference potential node; and

[0225] A first resistor is connected between the gate electrode of the second transistor and the gate electrode of the first transistor.

[0226] The second low-pass filter circuit mentioned above includes:

[0227] A second capacitor is connected between the gate electrode of the fifth transistor and the reference potential node; and

[0228] The second resistor is connected between the gate electrode of the fifth transistor and the gate electrode of the fifth transistor.

[0229] (Postscript 14)

[0230] According to any one of Appendices 11 to 13, in the differential amplifier circuit, the size of the third transistor is equal to the sum of the sizes of the first transistor, the second transistor, and the seventh transistor.

[0231] The size of the sixth transistor is equal to the sum of the sizes of the fourth transistor, the fifth transistor, and the eighth transistor.

[0232] (Postscript 15)

[0233] According to any one of Appendices 11 to 13, the differential amplifier circuit, wherein the second circuit comprises: a tenth transistor connected between the second transistor and the reference potential node; an eleventh transistor connected in parallel with the second transistor between the first input node and the reference potential node, the gate electrode of the eleventh transistor being connected to the gate of the first transistor without passing through the first low-pass filter circuit; a twelfth transistor connected between the eleventh transistor and the reference potential node; and a first converter, one of its input side and output side being connected to the gate electrode of the tenth transistor, and the other of its input side and output side being connected to the gate electrode of the twelfth transistor, wherein either the tenth transistor or the twelfth transistor is selectively switched on according to an input first control signal.

[0234] The seventh circuit described above includes: a thirteenth transistor connected between the seventh transistor and the reference potential node; a fourteenth transistor connected in parallel with the seventh transistor between the first input node and the reference potential node, the gate electrode of the fourteenth transistor being connected to the gate of the first transistor; a fifteenth transistor connected between the fourteenth transistor and the reference potential node; and a second converter, one of its input and output sides connected to the gate electrode of the fifteenth transistor, and the other of its input and output sides connected to the gate electrode of the thirteenth transistor, selectively switching either the thirteenth transistor or the fifteenth transistor to conduct according to an input second control signal.

[0235] The fifth circuit described above includes: an eighteenth transistor connected between the fifth transistor and the reference potential node; a nineteenth transistor connected in parallel with the fifth transistor between the second input node and the reference potential node, the gate electrode of the nineteenth transistor being connected to the gate of the fourth transistor without passing through the second low-pass filter circuit; a twentieth transistor connected between the nineteenth transistor and the reference potential node; and a third converter, one of its input and output sides connected to the gate electrode of the eighteenth transistor, and the other of its input and output sides connected to the gate electrode of the twentieth transistor, selectively switching either the eighteenth transistor or the twentieth transistor to conduct according to an input third control signal.

[0236] The eighth circuit described above includes: a twenty-first transistor connected between the eighth transistor and the reference potential node; a twenty-second transistor connected in parallel with the eighth transistor between the second input node and the reference potential node, the gate electrode of the twenty-second transistor being connected to the gate of the fourth transistor; a twenty-third transistor connected between the twenty-second transistor and the reference potential node; and a fourth converter, one of its input sides being connected to the gate electrode of the twenty-third transistor, and the other of its input side and output side being connected to the gate electrode of the twenty-first transistor, selectively switching either the twenty-first transistor or the twenty-third transistor to conduction according to an input fourth control signal.

[0237] (Postscript 16)

[0238] According to the differential amplifier circuit described in Appendix 15, a first circuit group comprising a plurality of the aforementioned first circuits connected in parallel, a second circuit group comprising a plurality of the aforementioned second circuits connected in parallel, a seventh circuit group comprising a plurality of the aforementioned seventh circuits connected in parallel, and a third circuit group comprising the aforementioned third circuits connected in parallel constitute the aforementioned first current mirror circuit.

[0239] The fourth circuit group comprising multiple fourth circuits connected in parallel, the fifth circuit group comprising multiple fifth circuits connected in parallel, and the eighth circuit group comprising multiple eighth circuits connected in parallel, together with the sixth circuit group comprising the sixth circuit connected in parallel, constitute the second current mirror circuit.

[0240] The aforementioned differential amplifier circuit includes a control circuit that, based on the DC gain and the boost gain, selectively inputs multiple of the aforementioned first control signals to the aforementioned second circuit group, multiple of the aforementioned second control signals to the aforementioned seventh circuit group, multiple of the aforementioned third control signals to the aforementioned fifth circuit group, and multiple of the aforementioned fourth control signals to the aforementioned eighth circuit group.

[0241] (Postscript 17)

[0242] According to the differential amplifier circuit described in Appendix 16, the aforementioned DC gain is the gain of the amplifier circuit when the frequency of the input current is lower than the cutoff frequency of the low-pass filter circuit.

[0243] The aforementioned gain enhancement refers to the gain of the amplifier circuit when the frequency of the input current is greater than the cutoff frequency of the low-pass filter circuit.

[0244] (Postscript 18)

[0245] According to the differential amplifier circuit described in Appendix 16 or 17, the number of the third circuits included in the third circuit group is equal to the total number of the first circuits included in the first circuit group, the number of the second circuits included in the second circuit group, and the number of the seventh circuits included in the seventh circuit group.

[0246] The number of sixth circuits included in the sixth circuit group is equal to the total number of fourth circuits included in the fourth circuit group, the total number of fifth circuits included in the fifth circuit group, and the total number of eighth circuits included in the eighth circuit group.

[0247] (Postscript 19)

[0248] According to any one of Appendices 15 to 18, in the differential amplifier circuit, the dimensions of the first transistor, the second transistor, the third transistor, the seventh transistor, the eleventh transistor, and the fourteenth transistor are equal.

[0249] The dimensions of the fourth transistor, the fifth transistor, the sixth transistor, the eighth transistor, the nineteenth transistor, and the twenty-second transistor are all equal.

[0250] (Postscript 20)

[0251] According to any one of Appendices 15 to 19, the difference in gain of the differential amplifier circuit between the cases where the frequencies of the first input current and the second input current are greater than the cutoff frequencies of the first low-pass filter circuit and the second low-pass filter circuit, and the cases where the frequencies of the first input current and the second input current are less than the cutoff frequencies of the first low-pass filter circuit and the second low-pass filter circuit, is determined based on the number of the second transistors turned on by the first control signal and the number of the fifth transistors turned on by the third control signal.

[0252] (Postscript 21)

[0253] According to any one of Appendices 15 to 20, the gain of the differential amplifier circuit is determined based on the number of the seventh transistor turned on by the second control signal and the number of the eighth transistor turned on by the fourth control signal when the frequencies of the first input current and the second input current are smaller than the cutoff frequencies of the first low-pass filter circuit and the second low-pass filter circuit.

[0254] (Postscript 22)

[0255] According to any one of Appendices 11 to 21, the gain of the differential amplifier circuit is greater than the gain of the differential amplifier circuit when the frequencies of the first input current and the second input current are greater than the cutoff frequencies of the first low-pass filter circuit and the second low-pass filter circuit.

[0256] (Postscript 23)

[0257] The differential amplifier circuit according to any one of Appendices 11 to 21 further comprises:

[0258] A first current source is connected in parallel with the first transistor and the second transistor between the first input node and the reference potential node; and

[0259] The second current source is connected in parallel with the fourth transistor and the fifth transistor between the second input node and the reference potential node.

[0260] (Postscript 24)

[0261] According to the differential amplifier circuit described in Appendix 23, when the frequency of the input current is lower than the cutoff frequency of the low-pass filter circuit, the gain of the amplifier circuit is determined by the dimensions of the first current source and the second current source.

[0262] (Postscript 25)

[0263] An amplifier circuit, wherein it is formed by connecting multiple stages of the amplifier circuit described in any one of Appendices 1 to 10.

[0264] (Postscript 26)

[0265] A differential amplifier circuit, wherein it is formed by connecting multiple stages of the differential amplifier circuit described in any one of Appendices 11 to 24.

[0266] (Postscript 27)

[0267] A receiving circuit, wherein:

[0268] The input circuit includes an amplifier circuit as described in any one of the appendices 1 to 10 and 25 that receives an input signal and performs equalization processing on the input signal, or a differential amplifier circuit as described in any one of the appendices 11 to 24 and 26.

[0269] The conversion circuit performs a specified conversion process on the output signal of the above input circuit.

[0270] (Postscript 28)

[0271] A semiconductor integrated circuit, wherein:

[0272] The receiving circuit described in Appendix 27; and

[0273] The processing circuit performs prescribed signal processing on the output signal of the aforementioned receiving circuit.

[0274] As described above, the amplifier circuit, differential amplifier circuit, receiver circuit, and semiconductor integrated circuit disclosed in one embodiment of this specification achieve both gain enhancement and miniaturization while maintaining the linearity of the gain.

[0275] Explanation of reference numerals in the attached figures

[0276] 7. Processing Circuit

[0277] 11 First Circuit

[0278] 12 Second Circuit

[0279] 13 Third Circuit

[0280] 14. Fourth Circuit

[0281] 15. Fifth Circuit

[0282] 16. The sixth circuit

[0283] 17. Seventh Circuit

[0284] 18. Eighth Circuit

[0285] 25 Controllers

[0286] 31 Reference Potential Node

[0287] 32 Input Nodes

[0288] 33 First Control Node

[0289] 34 Second Control Node

[0290] 35 Third Control Node

[0291] 36 Fourth Control Node

[0292] 40, 41 Constant Current Source

[0293] Input terminals 50 and 52

[0294] Input nodes 51 and 53

[0295] Output terminals 60 and 62

[0296] Output nodes 61 and 63

[0297] 80 Receiver Circuit

[0298] 81CTLE

[0299] 82DFE

[0300] 83DEMUX

[0301] 84, 85 Differential input terminals

[0302] 111 First transistor

[0303] 112 Ninth Transistor

[0304] 121 Second Transistor

[0305] 122 Tenth Transistor

[0306] 123 Eleventh Transistor

[0307] 124 Twelfth Transistor

[0308] 127 Low-pass filter circuit

[0309] 128 First Converter

[0310] 131 Third Transistor

[0311] 132 Sixteenth Transistor

[0312] 141 Fourth transistor

[0313] 142 Seventeenth Transistor

[0314] 151 Fifth Transistor

[0315] 152 Eighteenth Transistor

[0316] 153 The Nineteenth Transistor

[0317] 154 Twentieth Transistor

[0318] 157 Low-pass filter circuit

[0319] 158 Third Converter

[0320] 161 Sixth Transistor

[0321] 162 Twenty-fourth transistor

[0322] 171 The Seventh Transistor

[0323] 172 Thirteenth Transistor

[0324] 173 The Fourteenth Transistor

[0325] 174 The Fifteenth Transistor

[0326] 175 Second Converter

[0327] 181 Eighth transistor

[0328] 182 Twenty-first transistor

[0329] 183 Twenty-second transistor

[0330] 184 Twenty-third transistor

[0331] 185 Fourth Converter

[0332] 1271 and 1571 capacitors

[0333] 1272 and 1572 resistors

[0334] CM1 First Current Mirror Circuit

[0335] CM2 Second Current Mirror Circuit

[0336] Amplifier circuits D1, D2, D3, D3', D4, D5, D6

[0337] D7 Receiver Circuit

[0338] D8 Semiconductor Integrated Circuits

Claims

1. An amplifier circuit, wherein, have: A first circuit includes a first transistor connected between a reference potential node and an input node through which the input current flows, and the gate electrode of the first transistor is connected to the input node. The second circuit includes a low-pass filter circuit and a second transistor, which is connected in parallel with the first transistor between the input node and the reference potential node, and the gate electrode of the second transistor is connected to the gate electrode of the first transistor via the low-pass filter circuit. as well as The third circuit includes a third transistor connected between the reference potential node and the output node through which the output current flows, and the gate electrode of the third transistor is connected to the gate electrode of the first transistor.

2. The amplifier circuit according to claim 1, wherein, The first circuit, the second circuit, and the third circuit constitute a current mirror circuit.

3. The amplifier circuit according to claim 1, wherein, The above low-pass filter circuit includes: A capacitor is connected between the gate electrode of the second transistor and the reference potential node; and A resistor is connected between the gate electrode of the second transistor and the gate electrode of the first transistor.

4. The amplifier circuit according to claim 1, wherein, The size of the third transistor is equal to the sum of the sizes of the first transistor and the second transistor.

5. The amplifier circuit according to claim 4, wherein, The first transistor, the second transistor, and the third transistor are all planar transistors, and the dimensions correspond to the gate width of the planar transistors.

6. The amplifier circuit according to claim 4, wherein, The first transistor, the second transistor, and the third transistor are all FinFETs, and the dimensions correspond to the number of fins in the FinFET.

7. The amplifier circuit according to claim 1, wherein, It also has: A current source is connected in parallel with the first transistor and the second transistor between the input node and the reference potential node.

8. The amplifier circuit according to claim 7, wherein, When the frequency of the input current is lower than the cutoff frequency of the low-pass filter circuit, the gain of the amplifier circuit is determined by the size of the current source.

9. The amplifier circuit according to claim 1, wherein, The gain of the amplifier circuit is greater when the frequency of the input current is greater than the cutoff frequency of the low-pass filter circuit than when the frequency of the input current is less than the cutoff frequency of the low-pass filter circuit.

10. The amplifier circuit according to claim 9, wherein, The difference in gain of the amplifier circuit between the case where the frequency of the input current is greater than the cutoff frequency of the low-pass filter circuit and the case where the frequency of the input current is less than the cutoff frequency of the low-pass filter circuit is determined by the size of the second transistor.

11. A differential amplifier circuit, wherein, have: A first circuit includes a first transistor connected between a reference potential node and a first input node through which a first input current flows, and the gate electrode of the first transistor is connected to the first input node. The second circuit includes a first low-pass filter circuit and a second transistor, which is connected in parallel with the first transistor between the first input node and the reference potential node, and the gate electrode of the second transistor is connected to the gate electrode of the first transistor via the first low-pass filter circuit. The third circuit includes a third transistor connected between the reference potential node and the first output node through which the first output current flows, and the gate electrode of the third transistor is connected to the gate electrode of the first transistor. The fourth circuit includes a fourth transistor connected between the reference potential node and the second input node through which the second input current flows, and the gate electrode of the fourth transistor is connected to the second input node. The fifth circuit includes a second low-pass filter circuit and a fifth transistor, which is connected in parallel with the fourth transistor between the second input node and the reference potential node, and the gate electrode of the fifth transistor is connected to the gate electrode of the fourth transistor via the second low-pass filter circuit. The sixth circuit includes a sixth transistor connected between the reference potential node and the second output node through which the second output current flows, and the gate electrode of the sixth transistor is connected to the gate electrode of the fourth transistor. A seventh circuit includes a seventh transistor connected between the second input node and the reference potential node, and the gate electrode of the seventh transistor is connected to the gate electrode of the first transistor; and The eighth circuit includes an eighth transistor connected between the first input node and the reference potential node, and the gate electrode of the eighth transistor is connected to the gate electrode of the fourth transistor.

12. The differential amplifier circuit according to claim 11, wherein, The first circuit, the second circuit, the seventh circuit, and the third circuit described above constitute a first current mirror circuit. The fourth circuit, the fifth circuit, the eighth circuit, and the sixth circuit constitute the second current mirror circuit.

13. The differential amplifier circuit according to claim 11, wherein, The aforementioned first low-pass filter circuit includes: A first capacitor is connected between the gate electrode of the second transistor and the reference potential node; and A first resistor is connected between the gate electrode of the second transistor and the gate electrode of the first transistor. The second low-pass filter circuit mentioned above includes: A second capacitor is connected between the gate electrode of the fifth transistor and the reference potential node; and The second resistor is connected between the gate electrode of the fifth transistor and the gate electrode of the fourth transistor.

14. The differential amplifier circuit according to claim 11, wherein, The size of the third transistor is equal to the sum of the sizes of the first transistor, the second transistor, and the seventh transistor. The size of the sixth transistor is equal to the sum of the sizes of the fourth transistor, the fifth transistor, and the eighth transistor.

15. The differential amplifier circuit according to claim 11, wherein, The second circuit described above includes: a tenth transistor connected between the second transistor and the reference potential node; an eleventh transistor connected in parallel with the second transistor between the first input node and the reference potential node, the gate electrode of the eleventh transistor being connected to the gate of the first transistor without passing through the first low-pass filter circuit; a twelfth transistor connected between the eleventh transistor and the reference potential node; and a first converter, one of its input side and output side being connected to the gate electrode of the tenth transistor, and the other of its input side and output side being connected to the gate electrode of the twelfth transistor, selectively switching either the tenth transistor or the twelfth transistor to conduct according to an input first control signal. The seventh circuit described above includes: a thirteenth transistor connected between the seventh transistor and the reference potential node; a fourteenth transistor connected in parallel with the seventh transistor between the first input node and the reference potential node, the gate electrode of the fourteenth transistor being connected to the gate of the first transistor; a fifteenth transistor connected between the fourteenth transistor and the reference potential node; and a second converter, one of its input and output sides connected to the gate electrode of the fifteenth transistor, and the other of its input and output sides connected to the gate electrode of the thirteenth transistor, selectively switching either the thirteenth transistor or the fifteenth transistor to conduct according to an input second control signal. The fifth circuit described above includes: an eighteenth transistor connected between the fifth transistor and the reference potential node; a nineteenth transistor connected in parallel with the fifth transistor between the second input node and the reference potential node, the gate electrode of the nineteenth transistor being connected to the gate of the fourth transistor without passing through the second low-pass filter circuit; a twentieth transistor connected between the nineteenth transistor and the reference potential node; and a third converter, one of its input and output sides connected to the gate electrode of the eighteenth transistor, and the other of its input and output sides connected to the gate electrode of the twentieth transistor, selectively switching either the eighteenth transistor or the twentieth transistor to conduct according to an input third control signal. The eighth circuit described above includes: a twenty-first transistor connected between the eighth transistor and the reference potential node; a twenty-second transistor connected in parallel with the eighth transistor between the second input node and the reference potential node, the gate electrode of the twenty-second transistor being connected to the gate of the fourth transistor; a twenty-third transistor connected between the twenty-second transistor and the reference potential node; and a fourth converter, one of its input side and output side being connected to the gate electrode of the twenty-third transistor, and the other of its input side and output side being connected to the gate electrode of the twenty-first transistor, selectively switching either the twenty-first transistor or the twenty-third transistor to conduction according to an input fourth control signal.

16. The differential amplifier circuit according to claim 15, wherein, A first circuit group comprising multiple first circuits connected in parallel, a second circuit group comprising multiple second circuits connected in parallel, a seventh circuit group comprising multiple seventh circuits connected in parallel, and a third circuit group comprising the third circuits connected in parallel constitute a first current mirror circuit. The fourth circuit group, which includes multiple fourth circuits connected in parallel, the fifth circuit group, which includes multiple fifth circuits connected in parallel, and the eighth circuit group, which includes multiple eighth circuits connected in parallel, together with the sixth circuit group, constitute the second current mirror circuit. The aforementioned differential amplifier circuit includes a control circuit that, based on the DC gain and the boost gain, selectively inputs multiple of the aforementioned first control signals to the aforementioned second circuit group, multiple of the aforementioned second control signals to the aforementioned seventh circuit group, multiple of the aforementioned third control signals to the aforementioned fifth circuit group, and multiple of the aforementioned fourth control signals to the aforementioned eighth circuit group.

17. The differential amplifier circuit according to claim 16, wherein, The aforementioned DC gain is the gain of the differential amplifier circuit when the frequencies of the first input current and the second input current are respectively lower than the cutoff frequencies of the first low-pass filter circuit and the second low-pass filter circuit. The aforementioned boost gain is the gain of the differential amplifier circuit when the frequencies of the first input current and the second input current are respectively greater than the cutoff frequencies of the first low-pass filter circuit and the second low-pass filter circuit.

18. The differential amplifier circuit according to claim 16, wherein, The number of third circuits included in the third circuit group is equal to the total number of first circuits included in the first circuit group, the total number of second circuits included in the second circuit group, and the total number of seventh circuits included in the seventh circuit group. The number of sixth circuits included in the sixth circuit group is equal to the total number of fourth circuits included in the fourth circuit group, the total number of fifth circuits included in the fifth circuit group, and the total number of eighth circuits included in the eighth circuit group.

19. The differential amplifier circuit according to claim 15, wherein, The dimensions of the first transistor, the second transistor, the third transistor, the seventh transistor, the eleventh transistor, and the fourteenth transistor are all equal. The dimensions of the fourth transistor, the fifth transistor, the sixth transistor, the eighth transistor, the nineteenth transistor, and the twenty-second transistor are all equal.

20. The differential amplifier circuit according to claim 15, wherein, The difference in gain of the differential amplifier circuit between the cases where the frequencies of the first input current and the second input current are greater than the cutoff frequencies of the first low-pass filter circuit and the second low-pass filter circuit, and the cases where the frequencies of the first input current and the second input current are less than the cutoff frequencies of the first low-pass filter circuit and the second low-pass filter circuit, is determined by the number of the second transistors turned on by the first control signal and the number of the fifth transistors turned on by the third control signal.

21. The differential amplifier circuit according to claim 15, wherein, When the frequencies of the first input current and the second input current are lower than the cutoff frequencies of the first low-pass filter circuit and the second low-pass filter circuit, the gain of the differential amplifier circuit is determined by the number of the seventh transistor turned on by the second control signal and the number of the eighth transistor turned on by the fourth control signal.

22. The differential amplifier circuit according to claim 11, wherein, The gain of the differential amplifier circuit is greater when the frequencies of the first input current and the second input current are greater than the cutoff frequencies of the first low-pass filter circuit and the second low-pass filter circuit, than the gain of the differential amplifier circuit is greater when the frequencies of the first input current and the second input current are less than the cutoff frequencies of the first low-pass filter circuit and the second low-pass filter circuit.

23. The differential amplifier circuit according to claim 11, wherein, It also has: A first current source is connected in parallel with the first transistor and the second transistor between the first input node and the reference potential node; and The second current source is connected in parallel with the fourth transistor and the fifth transistor between the second input node and the reference potential node.

24. The differential amplifier circuit according to claim 23, wherein, When the frequencies of the first input current and the second input current are smaller than the cutoff frequencies of the first low-pass filter circuit and the second low-pass filter circuit, respectively, the gain of the differential amplifier circuit is determined based on the dimensions of the first current source and the second current source.

25. An amplifier circuit, wherein, It is formed by connecting multiple stages of the amplifier circuit described in claim 1.

26. A differential amplifier circuit, wherein, It is formed by connecting multiple stages of the differential amplifier circuit as described in claim 11.

27. A receiving circuit, wherein, have: The input circuit includes the amplifier circuit of claim 1, which receives the input signal and performs equalization processing on the input signal; and The conversion circuit performs a specified conversion process on the output signal of the above input circuit.

28. A receiving circuit, wherein, have: The input circuit includes the differential amplifier circuit of claim 11, which receives the input signal and performs equalization processing on the input signal; and The conversion circuit performs a specified conversion process on the output signal of the above input circuit.

29. A semiconductor integrated circuit, wherein, have: The receiving circuit as claimed in claim 27; and The processing circuit performs prescribed signal processing on the output signal of the aforementioned receiving circuit.

30. A semiconductor integrated circuit, wherein, have: The receiving circuit as claimed in claim 28; and The processing circuit performs prescribed signal processing on the output signal of the aforementioned receiving circuit.

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