System and method for initializing a bandgap circuit

Abstract

The present application relates to systems and methods for initializing a bandgap circuit. A semiconductor device may include a bandgap circuit that outputs a reference voltage. The bandgap circuit may include a bandgap core circuit and a startup circuit coupled to the bandgap core circuit. The startup circuit may connect a voltage source to a node corresponding to the output of the bandgap core circuit in response to the bandgap core circuit being initialized. The startup circuit may also disconnect the voltage source from the node in response to the output voltage being equal to or greater than a desired voltage (e.g., a threshold voltage) and one or more local voltages of the bandgap core circuit being equal to or greater than a local threshold voltage.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of bandgap circuits. More specifically, embodiments of the present disclosure relate to a startup circuit for initializing a bandgap circuit. Background Art

[0002] Electronic devices such as semiconductor devices, memory chips, microprocessor chips, image chips, etc. may use reference voltages to perform various tasks and operations. For example, reference voltages are used to provide a constant power supply and current supply so that the corresponding electronic device (e.g., memory device) can accurately perform its operations. Therefore, a bandgap reference circuit can be incorporated with an electronic device to provide a reference voltage due to its ability to maintain a stable output voltage. When the bandgap reference circuit is initialized, a startup circuit can be used to enable the bandgap reference circuit to ramp its output voltage to a certain value, after which the bandgap reference circuit may be able to maintain a constant reference voltage output. Since the circuit components (e.g., switches) of the bandgap reference circuit and the startup circuit are susceptible to different variables (e.g., changes in process, voltage, and temperature), the bandgap reference circuit may provide different reference voltages based on such variables. Such changes in the behavior of the bandgap reference circuit are undesirable. In view of this, it is necessary to provide an improved system and method for initializing a bandgap reference circuit. Summary of the invention

[0003] Aspects of the present disclosure provide a startup circuit, comprising: a current mirror circuit, comprising: a current reference branch, coupled between a source voltage and a ground connection, configured to generate a reference current; a second branch, coupled between the source voltage and a first node, configured to conduct a second current that is a first portion of the reference current; and a third branch, coupled between the source voltage and the first node, configured to conduct a third current that is a second portion of the reference current; a first feedback switch, coupled between the first node and the ground connection, wherein a gate of the first feedback switch is coupled to a voltage output node of a bandgap core circuit; and a first comparator switch, coupled between the first node and the ground connection, wherein a gate of the first comparator switch is coupled to a first local voltage node of the bandgap core circuit; wherein the startup circuit is configured to: couple the source voltage and the voltage output node of the bandgap core circuit based on the first node having a first voltage; and decouple the source voltage from the voltage output node of the bandgap core circuit based on the first node having a second voltage.

[0004] Another aspect of the present disclosure provides a bandgap circuit, comprising: a bandgap core circuit configured to output a reference voltage; a startup circuit coupled to the bandgap core circuit and configured to initialize the bandgap core circuit to output the reference voltage, wherein a feedback circuit and a comparator circuit are coupled between the startup circuit and the bandgap core circuit, and wherein the startup circuit is configured to: connect a voltage source to a node corresponding to the output of the bandgap core circuit when initializing the bandgap core circuit; and disconnect the voltage source from the node in response to the reference voltage being equal to or greater than a first threshold voltage and a local voltage of the bandgap core circuit being equal to or greater than a second threshold voltage.

[0005] Another aspect of the present disclosure provides a method, comprising: coupling an output voltage of a bandgap core circuit to a startup circuit via a feedback switch; coupling a local voltage of the bandgap core circuit to the startup circuit via a comparator switch; coupling the startup circuit and the bandgap core circuit via a switch in response to the output voltage of the bandgap core circuit being lower than a first threshold voltage and the local voltage of the bandgap core circuit being lower than a second threshold voltage; and disconnecting the startup circuit and the bandgap core circuit via the switch in response to the output voltage of the bandgap core circuit being equal to or greater than the first threshold voltage and the local voltage of the bandgap core circuit being equal to or greater than the second threshold voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a simplified block diagram illustrating a semiconductor device including a bandgap circuit according to an embodiment of the present disclosure;

[0007] Figure 2 It is to illustrate that according to the embodiment of the present disclosure, Figure 1 A schematic diagram of a bandgap circuit of a portion of a semiconductor device of the present invention, the bandgap circuit having a bandgap core circuit and a startup circuit including a feedback circuit and a replica operational amplifier (op-amp) circuit; and

[0008] Figure 3 It is to illustrate that according to the embodiment of the present disclosure, Figure 1 Schematic diagram of a bandgap circuit of a portion of a semiconductor device, the bandgap circuit having a bandgap core circuit and a startup circuit including a feedback circuit, a comparator circuit and a hysteresis circuit. DETAILED DESCRIPTION

[0009] One or more specific embodiments will be described below. In order to provide a brief description of these embodiments, not all features of the actual implementation will be described in this specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the specific goals of the developer, such as consistency with system-related and enterprise-related constraints, which may vary from one implementation to another. In addition, it should be understood that such development work may be complex and time-consuming, but for the general technician who benefits from this disclosure, these are routine tasks in design, construction and manufacturing.

[0010] Some semiconductor devices (e.g., memory devices) may use a bandgap circuit to provide a constant reference voltage, thereby enabling the semiconductor device to accurately perform its operations. Generally speaking, a bandgap circuit outputs a voltage (V bgr ), so that regardless of power supply changes, temperature changes, various circuit loads, etc., the output voltage V bgr The bandgap circuit may include a bandgap core circuit and a startup circuit. In addition, as will be appreciated, the bandgap circuit may operate in an initial state or an operating state.

[0011] The bandgap circuit outputs a stable output voltage V bgr Before, the startup circuit can be used to make the output voltage V of the bandgap core circuit bgr ramps up until the bandgap circuit reaches an operating state (e.g., output voltage V bgr In addition, the output voltage V bgr Ramping up to a desired voltage value (eg, a threshold voltage) can enable the bandgap circuit to operate in a stable state during the operating state. That is, the bandgap circuit can operate in the operating state where the output voltage V bgr is a constant voltage (eg, 1.25 volts), and operates in an initial state where the bandgap circuit does not output a voltage.

[0012] With this in mind, the startup circuit can assist the bandgap core circuit in initializing itself as the bandgap core circuit ramps up its power. However, if the startup circuit does not ramp up the power of the bandgap core circuit in an expected manner, the bandgap core circuit may not operate accurately. That is, if the bandgap circuit fails to start up correctly, it may output a reference voltage V bgr , the reference voltage V bgr The expected desired voltage values ​​to be received by other circuit components may not be matched, thereby causing the corresponding electronic device to operate inefficiently or incorrectly.

[0013] In certain examples, the startup circuit may not operate consistently across various process, voltage, temperature (PVT) corners or values, thereby causing the bandgap core circuit to start incorrectly. Specifically, when the process variations of the circuit components in the startup circuit and the bandgap core circuit change, the startup circuit may not consistently ramp the bandgap core circuit to an operating state. With this in mind, embodiments described herein include startup circuits that operate more consistently in conjunction with the bandgap core circuit over a wider range of PVT corners.

[0014] In one embodiment, the startup circuit may include a comparator circuit and a current mirror circuit to operate the bandgap circuit in an operating state. The comparator circuit may include a replica (or a scaled-down replica) of an amplifier circuit (e.g., a differential operational amplifier circuit) used in the bandgap core circuit. The replica design of the startup circuit may allow the startup circuit to receive the first and second local voltages V of the bandgap core circuit based on the first and second local voltages V be The operation of the bandgap core circuit is simulated. Therefore, the replica design can enable the bandgap core circuit and the startup circuit to operate in conjunction with each other. The current mirror circuit can include a feedback circuit coupled to the output voltage V bgr To further enable the two circuits to operate in conjunction with each other. In addition, the startup circuit may include a switch that can couple the voltage source VDD to the bandgap circuit to increase the output voltage VDD based on the output signal of the comparator unit and the current mirror. bgr Ramp up to operational state.

[0015] In another embodiment, the startup circuit may include a feedback circuit, a comparator circuit, and a hysteresis circuit integrated into a current mirror circuit to cause the bandgap circuit to operate in an operating state. The feedback circuit may be coupled to the output voltage V bgr , and the comparator circuit can be coupled to the local voltage V of the bandgap core circuit be The feedback circuit and the comparator may enable the bandgap core circuit and the startup circuit to operate in conjunction with each other.

[0016] In such embodiments, the current mirror may include a reference current branch coupled to a hysteresis circuit, a second branch, and a third branch. bgr When the second branch and the third branch of the current mirror can each reflect a portion (e.g., half, quarter) of the reference current of the reference current branch. The feedback circuit and the comparator can each be based on the output voltage V bgr and the local voltage V be The second branch and the third branch are connected or disconnected from the ground. For example, the feedback circuit and the comparator may initially disconnect the second branch and the third branch from the ground connection to make the output voltage V bgrThen, when the output voltage V bgr When ramping up to the desired voltage, the feedback circuit and comparator may connect the second branch and the third branch to the ground connection so that the startup circuit is disconnected from the bandgap core circuit.

[0017] In addition, the hysteresis circuit can be based on the startup circuit to set the output voltage V bgr The third branch may be connected or disconnected from the bandgap circuit to ramp up to an operating state or disconnected from the bandgap circuit. For example, the hysteresis circuit may disconnect the third branch from the startup circuit to reduce current flow and undesirable oscillations when the startup circuit is disconnected from the bandgap circuit. Thus, the hysteresis circuit may reduce, for example, time delays and undesirable oscillations within the startup circuit when the startup circuit and the bandgap circuit are connected or disconnected.

[0018] That is, the startup circuit may further include a switch that can couple the voltage source VDD to the bandgap circuit to make the output voltage V bgr In the above embodiment, the startup circuit can provide a gate signal to a switch (e.g., a low voltage gate signal to a P-type switch), which can couple the voltage source VDD to a node of the bandgap core circuit, which is coupled to the output voltage V bgr Therefore, the startup circuit can initialize the output voltage V of the bandgap core circuit by ramping up the voltage of the bandgap core circuit. bgr . The output voltage V bgr After reaching the desired voltage value, the bandgap core circuit can be used without providing the voltage source VDD and the output voltage V bgr Therefore, the startup circuit can be designed to operate at the output voltage V bgr After reaching the desired voltage value, the voltage source VDD is disconnected (eg, decoupled) from the bandgap circuit. As mentioned above and described in more detail below, when the output voltage V bgr When the desired voltage value is reached, the feedback circuit and the comparator circuit can disconnect the startup circuit from the bandgap core circuit.

[0019] The desired voltage value corresponds to an output voltage V that enables the bandgap core circuit to maintain an operating state. bgr In additional or alternative embodiments, a high voltage gate signal may be provided to the N-type switch for coupling the voltage source VDD to the output voltage V bgr The coupled node thus ramps up the output voltage V bgr In such embodiments, a low voltage gate signal may be provided to the N-type switch for coupling to the output voltage V bgr The node disconnects the voltage source VDD and thereby powers down the startup circuit.

[0020] Such a startup circuit can reflect the change in the operation of the bandgap core circuit to disconnect (eg, shut down) from the bandgap core circuit at an appropriate time, and allow the bandgap core circuit to output the output voltage V using a desired voltage value. bgr In addition, the use of the startup circuit described herein enables the bandgap circuit to operate consistently over a wide range of process, voltage, and temperature conditions while having a smaller design footprint. Figures 1 to 3 Describes additional details about the startup circuit.

[0021] Now turning to the diagram, Figure 1 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure. That is, for example, the semiconductor device 10 may use a bandgap circuit to perform various operations. Although the following description of the semiconductor device and the bandgap circuit will be described in the context of a memory device, it should be noted that the embodiments described herein with respect to the bandgap circuit may be used in any suitable electronic device. In fact, the following description of the memory device is provided to explain certain aspects of the bandgap circuit including the startup circuit of the present disclosure, and thus, the embodiments described herein should not be limited to memory devices.

[0022] Reference Figure 1 , for example, the semiconductor device 10 may be any suitable memory device, such as a low power double data rate type 4 (LPDDR4) synchronous dynamic random access memory (SDRAM) integrated into a single semiconductor chip. The semiconductor device 10 may be mounted on an external substrate 2 that is a memory module substrate, a motherboard, etc. The semiconductor device 10 may include a plurality of memory groups each having a plurality of memory cell arrays 11. Each memory cell array 11 may include a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word lines WL is performed by a row decoder 12, and the selection of the bit lines BL is performed by a column decoder 13. The sense amplifier 18 is coupled to the corresponding bit line BL and is connected to the local input / output (I / O) line pair LIOT / B. The local IO line pair LIOT / B is connected to the main IO line pair MIOT / B via a transfer gate TG 19 that acts as a switch.

[0023] Turning to explain the multiple external terminals included in the semiconductor device 10, the multiple external terminals include an address terminal 21, a command terminal 22, a data strobe (DQS) terminal 23, a data (DQ) terminal 24, and power supply terminals 25 and 26. The data terminal 24 can be coupled to an output buffer for a read operation of the memory. Alternatively, the data terminal 24 can be coupled to an input buffer for read / write access of the memory.

[0024] The address terminal 21 is supplied with an address signal ADD and a memory cell address signal BADD. The address signal ADD and the memory cell address signal BADD supplied to the address terminal 21 are transmitted to the address decoder 32 via the address input circuit 31. The address decoder 32 receives the address signal ADD and supplies the decoded row address signal XADD to the row decoder 12, and supplies the decoded column address signal YADD to the column decoder 13. The address decoder 32 also receives the memory cell address signal BADD, and supplies the memory cell address signal BADD to the row decoder 12 and the column decoder 13.

[0025] The command terminal 22 is supplied with a command signal COM. The command signal COM may include one or more separate signals. The command signal COM input to the command terminal 22 is input to the command decoder 34 via the command input circuit 33. The command decoder 34 decodes the command signal COM to generate various internal command signals. For example, the internal command may include a row command signal for selecting a word line and a column command signal for selecting a bit line, such as a read command or a write command.

[0026] Despite Figure 1 2 and 3. In the present disclosure, the address terminal 21 and the command terminal 22 are described as separate terminals, but it should be noted that in some embodiments, the address input circuit 31 and the command input circuit 33 may receive the address signal ADD and the command signal COM via one or more address and command terminals. That is, the address signal ADD and the command signal COM may be provided to the semiconductor device 10 via the same terminal. For example, the address and command terminals may provide the address signal at a falling clock edge (e.g., synchronized with the falling clock edge), and provide the command signal at a rising clock edge (e.g., synchronized with the rising clock edge). With this in mind, it should be understood that the description provided in the present disclosure with separate address terminals 21 and command terminals 22 is included for discussion purposes, and the techniques described herein should not be limited to the use of separate address terminals 21 and command terminals 22.

[0027] Therefore, when a read command is issued and the read command is supplied to the row address and the column address in time, read data can be read from the memory cell MC in the memory cell array 11 specified by these row address and column address. The read data DQ is output to the outside from the data terminal 24 via the read / write amplifier 15 and the input / output (IO) circuit 17. Similarly, when a write command is issued and the write command is supplied to the row address and the column address in time and then the write data DQ is supplied to the data terminal 24, the write data DQ is supplied to the memory cell array 11 via the input / output circuit 17 and the read / write amplifier 15 and the write data DQ is written in the memory cell MC specified by the row address and the column address.

[0028] According to one embodiment, the input / output circuit 17 may include an input buffer. The input / output circuit 17 receives an external clock signal as a timing signal for determining the input timing of the write data DQ and the output timing of the read data DQ. Power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 17. The power supply potentials VDDQ and VSSQ may be the same potentials as the power supply potentials VDD and VSS supplied to the power supply terminal 25, respectively, which will be described below. However, dedicated power supply potentials VDDQ and VSSQ may be used for the input / output circuit 17 so that power supply noise generated by the input / output circuit 17 does not propagate to other circuit blocks.

[0029] The power supply terminal 25 is supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS are supplied to the bandgap circuit 40. In some embodiments, the bandgap circuit 40 may be a voltage reference circuit that outputs a constant (e.g., fixed) voltage independent of power supply variations, temperature variations, circuit loads, process variations, etc. In some embodiments, the bandgap circuit 40 may include a bandgap core circuit and a startup circuit. In alternative or additional embodiments, the bandgap circuit 40 may include a bandgap core circuit, and the startup circuit may be located outside the bandgap circuit 40. In any case, as will be appreciated, the bandgap core circuit may output a constant voltage after being initialized by the startup circuit.

[0030] In some embodiments, the bandgap circuit 40 may generate various internal potentials VPP, VOD, VARY, VPERI, etc. to provide to various circuit components of the semiconductor device 10. For example, the internal potential VPP is mainly used in the row decoder 12, the internal potentials VOD and VARY may be mainly used in the sense amplifier 18 included in the memory cell array 11, and the internal potential VPERI is used in many other circuit blocks.

[0031] For example, Figure 2 Schematic diagram illustrating a bandgap circuit 40 including a startup circuit 42 and a bandgap core circuit 44 according to embodiments described herein. Figure 2 , the bandgap core circuit 44 may include a differential operational amplifier circuit 46, a resistor 48, a diode 50, and a switch 52 coupled between a power supply potential VDD or a voltage source VDD 54 and a ground connection 56. Although the voltage source VDD 54 is described herein as the power supply potential VDD, it should be appreciated that in alternative or additional embodiments, a different voltage source may be used in each of the voltage sources of the described embodiments. In any case, after an initialization period of the bandgap circuit 40, the bandgap core circuit 44 may generate an output voltage V bgr 58, which can be a constant voltage.

[0032] As discussed above, the startup circuit 42 can assist the bandgap core circuit 44 in initializing and generating the output voltage V at the node 60 during the initialization period of the bandgap circuit 40. bgr 58. That is, the startup circuit 42 can ramp up the output voltage V of the bandgap core circuit 44. bgr 58 can be operated in a stable state using the desired voltage value. bgr After ramping up to the desired voltage value, the startup circuit 42 can be disconnected from the bandgap core circuit 44. The differential operational amplifier circuit 46 can then keep the switch 52 of the bandgap core circuit 44 in a closed state (connected) to increase the output voltage V bgr 58 is maintained at the desired voltage value. Therefore, the bandgap core circuit 44 can be based on the output voltage V bgr 58 generates a first local voltage V in a self-biased manner be1 62 and the second local voltage V be2 64.

[0033] That is, the differential operational amplifier circuit 46 may include a plurality of switches, including, for example, any suitable transistor-type switches, such as bipolar junction transistors, field effect transistors, etc. Each of the switches of the differential operational amplifier circuit 46 may be susceptible to different process variations, such as temperature and voltage variations. Therefore, in the depicted embodiment, the startup circuit 42 may include a replica operational amplifier circuit 66 of the differential operational amplifier circuit 46 (e.g., a comparator circuit) to reproduce the process variations of the differential operational amplifier circuit 46 in the startup circuit 42. In a specific embodiment, the replica operational amplifier circuit 66 may be a scaled-down replica of the differential operational amplifier circuit 46 to reduce the current consumption of the startup circuit 42 and the size of the startup circuit 42. However, it should be noted that in different embodiments, the replica operational amplifier circuit 66 may take any suitable size.

[0034] In addition, to further ensure the output voltage V bgr 58 is ramped up to the desired voltage value, the startup circuit 42 may also include a feedback circuit 68 integrated as part of the current mirror circuit 70. The feedback circuit 68 may be coupled between a branch of the current mirror circuit 70 of the startup circuit 42 and a current mirror circuit associated with the output voltage V bgr 58 between nodes 60 of the bandgap core circuit 44. In the depicted embodiment, the output voltage V bgr 58 provides a gate input to a switch 72 of the feedback circuit 68. The switch 72 of the feedback circuit 68 can be based on the output voltage V bgr 58 connects or disconnects the branch of the current mirror circuit 70. Figure 2Two switches 72 are shown in FIG. 1 , but any number of switches 72 may be used in alternative or different embodiments. That is, the output signals from the replica operational amplifier circuit 66 and the current mirror circuit 70 may cause the voltage source VDD54 and the bandgap core circuit 44 to be connected or disconnected so that the output voltage V bgr 58 ramps up to the desired voltage value.

[0035] With the above ideas, the initialization process of the bandgap circuit 40 is described herein. The current mirror circuit 70 of the startup circuit 42 may include a switch 74 to generate a reference current (I bias )76. At the beginning of the initialization process, the output voltage V bgr 58 is at ground voltage (eg, zero reference voltage), and the switch 72 of the feedback circuit 68 is in an open state (disconnected). In one example, the switch 72 of the feedback circuit 68 may be an N-type switch, and the output voltage V bgr 58 may be coupled to a gate input of switch 72 .

[0036] Therefore, the source current (I source )78 flows through the switch 72 of the feedback circuit 68. Therefore, the voltage of the node 80 between the voltage source VDD 54 of the current mirror circuit 70 and the switch 72 of the feedback circuit 68 can be equal to VDD. In addition, the node 80 can also be coupled to the input of the inverter 82. Therefore, in response to the high voltage (e.g., VDD) of the node 80 during the initialization of the bandgap circuit 40, the inverter 82 can output a logic 0 to the input of the AND gate 84. The logic 0 input to the AND gate 84 ensures the logic 0 output from the AND gate 84.

[0037] The output of AND gate 84 may be coupled to the gate input of P-type switch 86. In addition, P-type switch 86 may be coupled between voltage source VDD 54 and bandgap core circuit 44. Therefore, during initialization of bandgap circuit 40, P-type switch 86 may be in a closed state to connect voltage source VDD 54 with bandgap core circuit 44 based on the logic 0 output of AND gate 84. Therefore, voltage source VDD 54 and node 60 of bandgap core circuit 44 may be connected so that output voltage V bgr 58 is ramped up to the desired voltage value. In the depicted embodiment, the resistor (R stup )88 is coupled between the P-type switch 86 and the bandgap core circuit 44 , and represents the resistance of the bandgap core circuit 44 as seen from the startup circuit 42 .

[0038] When the output voltage V bgrWhen the desired voltage value is reached, the startup circuit 42 can be disconnected from the bandgap core circuit 44 by opening (switching to an off state) the P-type switch 86. To turn off the P-type switch 86, the AND gate 84 can provide a logic 1 value to the gate input of the P-type switch 86. Therefore, both the replica operational amplifier circuit 66 and the inverter 82 can output a logic 1.

[0039] The replica operational amplifier circuit 66 can receive and compare the first local voltage V be1 62 and the second local voltage V be2 64. Based on the output voltage V bgr 58 rises to the desired voltage value, when the first local voltage V be1 62 and the second local voltage V be2 When the voltage difference between the first local voltage V be1 62 and the second local voltage V be2 The voltage of 64 may be respectively based on the resistance value of each of the resistor 48 and the diode 50 and based on the output voltage V bgr 58 rose alone.

[0040] In addition, when the output voltage V bgr When the output voltage V bgr When the desired voltage value is reached based on the gradual increase in the conductance of switch 72 (for example, when a transistor is used), switch 72 of feedback circuit 68 can be fully closed. In various embodiments, when the output voltage V bgr When the desired voltage value is reached by 58 (eg, when a MOSFET is used), the switch 72 of the feedback circuit 68 may be switched to a closed state.

[0041] Thus, the voltage source VDD 54 may become connected to the ground connection 56 of the current mirror circuit 70, thereby causing I source 78 Reflection I bias 76 and flows through switch 72 of feedback circuit 68 to ground connection 56. As a result, the voltage at node 80 may drop below a logic 1 threshold (e.g., to a ground voltage level). Subsequently, inverter 82 may output a logic 1 to AND gate 84. In this way, startup circuit 42 may ensure that output voltage V is above zero before disconnecting (cutting off) from bandgap core circuit 44. bgr 58. First local voltage V be1 62 and the second local voltage V be2 64 is at a sufficient voltage level.

[0042] Although the startup circuit 42 is described with respect to certain circuit components, it should be understood that other possible circuit components may be used to integrate the output voltage V bgr 58 (in the feedback function) and the impact of process variations of the differential operational amplifier circuit 46 and the startup circuit. For example, in different embodiments, the switch 72, the inverter 82, the AND gate 84 and the P-type switch 86 can be replaced by other feasible circuit components. In addition, different schematics can be used to use fewer or more circuit components to integrate the output voltage V bgr 58 and the differential operational amplifier circuit 46 and the startup circuit 42.

[0043] Reference Figure 3 , according to embodiments described herein, illustrates a schematic diagram of a bandgap circuit 40 including a bandgap core circuit 44 and a startup circuit 100. In some embodiments, Figure 3 The bandgap core circuit 44 may be similar to that described above. Figure 2 However, in alternative or additional embodiments, a bandgap core circuit having a different schematic diagram may also be used with the bandgap circuit 40 and the startup circuit 100.

[0044] The startup circuit 100 may include a feedback circuit 102, a comparator circuit 104, and a hysteresis circuit 106 integrated with a current mirror circuit 108. The startup circuit 100 may ensure that the output voltage V is 100 before shutting down and disconnecting from the bandgap core circuit 44. bgr 58 is at the desired voltage value and the first local voltage V be1 62 is at a sufficient voltage level. The current mirror circuit 108 may include three branches: a current reference branch (first branch) 110, a second branch 112, and a third branch 114. The current reference branch 110, the second branch 112, and the third branch 114 may each include a switch 116 of the current mirror circuit 108 disposed thereon.

[0045] The current reference branch 110 can generate I bias 76. Based on the architecture of the current mirror circuit 108, I bias 76 may be mirrored in similar or different proportions between the second branch 112 and the third branch 114. That is, the cumulative current passing through the second branch 112 and the third branch 114 may be equal to (eg, reflected by) I bias 76 or I source 78.

[0046] That is, the second branch 112 and the third branch 114 can be coupled to the output voltage V bgr The switch 120 of the feedback circuit 102 is coupled to the node 60 associated with the first local voltage V be1The third branch 114 is coupled to the switch 122 of the comparator circuit 104 associated with the node 118. As will be appreciated, the third branch 114 may also include a switch 124 of the hysteresis circuit 106 coupled to the output of the current mirror circuit 108. The open state of each of the switch 120 of the feedback circuit 102 or the switch 122 of the comparator circuit 104 may prevent current from flowing through the second branch 112 and the third branch 114. In addition, the open state of the switch 124 of the hysteresis circuit 106 may prevent current from flowing through the third branch 114.

[0047] In any case, when the switch 120 of the feedback circuit 102, the switch 122 of the comparator circuit 104, and the switch 124 of the hysteresis circuit 106 are in the closed state, I bias A portion of 76 may flow through the second branch 112 and the third branch 114 in similar or different proportions to reach the ground connection 56. The feedback circuit 102 and the comparator circuit 104 may enable the startup circuit 100 and the bandgap core circuit 44 to generate a voltage V bgr 58 and the first local voltage V be1 The output voltage V bgr Initialization of 58 may be less susceptible to variations in process, temperature, and voltage, among other variables. Additionally, incorporation of hysteresis circuit 106 may reduce undesirable oscillations when initializing bandgap circuit 40.

[0048] although Figure 3 , but any number of switches 120 may be used with the feedback circuit 102. Furthermore, the switches 122 of the comparator circuit 104 may be positioned between, above, or below the switches 120 of the feedback circuit 102. In alternative or additional embodiments, the comparator circuit 104 may also include a different number of switches 122.

[0049] With the foregoing ideas, the initialization process of the bandgap circuit 40 is described herein. As mentioned above, the current reference branch 110 of the startup circuit 100 can generate I bias 76. At the beginning of the initialization process, the output voltage V bgr 58 is at ground voltage (eg, zero reference voltage). Therefore, the switch 120 of the feedback circuit 102 and the switch 122 of the comparator circuit 104 are in an open state. In one example, the switch 120 of the feedback circuit 102 and the switch 122 of the comparator circuit 104 may be N-type switches.

[0050] Therefore, it is possible to prevent I source78 flows through the second branch 112 and the third branch 114 of the current mirror circuit 108. Therefore, the voltage of the node 126 between the voltage source VDD 54 and the switch 120 of the feedback circuit 102 and the switch 122 of the comparator circuit 104 can be equal to VDD. The node 126 can also be coupled to the input of the inverter 128. Therefore, in response to the high voltage (e.g., VDD) of the node 126, the inverter 128 can output a logic 0 to the input of the P-type switch 130.

[0051] The P-type switch 130 may be coupled between the voltage source VDD 54 and the bandgap core circuit 44. In the depicted embodiment, the resistor (R stup ) 88 is coupled between the P-type switch 130 and the bandgap core circuit 44, and represents the resistance of the bandgap core circuit 44 as seen from the startup circuit 100. Therefore, at the beginning of the initialization process, the P-type switch 130 may be in a state where the voltage source VDD 54 and the bandgap core circuit 44 are connected so that the output voltage V bgr 58 ramps up to the closed state of the desired voltage value.

[0052] In different embodiments, the switch 120 of the feedback circuit 102 and the switch 122 of the comparator circuit 104 may each be implemented using different switching techniques. For example, each of the switches 120 or 122 may be implemented using a transistor that can be gradually switched to closed (or open) or using a MOSFET that can be quickly flipped to closed (or open). In any case, when the output voltage V bgr When the output voltage V is ramped up to the desired voltage value, the switch 120 of the feedback circuit 102 can be switched to a closed state. bgr 58, resistor 48 and diode 50, the switch 122 of the comparator circuit 104 can be at the first local voltage V be1 62 switches to the closed state when it ramps up to a sufficient level (eg, a threshold voltage).

[0053] Furthermore, when the switch 120 of the feedback circuit 102 and the switch 122 of the comparator circuit 104 are in a closed state, current may flow through the switch 120 of the feedback circuit 102 and the switch 122 of the comparator circuit 104 to the ground connection 56. Subsequently, the voltage of the node 126 may drop below the logic 1 threshold, and the output of the inverter 128 may flip to logic 1. Based on the output from the inverter 128 being logic 1, the switch 124 and the P-type switch 130 of the hysteresis circuit 106 may flip to an open state.

[0054] Turning off the switch 124 of the hysteresis circuit 106 can prevent current from flowing through the third branch 114 of the current mirror circuit 108. sourceA portion of I 78 may flow through the second branch 112 of the current mirror circuit 108. Thus, when the hysteresis circuit 106 prevents current from flowing through the third branch 114, the startup circuit 100 may sink I 78 flowing through the second branch 112 to the ground connection 56. source 78 part. Therefore, when the output voltage V bgr 58 ramps up to the desired voltage value and the first local voltage V be1 When the voltage level 62 is ramped up to a sufficient voltage level, less current will go to ground. Therefore, the startup circuit 100 may experience a lower level of vibration due to flipping the P-type switch 130. In addition, due to the faster turn-off time of the startup circuit 100, less time may be used to perform the initialization process of the bandgap circuit 40.

[0055] After the initialization process, as described above, the bandgap core circuit 44 can generate an output voltage V in a self-biased manner. bgr 58. That is, when the output voltage V bgr When the voltage 58 is ramped up to the desired voltage value, the differential operational amplifier circuit 46 can provide a logic 1 signal to the switch 52 to ensure that the bandgap core circuit 44 can continue to generate the output voltage V in a self-biased manner. bgr 58.

[0056] Although the present disclosure may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the specific forms disclosed. In fact, the present disclosure is intended to cover all modifications, equivalents and alternatives that fall within the spirit and scope of the present disclosure defined by the appended claims.

[0057] The technology presented and claimed herein is referenced and applied to substantial objects and specific examples of a practical nature that improve the art in a demonstrable manner and are therefore not abstract, intangible, or purely theoretical. In addition, if any claim appended at the end of this specification contains one or more elements designated as "means for [performing] [the function] ..." or "steps for [performing] [the function] ...", it is intended that such elements should be interpreted in accordance with 35 U.S.C. 112(f). However, for any claim containing elements designated in any other manner, it is intended that such elements will not be interpreted in accordance with 35 U.S.C. 112(f).

Claims

1. A starting circuit, comprising: A current mirror circuit comprising: a current reference branch coupled to a source voltage and a ground connection, the current reference branch configured to generate a reference current; a second branch coupled to the source voltage and a first node, the second branch configured to conduct a second current that is a first portion of the reference current; and a third branch coupled to the source voltage and the first node, the third branch configured to conduct a third current that is a second portion of the reference current; a first feedback switch coupled to the first node and the ground connection, wherein a gate of the first feedback switch is coupled to a voltage output node of the bandgap core circuit; and a first comparator switch coupled to the first node and the ground connection, wherein a gate of the first comparator switch is coupled to a first local voltage node of the bandgap core circuit; The startup circuit is configured to: coupling the source voltage to the voltage output node of the bandgap core circuit based on the first node having a first voltage; and The source voltage is decoupled from the voltage output node of the bandgap core circuit based on the first node having a second voltage.

2. The startup circuit of claim 1 , comprising a switch coupled to the source voltage and the voltage output node of the bandgap core circuit, the switch configured to couple the source voltage to the voltage output node of the bandgap core circuit and decouple the source voltage from the voltage output node of the bandgap core circuit. 3 . The startup circuit of claim 2 , wherein a gate of the switch is configured to be coupled to the first node via an inverter circuit. 4 . The startup circuit of claim 1 , wherein the startup circuit is configured to couple the source voltage to the voltage output node of the bandgap core circuit to ramp a voltage of the voltage output node to a first threshold.

5. The startup circuit of claim 4, wherein the startup circuit is configured to decouple the source voltage from the voltage output node of the bandgap core circuit when the voltage of the voltage output node of the bandgap core circuit reaches the first threshold. 6 . The startup circuit of claim 5 , wherein the startup circuit is configured to determine whether the voltage output node of the bandgap core circuit reaches the first threshold based on operations of the first feedback switch and the first comparator switch.

7. The startup circuit of claim 1 , wherein the first feedback switch is configured to: decoupling the first node from the ground connection when the voltage of the voltage output node is lower than a first threshold voltage; and When the voltage at the voltage output node is equal to or greater than the first threshold voltage, the first node is coupled to the ground connection.

8. The startup circuit of claim 1 , wherein the first comparator switch is configured to: decoupling the first node from the ground connection when the voltage of the first local voltage node is below a second threshold voltage; and When the voltage of the first local voltage node is equal to or greater than the second threshold voltage, coupling the first node to the ground connection.

9. The startup circuit of claim 1, comprising a second feedback switch coupled to the first node and the ground connection, wherein a gate of the second feedback switch is coupled to the voltage output node of the bandgap core circuit.

10. The startup circuit of claim 1, wherein the third branch comprises a hysteresis switch, wherein the hysteresis switch is configured to: coupling the source voltage to the first node on the third branch based on the first node having the first voltage; and The source voltage is decoupled from the first node on the third branch based on the first node having the second voltage.

11. A bandgap circuit, comprising: a bandgap core circuit configured to output a reference voltage; and A starting circuit comprising: A current mirror circuit comprising: a current reference branch coupled to a source voltage and a ground connection, the current reference branch configured to generate a reference current; a second branch coupled to the source voltage and a first node, the second branch configured to conduct a second current that is a first portion of the reference current; and a third branch coupled to the source voltage and the first node, the third branch configured to conduct a third current that is a second portion of the reference current; a first feedback switch coupled to the first node and the ground connection, wherein a gate of the first feedback switch is coupled to the bandgap core circuit, wherein the gate of the first feedback switch is configured to receive the reference voltage; and a first comparator switch coupled to the first node and the ground connection, wherein a gate of the first comparator switch is coupled to a first local voltage node of the bandgap core circuit; The startup circuit is configured to: coupling the source voltage to the bandgap core circuit based on the first node having a first voltage; and The source voltage is decoupled from the bandgap core circuit based on the first node having a second voltage.

12. The bandgap circuit of claim 11, comprising a switch coupled to the source voltage and the bandgap core circuit, the switch configured to couple the source voltage to the bandgap core circuit and decouple the source voltage from the bandgap core circuit.

13. The bandgap circuit of claim 12, wherein a gate of the switch is configured to be coupled to the first node via an inverter circuit.

14. The bandgap circuit of claim 11, wherein the startup circuit is configured to couple the source voltage to the bandgap core circuit to ramp a voltage value of the reference voltage of the bandgap core circuit to a first threshold.

15. The bandgap circuit of claim 14, wherein the startup circuit is configured to decouple the source voltage from the bandgap core circuit when the voltage value of the reference voltage reaches the first threshold. 16 . The bandgap circuit of claim 15 , wherein the startup circuit is configured to determine whether the voltage value of the reference voltage reaches the first threshold based on operations of the first feedback switch and the first comparator switch.

17. The bandgap circuit of claim 11, wherein the first feedback switch is configured to: decoupling the first node from the ground connection when the voltage value of the reference voltage is lower than a first threshold voltage; and When the voltage value of the reference voltage is equal to or greater than the first threshold voltage, the first node is coupled to the ground connection.

18. The bandgap circuit of claim 11, wherein the first comparator switch is configured to: decoupling the first node from the ground connection when the voltage of the first local voltage node is below a second threshold voltage; and When the voltage of the first local voltage node is equal to or greater than the second threshold voltage, coupling the first node to the ground connection.

19. The bandgap circuit of claim 11, comprising a second feedback switch coupled to the first node and the ground connection, wherein a gate of the second feedback switch is coupled to the bandgap core circuit.

20. The bandgap circuit of claim 11, wherein the third branch comprises a hysteresis switch, wherein the hysteresis switch is configured to: coupling the source voltage to the first node on the third branch based on the first node having the first voltage; and The source voltage is decoupled from the first node on the third branch based on the first node having the second voltage.

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