Low dropout linear voltage regulator circuit

Abstract

The application provides a low voltage difference linear voltage stabilizing circuit, which comprises a first current mirror, an input end of which is electrically connected with a bias current source; a second current mirror, an input end of which is electrically connected with an output end of the first current mirror; a differential circuit, which comprises a pair of input pair tubes, wherein a source electrode of the input pair tubes is electrically connected with an output end of the second current mirror; a gate electrode of one MOS tube of the input pair tubes is electrically connected with a reference voltage; a common source and common gate amplifying circuit, a same-phase input end and an inverse-phase input end of which are electrically connected with drain electrodes of the input pair tubes; an output circuit, an input end of which is electrically connected with an output end of the common source and common gate amplifying circuit, an output end of the output circuit is fed back to a gate electrode of another MOS tube of the input pair tubes through resistance voltage division, and the output end of the output circuit is electrically connected with the same-phase input end of the common source and common gate amplifying circuit. The low voltage difference linear voltage stabilizing circuit provided by the application can have good load response and temperature drift characteristics.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, and in particular to a low-dropout linear voltage regulator. BACKGROUND

[0002] MRAM (Magneto resistive Random Access Memory) is a kind of non-volatile magnetic random access memory. It has the high-speed read-write capability of static random access memory SRAM and the high integration of dynamic random access memory DRAM, and can basically repeat writing infinitely. Among them, MRAM has low power consumption, high-speed read-write and other index requirements, which puts high requirements on the wide temperature range, low temperature drift, low power consumption and small area of the read-write power supply from the design point of view.

[0003] In the prior art, the low-dropout linear voltage regulator used in the MRAM read operation usually has high power consumption and large temperature drift, resulting in a too small MRAM data current sampling window and affecting the read performance index. SUMMARY

[0004] The low-dropout linear voltage regulator provided by the present application can have good load response and temperature drift characteristics.

[0005] The present application provides a low-dropout linear voltage regulator, comprising:

[0006] A first current mirror, an input end of which is electrically connected with a bias current source, for amplifying the current input by the bias current source to a first bias current according to a predetermined first ratio;

[0007] A second current mirror, an input end of which is electrically connected with an output end of the first current mirror, for amplifying the first bias current to a second bias current according to a predetermined second ratio;

[0008] A differential circuit comprising a pair of input pair tubes, wherein the source of the input pair tube is electrically connected with the output end of the second current mirror; the gate of one of the MOS tubes of the input pair tube is electrically connected with a reference voltage;

[0009] A common-source common-gate amplification circuit, whose non-inverting input end and inverting input end are respectively electrically connected with the drain of the input pair tube;

[0010] An output circuit, an input end of which is electrically connected with the output end of the common-source common-gate amplification circuit, the output end of the output circuit is fed back to the gate of the other MOS tube of the input pair tube after being divided by a resistor, and the output end of the output circuit is electrically connected with the non-inverting input end of the common-source common-gate amplification circuit.

[0011] Optionally, the first current mirror comprises:

[0012] a first resistor, a first end of the first resistor being electrically connected with a current source;

[0013] a first NMOS transistor, a drain of the first NMOS transistor being electrically connected with a second end of the first resistor;

[0014] a second NMOS transistor, a drain of the second NMOS transistor being electrically connected with a source of the first NMOS transistor, a source of the second NMOS transistor being grounded;

[0015] a third NMOS transistor, a source of the third NMOS transistor being grounded, the third NMOS transistor being a common gate with the second NMOS transistor and being electrically connected with the second end of the first resistor;

[0016] a fourth NMOS transistor, a source of the fourth NMOS transistor being electrically connected with a drain of the third NMOS transistor, the fourth NMOS transistor being a common gate with the first NMOS transistor and being electrically connected with the first end of the first resistor, a drain of the fourth NMOS transistor being used for outputting a first bias current.

[0017] Optionally, the second current mirror comprises:

[0018] a second resistor, a first end of the second resistor being electrically connected with the drain of the fourth NMOS transistor;

[0019] a first PMOS transistor, a drain of the first PMOS transistor being electrically connected with a second end of the second resistor;

[0020] a second PMOS transistor, a drain of the second PMOS transistor being electrically connected with a source of the first PMOS transistor, a source of the second PMOS transistor being electrically connected with a voltage source;

[0021] a third PMOS transistor, a source of the third PMOS transistor being electrically connected with the voltage source, the third PMOS transistor being a common gate with the second PMOS transistor and being electrically connected with the second end of the second resistor;

[0022] a fourth PMOS transistor, a source of the fourth PMOS transistor being electrically connected with a drain of the third PMOS transistor, the fourth PMOS transistor being a common gate with the first PMOS transistor and being electrically connected with a first end of the second resistor, a drain of the fourth PMOS transistor being used for outputting a second bias current.

[0023] Optionally, the differential circuit comprises a pair of input pair transistors, the input pair transistors comprising:

[0024] a fifth PMOS transistor, a source end of the fifth PMOS transistor is electrically connected with a drain end of the fourth PMOS transistor, a drain end of the fifth PMOS transistor is electrically connected with a non-inverting input end of the common-source common-gate amplifier circuit, and a gate of the fifth PMOS transistor is electrically connected with a reference voltage source;

[0025] a sixth PMOS transistor, a source end of the sixth PMOS transistor is electrically connected with the drain end of the fourth PMOS transistor, a drain end of the sixth PMOS transistor is electrically connected with an inverting input end of the common-source common-gate amplifier circuit, and a gate of the sixth PMOS transistor is used for inputting a signal fed back by the output circuit.

[0026] Optionally, the common-source common-gate amplifier circuit comprises:

[0027] a seventh PMOS transistor and an eighth PMOS transistor arranged in common gate, source ends of the seventh PMOS transistor and the eighth PMOS transistor are electrically connected with a voltage source;

[0028] a ninth PMOS transistor and a tenth PMOS transistor arranged in common gate, source ends of the ninth PMOS transistor and the tenth PMOS transistor are electrically connected with drain ends of the seventh PMOS transistor and the eighth PMOS transistor respectively, wherein a drain end of the ninth PMOS transistor is electrically connected with source ends of the seventh PMOS transistor and the eighth PMOS transistor, gate ends of the ninth PMOS transistor and the tenth PMOS transistor are electrically connected with gates of the first PMOS transistor and the fourth PMOS transistor, and a drain end of the tenth PMOS transistor is used as an output end of the amplifier circuit;

[0029] a fifth NMOS transistor and a sixth NMOS transistor arranged in common gate, drain ends of the fifth NMOS transistor and the sixth NMOS transistor are electrically connected with drain ends of the ninth PMOS transistor and the tenth PMOS transistor respectively, wherein gate ends of the fifth NMOS transistor and the sixth NMOS transistor are electrically connected with gates of the first NMOS transistor and the fourth NMOS transistor, a source end of the fifth NMOS transistor is used as a non-inverting input end of the amplifier circuit, and a source end of the sixth NMOS transistor is used as an inverting input end of the amplifier circuit;

[0030] a seventh NMOS transistor and an eighth NMOS transistor arranged in common gate, drain ends of the seventh NMOS transistor and the eighth NMOS transistor are electrically connected with source ends of the fifth NMOS transistor and the sixth NMOS transistor respectively, source ends of the seventh NMOS transistor and the eighth NMOS transistor are grounded, and gate ends of the seventh NMOS transistor and the eighth NMOS transistor are electrically connected with gates of the second NMOS transistor and the third NMOS transistor.

[0031] Optionally, the output circuit comprises:

[0032] a driving transistor, a gate of the driving transistor is electrically connected with an output end of the common-source common-gate amplifier circuit, and one of a source and a drain of the driving transistor is electrically connected with the voltage source.

[0033] An adjustable resistor has its first end electrically connected to the source or drain of the driving transistor; the first end of the adjustable resistor is electrically connected to the source of the fifth NMOS transistor through a first capacitor C1; the first end of the adjustable resistor serves as an output terminal and is grounded through a second capacitor.

[0034] The third resistor has its first end electrically connected to the second end of the adjustable resistor, and its second end grounded; the first end of the third resistor is electrically connected to the gate of the sixth PMOS transistor.

[0035] Optionally, the size ratio of the second NMOS transistor, the third NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor is 1:1:5:5.

[0036] Optionally, the size ratio of the second PMOS transistor to the third PMOS transistor is 1:5.

[0037] Optionally, the size ratio of the seventh PMOS transistor to the eighth PMOS transistor is 1:1.

[0038] Optionally, the first NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor adopt a width-to-length ratio inverse dimension, and the first PMOS transistor, the fourth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor adopt a width-to-length ratio inverse dimension.

[0039] The technical solution provided by this invention combines a first current mirror and a second current mirror to avoid current imbalance during the mirroring process. By amplifying the differential current through a common-source, common-gate amplifier circuit, the load response and temperature drift characteristics can be effectively improved, while also increasing the power supply rejection ratio. The technical solution provided by this invention can be applied to MRAM read operation power supplies, is compatible with various process platform designs, and has high reusability. It also meets requirements for low power consumption, wide temperature range, and low temperature drift. The design can achieve a quiescent current of 6uA, an output temperature drift of 3-5mV in the range of -40℃ to +125℃, and a 12% reduction in area compared to the original design, meeting the high-performance requirement of VPP < 35mV under full PVT (Process, Voltage, Temperature) during 5ns read operations. Attached Figure Description

[0040] Fig. 1 This is a schematic diagram of a low-dropout linear voltage regulator circuit according to an embodiment of the present invention;

[0041] Fig. 2 This is a schematic diagram of a low-dropout linear voltage regulator circuit according to another embodiment of the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] This invention provides a low-dropout linear voltage regulator circuit, such as... Figs. 1-2 As shown, it includes:

[0044] The first current mirror has its input terminal electrically connected to the bias current source, and is used to amplify the current input from the bias current source into a first bias current according to a predetermined first ratio.

[0045] The second current mirror has its input terminal electrically connected to the output terminal of the first current mirror, and is used to amplify the first bias current into a second bias current according to a predetermined second ratio.

[0046] A differential circuit includes a pair of input transistors, wherein the source of the input transistors is electrically connected to the output terminal of the second current mirror; the gate of one of the MOS transistors in the input pair is electrically connected to a reference voltage.

[0047] In a common-source common-gate amplifier circuit, the non-inverting input terminal and the inverting input terminal are respectively electrically connected to the drain of the input pair transistors;

[0048] The output circuit has its input terminal electrically connected to the output terminal of the common-source cascode amplifier circuit. The output terminal of the output circuit is fed back to the gate of the other MOS transistor in the input pair after being divided by a resistor. The output terminal of the output circuit is electrically connected to the non-inverting input terminal of the common-source cascode amplifier circuit.

[0049] In the technical solution provided in this embodiment, a first current mirror and a second current mirror are used in combination to avoid current imbalance during the mirroring process. The differential current is amplified through a common-source, common-gate amplifier circuit, effectively improving load response and temperature drift characteristics, while also increasing the power supply rejection ratio. The technical solution provided in this embodiment can be applied to MRAM read operation power supplies, is compatible with various process platform designs, and has high reusability. It also meets requirements for low power consumption, wide temperature range, and low temperature drift. The design can achieve a quiescent current of 6uA, an output temperature drift of 3-5mV in the range of -40℃ to +125℃, and a 12% reduction in area compared to the original design, meeting the high-performance requirement of VPP < 35mV under full PVT (Process, Voltage, Temperature) during 5ns read operations.

[0050] As an optional implementation, continue as follows Figs. 1-2 As shown, the first current mirror includes:

[0051] The first resistor R1 is electrically connected to the current source at its first end.

[0052] The drain of the first NMOS transistor N5 is electrically connected to the second terminal of the first resistor.

[0053] The second NMOS transistor N1 has its drain terminal electrically connected to the source terminal of the first NMOS transistor, and the source terminal of the second NMOS transistor is grounded.

[0054] The third NMOS transistor N2 has its source terminal grounded, and it shares a common gate with the second NMOS transistor and is electrically connected to the second terminal of the first resistor.

[0055] The fourth NMOS transistor N6 has its source terminal electrically connected to the drain terminal of the third NMOS transistor. The fourth NMOS transistor shares a common gate with the first NMOS transistor and is electrically connected to the first terminal of the first resistor. The drain terminal of the fourth NMOS transistor is used to output the first bias current.

[0056] In this embodiment, the first resistor R1, the second NMOS transistor N1, the third NMOS transistor N2, the first NMOS transistor N5, and the fourth NMOS transistor N6 constitute an N-type self-biased low-voltage cascaded common-source cascode current mirror, which keeps the second NMOS transistor N1 and the third NMOS transistor N2 in the saturation region during normal operation, ensuring accurate mirror bias current.

[0057] As an optional implementation, continue as follows Figs. 1-2 As shown, the second current mirror includes:

[0058] The second resistor R4 has its first end electrically connected to the drain of the four NMOS transistors.

[0059] The drain of the first PMOS transistor P7 is electrically connected to the second terminal of the second resistor.

[0060] The second PMOS transistor P3 has its drain terminal electrically connected to the source terminal of the first PMOS transistor, and its source terminal is electrically connected to a voltage source.

[0061] The third PMOS transistor P4 has its source terminal electrically connected to a voltage source, and it shares a common gate with the second PMOS transistor and is electrically connected to the second terminal of the second resistor.

[0062] The fourth PMOS transistor P8 has its source terminal electrically connected to the drain terminal of the third PMOS transistor. The fourth PMOS transistor shares a common gate with the first PMOS transistor and is electrically connected to the first terminal of the second resistor. The drain terminal of the fourth PMOS transistor is used to output the second bias current.

[0063] In this embodiment, the second resistor R4, the second PMOS transistor P3, the third PMOS transistor P4, the first PMOS transistor P7, and the fourth PMOS transistor P8 constitute a P-type self-biased low-voltage cascaded common-source cascode current mirror, which keeps the second PMOS transistor P3 and the third PMOS transistor P4 in the saturation region during normal operation, ensuring accurate mirror bias current.

[0064] As an optional implementation, continue as follows Figs. 1-2 As shown, the differential circuit includes a pair of input transistors, the input transistors comprising:

[0065] The source terminal of the fifth PMOS transistor P1 is electrically connected to the drain terminal of the fourth PMOS transistor, the drain terminal of the fifth PMOS transistor is electrically connected to the non-inverting input terminal of the common-source common-gate amplifier circuit, and the gate of the fifth PMOS transistor is electrically connected to the reference voltage source.

[0066] The source terminal of the sixth PMOS transistor P2 is electrically connected to the drain terminal of the fourth PMOS transistor. The drain terminal of the sixth PMOS transistor is electrically connected to the inverting input terminal of the common-source common-gate amplifier circuit. The gate of the sixth PMOS transistor is used to input the signal fed back by the output circuit.

[0067] As an optional implementation, continue as follows Figs. 1-2 As shown, the common-source cascode amplifier circuit includes:

[0068] The seventh PMOS transistor P5 and the eighth PMOS transistor P6 are configured with a common gate, and the source terminals of the seventh PMOS transistor and the eighth PMOS transistor are both electrically connected to a voltage source.

[0069] A ninth PMOS transistor P9 and a tenth PMOS transistor P10 are configured with a common gate. The source terminals of the ninth and tenth PMOS transistors are electrically connected to the drain terminals of the seventh and eighth PMOS transistors, respectively. The drain terminal of the ninth PMOS transistor is electrically connected to the source terminals of the seventh and eighth PMOS transistors. The gate terminals of the ninth and tenth PMOS transistors are electrically connected to the gate terminals of the first and fourth PMOS transistors. The drain terminal of the tenth PMOS transistor serves as the output terminal of the amplifier circuit.

[0070] A fifth NMOS transistor N7 and a sixth NMOS transistor N8 are configured with a common gate. The drain terminals of the fifth and sixth NMOS transistors are electrically connected to the drain terminals of the ninth and tenth PMOS transistors, respectively. The gate terminals of the fifth and sixth NMOS transistors are electrically connected to the gate terminals of the first and fourth NMOS transistors. The source terminal of the fifth NMOS transistor serves as the non-inverting input terminal of the amplifier circuit, and the source terminal of the sixth NMOS transistor serves as the inverting input terminal of the amplifier circuit.

[0071] The seventh NMOS transistor N3 and the eighth NMOS transistor N4 are configured with a common gate. The drain terminals of the seventh NMOS transistor and the eighth NMOS transistor are electrically connected to the source terminals of the fifth NMOS transistor and the sixth NMOS transistor, respectively. The source terminals of the seventh NMOS transistor and the eighth NMOS transistor are grounded. The gate terminals of the seventh NMOS transistor and the eighth NMOS transistor are electrically connected to the gate terminals of the second NMOS transistor and the third NMOS transistor.

[0072] In this embodiment, the fifth PMOS transistor P1, the sixth PMOS transistor P2, the third PMOS transistor P4, the fourth PMOS transistor P8, the seventh PMOS transistor P5, the eighth PMOS transistor P6, the ninth PMOS transistor P9, the tenth PMOS transistor P10, the seventh NMOS transistor N3, the eighth NMOS transistor N4, the fifth NMOS transistor N7, and the sixth NMOS transistor N8 form a folded cascaded common-source common-gate structure. The P-type current buffer formed by the ninth PMOS transistor P9 and the tenth PMOS transistor P10 and the N-type current buffer formed by the fifth NMOS transistor N7 and the sixth NMOS transistor N8 are folded into a P-type current mirror, which is composed of the seventh PMOS transistor P5 and the eighth PMOS transistor P6. In this structure, the mirror bias current of the seventh NMOS transistor N3 and the eighth NMOS transistor N4 needs to provide at least 1.5 times the current of the third PMOS transistor P4. This ensures that the fifth NMOS transistor N7, the sixth NMOS transistor N8, the seventh PMOS transistor P5, the eighth PMOS transistor P6, the ninth PMOS transistor P9, and the tenth PMOS transistor P10 will not enter the linear region due to the insufficient bias current of the third PMOS transistor P4. Furthermore, even if the current of the third PMOS transistor P4 drops to zero, the fifth NMOS transistor N7, the sixth NMOS transistor N8, the seventh PMOS transistor P5, the eighth PMOS transistor P6, the ninth PMOS transistor P9, and the tenth PMOS transistor P10 will not be completely turned off, avoiding the extra time consumed by re-turning on the turned-off transistors. In the above structure, the output terminal of the folded cascaded structure is the drain terminal Vo of the tenth PMOS transistor P10, and the output voltage swing is:

[0073] VDS4+VDS8(SAT) <Vo<VIO-VSD6-VSD10(SAT),

[0074] Wherein, VDS4 is the voltage difference between the drain and source terminals of the eighth NMOS transistor N4.

[0075] VDS8(SAT) is the saturation voltage difference between the drain and source terminals of the sixth NMOS transistor N8.

[0076] Vo is the output voltage at the VOUT terminal.

[0077] VIO is the voltage source voltage.

[0078] VSD6 is the voltage difference between the source and drain terminals of the eighth PMOS transistor P6.

[0079] VSD10(SAT) is the saturation voltage difference between the source and drain terminals of the tenth PMOS transistor P10.

[0080] As an optional implementation, the output circuit includes:

[0081] The gate of the driving transistor is electrically connected to the output terminal of the common-source common-gate amplifier circuit; one of its source or drain is electrically connected to the voltage source.

[0082] The first end of the adjustable resistor R2 is electrically connected to the other of the source or drain of the driving transistor; the first end of the adjustable resistor is electrically connected to the source of the fifth NMOS transistor through the first capacitor C1; the first end of the adjustable resistor serves as the output terminal and is grounded through the second capacitor.

[0083] The third resistor R3 has its first end electrically connected to the second end of the adjustable resistor, and its second end grounded; the first end of the third resistor is electrically connected to the gate of the sixth PMOS transistor.

[0084] In this embodiment, the driving transistor can be either an NMOS transistor N9 or a PMOS transistor P11. For wide power domain chips, both driving structures can be integrated simultaneously. The VIO voltage judgment module integrated within the chip determines which driving design architecture to use. When VIO is high, an NMOS transistor (N9) is selected as the driving transistor design architecture. When VIO is low, a PMOS transistor P11 is selected as the driving transistor design. The output voltage Vout is fed back to the gate terminal of the operational amplifier's negative terminal P2 through a voltage divider formed by resistors R2 and R3. C1 is a Miller compensation capacitor to improve the frequency characteristics and phase margin performance of the operational amplifier.

[0085] As an optional implementation, the size ratio of the second, third, seventh, and eighth NMOS transistors is 1:1:5:5. In this embodiment, the aforementioned ratio ensures accurate output of the first current mirror for the first bias current. In this embodiment, the size ratio refers to the multiplier ratio of the second, third, seventh, and eighth NMOS transistors.

[0086] As an optional implementation, the size ratio of the second PMOS transistor to the third PMOS transistor is 1:5. In this embodiment, the aforementioned ratio ensures that the second current mirror amplifies the first bias current, thus ensuring the accurate output of the second bias current.

[0087] As an optional implementation, the size ratio of the seventh PMOS transistor to the eighth PMOS transistor is 1:1. In this embodiment, to ensure accurate differential current distribution between the input pair transistors, PMOS transistors with a size ratio of 1:1 are used.

[0088] As an optional implementation, the first, fourth, fifth, and sixth NMOS transistors adopt an inverse width-to-length ratio, and the first, fourth, ninth, and tenth PMOS transistors adopt an inverse width-to-length ratio. The inverse ratio refers to a MOS transistor channel width W / channel length L < 1. Using an inverse ratio ensures that these devices operate in the saturation region under DC conditions within the power domain, and also benefits the improvement of the LDO's PSRR (Power Supply Rejection Ratio).

[0089] Those skilled in the art will understand that all or part of the processes in the above method embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0090] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A low dropout linear voltage regulator circuit, characterized by comprising: The application relates to a differential amplifier circuit, comprising: a first current mirror, an input end of which is electrically connected with a bias current source, for amplifying a current input by the bias current source into a first bias current according to a predetermined first ratio; a second current mirror, an input end of which is electrically connected with an output end of the first current mirror, for amplifying the first bias current into a second bias current according to a predetermined second ratio; a differential circuit, comprising a pair of input pair tubes, wherein source ends of the input pair tubes are electrically connected with an output end of the second current mirror; and a gate end of one MOS tube of the input pair tubes is electrically connected with a reference voltage; a common-source common-gate amplification circuit, whose non-inverting input end and inverting input end are respectively electrically connected with drain ends of the input pair tubes; an output circuit, an input end of which is electrically connected with an output end of the common-source common-gate amplification circuit, and an output end of the output circuit is fed back to a gate end of another MOS tube of the input pair tubes after being divided by a resistor; and the output end of the output circuit is electrically connected with the non-inverting input end of the common-source common-gate amplification circuit; wherein the differential circuit comprises a pair of input pair tubes, and the input pair tubes comprise: a fifth PMOS tube, a source end of which is electrically connected with an output end of the second current mirror; a drain end of the fifth PMOS tube is electrically connected with the non-inverting input end of the common-source common-gate amplification circuit; and a gate end of the fifth PMOS tube is electrically connected with a reference voltage source; a sixth PMOS tube, a source end of which is electrically connected with the output end of the second current mirror; a drain end of the sixth PMOS tube is electrically connected with the inverting input end of the common-source common-gate amplification circuit; and a gate end of the sixth PMOS tube is used for inputting a signal fed back by the output circuit; wherein the common-source common-gate amplification circuit comprises: a seventh PMOS tube and an eighth PMOS tube arranged in a common-gate mode, source ends of the seventh PMOS tube and the eighth PMOS tube are electrically connected with a voltage source; a ninth PMOS tube and a tenth PMOS tube arranged in a common-gate mode, source ends of the ninth PMOS tube and the tenth PMOS tube are respectively electrically connected with drain ends of the seventh PMOS tube and the eighth PMOS tube; wherein a drain end of the ninth PMOS tube is electrically connected with source ends of the seventh PMOS tube and the eighth PMOS tube; gate ends of the ninth PMOS tube and the tenth PMOS tube are electrically connected with an input end of the second current mirror; and a drain end of the tenth PMOS tube is used as an output end of the amplification circuit; a fifth NMOS tube and a sixth NMOS tube arranged in a common-gate mode, drain ends of the fifth NMOS tube and the sixth NMOS tube are respectively electrically connected with drain ends of the ninth PMOS tube and the tenth PMOS tube; wherein gate ends of the fifth NMOS tube and the sixth NMOS tube are electrically connected with the bias current source; a source end of the fifth NMOS tube is used as a non-inverting input end of the amplification circuit; and a source end of the sixth NMOS tube is used as an inverting input end of the amplification circuit. A seventh NMOS transistor and an eighth NMOS transistor in common gate configuration, the drain of the seventh NMOS transistor and the drain of the eighth NMOS transistor are electrically connected to the source of the fifth NMOS transistor and the source of the sixth NMOS transistor respectively, the source of the seventh NMOS transistor and the source of the eighth NMOS transistor are grounded, wherein the gate of the seventh NMOS transistor and the gate of the eighth NMOS transistor are electrically connected to the input of the first current mirror.

2. The low dropout linear regulator circuit of claim 1, wherein, The first current mirror comprises: A first resistor, the first end of the first resistor is electrically connected to a current source; A first NMOS transistor, the drain of the first NMOS transistor is electrically connected to the second end of the first resistor; A second NMOS transistor, the drain of the second NMOS transistor is electrically connected to the source of the first NMOS transistor, the source of the second NMOS transistor is grounded; A third NMOS transistor, the source of the third NMOS transistor is grounded, the third NMOS transistor is in common gate configuration with the second NMOS transistor and is electrically connected to the second end of the first resistor; A fourth NMOS transistor, the source of the fourth NMOS transistor is electrically connected to the drain of the third NMOS transistor, the fourth NMOS transistor is in common gate configuration with the first NMOS transistor and is electrically connected to the first end of the first resistor, the drain of the fourth NMOS transistor is used for outputting a first bias current.

3. The low dropout linear regulator of claim 2, wherein, The second current mirror comprises: A second resistor, the first end of the second resistor is electrically connected to the drain of the fourth NMOS transistor; A first PMOS transistor, the drain of the first PMOS transistor is electrically connected to the second end of the second resistor; A second PMOS transistor, the drain of the second PMOS transistor is electrically connected to the source of the first PMOS transistor, the source of the second PMOS transistor is electrically connected to a voltage source; A third PMOS transistor, the source of the third PMOS transistor is electrically connected to a voltage source, the third PMOS transistor is in common gate configuration with the second PMOS transistor and is electrically connected to the second end of the second resistor; A fourth PMOS transistor, the source of the fourth PMOS transistor is electrically connected to the drain of the third PMOS transistor, the fourth PMOS transistor is in common gate configuration with the first PMOS transistor and is electrically connected to the first end of the second resistor, the drain of the fourth PMOS transistor is used for outputting a second bias current.

4. The low dropout linear regulator of claim 3, wherein, The output circuit comprises: A driving transistor, the gate of the driving transistor is electrically connected to the output of the common source common gate amplifier circuit; one of the source or the drain of the driving transistor is electrically connected to the voltage source; An adjustable resistor, the first end of the adjustable resistor is electrically connected to the other of the source or the drain of the driving transistor; the first end of the adjustable resistor is electrically connected to the source of the fifth NMOS transistor through a first capacitor C1; the first end of the adjustable resistor is used as an output and is grounded through a second capacitor; A third resistor, the first end of the third resistor is electrically connected to the second end of the adjustable resistor, the second end of the third resistor is grounded; the first end of the third resistor is electrically connected to the gate of the sixth PMOS transistor.

5. The low dropout linear regulator of claim 4, wherein, The size ratio of the second NMOS transistor, the third NMOS transistor, the seventh NMOS transistor and the eighth NMOS transistor is 1:1:5:

5.

6. The low dropout linear regulator of any of claims 3-4, wherein, The size ratio of the second PMOS transistor and the third PMOS transistor is 1:

5.

7. The low dropout linear regulator of claim 4, wherein, The size ratio of the seventh PMOS tube and the eighth PMOS tube is 1:

1.

8. The low dropout linear regulator of claim 4, wherein, The first NMOS tube, the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube adopt an inverse ratio size of width to length, and the first PMOS tube, the fourth PMOS tube, the ninth PMOS tube and the tenth PMOS tube adopt an inverse ratio size of width to length.

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