Electrode structure, display panel and electronic device

Abstract

The embodiments of the present disclosure relate to an electrode structure, a display panel and an electronic device. The electrode structure comprises: a first electrode portion (20) and a second electrode portion (21) arranged at intervals in a first direction (Y), and a conductive connecting portion (22) located between the first electrode portion (20) and the second electrode portion (21), wherein the first electrode portion (20) comprises a first connecting strip (201) extending in the first direction (Y) and a plurality of first electrode strips (202) arranged at intervals in the first direction (Y), the first connecting strip (201) having a first side (201a) and a second side (201b) opposite to each other in a second direction (X), the plurality of first electrode strips (202) being located on a first side (201a) of the first connecting strip (201) and connected to the first connecting strip (201), and the ends of adjacent first electrode strips (202) away from the first connecting strip (201) are open; the second electrode portion (21) comprises a second connecting strip (211) extending in the first direction (Y) and a plurality of first electrode strips (212) arranged at intervals in the first direction (X) The invention relates to a plurality of second electrode strips (212) arranged at intervals on a first side (201a) and a second connecting strip (211), wherein the second connecting strip (211) is located at a position on the first side (201a) away from the second side (201b), the second connecting strip (211) has a third side (211a) and a fourth side (211b) opposite to each other in the second direction (X), and the third side (211a) is located at a position on the fourth side (211b) close to the first side (201a); the plurality of second electrode strips (212) are located on the third side (211a) of the second connecting strip (211) and connected to the second connecting strip (211), and the ends of adjacent second electrode strips (212) away from the second connecting strip (211) are in an opening shape; the two ends of the conductive connecting portion (22) are respectively connected to the first connecting strip (201) and the second connecting strip (211), and the design of the electrode structure can improve the light effect around the electrode structure, thereby improving the quality of the display panel when the electrode structure is used in the display panel.

Description

[0001] This application claims the priority of Chinese Patent Application No. 202110041652.X filed on January 13, 2021, the priority of PCT International Application No. PCT / CN2021 / 083044 filed on March 25, 2021, and the priority of PCT International Application No. PCT / CN2021 / 085622 filed on April 6, 2021. The contents disclosed in the above-mentioned Chinese patent application and PCT international application are hereby cited in their entirety as part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to the field of display technology, and in particular, to an electrode structure, a display panel, and an electronic device. Background Art

[0003] With the continuous development of liquid crystal display panels, high-resolution products are being developed continuously, but with the increase in pixels, a series of problems are likely to occur, such as bright spots, snowflakes and other uneven brightness problems when performing certain pressure tests or drop tests on liquid crystal display panels. In addition, the electrode structure in the liquid crystal display panel is easily affected by foreign particles (Partical) during the manufacturing process, which is very likely to cause adverse conditions such as broken wires, resulting in pixel failure, thereby reducing the yield of the liquid crystal display panel and affecting the reliability and product quality of the liquid crystal display panel. Summary of the invention

[0004] The embodiments of the present disclosure provide an electrode structure, a display panel, and an electronic device. The first electrode portion and the second electrode portion of the electrode structure are respectively designed to have a first gap and a second gap that are semi-open, so that liquid crystal molecule deflection can also occur at the openings of the first gap and the second gap, and the first gap and the second gap are in a semi-open state, which can also improve the light efficiency around the electrode structure, thereby at least to a certain extent overcoming one or more problems caused by the limitations and defects of the relevant technology.

[0005] At least one embodiment of the present disclosure provides a display panel, which includes an array substrate and an opposing substrate arranged in a box: the array substrate includes a first substrate and a scan line, a data line, a first blocking wall and a second blocking wall formed on a side of the first substrate close to the opposing substrate; the data line extends in a first direction, the scan line extends in a second direction, and the first direction intersects with the second direction; the first blocking wall and the second blocking wall are respectively located on opposite sides of the scan line in the first direction, and the first blocking wall and the second blocking wall both include a first blocking layer arranged in the same layer as the scan line and spaced from each other, and a second blocking layer arranged in the same layer as the data line and spaced from each other, and the orthographic projection of the second blocking layer on the first substrate is parallel to the scanning line. The orthographic projection of the first blocking layer on the first substrate overlaps; the spacing between the first blocking layer and the scanning line in the first direction is a first spacing, and the spacing between the second blocking layer and the scanning line in the first direction is a second spacing, and the second spacing is greater than the first spacing; the opposing substrate comprises a second substrate and a spacer located on a side of the second substrate close to the array substrate, the surface of the spacer close to the first substrate is the top surface, the orthographic projection of the top surface of the spacer on the first substrate is located within the orthographic projection of the scanning line on the first substrate, and is located between the orthographic projections of the first blocking wall and the second blocking wall on the first substrate; and the size of the top surface of the spacer in the first direction is greater than the first spacing.

[0006] For example, in the display panel provided by at least one embodiment of the present disclosure, a ratio between a size of a top surface of the spacer in the first direction and the first interval is greater than or equal to 2.

[0007] For example, in the display panel provided in at least one embodiment of the present disclosure, the distance between the second barrier layer and the spacer in the first direction is a third distance, and the ratio of the third distance to the size of the top surface of the spacer in the first direction is greater than or equal to 0.5.

[0008] For example, in the display panel provided by at least one embodiment of the present disclosure, a ratio of the third interval to a dimension of the top surface of the spacer in the first direction is greater than or equal to 1.

[0009] For example, in the display panel provided by at least one embodiment of the present disclosure, the ratio of the third interval to the dimension of the data line in the second direction is 2 to 4.

[0010] For example, in the display panel provided in at least one embodiment of the present disclosure, the orthographic projection of the second barrier layer on the first substrate is located within the orthographic projection of the first barrier layer on the first substrate, and the first direction is perpendicular to the second direction.

[0011] For example, in the display panel provided in at least one embodiment of the present disclosure, the array substrate also includes a first common line formed on the first substrate and extending in the second direction, the first common line and the scanning line are arranged in the same layer and spaced from each other; and the first blocking layer of the second blocking wall is a partial structure of the first common line.

[0012] For example, in the display panel provided in at least one embodiment of the present disclosure, the array substrate also includes a plurality of sub-pixel units, which are arranged in an array on the first substrate along the second direction and the first direction; each of the sub-pixel units includes a pixel electrode, a common electrode and a transistor: the transistor includes a gate, a first electrode and a second electrode, the gate is connected to the scan line, the first electrode is connected to the pixel electrode, and the second electrode is connected to the data line; the orthographic projection of the common electrode on the first substrate overlaps with the orthographic projection of the pixel electrode on the first substrate, and the common electrode is connected to the first common line.

[0013] For example, in the display panel provided by at least one embodiment of the present disclosure, the pixel electrode is located on a side of the common electrode away from the first substrate, and the pixel electrode includes: a first electrode portion, including a first connecting bar extending in the first direction and a plurality of first electrode bars arranged at intervals in the first direction, the first connecting bar having a first side and a second side opposite to each other in the second direction, the plurality of first electrode bars being located on a first side of the first connecting bar and connected to the first connecting bar, and ends of adjacent first electrode bars away from the first connecting bar are open;

[0014] A second electrode portion is arranged at intervals with the first electrode portion in the first direction, the second electrode portion includes a second connecting strip extending in the first direction and a plurality of second electrode strips arranged at intervals in the first direction, the second connecting strip is located at a position on the first side away from the second side, the second connecting strip has a third side and a fourth side opposite to each other in the second direction, the third side is located at a position on the fourth side close to the first side; the plurality of second electrode strips are located on the third side of the second connecting strip and connected to the second connecting strip, and an opening is formed between the ends of adjacent second electrode strips away from the second connecting strip; a conductive connecting portion is located between the first electrode portion and the second electrode portion, the two ends of the conductive connecting portion are respectively connected to the first connecting strip and the second connecting strip; and the area of ​​the conductive connecting portion is larger than the area of ​​the first electrode strip and the area of ​​the second electrode strip.

[0015] For example, in the display panel provided in at least one embodiment of the present disclosure, the conductive connection portion includes a first conductive connection strip and a second conductive connection strip arranged at intervals in the second direction and both extending in the first direction, and at least two third conductive connection strips located between the first conductive connection strip and the second conductive connection strip and arranged at intervals in the first direction, and both ends of each of the third conductive connection strips are respectively connected to the first conductive connection strip and the second conductive connection strip; wherein the first conductive connection strip is connected to the first connection strip, and the second conductive connection strip is connected to the second connection strip.

[0016] For example, in the display panel provided by at least one embodiment of the present disclosure, the first electrode strip, the second electrode strip and the third conductive connection strip all extend in a third direction, and the first widths of the first electrode strip, the second electrode strip and the third conductive connection strip are equal; wherein the first width is the dimension in a fourth direction, the third direction is perpendicular to the fourth direction, and the third direction intersects with the first direction and the second direction.

[0017] For example, in the display panel provided in at least one embodiment of the present disclosure, the array substrate also includes: a second common line arranged in the same layer as the data line and spaced apart from each other, the second common line extends in the first direction, and the two ends of the second common line are respectively connected to the common electrodes of two adjacent sub-pixel units in the first direction through a first via structure.

[0018] For example, in the display panel provided in at least one embodiment of the present disclosure, the first via structure includes a first via portion, a second via portion and a via connecting portion, the via connecting portion and the pixel electrode are arranged in the same layer and spaced apart from each other, the via connecting portion is connected to the second common line through the first via portion, and the via connecting portion is connected to the common electrode through the second via portion.

[0019] At least one embodiment of the present disclosure further provides an electronic device, which includes the display panel in any of the above embodiments.

[0020] At least one embodiment of the present disclosure further provides an electrode structure, which includes a first electrode portion and a second electrode portion arranged at intervals in a first direction, and a conductive connecting portion located between the first electrode portion and the second electrode portion: the first electrode portion includes a first connecting strip extending in the first direction and a plurality of first electrode strips arranged at intervals in the first direction, the first connecting strip having a first side and a second side opposite to each other in a second direction, the plurality of first electrode strips being located on the first side of the first connecting strip and connected to the first connecting strip, and an opening is formed between ends of adjacent first electrode strips away from the first connecting strip; the second electrode portion includes a second connecting strip extending in the first direction and a plurality of second electrode strips arranged at intervals in the first direction, the second connecting strip being located at a position on the first side away from the second side, the second connecting strip having a third side and a fourth side opposite to each other in the second direction, the third side being located at a position on the fourth side close to the first side; the plurality of second electrode strips being located on the third side of the second connecting strip and connected to the second connecting strip, and an opening is formed between ends of adjacent second electrode strips away from the second connecting strip; the two ends of the conductive connecting portion are respectively connected to the first connecting strip and the second connecting strip.

[0021] For example, in the electrode structure provided in at least one embodiment of the present disclosure, the area of ​​the conductive connection portion is larger than the area of ​​the first electrode strip, and larger than the area of ​​the second electrode strip.

[0022] For example, in the electrode structure provided in at least one embodiment of the present disclosure, the area of ​​the first electrode portion and the area of ​​the second electrode portion are both larger than the area of ​​the conductive connection portion.

[0023] For example, in the electrode structure provided in at least one embodiment of the present disclosure, the conductive connection portion includes a first conductive connection strip and a second conductive connection strip arranged at intervals in the second direction and both extending in the first direction, and at least two third conductive connection strips located between the first conductive connection strip and the second conductive connection strip and arranged at intervals in the first direction, and both ends of each of the third conductive connection strips are respectively connected to the first conductive connection strip and the second conductive connection strip; the first conductive connection strip is connected to the first connection strip, and the second conductive connection strip is connected to the second connection strip.

[0024] For example, in the electrode structure provided in at least one embodiment of the present disclosure, the first electrode strip, the second electrode strip and the third conductive connection strip all extend in a third direction, and the first widths of the first electrode strip, the second electrode strip and the third conductive connection strip in a fourth direction are equal; the third direction is perpendicular to the fourth direction, and the third direction intersects with the first direction and the second direction.

[0025] For example, in the electrode structure provided in at least one embodiment of the present disclosure, ends of adjacent first electrode strips away from the first connecting strip are not connected to each other; ends of adjacent second electrode strips away from the second connecting strip are not connected to each other.

[0026] For example, in the electrode structure provided in at least one embodiment of the present disclosure, a first gap is provided between adjacent first electrode strips, the first electrode strip and the first gap extend in the same direction, and the first gap is semi-open; a second gap is provided between adjacent second electrode strips, the second electrode strip and the second gap extend in the same direction, and the second gap is semi-open; the opening directions of the first gap and the second gap are opposite.

[0027] For example, in the electrode structure provided in at least one embodiment of the present disclosure, the first widths of the first electrode strip and the second electrode strip in the fourth direction are equal, and the first widths of the first gap and the second gap in the fourth direction are equal.

[0028] For example, in the electrode structure provided by at least one embodiment of the present disclosure, the first width of the first gap in the fourth direction is 1 to 4 times the first width of the first electrode strip in the fourth direction.

[0029] For example, in the electrode structure provided in at least one embodiment of the present disclosure, the first width of the first electrode strip in the fourth direction and the first width of the second electrode strip in the fourth direction are both 1.8 μm to 3 μm; the first width of the first gap in the fourth direction and the first width of the second gap in the fourth direction are both 3 μm to 7 μm.

[0030] For example, in the electrode structure provided in at least one embodiment of the present disclosure, there is a third gap between adjacent third conductive connecting strips, and the third gap is closed on all sides.

[0031] For example, in the electrode structure provided in at least one embodiment of the present disclosure, the conductive connection portion includes a plurality of the third gaps.

[0032] For example, in the electrode structure provided in at least one embodiment of the present disclosure, the first width of the third conductive connecting strip in the fourth direction is equal to the first width of the first electrode strip in the fourth direction, and the first widths of the third gap, the first gap and the second gap in the fourth direction are equal.

[0033] For example, in the electrode structure provided in at least one embodiment of the present disclosure, there is a fourth gap between the third conductive connection strip and the first electrode strip adjacent thereto, and there is a fifth gap between the third conductive connection strip and the second electrode strip adjacent thereto, and the first widths of the first gap, the second gap, the third gap, the fourth gap and the fifth gap in the fourth direction are equal.

[0034] For example, in the electrode structure provided in at least one embodiment of the present disclosure, the first width of the first electrode strip in the fourth direction and the first width of the second electrode strip in the fourth direction are smaller than the first width of the entire conductive connection portion in the fourth direction.

[0035] For example, in the electrode structure provided in at least one embodiment of the present disclosure, the second width of the first connecting strip in the second direction is equal to the second width of the second connecting strip in the second direction; the second width of the first connecting strip and the second connecting strip in the second direction is greater than or equal to the first width of the first electrode strip and the second electrode strip in the fourth direction.

[0036] For example, in the electrode structure provided in at least one embodiment of the present disclosure, the length of the first conductive connecting strip in the first direction and the length of the second conductive connecting strip in the first direction are both smaller than the length of the first connecting strip in the first direction, and smaller than the length of the second connecting strip in the first direction.

[0037] For example, in the electrode structure provided in at least one embodiment of the present disclosure, the length of the first connecting bar in the first direction is smaller than the length of the second connecting bar in the first direction.

[0038] For example, in the electrode structure provided in at least one embodiment of the present disclosure, a ratio of a length of the first connecting bar in the first direction to a length of the second connecting bar in the first direction is 0.1 to 0.9.

[0039] For example, in the electrode structure provided in at least one embodiment of the present disclosure, the first connecting strip, the conductive connecting portion and the second connecting strip are connected in a zigzag shape as a whole, one end of the first connecting strip is connected to one end of the conductive connecting portion, and the other end of the conductive connecting portion is connected to one end of the second connecting strip, and the first connecting strip and the second connecting strip are located on different sides of the conductive connecting portion in the second direction.

[0040] For example, in the electrode structure provided in at least one embodiment of the present disclosure, the second width of the first conductive connecting strip in the second direction is equal to the second width of the first connecting strip in the second direction, and the second width of the second conductive connecting strip in the second direction is equal to the second width of the second connecting strip in the second direction.

[0041] For example, in the electrode structure provided in at least one embodiment of the present disclosure, the conductive connection portion includes a conductive connection strip, and the conductive connection strip extends in a third direction, and the third direction intersects with the first direction and the second direction.

[0042] For example, in the electrode structure provided in at least one embodiment of the present disclosure, the third direction is perpendicular to the fourth direction, and the ratio of the first width of the conductive connection strip in the fourth direction to the first width of the first electrode strip in the fourth direction is 1.5 to 5.5.

[0043] For example, in the electrode structure provided in at least one embodiment of the present disclosure, the first width of the conductive connection strip in the fourth direction is 5 μm to 10 μm, and the first width of the first electrode strip in the fourth direction is 1.8 μm to 3 μm.

[0044] For example, in the electrode structure provided in at least one embodiment of the present disclosure, the second width of the first connecting strip in the second direction and the second width of the second connecting strip in the second direction are both 2.3 μm to 2.7 μm, the first width of the conductive connecting strip in the fourth direction is 2.5 μm to 3.0 μm, and the first width of the first electrode strip and the second electrode strip in the fourth direction are both 1.8 μm to 2.6 μm.

[0045] For example, in the electrode structure provided in at least one embodiment of the present disclosure, the second electrode portion further includes a signal connection portion, which is located on a side of the plurality of second electrode strips away from the conductive connection portion and connected to the second connection strips.

[0046] For example, in the electrode structure provided in at least one embodiment of the present disclosure, the first connecting strip and the second electrode strip are arranged in a mirror image with respect to the second direction.

[0047] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0048] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0050] Figure 1 is a schematic diagram of a planar structure of an electrode structure;

[0051] Figure 2 A schematic diagram of a planar structure of an electrode structure provided in one embodiment of the present disclosure;

[0052] Figure 3 A schematic diagram of a planar structure of another electrode structure provided in an embodiment of the present disclosure;

[0053] Figure 4 A schematic diagram of a partial cross-sectional structure of a display panel provided in one embodiment of the present disclosure;

[0054] Figure 5 A schematic diagram of a planar structure of a display panel provided in one embodiment of the present disclosure;

[0055] Figure 6 for Figure 5 An enlarged schematic diagram of the structure of part A shown in FIG.

[0056] Figure 7 for Figure 6 A schematic cross-sectional view of the structure along the CC direction; and

[0057] Figure 8 for Figure 5 Schematic diagram of the enlarged structure of the first via structure.

[0058] Figure 1 Reference numerals in the figures:

[0059] 10. Slit electrode; 11. Slit;

[0060] Figures 2 to 8 Reference numerals in the figures:

[0061] 20, first electrode portion; 201, first connecting bar; 201a, first side; 201b, second side; 202, first electrode bar; 21, second electrode portion; 211, second connecting bar; 211a, third side; 211b, fourth side; 212, second electrode bar; 213, signal connecting portion; 22, conductive connecting portion; 221, first conductive connecting bar; 222, second conductive connecting bar; 223, third conductive connecting bar;

[0062] 3. Array substrate; 30. First substrate; 301. Sub-pixel region; 302. First wiring region; 303. Second wiring region; 31. Scan line; 32. First common line; 33. Data line; 34. Pixel electrode; 35. Common electrode; 36. Transistor; 360. Active layer; 361. Gate; 362. First electrode; 363. Second electrode; 37. Second common line; 38a. First retaining wall; 38b. Second retaining wall; 381. First blocking layer; 382. Second blocking layer;

[0063] 4. Counter substrate; 40. Shielding layer; 41. Second substrate; 42. Spacer;

[0064] 5. Liquid crystal molecules. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0066] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. The words "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0067] Thin Film Transistor-Liquid Crystal Display (TFT-LCD) technology is a technology that cleverly combines microelectronics technology with liquid crystal display technology. Those skilled in the art use the technology of microelectronics fine processing on silicon substrate (Si) and then transplant it to large-area glass to process thin film transistor (TFT) arrays to form an array substrate, and then use the mature liquid crystal display (LCD) technology to align the array substrate with another substrate with a color filter layer (i.e., the opposing substrate) to form a liquid crystal box, and then go through subsequent processes, such as laminating polarizers, etc., to finally form a liquid crystal display panel.

[0068] It should be understood that the liquid crystal box also includes a spacer (Photo Spacer, abbreviated as: PS), the main function of which is to support the liquid crystal box so that the box thickness of each area of ​​the liquid crystal display panel remains consistent and the brightness of the display panel is uniform. However, for horizontal electric field deflection products such as Advanced Super Dimension Switch (ADS) or In-Plane Switching (IPS), when the display panel is subjected to external stress, the spacer will move. If the movement is large, the spacer may scratch the alignment film (i.e., PI film) on the slit electrode (electrode structure with a gap), causing the alignment of the liquid crystal in the area to fail, resulting in light leakage when the display panel is working, thereby forming irregular bright spots on a macro scale, which in turn affects the quality of the product.

[0069] For example, Figure 1 is a schematic diagram of a planar structure of an electrode structure, such as Figure 1 As shown, the electrode structure 10 of the liquid crystal display panel is designed to have a slit 11 opened inside, and the slit 11 is closed all around. However, the light efficiency around the slit electrode 10 is poor, so poor display is likely to occur.

[0070] The embodiments of the present disclosure provide an electrode structure, which is designed to have a first slit and a second slit in a semi-open state by respectively designing a first electrode portion and a second electrode portion, so that the liquid crystal molecules can also be deflected at the openings of the first slit and the second slit, and the first slit and the second slit are in a semi-open state, and the light efficiency around the electrode structure can be improved, thereby overcoming one or more problems caused by the limitations and defects of the related art at least to a certain extent, and the electrode structure can be used in a liquid crystal display panel, and can be used as a pixel electrode or a common electrode of the liquid crystal display panel. In one example, the material of the electrode structure is indium tin oxide, that is, the electrode structure can be an ITO (indium tin oxide) electrode, and the electrode structure has a light-transmitting property.

[0071] For example, Figure 2 A schematic diagram of a planar structure of an electrode structure provided in one embodiment of the present disclosure is shown in FIG. Figure 2As shown, the electrode structure includes a first electrode portion 20, a conductive connecting portion 22 and a second electrode portion 21 arranged in sequence in a first direction Y. The first electrode portion 20 may include a first connecting strip 201 extending in the first direction Y and a plurality of first electrode strips 202 arranged at intervals in the first direction Y. The first connecting strip 201 has a first side 201a and a second side 201b opposite to each other in the second direction X. The plurality of first electrode strips 202 are located on the first side 201a of the first connecting strip 201 and are connected to the first connecting strip 201. The ends of adjacent first electrode strips 202 that are away from the first connecting strip 201 are open, that is, the ends of adjacent first electrode strips 202 that are away from the first connecting strip 201 are not connected to each other.

[0072] It should be noted that the aforementioned plurality of first electrode strips 202 are arranged at intervals in the first direction Y, which means that there is a first gap S1 between adjacent first electrode strips 202 , and the first gap S1 is semi-open.

[0073] For example, Figure 2 As shown, the second electrode portion 21 includes a second connecting strip 211 extending in the first direction Y and a plurality of second electrode strips 212 arranged at intervals in the first direction Y, the second connecting strip 211 is located at a position on the first side 201a away from the second side 201b, the second connecting strip 211 has a third side 211a and a fourth side 211b opposite to each other in the second direction X, the third side 211a is located at a position on the fourth side 211b close to the first side 201a, it should be noted that the second direction X and the first direction Y are perpendicular to each other; the plurality of second electrode strips 212 are located on the third side 211a of the second connecting strip 211 and are connected to the second connecting strip 211, and the ends of adjacent second electrode strips 212 away from the second connecting strip 211 are open, that is, the ends of adjacent second electrode strips 212 away from the second connecting strip 211 are not connected to each other.

[0074] It should be noted that the aforementioned plurality of second electrode strips 212 are arranged at intervals in the first direction Y, which means that there is a second gap S2 between adjacent second electrode strips 212 , and the second gap S2 is semi-open.

[0075] For example, Figure 2 As shown, the conductive connection portion 22 is located between the first electrode portion 20 and the second electrode portion 21 , and two ends of the conductive connection portion 22 are respectively connected to the first connection bar 201 and the second connection bar 211 .

[0076] For example, in the embodiment of the present disclosure, the first electrode portion 20 and the second electrode portion 21 of the electrode structure are respectively designed to have a semi-open first slit S1 and a second slit S2, so that liquid crystal molecules can also be deflected at the openings of the first slit S1 and the second slit S2. Figure 1 The electrode structure shown is closed around the gap, which can improve the light effect around the electrode structure.

[0077] In addition, if Figure 2 As shown, one of the first slit S1 of the first electrode portion 20 and the second slit S2 of the second electrode portion 21 has an opening direction facing rightward, and the other has an opening direction facing leftward, that is, the opening directions of the first slit S1 of the first electrode portion 20 and the second slit S2 of the second electrode portion 21 are opposite, so that the electrode structure can be balanced on both sides of the second direction X (that is: Figure 2 The light effect on the left and right sides of the electrode structure is balanced to improve the display effect.

[0078] For instance, in one example, the orthographic projections of the first electrode portion 20, the second electrode portion 21 and the conductive connection portion 22 on the reference plane overlap with each other. The overlap mentioned here refers to complete overlap within the allowable error range. Such a design can reduce the difficulty of designing the electrode structure, thereby facilitating the arrangement of multiple electrode structures in the array substrate. However, the embodiments of the present disclosure are not limited to this. The orthographic projections of the first electrode portion 20, the second electrode portion 21 and the conductive connection portion 22 on the reference plane may not overlap, depending on the specific circumstances.

[0079] It should be noted that the reference plane mentioned in the embodiments of the present disclosure is a plane perpendicular to the first direction Y.

[0080] For example, in one example, the first electrode strips 202 and the second electrode strips 212 mentioned above can be parallel to each other, that is, the extension directions of the first electrode strips 202 and the second electrode strips 212 are parallel to each other to balance the light effects at the first electrode portion 20 and the second electrode portion 21. Specifically, the first electrode strips 202 and the second electrode strips 212 both extend in a third direction Q, and the third direction Q intersects with the first direction Y and the second direction X, that is, the third direction Q is not parallel to or colinear with the first direction Y and the second direction X. Such a design can reduce color deviation to improve the display effect of the display panel when the electrode structure is used in the display panel.

[0081] For example, in one example, the acute angle between the third direction Q and the second direction X may be 5° to 15°, such as 5°, 7°, 9°, 11°, 13°, 15°, etc., which is not limited in the embodiments of the present disclosure.

[0082] For example, in one example, the first width of the first electrode strip 202 may be equal to the first width of the second electrode strip 212. In addition, the first width of the first slit S1 may be equal to the first width of the second slit S2, so that the light effect at the first electrode portion 20 and the second electrode portion 21 can be further balanced to improve the display effect of the display panel when the electrode structure is used in the display panel.

[0083] It should be noted that the first width mentioned in the embodiment of the present disclosure refers to the dimension in the fourth direction P, and the fourth direction P and the third direction Q are perpendicular to each other.

[0084] For instance, in one example, in order to ensure that the liquid crystal molecules at the first electrode portion 20 and the second electrode portion 21 are well deflected so as to improve the light efficiency at the first electrode portion 20 and the second electrode portion 21, the first width of the first electrode strip 202 in the fourth direction P, the first width of the first slit S1 in the fourth direction P, the first width of the second electrode strip 212 in the fourth direction P, and the first width of the second slit S2 in the fourth direction P need to meet certain requirements, that is, the ratio of the first width of the first slit S1 in the fourth direction P to the first width of the first electrode strip 202 in the fourth direction P can be 1 to 4, for example: 1, 1.5, 2, 2.5, 3, 3.5, 4, etc., which is not limited to the embodiments of the present disclosure.

[0085] For example, in one example, the first width of the first electrode strip 202 and the second electrode strip 212 in the fourth direction P can be 1.8μm to 3μm, such as: 1.8μm, 2μm, 2.2μm, 2.4μm, 2.6μm, 2.8μm, 3μm, etc.; the first width of the first gap S1 and the second gap S2 in the fourth direction P can be 3μm to 7μm, such as: 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm, etc.

[0086] In addition, in order to further balance the light effect at the first electrode portion 20 and the second electrode portion 21, so as to improve the display effect of the display panel when the electrode structure is used in the display panel, the second width of the first connecting bar 201 in the second direction X and the second width of the second connecting bar 211 in the second direction X can be set to be equal. For example, the second width of the first connecting bar 201 and the second connecting bar 211 in the second direction X can be equal to the first width of the first electrode bar 202 and the second electrode bar 212 in the fourth direction P, but the embodiments of the present disclosure are not limited thereto, and the second width of the first connecting bar 201 and the second connecting bar 211 in the second direction X can also be slightly larger than the first width of the first electrode bar 202 and the second electrode bar 212 in the fourth direction P, so as to improve the light effect and improve the problem that the first connecting bar 201 and the second connecting bar 211 are easy to break due to the first width of the first connecting bar 201 and the second connecting bar 211 in the fourth direction P being too small, thereby improving the yield of the finally formed display panel.

[0087] It should be noted that the second width mentioned in the embodiment of the present disclosure is the dimension in the second direction X.

[0088] For example, the first electrode portion 20 and the second electrode portion 21 of the aforementioned electrode structure are connected by a conductive connection portion 22. In order to avoid the conductive connection portion 22 being affected by impurity particles (Partical) and causing disconnection during the manufacturing process, the area of ​​the conductive connection portion 22 is designed to be larger in the embodiment of the present disclosure to avoid the problem of disconnection that easily causes pixel failure. For example, in one example, the area of ​​the conductive connection portion 22 is larger than the area of ​​the first electrode strip 202, and larger than the area of ​​the second electrode strip 212.

[0089] It should be understood that the conductive connection portion 22 as a whole may also extend in the third direction Q to reduce the difficulty of processing design. For example, when the orthographic projection of the conductive connection portion 22 on the reference plane coincides with the orthographic projection of the first electrode portion 20 and the second electrode portion 21 on the reference plane, in order to make the area of ​​the conductive connection portion 22 larger than the area of ​​the first electrode strip 202 and the second electrode strip 212, in one example, the first width of the first electrode strip 202 in the fourth direction P and the first width of the second electrode strip 212 in the fourth direction P may be smaller than the first width of the conductive connection portion 22 as a whole in the fourth direction P.

[0090] For example, in one example, Figure 2As shown, the conductive connection portion 22 may be a conductive connection strip 22a, which extends in the third direction Q, wherein the ratio of the first width of the conductive connection strip 22a in the fourth direction P to the first width of the first electrode strip 202 in the fourth direction P may be 1.5 to 5.5, that is, the conductive connection portion 22 is widened compared to the first electrode strip 202 to improve the situation where the conductive connection portion 22 is easily broken, thereby ensuring the quality of the display panel finally formed.

[0091] For example, in one example, when the conductive connection portion 22 is only a conductive connection strip 22a, the first width of the conductive connection strip 22a in the fourth direction P can be 5μm to 10μm, for example: 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, etc.

[0092] For example, in one example, the second width of the first connecting strip 201 in the second direction X and the second width of the second connecting strip 211 in the second direction X are both 2.3 μm to 2.7 μm, the first width of the conductive connecting strip 22a in the fourth direction P is 2.5 μm to 3.0 μm, and the first width of the first electrode strip 202 and the second electrode strip 212 in the fourth direction P are both 1.8 μm to 2.6 μm.

[0093] For example, in one example, the first connecting bar 201 and the second electrode bar 212 are arranged in a mirror image with respect to the second direction X, which can simplify the process of preparing the electrode structure.

[0094] For example, Figure 3 A schematic diagram of a planar structure of another electrode structure provided in an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the conductive connection portion 22 may include a first conductive connection strip 221, a second conductive connection strip 222 and at least two third conductive connection strips 223, wherein the first conductive connection strip 221 and the second conductive connection strip 222 both extend in the first direction Y, and the first conductive connection strip 221 and the second conductive connection strip 222 are arranged at intervals in the second direction X, the first conductive connection strip 221 is connected to the first connection strip 201, and the second conductive connection strip 222 is connected to the second connection strip 211; at least two third conductive connection strips 223 are arranged at intervals in the first direction Y, and are located between the first conductive connection strip 221 and the second conductive connection strip 222, and both ends of each third conductive connection strip 223 (i.e., both ends in the extension direction thereof) are respectively connected to the first conductive connection strip 221 and the second conductive connection strip 222, that is, a third gap S3 is provided between adjacent third conductive connection strips 223, and the third gap S3 is closed all around. For example, the number of the third slits S3 included in the conductive connection portion 22 is not limited, and the conductive connection portion 22 may further include a plurality of third slits S3.

[0095] For example, Figure 3 As shown, by designing a slit (i.e., the third slit S3) inside the conductive connection portion 22, on the one hand, the light efficiency loss above the conductive connection portion 22 can be reduced, thereby improving the overall light efficiency of the electrode structure, and on the other hand, the first electrode portion 20 and the second electrode portion 21 can be connected and conducted through at least two wires (i.e., the third conductive connection strip 223). In this way, even if impurity particles cause one of the wires to be disconnected, there are still other wires connected to conduct the first electrode portion 20 and the second electrode portion 21, thereby greatly reducing the incidence of pixel failure, that is, the yield of the subsequent display panel formation can be improved.

[0096] For example, in one example, the third conductive connection strip 223 is arranged as two strips. While ensuring the stable connection and conduction between the first electrode portion 20 and the second electrode portion 21, the proportion of the conductive connection portion 22 in the electrode structure can be appropriately reduced, that is, more design space can be provided for the first electrode portion 20 and the second electrode portion 21. In other words, the areas of the first electrode portion 20 and the second electrode portion 21 can be larger than the area of ​​the conductive connection portion 22. Since the first gap S1 in the first electrode portion 20 and the second gap S2 in the second electrode portion 21 are both semi-open designs, and the third gap S3 in the conductive connection portion 22 is a closed design, the light efficiency at the first electrode portion 20 and the second electrode portion 21 is better than the light efficiency at the conductive connection portion 22. In this way, by making the areas of the first electrode portion 20 and the second electrode portion 21 larger than the area of ​​the conductive connection portion 22, the overall light efficiency of the electrode structure can be improved, thereby improving the quality of the display panel when the electrode structure is used in the display panel. In addition, since the third gap S3 is opened in the conductive connection part 22, the situation where foreign particles adhere to the conductive connection part 22 during the process of manufacturing the electrode structure can be alleviated, thereby alleviating the situation where the resistance of the conductive connection part 22 increases due to the adhesion of foreign particles, and then alleviating the impact on the driving of the pixel.

[0097] However, it should be understood that the third conductive connection strips 223 are not limited to being set to two, but may also be set to three or four, etc., depending on the specific situation, and the embodiments of the present disclosure are not limited to this.

[0098] For example, in order to further reduce the proportion of the conductive connection portion 22 in the electrode structure, the length of the first conductive connection strip 221 and the length of the second conductive connection strip 222 can be smaller than the length of the first connection strip 201 and smaller than the length of the second connection strip 211. It should be understood that the length mentioned here is the dimension in the first direction Y.

[0099] For example, in one example, the length of the first connecting bar 201 in the first direction Y is smaller than the length of the second connecting bar 211 in the first direction Y.

[0100] For example, in one example, the ratio of the length of the first connecting bar 201 in the first direction Y to the length of the second connecting bar 211 in the first direction Y is 0.1-0.9, for example, the ratio is 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8 or 0.9.

[0101] For example, Figure 2 and Figure 3 As shown, the first connecting strip 201, the conductive connecting portion 22 and the second connecting strip 211 are connected in a zigzag shape as a whole, one end of the first connecting strip 201 is connected to one end of the conductive connecting portion 22, the other end of the conductive connecting portion 22 is connected to one end of the second connecting strip 211, and the first connecting strip 201 and the second connecting strip 211 are located on different sides of the conductive connecting portion 22 in the second direction X.

[0102] For example, the second width of the first conductive connection strip 221 in the second direction X may be equal to the second width of the first connection strip 201 in the second direction X, and the second width of the second conductive connection strip 222 in the second direction X may be equal to the second width of the second connection strip 211 in the second direction X.

[0103] For example, Figure 3 As shown, the third conductive connection strip 223 may also extend in the third direction Q. The first width of the third conductive connection strip 223 in the fourth direction P may be equal to the first width of the first electrode strip 202 in the fourth direction P. In addition, the first width of the third gap S3 between adjacent third conductive connection strips 223 in the fourth direction P may be equal to the first width of the first gap S1 between adjacent first electrode strips 202 in the fourth direction P and the first width of the second gap S2 between adjacent second electrode strips 212 in the fourth direction P, so that the light effect at the conductive connection portion 22 and the first electrode portion 20 and the second electrode portion 21 can be balanced, so as to improve the display effect of the display panel when the electrode structure is used in the display panel.

[0104] Furthermore, a fourth gap S4 is provided between the third conductive connection strip 223 and the first electrode strip 202 adjacent thereto, and a fifth gap S5 is provided between the third conductive connection strip 223 and the second electrode strip 212 adjacent thereto. The first widths of the fourth gap S4 and the fifth gap S5 in the fourth direction (P) are equal to those of the first gap S1, the second gap S2 and the third gap S3 mentioned above, so as to balance the light effects at the conductive connection portion 22, the first electrode portion 20, the second electrode portion 21 and between the three, thereby improving the display effect of the display panel when the electrode structure is used in the display panel.

[0105] In one embodiment of the present disclosure, Figure 2 and Figure 3 As shown, the second electrode portion 21 may further include a signal connection portion 213, which may be located on a side of the plurality of second electrode strips 212 away from the conductive connection portion 22 and connected to the second connection strip 211. For example, when the electrode structure in the embodiment of the present disclosure is a common electrode, the signal connection portion 213 may be connected to a common line in the array substrate, that is, the signal connection portion 213 may be used to receive a common signal, but the embodiment of the present disclosure is not limited thereto. When the electrode structure in the embodiment of the present disclosure is a pixel electrode, the signal connection portion 213 may also be connected to a source-drain electrode of a transistor in the array substrate, and the signal connection portion 213 is used to receive a signal transmitted from the source-drain electrode, such as a data signal.

[0106] It should be noted that Figure 2 and Figure 3 The dotted line has no practical meaning and is only used to distinguish the aforementioned structures to facilitate understanding of the positional relationship between the aforementioned structures.

[0107] In addition, it should be understood that the shape of the signal connection portion 213 is not limited to Figure 2 and Figure 3 The shape shown may also be other shapes, depending on the specific situation, and the embodiments of the present disclosure do not limit this. It should also be noted that the electrode structure mentioned in the embodiments of the present disclosure is an integrated structure.

[0108] The present disclosure also provides a display panel, which may be a liquid crystal display panel. Figure 4 A partial cross-sectional structure diagram of a display panel provided in one embodiment of the present disclosure is shown in FIG. Figure 4 As shown, the display panel may include an array substrate 3 and an opposing substrate 4 which are arranged in a cell-to-cell manner, and may also include liquid crystal molecules 5 located between the opposing substrate 4 and the array substrate 3 .

[0109] The following is combined with Figures 2 to 8 The display panel of the embodiment of the present disclosure is described in detail.

[0110] Combination Figures 5 to 7 As shown, the array substrate 3 may include a first substrate 30 and a plurality of sub-pixel units, a plurality of rows of scan lines 31 , a plurality of rows of first common lines 32 , and a plurality of columns of data lines 33 formed on the first substrate 30 .

[0111] For example, Figure 5 A schematic diagram of a planar structure of a display panel provided in an embodiment of the present disclosure is shown in FIG. Figure 5As shown, the first substrate 30 may have a plurality of sub-pixel regions 301 arranged in an array along a row direction X (second direction) and a column direction Y (first direction), a first wiring region 302 located between two adjacent rows of sub-pixel regions 301, and a second wiring region 303 located between two adjacent columns, and there is an overlap between the first wiring region 302 and the second wiring region 303.

[0112] like Figure 5 As shown, a plurality of sub-pixel units are formed on a first substrate 30, and each sub-pixel unit includes a pixel electrode 34 at least partially located in a sub-pixel region 301, a common electrode 35, and a transistor 36 at least partially located in a first wiring region 302. In addition, the sub-pixel unit may also include a storage capacitor (not shown in the figure).

[0113] For example, Figure 6 for Figure 5 The enlarged structural diagram of part A shown in FIG. Figure 5 and Figure 6 As shown, the transistor 36 may include an active layer 360, a gate 361, and a first electrode 362 and a second electrode 363 disposed in the same layer, wherein an insulating layer may be disposed between the gate 361 and the active layer 360 to insulate the gate 361 from the active layer 360, and the insulating layer may be made of an inorganic material, such as silicon oxide, silicon nitride, and other inorganic materials. It should be noted that the gate 361 may be disposed in the same layer as the scan line 31, and the gate 361 may be a part of the scan line 31 mentioned above.

[0114] For example, the transistor 36 may be a top-gate thin film transistor or a bottom-gate thin film transistor. In the embodiment of the present disclosure, the transistor 36 is mainly described as a bottom-gate thin film transistor. When the transistor 36 is a bottom-gate thin film transistor, the gate 361 is formed on the first substrate 30. The material of the gate 361 may include a metal material or an alloy material, for example, molybdenum, aluminum and titanium, etc., to ensure its good conductivity. An insulating layer is formed on the first substrate 30 and covers the gate 361. The insulating layer may be made of an inorganic material, for example, silicon oxide, silicon nitride and other inorganic materials. The active layer 360 is formed on the side of the insulating layer away from the first substrate 30. The first pole 362 and the second pole 363 are respectively connected to the two doped regions of the active layer 360. The material of the first pole 362 and the second pole 363 may include a metal material or an alloy material, for example, a metal single layer or multilayer structure formed by molybdenum, aluminum and titanium, etc. For example, the multilayer structure is a multi-metal layer stack, such as a titanium, aluminum, titanium three-layer metal stack (Al / Ti / Al), etc.

[0115] It should be understood that the number of transistors 36 in the sub-pixel unit can be set to be multiple, and the transistors 36 are also divided into N-type transistors and P-type transistors, etc.

[0116] For example, combined with Figure 5 and Figure 6 As shown, the pixel electrode 34 can be connected to the first electrode 362, wherein the first electrode 362 of the transistor 36 can be a drain electrode, and the second electrode 363 can be a source electrode, but the embodiments of the present disclosure are not limited to this. The first electrode 362 of the transistor 36 can also be a source electrode, and the second electrode 363 can be a drain electrode, depending on the specific situation, and the positive projection of the common electrode 35 on the first substrate 30 can overlap with the positive projection of the pixel electrode 34 on the first substrate 30.

[0117] For example, at least one of the pixel electrode 34 and the common electrode 35 is an electrode structure described in any of the above embodiments, so that the light efficiency around the pixel can be improved, and the quality of the display panel can be improved when the electrode structure is used in the display panel. It should be noted that the row direction X mentioned in the embodiments of the present disclosure can be the second direction X mentioned above, and the column direction Y can be the first direction Y mentioned above.

[0118] For example, Figure 7 for Figure 6 The cross-sectional structure diagram along the CC direction is as follows: Figure 7 As shown, the first substrate 30 can be a single-layer structure, and the first substrate 30 can be a glass substrate, but the embodiments of the present disclosure are not limited thereto. The first substrate 30 can also be a multi-layer structure, and the material of the first substrate 30 is not limited to glass, but can also be other materials, such as polyimide (PI) and other materials, depending on the specific circumstances.

[0119] In the embodiments of the present disclosure, Figure 7 As shown, the pixel electrode 34 can be located on a side of the common electrode 35 away from the first substrate 30, that is, the common electrode 35 can be formed on the first substrate 30 before the pixel electrode 34. For example, the common electrode 35 can be a plate-shaped electrode, that is, the common electrode 35 is a whole piece without a slit, and the pixel electrode 34 can be an electrode structure described in any of the above embodiments. By generating an electric field between the pixel electrode 34 and the common electrode 35, all liquid crystal molecules between the electrodes and directly above the electrodes are deflected, thereby improving the working efficiency of the liquid crystal and increasing the light transmission efficiency.

[0120] It should be understood that in the embodiments of the present disclosure, the positional relationship between the pixel electrode 34 and the common electrode 35 is not limited to the relationship mentioned above. For example, the pixel electrode 34 may be located on the side of the common electrode 35 close to the first substrate 30, and the common electrode 35 may be the electrode structure described in any of the aforementioned embodiments, while the pixel electrode 34 may be a plate-shaped electrode.

[0121] In the embodiment of the present disclosure, in order to ensure the transmittance of the array substrate, the pixel electrode 34 can be made of indium tin oxide (ITO) material, but the embodiment of the present disclosure is not limited to this, and can also be made of transparent materials such as indium zinc oxide (IZO) and zinc oxide (ZnO). That is to say, since the material used for the pixel electrode 34 is different from the material of the gate 361, the first electrode 362 and the second electrode 363 of the transistor 36, the pixel electrode 34 and the gate 361, the first electrode 362 and the second electrode 363 of the transistor 36 can be made using different composition processes.

[0122] For example, Figure 7 As shown, the common electrode 35 can be located on the side of the first electrode 362 and the second electrode 363 of the transistor 36 close to the first substrate 30. The common electrode 35 can be formed on the first substrate 30 before the gate 361 of the transistor 36 is formed. That is, when manufacturing the array substrate, the common electrode 35 can be formed on the first substrate 30 by a patterning process, and then the gate 361 of the transistor 36 can be formed on the first substrate 30 by another patterning process. It should be noted that although the common electrode 35 and the gate 361 are both formed on the first substrate 30, the common electrode 35 and the gate 361 are disconnected from each other (i.e., there is no connection). It should be understood that the common electrode 35 can also be formed on the first substrate 30 after the gate 361 of the transistor 36 is formed, and the common electrode 35 can also be located on the side of the gate 361 away from the first substrate 30, depending on the specific situation.

[0123] Similarly, in order to ensure the transmittance of the array substrate, the pixel electrode 34 can also be made of a transparent conductive material such as ITO. The pixel electrode 34 can be formed on the side of the first electrode 362 and the second electrode 363 of the transistor 36 away from the first substrate 30. It should be understood that there is also an insulating layer between the pixel electrode 34 and the first electrode 362 and the second electrode 363 of the transistor 36. The pixel electrode 34 can be connected to the first electrode 362 of the transistor through the second via structure H2. Specifically, when the pixel electrode 34 is the electrode structure mentioned in the above embodiment, the pixel electrode 34 can be connected to the first electrode 362 of the transistor through the signal connection part 213 through the second via structure H2. It should be understood that this signal connection part 213 can be located in the first wiring area 302.

[0124] For example, when the pixel electrode 34 is the electrode structure mentioned in the above embodiment, the slit opening directions of the first electrode portion 20 in two adjacent pixel electrodes 34 in the first direction Y and the second direction X are opposite, and the slit openings of the second electrode portion 21 are opposite. In addition, it should be noted that the overall shapes of the electrode structures in the array substrate 3 may be slightly different, for example, some electrode structures need to be designed to avoid other structures in the array substrate 3, etc., but it should be understood that although the overall shapes of the electrode structures in the array substrate 3 may not be exactly the same, the overall design concept should be the same, that is, the first electrode portion 20 and the second electrode portion 21 are both semi-open slit designs, and the first width of the conductive connection portion 22 in the fourth direction P is greater than the first width of the first electrode strip 202 in the fourth direction P and the first width of the second electrode strip 212 in the fourth direction P.

[0125] For example, Figure 5 As shown, at least one row of scan lines 31 may be located in one first wiring area 302. In other words, at least one row of scan lines 31 may be provided in each first wiring area 302. It should be understood that the entire scan line 31 may be considered to extend in the row direction X. The scan line 31 is connected to the gate 361 of the transistor 36 in the sub-pixel unit. As mentioned above, the scan line 31 may be provided in the same layer as the gate 361 of the transistor 36 and may be an integrated structure. The scan line 31 is configured to provide a scan signal to the sub-pixel unit.

[0126] For example, Figure 5 As shown, at least one row of first common lines 32 may be located in a first wiring area 302. In other words, at least one row of first common lines 32 may be provided in each first wiring area 302. It should be understood that the first common lines 32 as a whole may be regarded as extending in the row direction X. The first common lines 32 may be connected to a common electrode 35, which is configured to provide a common signal to the sub-pixel unit.

[0127] For example, the first common line 32 can be set in the same layer as the scanning line 31, wherein the common electrode 35 mentioned above can be set on the first substrate 30 before the scanning line 31. Therefore, in order to connect the first common line 32 with the common electrode 35, the first common line 32 and the common electrode 35 can be overlapped together during the process of manufacturing the first common line 32.

[0128] For example, Figure 5As shown, a row of scan lines 31 and a row of first common lines 32 may be provided in each first wiring area 302. It should be understood that the scan lines 31 and the first common lines 32 are disconnected from each other, that is, the orthographic projection of the scan lines 31 on the first substrate 30 does not overlap with the orthographic projection of the first common lines 32 on the first substrate 30. It should be noted that the first wiring area 302 is not limited to having a row of scan lines 31 and a row of first common lines 32, and two rows of scan lines 31 may also be provided, or no first common lines 32 may be provided, etc., depending on the specific circumstances, and the embodiments of the present disclosure are not limited to this. The embodiments of the present disclosure are mainly described by assuming that a row of scan lines 31 and a row of first common lines 32 are provided in each first wiring area 302.

[0129] For example, Figure 5 As shown, at least one column of data lines 33 may be located in one second wiring area 303. In other words, at least one column of data lines 33 is disposed in each second wiring area 303. It should be understood that the entire data line 33 may be considered to extend in the column direction Y, and the orthographic projection of the data line 33 on the first substrate 30 overlaps with the orthographic projection of the scan line 31 and the first common line 32 on the first substrate 30. For example, the data line 33 may be connected to the second electrode 363 of the transistor 36 in the sub-pixel unit, which is configured to provide a data signal to the sub-pixel unit.

[0130] For example, the data line 33 in the embodiment of the present disclosure can be arranged in the same layer as the first electrode 362 and the second electrode 363 of the transistor 36 in the sub-pixel unit, that is, it can be manufactured using the same composition process to reduce the mask cost; however, the embodiment of the present disclosure is not limited to this, and can also be manufactured using different composition processes, depending on the specific circumstances.

[0131] For example, Figure 5 As shown, a column of data lines 33 may be disposed in each second wiring area 303, and the data lines 33 may be connected to the second electrodes 363 of each sub-pixel unit in the same column, that is, the data lines 33 may provide data signals for the sub-pixel units in the same column.

[0132] In the embodiment of the present disclosure, each column of data lines 33 may be symmetrically arranged about its central axis. It should be noted that the central axis mentioned here is a line passing through the center of the data line 33 and extending in the column direction Y.

[0133] For example, in a column of sub-pixel units, the first electrodes 362 of each sub-pixel unit and the data line 33 connected thereto are spaced equally in the row direction X, so as to ensure that the coupling capacitance between the transistor 36 and the data line 33 of each sub-pixel unit in each column is nearly consistent, thereby ensuring the uniformity of the light effect at each sub-pixel unit in each column. It should be noted that while the first electrodes 362 of each sub-pixel unit in a column of sub-pixel units and the data line 33 connected thereto are spaced equally in the row direction X, the overlapping area of ​​the first electrode 362 and the gate 361 of the column needs to be consistent with that of other columns.

[0134] For example, Figure 5 As shown, the array substrate may further include a second common line 37, which may be disposed in the same layer as the data line 33 and spaced from each other. The second common line 37 extends in the first direction Y, and the middle part of the orthographic projection of the second common line 37 on the first substrate 30 is located in the first wiring area 302, and both ends of the second common line 37 are respectively located in the sub-pixel area 301. In the embodiment of the present disclosure, both ends of the second common line 37 are connected to the common electrodes 35 of two adjacent sub-pixels in the first direction Y through the first via structure H1.

[0135] For example, Figure 8 for Figure 5 The enlarged structural diagram of the first via structure in FIG. Figure 8 As shown, the first via structure H1 includes a first via portion H11, a second via portion H12 and a via connection portion H13. The via connection portion H13 and the pixel electrode 34 are arranged in the same layer and are spaced apart from each other. The via connection portion H13 is connected to the second common line 37 through the first via portion H11, and the via connection portion H13 is connected to the common electrode 35 through the second via portion H12.

[0136] For example, Figures 5 to 7 As shown, the counter substrate 4 may further include a second substrate 41, a spacer 42 located on the side of the second substrate 41 close to the array substrate 3, and a shielding layer 40 located on the side of the spacer 42 close to the second substrate 41. The specific structure of the second substrate 41 can refer to the description of the first substrate 30, and will not be repeated here. The orthographic projection of the shielding layer 40 on the first substrate 30 can completely cover the first wiring area 302, the second wiring area 303 and at least part of the sub-pixel area 30, and the spacer 42 can be provided in plurality. The provision of the spacer 42 can improve the uniformity of the overall thickness of the display panel, and can improve the tolerance of the display panel to the fluctuation of the liquid crystal molecules, thereby improving the yield of the display panel.

[0137] For example, the multiple spacers 42 may include a main spacer and an auxiliary spacer. When the display panel is not subjected to external pressure, the end of the main spacer away from the second substrate 41 is in contact with the array substrate 3, and the main spacer mainly plays a supporting role. When the display panel is not subjected to external pressure, the end of the auxiliary spacer away from the second substrate 41 has a certain distance from the array substrate 1, that is, there is a step difference (height difference) between the main spacer and the auxiliary spacer. By adjusting the step difference between the main spacer and the auxiliary spacer, the thickness of the display panel can be fine-tuned.

[0138] Exemplarily, the height of the main spacer is greater than the height of the auxiliary spacer. When the display panel is subjected to external pressure, the main spacer first bears all the pressure and is compressed. When the main spacer is compressed to the point where the step difference between the main spacer and the auxiliary spacer drops to 0, the main spacer and the auxiliary spacer bear the external pressure together.

[0139] It should be noted that the main spacers and auxiliary spacers can be arranged in a certain period. The size and height of different types of spacers need to be monitored during the process. Because the size of the spacers is small and the main spacers are generally small, it is difficult for the equipment to accurately identify the position of the main spacers based on the size alone. Usually, a certain position around the main spacer is designed to be empty (that is, no spacers are set) to facilitate faster and more accurate identification of the main spacer position and monitoring. For example, when designing, no spacers are set under the main spacer. When monitoring, the position where no spacers are set can be quickly determined first, and then the aforementioned design rules can be used to clearly indicate that the spacer at the upper position where no spacers are set is the main spacer.

[0140] It should be noted that the surface of the spacer 42 in the embodiment of the present disclosure close to the first substrate 30 may be the top surface, and the surface away from the first substrate 30 may be the bottom surface. Figure 5 As shown, the orthographic projection of the top surface of the spacer 42 on the first substrate 30 is located within the orthographic projection of the scan line 31 on the first substrate 30, that is, the outer contour of the orthographic projection of the top surface of the spacer 42 on the first substrate 30 is located inside the outer contour of the orthographic projection of the scan line 31 on the first substrate 30, thereby ensuring the flatness of the support of the spacer 42, so as to ensure that the spacer 42 is stably supported on the array substrate 3. It should be noted that the orthographic projection of the spacer 42 on the first substrate 30 in the embodiment of the present disclosure does not overlap with the orthographic projection of the data line 33 and the transistor on the first substrate 30.

[0141] It should be understood that the orthographic projection of the top surface of the spacer 42 in the embodiment of the present disclosure on the first substrate 30 can be located within the orthographic projection of the bottom surface of the spacer 42 on the first substrate 30, that is, the entire spacer 42 can be similar to a cone, but the embodiments of the present disclosure are not limited to this. The orthographic projection of the top surface of the spacer 42 in the embodiment of the present disclosure on the first substrate 30 may also completely coincide with the orthographic projection of the bottom surface of the spacer 42 on the first substrate 30, depending on the specific circumstances.

[0142] In addition, it should be noted that the orthographic projection of the bottom surface of the spacer 42 on the first substrate 30 may be located within the orthographic projection of the scanning line 31 on the first substrate 30, but the embodiments of the present disclosure are not limited to this. The contour of the spacer 42 in the column direction Y may also exceed the contour of the scanning line 31 in the column direction Y.

[0143] For example, in order to prevent the spacer 42 from scratching the alignment film and causing red spots after being moved by external force, a retaining wall can be set around the spacer 42. Specifically, since the orthographic projection of the spacer 42 on the first substrate 30 is located within the orthographic projection of the scan line 31 on the first substrate 30, and the scan line 31 is covered by the shielding layer 40, even if the spacer 42 moves in the row direction X, it is still within the range covered by the shielding layer 40, and basically does not affect the display effect; based on this, it is not necessary to set retaining walls on the opposite sides of the spacer 42 in the row direction X to reduce the design difficulty.

[0144] In addition, if Figure 5 As shown, transistors are arranged on opposite sides of the spacer 42 in the row direction X, and the overall height of the area where the transistors are located in the array substrate 3 is greater than the overall height of the area where the spacer 42 is located. That is, this transistor can serve as a barrier to prevent the spacer 42 from sliding in the row direction X.

[0145] In order to prevent the spacer 42 from excessively sliding in the column direction Y due to external force, Figure 5 and Figure 6 As shown, a first retaining wall 38a and a second retaining wall 38b may be provided on the array substrate 3, and the first retaining wall 38a and the second retaining wall 38b are respectively located on opposite sides of the scanning line 31 in the column direction Y, wherein the orthographic projection of the spacer 42 on the first substrate 30 may be located between the orthographic projections of the first retaining wall 38a and the second retaining wall 38b on the first substrate 30; in other words, the first retaining wall 38a and the second retaining wall 38b may be provided on opposite sides of the spacer 42 in the column direction Y.

[0146] It should be noted that at least a portion of the first blocking wall 38 a and the second blocking wall 38 b may be located in the sub-pixel region 301 ; and the first blocking wall 38 a and the second blocking wall 38 b may be shielded by the shielding layer 40 .

[0147] For example, the first barrier wall 38a and the second barrier wall 38b each include a first barrier layer 381 disposed on the same layer as the scan line 31 and spaced apart from each other, and a second barrier layer 382 disposed on the same layer as the data line 33 and spaced apart from each other, and the orthographic projection of the second barrier layer 382 on the first substrate 30 overlaps with the orthographic projection of the first barrier layer 381 on the first substrate. Figures 5 to 7 As shown in the figure, the spacing between the first blocking layer 381 and the scanning line 31 in the first direction Y is a first spacing W1, and the spacing between the second blocking layer 382 and the scanning line 31 in the first direction Y is a second spacing W2, and the second spacing W2 is greater than the first spacing W1; that is, the first blocking layer 381 is protruded toward the direction close to the spacer 42 compared with the second blocking layer 382, ​​and the protruding portion can play a supporting role when the spacer moves under force, so as to alleviate the situation where the spacer 42 falls into the gap between the scanning line 31 and the first blocking layer 381 and cannot be restored to its original state. At the same time, the spacing between the second blocking layer 382 and the spacer 42 in the embodiment of the present disclosure is greater than that of the first blocking layer. The distance between the blocking layer 381 and the spacer 42 is relatively large. Compared with the scheme in which the distance between the second blocking layer 382 and the spacer 42 and the distance between the first blocking layer 381 and the spacer 42 are designed to be equal, when the spacer 42 is subjected to the same external stress, the tilting angle of the spacer 42 can be reduced. In this way, when the external stress on the spacer 42 is a force in the horizontal direction (for example, the first direction Y), the resistance in the vertical direction (that is, the thickness direction of the display panel) can be reduced. At this time, it is more difficult for the spacer 42 to cross the blocking wall and scratch the alignment film in the light-transmitting area (that is, the area in the sub-pixel area 301 not covered by the shielding layer 40), that is, the risk of scratching the alignment film is reduced. In addition, the vertical deformation of the display panel is reduced, and T-DNU (Touch-Dark Non-uniformity, the dark state unevenness of the panel after touching) is also improved.

[0148] It should be noted that the surface of the spacer 42 in the embodiment of the present disclosure close to the first substrate 30 can be a top surface, and the dimension W4 of the top surface of the spacer 42 in the first direction Y can be greater than the first spacing W1 to alleviate the situation where the spacer 42 falls into the gap between the scanning line 31 and the first blocking layer 381 during movement and cannot return to its original state.

[0149] For example, the ratio of the dimension W4 of the top surface of the spacer 42 in the first direction Y to the first spacing W1 is greater than or equal to 2, so as to further alleviate the situation where the spacer 42 falls into the gap between the scan line 31 and the first barrier layer 381 during movement and cannot be restored to its original state.

[0150] For example, the spacing between the second barrier layer 382 and the spacer 42 in the first direction Y is a third spacing W3, and the ratio of the third spacing W3 to the size of the top surface of the spacer 42 in the first direction Y is greater than or equal to 0.5. This design can reduce the risk of the spacer 42 crossing the barrier wall, thereby reducing the risk of scratching the alignment film in the light-transmitting area; further, the ratio of the third spacing W3 to the size W4 of the top surface of the spacer 42 in the first direction Y can be greater than or equal to 1.

[0151] For example, the ratio of the third spacing W3 to the size of the data line 33 in the second direction X is 2 to 4; wherein the size of the data line 33 in the second direction X may be 5μm to 7μm, such as 5μm, 5.5μm, 6μm, 6.5μm, 7μm, etc. At this time, the third spacing W3 may be 10μm to 28μm, such as 10μm, 13μm, 17μm, 21μm, 25μm, 28μm, etc.

[0152] It should be understood that the orthographic projection of the second barrier layer 382 mentioned above on the first substrate 30 is located within the orthographic projection of the first barrier layer 381 on the first substrate 30, so that the film layer (i.e., the second barrier layer 382) that mainly plays a blocking role in the first barrier wall 38a and the second barrier wall 38b can be ensured to have a sufficient width in the first direction Y to better prevent the spacer 42 from sliding in the first direction Y. In other words, Figure 7 As shown, the longitudinal section of the first retaining wall 38a and the second retaining wall 38b of the embodiment of the present disclosure may appear to be "L" shaped as a whole, where the longitudinal section refers to a surface parallel to the thickness direction of the display panel and the first direction Y.

[0153] It should be noted that the first barrier layer 381 of the second barrier wall 38b mentioned above may be a partial structure of the first common line 32. It should also be noted that the first spacing W1, the second spacing W2 between the second barrier wall 38b and the scanning line 31, and the third spacing W3 between the second barrier wall 38b and the spacer 42 may be equal to or different from the first spacing W1, the second spacing W2, and the third spacing W3 between the first barrier wall 38a and the scanning line 31, depending on the specific situation.

[0154] In the embodiment of the present disclosure, the aforementioned shielding layer 40 not only completely covers the first wiring area 302 and the second wiring area 303, but also covers part of the sub-pixel area 301, specifically, part of the common electrode 35 and part of the pixel electrode 34. There is a coupling electric field near the edge of the pixel electrode 34 near the scanning line 31 and the data line 33, which will cause the liquid crystal arrangement to be disordered during the display process, generate a failure area, and cause light leakage at the edge of the dark pixel, so the shielding layer 40 is required to shield this part of the failure area.

[0155] For example, there is a coupled electric field between the pixel electrode 34 and the scanning line 31, that is, there is a failure area in the portion of the pixel electrode 34 close to the scanning line 31. In order to shield this failure area, in the column direction Y, the shielding layer 40 can cover the edge of the pixel electrode 34 by at least 5μm. It should be noted that when the color filter layer is located on the opposing substrate, considering the accuracy of the upper and lower substrates, it needs to be widened more, but it must not exceed 10μm to avoid excessively affecting the pixel opening rate.

[0156] In addition, there is also a coupling electric field between the data line 33 and the edge of the pixel electrode 34, that is, there is a failure area in the portion of the pixel electrode 34 near the data line 33 in the embodiment of the present disclosure. For example, when the liquid crystal molecules 5 are negative liquid crystal molecules, the electric field will not cause the liquid crystal to rotate, and the shielding layer 40 can cover the edge of the pixel electrode 34 by about 1 μm to shield the shadow area near the data line 33; and if the liquid crystal molecules 5 are positive liquid crystal molecules, the coupling electric field between the data line 33 and the pixel electrode 34 will not cause obvious dark state light leakage, but will cause the crosstalk phenomenon caused by the liquid crystal molecules to be aggravated. At this time, the shielding layer 40 can cover the edge of the pixel electrode 34 by at least 6 μm to shield the coupling electric field area.

[0157] It should be noted that the color filter layer used in the liquid crystal display panel can be located on the counter substrate 4 or on the array substrate 3, depending on the specific situation.

[0158] Based on the above content, the liquid crystal display panel in the embodiments of the present disclosure can be used in display products with 4K resolution or 8K resolution.

[0159] An embodiment of the present disclosure further provides an electronic device, which includes the display panel described in any of the above embodiments.

[0160] According to the embodiments of the present disclosure, the specific type of the electronic device is not particularly limited, and any type of electronic device commonly used in the field can be used, such as liquid crystal display screens, mobile phones, laptop computers and other mobile devices, watches and other wearable devices, VR devices, etc. Those skilled in the art can make corresponding choices based on the specific purpose of the display device, which will not be repeated here.

[0161] It should be noted that in addition to the display panel, the electronic device also includes other necessary components and components. Taking the display as an example, it can also include a backlight module, a casing, a main circuit board, a power cord, etc. The technical field can make corresponding supplements according to the specific use requirements of the electronic device, which will not be repeated here.

[0162] It should be noted that the terms “on…”, “formed on…” and “disposed on…” mentioned herein may mean that one layer is directly formed or disposed on another layer, or may mean that one layer is indirectly formed or disposed on another layer, i.e., there are other layers between the two layers.

[0163] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.

[0164] In the present disclosure, unless otherwise specified, the term "same-layer arrangement" is used to mean that two layers, parts, components, elements or portions can be formed by the same patterning process, and the two layers, parts, components, elements or portions are generally formed of the same material.

[0165] In the present disclosure, unless otherwise specified, the expression "patterning process" generally includes steps such as photoresist coating, exposure, development, etching, photoresist stripping, etc. The expression "one-time patterning process" means a process of forming patterned layers, components, members, etc. using one mask.

[0166] There are a few points to note:

[0167] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0168] (2) In the absence of conflict, features in the same embodiment or in different embodiments of the present disclosure may be combined with each other.

[0169] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A display panel, comprising an array substrate (3) and a counter substrate (4) arranged in a box, wherein: The array substrate (3) comprises a first substrate (30) and a scan line (31), a data line (33), a first retaining wall (38a) and a second retaining wall (38b) formed on a side of the first substrate (30) close to the counter substrate (4); the data line (33) extends in a first direction (Y), the scan line (31) extends in a second direction (X), and the first direction (Y) intersects with the second direction (X); The first blocking wall (38a) and the second blocking wall (38b) are respectively located on opposite sides of the scan line (31) in the first direction (Y), and the first blocking wall (38a) and the second blocking wall (38b) both comprise a first blocking layer (381) arranged in the same layer as the scan line (31) and spaced apart from each other, and a second blocking layer (382) arranged in the same layer as the data line (33) and spaced apart from each other, the orthographic projection of the second blocking layer (382) on the first substrate (30) overlaps with the orthographic projection of the first blocking layer (381) on the first substrate (30); the spacing between the first blocking layer (381) and the scan line (31) in the first direction (Y) is a first spacing (W1), the spacing between the second blocking layer (382) and the scan line (31) in the first direction (Y) is a second spacing (W2), and the second spacing (W2) is greater than the first spacing (W1); The counter substrate (4) comprises a second substrate (41) and a spacer (42) located on a side of the second substrate (41) close to the array substrate (3); the surface of the spacer (42) close to the first substrate (30) is a top surface; the orthographic projection of the top surface of the spacer (42) on the first substrate (30) is located within the orthographic projection of the scan line (31) on the first substrate (30), and is located between the orthographic projections of the first retaining wall (38a) and the second retaining wall (38b) on the first substrate (30); and the size (W4) of the top surface of the spacer (42) in the first direction (Y) is greater than the first spacing (W1); The array substrate (3) further comprises a plurality of sub-pixel units arranged in an array on the first substrate (30) along the second direction (X) and the first direction (Y), each of the sub-pixel units comprising a pixel electrode (34), the pixel electrode (34) comprising: A first electrode portion (20), comprising a first connecting strip (201) extending in the first direction (Y) and a plurality of first electrode strips (202) arranged at intervals in the first direction (Y), the first connecting strip (201) having a first side (201a) and a second side (201b) opposite to each other in the second direction (X), the plurality of first electrode strips (202) being located on the first side (201a) of the first connecting strip (201) and connected to the first connecting strip (201), and an opening is formed between ends of adjacent first electrode strips (202) that are away from the first connecting strip (201); a second electrode portion (21) arranged at intervals with the first electrode portion (20) in the first direction (Y), the second electrode portion (21) comprising a second connecting strip (211) extending in the first direction (Y) and a plurality of second electrode strips (212) arranged at intervals in the first direction (Y), the second connecting strip (211) being located at a position on the first side (201a) away from the second side (201b), the second connecting strip (211) having a third side (211a) and a fourth side (211b) opposite to each other in the second direction (X), the third side (211a) being located at a position on the fourth side (211b) close to the first side (201a); the plurality of second electrode strips (212) being located on the third side (211a) of the second connecting strip (211) and connected to the second connecting strip (211), and an opening is formed between ends of adjacent second electrode strips (212) away from the second connecting strip (211); a conductive connection portion (22) located between the first electrode portion (20) and the second electrode portion (21), wherein two ends of the conductive connection portion (22) are respectively connected to the first connection bar (201) and the second connection bar (211); and an area of ​​the conductive connection portion (22) is larger than an area of ​​the first electrode bar (202) and an area of ​​the second electrode bar (212); The conductive connection portion (22) comprises a first conductive connection strip (221) and a second conductive connection strip (222) which are arranged at intervals in the second direction (X) and both extend in the first direction (Y), and at least two third conductive connection strips (223) which are located between the first conductive connection strip (221) and the second conductive connection strip (222) and are arranged at intervals in the first direction (Y), wherein two ends of each third conductive connection strip (223) are respectively connected to the first conductive connection strip (221) and the second conductive connection strip (222); wherein the first conductive connection strip (221) is connected to the first connection strip (201), and the second conductive connection strip (222) is connected to the second connection strip (211).

2. The display panel according to claim 1, wherein: The ratio between the size (W4) of the top surface of the spacer (42) in the first direction (Y) and the first distance (W1) is greater than or equal to 2.

3. The display panel according to claim 2, wherein: The distance between the second barrier layer (382) and the spacer (42) in the first direction (Y) is a third distance (W3), and the ratio between the third distance (W3) and the size (W4) of the top surface of the spacer (42) in the first direction (Y) is greater than or equal to 0.

5.

4. The display panel according to claim 3, wherein: The ratio between the third distance (W3) and the dimension (W4) of the top surface of the spacer (42) in the first direction (Y) is greater than or equal to 1.

5. The display panel according to claim 3, wherein: The ratio between the third spacing (W3) and the size of the data line (33) in the second direction (X) is 2 to 4.

6. The display panel according to any one of claims 1 to 5, wherein: The orthographic projection of the second barrier layer (382) on the first substrate (30) is located within the orthographic projection of the first barrier layer (381) on the first substrate (30), and the first direction (Y) is perpendicular to the second direction (X).

7. The display panel according to claim 6, wherein: The array substrate (3) further comprises a first common line (32) formed on the first substrate (30) and extending in the second direction (X), the first common line (32) and the scanning line (31) being arranged in the same layer and spaced apart from each other; and the first blocking layer (381) of the second blocking wall (38b) is a partial structure of the first common line (32).

8. The display panel according to claim 7, wherein: Each of the sub-pixel units further comprises a common electrode (35) and a transistor (36): the transistor (36) comprises a gate electrode (361), a first electrode (362) and a second electrode (363), the gate electrode (361) is connected to the scan line (31), the first electrode (362) is connected to the pixel electrode (34), and the second electrode (363) is connected to the data line (33); The orthographic projection of the common electrode (35) on the first substrate (30) overlaps with the orthographic projection of the pixel electrode (34) on the first substrate (30), and the common electrode (35) is connected to the first common line (32).

9. The display panel according to claim 1, wherein: The first electrode strip (202), the second electrode strip (212) and the third conductive connecting strip (223) all extend in a third direction (Q), and the first widths of the first electrode strip (202), the second electrode strip (212) and the third conductive connecting strip (223) are equal; The first width is a dimension in a fourth direction (P), the third direction (Q) is perpendicular to the fourth direction (P), and the third direction (Q) intersects with the first direction (Y) and the second direction (X).

10. The display panel according to claim 8, wherein: The array substrate (3) further comprises: a second common line (37) arranged in the same layer as the data line (33) and spaced apart from each other, the second common line (37) extending in the first direction (Y), and two ends of the second common line (37) respectively connected to the common electrodes (35) of two adjacent sub-pixel units in the first direction (Y) through a first via structure (H1).

11. The display panel according to claim 10, wherein: The first via hole structure (H1) comprises a first via hole portion (H11), a second via hole portion (H12) and a via hole connecting portion (H13); the via hole connecting portion (H13) and the pixel electrode (34) are arranged in the same layer and are spaced apart from each other; the via hole connecting portion (H13) is connected to the second common line (37) through the first via hole portion (H11); and the via hole connecting portion (H13) is connected to the common electrode (35) through the second via hole portion (H12).

12. The display panel according to claim 1, wherein: The area of ​​the conductive connection portion (22) is larger than the area of ​​the first electrode strip (202), and larger than the area of ​​the second electrode strip (212).

13. The display panel according to claim 1, wherein: The area of ​​the first electrode portion (20) and the area of ​​the second electrode portion (21) are both greater than the area of ​​the conductive connection portion (22).

14. The display panel according to claim 9, wherein: Ends of adjacent first electrode strips (202) that are away from the first connecting strip (201) are not connected to each other; and ends of adjacent second electrode strips (212) that are away from the second connecting strip (211) are not connected to each other.

15. The display panel according to claim 14, wherein: A first slit (S1) is provided between adjacent first electrode strips (202), the first electrode strips (202) and the first slit (S1) extend in the same direction, and the first slit (S1) is in a semi-open state; a second slit (S2) is provided between adjacent second electrode strips (212), the second electrode strips (212) and the second slit (S2) extend in the same direction, and the second slit (S2) is in a semi-open state; the first slit (S1) and the second slit (S2) have opposite opening directions.

16. The display panel according to claim 15, wherein: A first width of the first slit (S1) in the fourth direction (P) is equal to a first width of the second slit (S2) in the fourth direction (P).

17. The display panel according to claim 16, wherein: A first width of the first slit (S1) in the fourth direction (P) is 1 to 4 times the first width of the first electrode strip (202) in the fourth direction (P).

18. The display panel according to claim 17, wherein: The first width of the first electrode strip (202) in the fourth direction (P) and the first width of the second electrode strip (212) in the fourth direction (P) are both 1.8 μm to 3 μm; the first width of the first slit (S1) in the fourth direction (P) and the first width of the second slit (S2) in the fourth direction (P) are both 3 μm to 7 μm.

19. The display panel according to claim 15, wherein: A third gap (S3) is provided between adjacent third conductive connection strips (223), and the third gap (S3) is closed all around.

20. The display panel according to claim 19, wherein: The conductive connection portion (22) comprises a plurality of third slits (S3).

21. The display panel according to claim 19, wherein: The first widths of the third slit (S3), the first slit (S1), and the second slit (S2) in the fourth direction (P) are equal.

22. The display panel according to claim 21, wherein: A fourth gap (S4) is provided between the third conductive connecting strip (223) and the first electrode strip (202) adjacent thereto, and a fifth gap (S5) is provided between the third conductive connecting strip (223) and the second electrode strip (212) adjacent thereto, and the first gap (S1), the second gap (S2), the third gap (S3), the fourth gap (S4) and the fifth gap (S5) have the same first width in the fourth direction (P).

23. The display panel according to claim 9, wherein: The first width of the first electrode strip (202) in the fourth direction (P) and the first width of the second electrode strip (212) in the fourth direction (P) are smaller than the first width of the entire conductive connection portion (22) in the fourth direction (P).

24. The display panel according to claim 9, wherein: The second width of the first connecting strip (201) in the second direction (X) is equal to the second width of the second connecting strip (211) in the second direction (X); and the second width of the first connecting strip (201) and the second connecting strip (211) in the second direction (X) is greater than or equal to the first width of the first electrode strip (202) and the second electrode strip (212) in the fourth direction (P).

25. The display panel according to claim 9, wherein: The length of the first conductive connecting strip (221) in the first direction (Y) and the length of the second conductive connecting strip (222) in the first direction (Y) are both shorter than the length of the first connecting strip (201) in the first direction (Y), and shorter than the length of the second connecting strip (211) in the first direction (Y).

26. The display panel according to claim 25, wherein: The length of the first connecting bar (201) in the first direction (Y) is smaller than the length of the second connecting bar (211) in the first direction (Y).

27. The display panel according to claim 26, wherein: The ratio of the length of the first connecting bar (201) in the first direction (Y) to the length of the second connecting bar (211) in the first direction (Y) is 0.1-0.

9.

28. The display panel according to claim 1, wherein: The first connecting strip (201), the conductive connecting portion (22) and the second connecting strip (211) are connected in a zigzag shape as a whole; one end of the first connecting strip (201) is connected to one end of the conductive connecting portion (22), and the other end of the conductive connecting portion (22) is connected to one end of the second connecting strip (211); and the first connecting strip (201) and the second connecting strip (211) are located on different sides of the conductive connecting portion (22) in the second direction (X).

29. The display panel according to claim 1, wherein: The second width of the first conductive connecting strip (221) in the second direction (X) is equal to the second width of the first connecting strip (201) in the second direction (X), and the second width of the second conductive connecting strip (222) in the second direction (X) is equal to the second width of the second connecting strip (211) in the second direction (X).

30. The display panel according to claim 1, wherein: The second electrode portion (21) further comprises a signal connection portion (213), wherein the signal connection portion (213) is located on a side of the plurality of second electrode strips (212) away from the conductive connection portion (22) and is connected to the second connection strips (211).

31. An electronic device comprising the display panel according to any one of claims 1 to 30.

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