Sampling rate microcontroller system

Abstract

The present application provides a sampling rate micro-control system, comprising a frequency generating device, a control device, a frequency micro-control device and a sampling device. The frequency generating device outputs a sampling frequency signal. The control device outputs a control signal including an expected frequency range. The input end of the frequency micro-control device is respectively connected to the frequency generating device and the control device. The frequency micro-control device adjusts the sampling frequency signal to the expected frequency range and outputs a sampling frequency stabilization signal. The input end of the sampling device is connected to the frequency micro-control device, and samples the target signal according to the sampling frequency stabilization signal.

Description

Technical Field

[0001] The present application belongs to the field of signal processing technology, and in particular, relates to a sampling rate micro-control system. Background Art

[0002] In the field of signal processing, sampling is the process of converting a signal from an analog signal in the continuous time domain to a discrete signal in the discrete time domain. The analog signal is first sampled by a sampling circuit at a certain time interval to obtain a discrete signal in time, and then the analog-to-digital converter (ADC) discretizes the value to obtain a digital signal that is discrete in both value and time.

[0003] The discrete form of the signal obtained in this way often introduces some errors to the data, and the errors mainly come from two aspects, the sampling rate related to the spectrum of the continuous analog signal, and the word length used for quantization. The sampling rate refers to the frequency of sampling the continuous signal. It represents the accuracy of the discrete signal in the time domain and space domain. The word length (the number of binary bits) is used to represent the value of the discrete signal, which reflects the accuracy of the signal size.

[0004] The sampling rate (also called sampling speed or sampling frequency) defines the number of samples extracted from a continuous signal per second to form a discrete signal, and is expressed in Hertz (Hz). However, the sampling rate of a commonly used sampling loop is sampled by the input frequency. When the input frequency is inaccurate, the sampling rate will be inaccurate. When the sampling rate is inaccurate, the input buffer will overflow, causing system abnormalities. Summary of the invention

[0005] The embodiment of the present application provides a sampling rate micro-control system, which can solve the problem of system abnormality caused by buffer overflow.

[0006] In the first aspect, the embodiment of the present application provides a sampling rate micro-control system, including a frequency generating device, a control device, a frequency micro-control device and a sampling device. The frequency generating device outputs a sampling frequency signal. The control device outputs a control signal including an expected frequency range. The input end of the frequency micro-control device is respectively connected to the frequency generating device and the control device. The frequency micro-control device includes a comparison decision module, a noise adjustment module arranged at the output end of the comparison decision module, a mapping module arranged at the output end of the noise adjustment module and a frequency adjustment module arranged at the output end of the mapping module. The input end of the comparison decision module is respectively connected to the output end of the frequency adjustment module and the control device, and according to whether the sampling frequency stabilization signal exceeds the range of the control signal, the decision output comparison decision signal is output, the noise adjustment module outputs an output code corresponding to frequency acceleration or corresponding to frequency deceleration according to the comparison decision signal, the mapping module maps and outputs a frequency modulation signal according to the output code, and the frequency adjustment module corrects the sampling frequency signal according to the frequency modulation signal and outputs the sampling frequency stabilization signal adjusted to the expected frequency range. The input end of the sampling device is connected to the frequency micro-control device and samples the target signal according to the sampling frequency stabilization signal.

[0007] In one possible implementation, the comparison decision module outputs a falling wave signal when the sampling frequency stability signal received is higher than the upper limit value of the expected frequency range; the comparison decision module outputs a rising wave signal when the sampling frequency stability signal received is lower than the lower limit value of the expected frequency range.

[0008] In one possible implementation, the expected frequency range of the control signal is obtained by calculating a preset expected frequency and an expected range, the upper limit of the expected frequency range is the expected frequency plus the expected range, and the lower limit of the expected frequency range is the expected frequency minus the expected range.

[0009] In one possible implementation, the comparison decision module outputs a falling wave signal when the sampling frequency stability signal received is higher than the upper limit value of the expected frequency range; the comparison decision module outputs a rising wave signal when the sampling frequency stability signal received is lower than the lower limit value of the expected frequency range.

[0010] In one possible implementation, the noise adjustment module includes a delay unit whose input end is connected to the comparison and decision module, and a multi-level quantizer whose input ends are respectively connected to the delay unit and the comparison and decision module, wherein the delay unit includes a first adder whose input end is connected to the comparison and decision module, a second adder whose input ends are respectively connected to the output end of the first adder and the output end of the multi-level quantizer, and a delayer whose input end is connected to the output end of the second adder, and the output end of the delayer is connected to another input end of the first adder.

[0011] In a possible implementation, the noise adjustment module outputs the output code according to the following relationship:

[0012] A(N)=X(N)+Y(N-1)-A(N-1);

[0013]

[0014] Among them, X(N) is the comparison decision signal input to the delay unit in the Nth stage, Y(N) is the output code output in the Nth stage, Y(N-1) is the output code output in the N-1th stage, A(N) is the output signal output by the delay unit to the multi-level quantizer in the Nth stage, A(N-1) is the output signal output by the delay unit to the multi-level quantizer in the N-1th stage, M is the preset level value of the multi-level quantizer, and floor() is the floor function.

[0015] In a possible implementation, the mapping module maps and outputs the frequency modulation signal according to the following relationship:

[0016] If Y(N)≤2 (Z-1) , then D(N)={-[2 (Z-1) -Y(N)]}×PPM;

[0017] If Y(N)>2 (Z-1) , then D(N)={2 (Z-1) +[Y(N)-2 Z ]}×PPM;

[0018] Wherein, Y(N) is the output code input to the mapping module in the Nth stage, D(N) is the frequency modulation signal output by the mapping in the Nth stage, Z is a positive integer, and PPM is Parts Per Million (PPM).

[0019] In a possible implementation, the frequency adjustment module outputs the sampling frequency stabilization signal according to the following relationship:

[0020] C(N)=E(N)×[1+D(N)];

[0021] Wherein, D(N) is the frequency modulation signal input to the frequency adjustment module in the Nth stage, E(N) is the sampling frequency signal input to the frequency adjustment module in the Nth stage, and C(N) is the sampling frequency stabilization signal output by the frequency adjustment module in the Nth stage.

[0022] In a possible implementation manner, the sampling frequency signal and the sampling frequency stabilization signal are square waves composed of 0s and 1s.

[0023] Therefore, compared with the prior art, the present application can stabilize the input frequency of the sampling rate and avoid input buffer overflow, thereby solving the problem of system abnormality caused by buffer overflow. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0025] Figure 1 It is a module schematic diagram of a sampling rate micro-control system provided by an embodiment of the present application;

[0026] Figure 2 is a module schematic diagram of a frequency micro-control device provided in one embodiment of the present application;

[0027] Figure 3 is a module schematic diagram of a noise adjustment module provided in another embodiment of the present application;

[0028] Figure 4 It is a flow chart of a sampling rate micro-control system provided in one embodiment of the present application.

[0029] Among them, the main marks of the drawings in the figure are:

[0030] 100 sampling rate micro-control system; 10 frequency generating device; 20 control device; 30 frequency micro-control device; 32 comparison decision module; 34 noise adjustment module; 342 delay unit; 3422 first adder; 3424 second adder; 3426 delay; 344 multi-level quantizer; 36 mapping module; 38 frequency adjustment module; 40 sampling device. DETAILED DESCRIPTION

[0031] The detailed description and technical content of this application are now described in conjunction with the accompanying drawings. Furthermore, for the convenience of explanation, the drawings in this application may not be drawn in accordance with the actual proportions, and the multiple drawings and their proportions are not intended to limit the scope of this application, which is explained in advance.

[0032] The following is a description of one of the preferred embodiments of the present application. Figure 1 , Figure 2 and Figure 3 , respectively, are schematic diagrams of the sampling rate micro-control system, frequency micro-control device, and noise adjustment module of the present application, as shown in the figure:

[0033] See also Figure 1This embodiment discloses a sampling rate micro-control system 100, which mainly includes a frequency generating device 10, a control device 20, a frequency micro-control device 30 whose input ends are respectively connected to the frequency generating device 10 and the control device 20, and a sampling device 40 whose input end is connected to the frequency micro-control device 30.

[0034] The combination of devices, modules, circuits or units described in the sampling rate microcontroller system 100 of the present application and the corresponding functions can be executed by a single chip or a combination of multiple chips, and the number of multiple chip configurations is not within the scope of the present application. In addition, the chip can be, but is not limited to, a processor (Processor), a central processing unit (CPU), a microprocessor (Microprocessor), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD), and other similar devices or combinations of these devices that can process, convert or have special purposes for information or signals, which are not limited in the present application.

[0035] The frequency generating device 10 outputs a sampling frequency signal. The frequency generating device 10 may be, but is not limited to, a digital signal processor (DSP), a function signal generator (function generator), an arbitrary waveform generator (AWG), a signal generator, or other devices that can generate a signal, and is not limited in the present application.

[0036] The control device 20 outputs a control signal including an expected frequency range. The control device 20 is a processor. The processor is not limited to a single one. If necessary, multiple processors can be used to execute programs and complete the work. In one embodiment, the processor is, for example, a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors (Microprocessors), digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations of these devices, which are not limited in this application.

[0037] The input end of the frequency micro-control device 30 is connected to the frequency generating device 10 and the control device 20, so as to adjust the sampling frequency signal within the expected frequency range and output a sampling frequency stabilization signal. Figure 2 The frequency micro-control device 30 includes a comparison decision module 32, a noise adjustment module 34 disposed at the output end of the comparison decision module 32, a mapping module 36 disposed at the output end of the noise adjustment module 34, and a frequency adjustment module 38 disposed at the output end of the mapping module 36. In a preferred embodiment, the input end of the comparison decision module 32 is respectively connected to the output end of the frequency adjustment module 38 and the control device 20, and the comparison decision signal is output according to whether the sampling frequency stability signal exceeds the range of the control signal. The comparison decision module 32 includes at least one signal analyzer (Signal Analyzer) for converting discrete signals into numerical values. The signal analyzer can be, but is not limited to, a spectrum analyzer or other devices that can be used as signal conversion functions, which are not limited in this application.

[0038] See also Figure 3, the noise adjustment module 34 outputs an output code corresponding to frequency acceleration or frequency deceleration according to the comparison decision signal. In an optional embodiment, the noise adjustment module 34 includes a delay unit 342 whose input end is connected to the comparison decision module 32, and a multi-level quantizer 344 whose input ends are respectively connected to the delay unit 342 and the comparison decision module 32. Among them, the delay unit 342 includes a first adder 3422 whose input end is connected to the comparison decision module 32, a second adder 3424 whose input ends are respectively connected to the output end of the first adder 3422 and the output end of the multi-level quantizer 344, and a delay 3426 whose input end is connected to the output end of the second adder 3424, and the output end of the delay 3426 is connected to the other input end of the first adder 3422.

[0039] The first adder 3422 and the second adder 3424 may be, but are not limited to, adder circuits, half adders, full adders, ripple carry adders, carry lookahead adders or other digital circuits, logic gates, devices or combinations of these devices for performing addition operations, and are not limited in the present application.

[0040] The delay device 3426 may be, but is not limited to, an integrator, a counter, or other circuits that can be used for signal delay or integration, or a combination thereof, and is not limited in this application.

[0041] The mapping module 36 outputs the frequency modulation signal according to the output code mapping. The mapping module 36 may be a processor or an arithmetic logic unit (ALU) having an associative array search function (lookup table), which is not limited in the present application.

[0042] The frequency adjustment module 38 corrects the sampling frequency signal according to the frequency modulation signal and outputs the sampling frequency stable signal adjusted to the expected frequency range. In a preferred embodiment, the frequency adjustment module 38 can be, but is not limited to, a voltage-controlled oscillator (Voltage-Controlled Oscillator) or other devices that can be used for frequency adjustment, which is not limited in this application.

[0043] See also Figure 1 The input end of the sampling device 40 is connected to the frequency micro-control device 30, and the target signal is sampled according to the sampling frequency stabilization signal. The sampling device 40 is a sampling loop, which is a device or circuit that can sample at a certain time interval and obtain a time-discrete signal, and is not limited in this application.

[0044] The above is a description of the specific embodiment of the hardware architecture of the present application. The implementation of the present application will be further described below. Figure 4 , is a flow chart of the sampling rate micro-control system 100 of the present application:

[0045] In this embodiment, the sampling frequency signal and the sampling frequency stabilization signal are square waves composed of 0 and 1. In other embodiments, the sampling frequency signal and the sampling frequency stabilization signal can be other waveforms, and the peak value of the waveform is not limited to the scope of this application, which is explained in advance.

[0046] First, the control device 20 outputs a control signal including an expected frequency range to the frequency micro-control device 30 according to user settings or factory settings; the frequency generating device 10 outputs a sampling frequency signal to the frequency micro-control device 30 (step S201 ).

[0047] In one optional embodiment, the expected frequency range can be a user-set value or a value set at the factory; in another embodiment, the expected frequency range of the control signal is obtained by calculating a preset expected frequency and an expected range corresponding to the expected frequency, and the upper limit value of the expected frequency range is the expected frequency plus the expected range, and the lower limit value of the expected frequency range is the expected frequency minus the expected range.

[0048] Furthermore, the comparison decision module 32 of the frequency micro-control device 30 receives the control signal and the sampling frequency stabilization signal of the frequency adjustment module 38, and outputs the comparison decision signal to the noise adjustment module 34 according to whether the sampling frequency stabilization signal exceeds the expected frequency range of the control signal (step S202).

[0049] In this embodiment, when the sampling frequency stability signal received by the comparison decision module 32 is higher than the upper limit value of the expected frequency range, a falling wave signal is output; when the sampling frequency stability signal received by the comparison decision module 32 is lower than the lower limit value of the expected frequency range, a rising wave signal is output; when the sampling frequency stability signal received by the comparison decision module 32 is within the upper limit value and the lower limit value of the expected frequency range, the comparison decision module 32 will not output a signal, so that the subsequent frequency adjustment module 38 does not adjust the sampling frequency signal but directly outputs the sampling frequency signal.

[0050] Furthermore, the noise adjustment module 34 outputs an output code corresponding to frequency acceleration or frequency deceleration to the mapping module 36 according to the received comparison decision signal (step S203 ).

[0051] In this embodiment, the noise adjustment module 34 outputs the output code according to the following relationship:

[0052] A(N)=X(N)+Y(N-1)-A(N-1);

[0053]

[0054] Among them, X(N) is the comparison decision signal input to the delay unit 342 in the Nth stage, Y(N) is the output code output in the Nth stage, Y(N-1) is the output code output in the N-1th stage, A(N) is the output signal output from the delay unit 342 to the multi-level quantizer 344 in the Nth stage, A(N-1) is the output signal output from the delay unit 342 to the multi-level quantizer 344 in the N-1th stage, M is the preset level value of the multi-level quantizer 344, and floor() is the floor function.

[0055] Furthermore, the mapping module 36 maps the output frequency modulation signal to the frequency adjustment module 38 according to the received output code (step S204 ).

[0056] In this embodiment, the mapping module 36 maps the output frequency modulation signal according to the following relationship:

[0057] If Y(N)≤2 (Z-1) , then D(N)={-[2 (Z-1) -Y(N)]}×PPM;

[0058] If Y(N)>2 (Z-1) , then D(N)={2 (Z-1) +[Y(N)-2 Z ]}×PPM;

[0059] Wherein, Y(N) is the output code input to the mapping module 36 in the Nth stage, D(N) is the frequency modulation signal output by the mapping in the Nth stage, Z is a positive integer, and PPM is Parts Per Million (PPM).

[0060] Furthermore, the frequency adjustment module 38 receives the FM signal and the sampling frequency signal of the frequency generating device 10 , and the frequency adjustment module 38 corrects the sampling frequency signal according to the FM signal and outputs the sampling frequency stabilization signal adjusted to the expected frequency range to the sampling device 40 (step S205 ).

[0061] In this embodiment, the frequency adjustment module 38 outputs the sampling frequency stabilization signal according to the following relationship:

[0062] C(N)=E(N)×[1+D(N)];

[0063] Wherein, D(N) is the frequency modulation signal input to the frequency adjustment module 38 in the Nth stage, E(N) is the sampling frequency signal input to the frequency adjustment module 38 in the Nth stage, and C(N) is the sampling frequency stabilization signal output by the frequency adjustment module 38 in the Nth stage.

[0064] Finally, the sampling device 40 receives the sampling frequency stabilization signal from the frequency micro-control device 30 and samples the target signal according to the sampling frequency stabilization signal (step S206 ).

[0065] The sampling frequency stability signal is fed back to the comparison decision module 32 for comparison to confirm whether the sampling frequency stability signal is maintained within the expected frequency.

[0066] In summary, compared with the prior art, the present application can stabilize the input frequency of the sampling rate and avoid the problem of input buffer overflow causing system abnormality.

[0067] The present application has been described in detail above. However, what is described above is only a preferred embodiment of the present application and should not be used to limit the scope of implementation of the present application. That is, all equivalent changes and modifications made according to the scope of the patent application of the present application should still fall within the scope of the patent application of the present application.

Claims

1. A sampling rate microcontrol system, It is characterized in that include: A frequency generating device outputs a sampling frequency signal; A control device outputting a control signal including a desired frequency range; A frequency micro-control device, whose input end is respectively connected to the frequency generating device and the control device, the frequency micro-control device comprises a comparison decision module, a noise adjustment module arranged at the output end of the comparison decision module, a mapping module arranged at the output end of the noise adjustment module, and a frequency adjustment module arranged at the output end of the mapping module, the input end of the comparison decision module is respectively connected to the output end of the frequency adjustment module and the control device, and makes a decision and outputs a comparison decision signal according to whether the sampling frequency stabilization signal exceeds the range of the control signal, the noise adjustment module outputs an output code corresponding to frequency acceleration or frequency deceleration according to the comparison decision signal, the mapping module maps and outputs a frequency modulation signal according to the output code, and the frequency adjustment module corrects the sampling frequency signal according to the frequency modulation signal and outputs the sampling frequency stabilization signal adjusted to the expected frequency range; as well as A sampling device, whose input end is connected to the frequency micro-control device, and the sampling device samples the target signal according to the sampling frequency stabilization signal; The noise adjustment module includes a delay unit whose input terminal is connected to the comparison and decision module, and a multi-level quantizer whose input terminals are respectively connected to the delay unit and the comparison and decision module; the noise adjustment module outputs the output code according to the following relationship: A(N)=X(N)+Y(N-1)-A(N-1); Among them, X(N) is the comparison decision signal input to the delay unit in the Nth stage, Y(N) is the output code output in the Nth stage, Y(N-1) is the output code output in the N-1th stage, A(N) is the output signal output by the delay unit to the multi-level quantizer in the Nth stage, A(N-1) is the output signal output by the delay unit to the multi-level quantizer in the N-1th stage, M is the preset level value of the multi-level quantizer, and floor() is the floor function.

2. The system according to claim 1, It is characterized in that The comparison and decision module outputs a falling wave signal when the sampling frequency stability signal received is higher than the upper limit of the expected frequency range; the comparison and decision module outputs a rising wave signal when the sampling frequency stability signal received is lower than the lower limit of the expected frequency range.

3. The system according to claim 1, It is characterized in that The expected frequency range of the control signal is obtained by calculating the preset expected frequency and the expected range, the upper limit of the expected frequency range is the expected frequency plus the expected range, and the lower limit of the expected frequency range is the expected frequency minus the expected range.

4. The system according to claim 3, It is characterized in that The comparison and decision module outputs a falling wave signal when the sampling frequency stability signal received is higher than the upper limit of the expected frequency range; the comparison and decision module outputs a rising wave signal when the sampling frequency stability signal received is lower than the lower limit of the expected frequency range.

5. The system according to claim 1, It is characterized in that The delay unit includes a first adder whose input end is connected to the comparison decision module, a second adder whose input ends are respectively connected to the output end of the first adder and the output end of the multi-level quantizer, and a delayer whose input end is connected to the output end of the second adder, and the output end of the delayer is connected to another input end of the first adder.

6. The system of claim 1, It is characterized in that The mapping module maps and outputs the frequency modulation signal according to the following relationship: If Y(N)≤2 (Z-1) , then D(N)={-[2 (Z-1) -Y(N)]}×PPM; If Y(N)>2 (Z-1) , then D(N)={2 (Z-1) +[Y(N)-2 Z ]}×PPM; Wherein, Y(N) is the output code input to the mapping module in the Nth stage, D(N) is the frequency modulation signal output by the mapping in the Nth stage, Z is a positive integer, and PPM is Parts Per Million (PPM).

7. The system according to claim 6, It is characterized in that The frequency adjustment module outputs the sampling frequency stabilization signal according to the following relationship: C(N)=E(N)×[1+D(N)]; Among them, D(N) is the frequency modulation signal input to the frequency adjustment module in the Nth stage, E(N) is the sampling frequency signal input to the frequency adjustment module in the Nth stage, and C(N) is the sampling frequency stabilization signal output by the frequency adjustment module in the Nth stage.

8. The system according to any one of claims 1 to 7, It is characterized in that The sampling frequency signal and the sampling frequency stabilization signal are square waves composed of 0s and 1s.

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