Techniques for memory region resizing

Abstract

This application relates to methods, systems, and devices for techniques for memory region resizing. A memory system can dynamically update a size of a stale region configured to store data written during a write burst or write booster mode. The stale region can be a portion of a first block of memory cells and can retain data during a transfer operation such as a flush operation. The size of the stale region can be updated in response to the memory system receiving a command such as an unmap command. The size of the stale region can be determined based on an available region size, an amount of data indicated in the command, an amount of data indicated in the command that has been transferred to a second block of memory cells, or a combination thereof.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 230,498, filed August 6, 2021, titled “TECHNIQUES FOR MEMORY ZONE SIZE ADJUSTMENT,” by Bi, and U.S. Patent Application No. 17 / 726,101, filed April 21, 2022, titled “TECHNIQUES FOR MEMORY ZONE SIZE ADJUSTMENT,” by Bi, each of which is assigned to the assignee hereof, and each of which is hereby expressly incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] The technical field relates to techniques for memory zone size adjustment. BACKGROUND

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communications devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory devices into various states. For example, binary memory cells can be programmed into one of two supported states, typically corresponding to a logical 1 or a logical 0. In some examples, an individual memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by a memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to a corresponding state.

[0005] There are a variety of types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3D cross point memory, or non-volatile (NOR) and NAND memory devices, among others. A memory device can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods of time even in the absence of an external power source. SUMMARY

[0006] An apparatus is described. The apparatus can include a memory device; and a controller coupled with the memory device and configured to cause the apparatus to: receive, at the memory device, a command to remove data associated with a block of memory cells; set, based at least in part on receiving the command, a first region size based at least in part on a size of the data, the first region size comprising a first set of memory cells in the block of memory cells and corresponding to a first amount of space comprising data to be removed based at least in part on the received command; determine whether the first region size satisfies a threshold based at least in part on an available region size corresponding to a second amount of space available for storing data in the block of memory cells; set, based at least in part on determining that the first region size satisfies the threshold, a second region size, the second region size comprising a second set of memory cells in the block of memory cells, wherein the second region size is less than or equal to the available region size; and execute the received command based at least in part on setting the second region size.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium can include instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive, at the electronic device, a command to remove data associated with a block of memory cells; set, based at least in part on receiving the command, a first region size based at least in part on a size of the data, the first region size comprising a first set of memory cells in the block of memory cells and corresponding to a first amount of space comprising data to be removed based at least in part on the received command; determine whether the first region size satisfies a threshold based at least in part on an available region size corresponding to a second amount of space available for storing data in the block of memory cells; set, based at least in part on determining that the first region size satisfies the threshold, a second region size, the second region size comprising a second set of memory cells in the block of memory cells, wherein the second region size is less than or equal to the available region size; and execute the received command based at least in part on setting the second region size.

[0008] A method is described. The method can include receiving, at a memory system, a command to remove data associated with a block of memory cells; setting, based at least in part on receiving the command, a first region size based at least in part on a size of the data, the first region size comprising a first set of memory cells in the block of memory cells and corresponding to a first amount of space comprising data to be removed based at least in part on the received command; determining whether the first region size satisfies a threshold based at least in part on an available region size corresponding to a second amount of space available for storing data in the block of memory cells; setting, based at least in part on determining that the first region size satisfies the threshold, a second region size, the second region size comprising a second set of memory cells in the block of memory cells, wherein the second region size is less than or equal to the available region size; and performing, based at least in part on setting the second region size, the received command. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 An example of a system that supports techniques for memory region resizing is described in accordance with examples as disclosed herein.

[0010] Figure 2 An example of a system that supports techniques for memory region resizing is described in accordance with examples as disclosed herein.

[0011] Figure 3 An example of a process flow 300 that supports techniques for memory region resizing is described in accordance with examples as disclosed herein.

[0012] Figure 4 An example of a process flow 400 that supports techniques for memory region resizing is described in accordance with examples as disclosed herein.

[0013] Figure 5 A block diagram of a memory system that supports techniques for memory region resizing is shown in accordance with examples as disclosed herein.

[0014] Figure 6 A flow diagram illustrating one or more methods that support techniques for memory region resizing is described in accordance with examples as disclosed herein. DETAILED DESCRIPTION

[0015] In some memory devices, background operations such as a clean operation can transfer data from a set of memory cells to a second set of memory cells (e.g., transfer data from a single level cell (SLC) block to a triple level cell (TLC) block). Some memory devices can include a set of memory cells configured to retain data during a clean operation. In some cases, the set of memory cells configured to retain data can be referred to as a stale zone. For example, the stale zone can be configured to store recent data received from a host during a write burst (WB) mode of operation. In some examples, the recent data can include temporary data (i.e., temporary data that can be subsequently deleted). In some cases, the stale zone can have a static size, and recent data that exceeds the size of the stale zone can be stored in other portions of the SLC block. The excess data stored in the other portions of the SLC block can be transferred to the TLC block, and the memory device can delete the transferred data using power resources, for example, when the memory device receives a command to remove the temporary data (e.g., an unmap command), which can reduce the efficiency of the memory device and cause unwanted power consumption, among other drawbacks.

[0016] As described herein, a memory device can dynamically update the size of a zone, such as a stale zone, to accommodate recent data from a host device. For example, recent data can be written during a WB mode. In some examples, the memory device can determine a size of the data (e.g., a size of the data to be removed indicated in an unmap command) and an amount of available space in the SLC block in response to receiving a command to remove at least a portion of the recent data (e.g., an unmap command), and set the size of the stale zone to include the available space. In other embodiments, the memory device can determine the stale zone size based on additional parameters, such as one or more host data size thresholds (e.g., an amount of data to be removed in the SLC block). For example, the memory device can determine to set the stale zone size to a default zone size or to a size determined from a previous size of data to be removed.

[0017] Reference is first made to Figures 1-2 The features of the present disclosure are described in the context of systems, apparatuses, and circuitry. Reference is made to Figures 3-4 The features of the present disclosure are described in the context of process flows. Reference is made to Figures 5-6 These and other features of the present disclosure are further illustrated by and described in the context of apparatus diagrams and flow diagrams related to techniques for memory zone size adjustment.

[0018] Figure 1 An example of a system 100 that supports techniques for memory zone size adjustment according to examples as disclosed herein is illustrated. The system 100 includes a host system 105 coupled with a memory system 110.

[0019] Memory system 110 can be or include any device or collection of devices that includes at least one memory array. For example, memory system 110 can be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-Line Memory Module (DIMM), a Small Outline DIMM (SO-DIMM), or a Non-Volatile DIMM (NVDIMM), among other possibilities.

[0020] System 100 can be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other conveyance), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes memory and a processing device.

[0021] System 100 can include a host system 105 that can be coupled with memory system 110. In some examples, this coupling can include an interface with a host system controller 106, which can be an example of a controller or control component configured to cause host system 105 to perform various operations in accordance with examples as described herein. Host system 105 can include one or more devices, and in some cases can include a processor chipset and a software stack executed by the processor chipset. For example, host system 105 can include an application configured to communicate with memory system 110 or a device therein. The processor chipset can include one or more cores, one or more caches (e.g., memory local to or included in host system 105), a memory controller (e.g., a NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 105 can use memory system 110, for example, to write data to and read data from memory system 110. Although Figure 1 Although one memory system 110 is shown in FIG. 1, host system 105 can be coupled with any number of memory systems 110.

[0022] The host system 105 can be coupled with the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise convey control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces can include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DDR-enabled DIMM socket interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces can be included in, or otherwise supported between, a host system controller 106 of the host system 105 and a memory system controller 115 of the memory system 110. In some examples, the host system 105 can be coupled with the memory system 110 via a respective physical host interface for each memory device 130 included in the memory system 110, or via a respective physical host interface for each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 can be coupled with the memory system controller 115).

[0023] The memory system 110 can include a memory system controller 115 and one or more memory devices 130. The memory devices 130 can include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). While two memory devices 130-a and 130-b are shown in the example of FIG. 1, the memory system 110 can include any number of memory devices 130. Additionally, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 can include the same or different types of memory cells. Figure 1

[0024] ​The memory system controller 115 can be coupled with and in communication with the host system 105 (e.g., via a physical host interface) and can be an example of a controller or control component configured to cause the memory system 110 to perform various operations in accordance with examples as described herein. The memory system controller 115 can also be coupled with and in communication with the memory devices 130 to perform operations at the memory devices 130 that can be generally referred to as access operations, such as reading data, writing data, erasing data, or refreshing data, among other such operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with the one or more memory devices 130 to perform such commands (e.g., at memory arrays within the one or more memory devices 130). For example, the memory system controller 115 can receive a command or operation from the host system 105 and can convert the command or operation into instructions or appropriate commands to effectuate a desired access of the memory devices 130. In some cases, the memory system controller 115 can exchange data with the host system 105 and with the one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 can convert responses (e.g., data packets or other signals) associated with the memory devices 130 into corresponding signals for the host system 105.

[0025] The memory system controller 115 can be configured for other operations associated with the memory devices 130. For example, the memory system controller 115 can perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory devices 130.

[0026] The memory system controller 115 can include hardware such as one or more integrated circuits or discrete components, a buffer memory, or a combination thereof. The hardware can include circuitry with special-purpose (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 can be or include a microcontroller, special-purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0027] The memory system controller 115 can also include a local memory 120. In some cases, the local memory 120 can include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 can additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for internal storage or computation, for example, in connection with the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 can serve as a cache for the memory system controller 115. For example, if reading from or writing to the memory devices 130, data can be stored in the local memory 120, and the data can be available within the local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a cache policy (e.g., with reduced latency relative to the memory devices 130).

[0028] While Figure 1 Although an example of the memory system 110 has been illustrated as including the memory system controller 115, in some cases, the memory system 110 can not include the memory system controller 115. For example, the memory system 110 can additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or can include one or more local controllers 135, respectively, internal to the memory devices 130, to perform the functions attributed herein to the memory system controller 115. Generally, one or more functions attributed herein to the memory system controller 115 can in some cases instead be performed by the host system 105, the local controllers 135, or any combination thereof. In some cases, a memory device 130 that is at least partially managed by the memory system controller 115 can be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0029] Memory devices 130 can include one or more arrays of non-volatile memory cells. For example, memory devices 130 can include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), resistive memory, other chalcogenide-based memory, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, memory devices 130 can include one or more arrays of volatile memory cells. For example, memory devices 130 can include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0030] In some examples, memory devices 130 can include (e.g., on the same die or within the same package) local controllers 135 that can perform operations on one or more memory cells of respective memory devices 130. Local controllers 135 can operate in conjunction with memory system controller 115, or can perform one or more functions attributed herein to memory system controller 115. For example, as described in Figure 1 Memory device 130-a can include local controller 135-a, and memory device 130-b can include local controller 135-b.

[0031] In some cases, memory devices 130 can be or include NAND devices (e.g., NAND flash devices). Memory devices 130 can be or include memory dies 160. For example, in some cases, memory devices 130 can be packages that include one or more dies 160. In some examples, a die 160 can be a piece of electronic-grade semiconductor (e.g., a silicon die cut from a silicon wafer) that is cut from a wafer. Each die 160 can include one or more planes 165, and each plane 165 can include a respective set of blocks 170, where each block 170 can include a respective set of pages 175, and each page 175 can include a set of memory cells.

[0032] In some cases, the NAND memory devices 130 can include memory cells configured to each store one bit of information, which can be referred to as SLC. Additionally or alternatively, the NAND memory devices 130 can include memory cells configured to each store multiple bits of information, which can be referred to as multi-level cells (MLC) if configured to each store two bits of information, as TLC if configured to each store three bits of information, as quad-level cells (QLC) if configured to each store four bits of information, or more generally as multi-level memory cells. Multi-level memory cells can provide greater storage density relative to SLC memory cells, but in some cases can involve narrower read or write margins or greater complexity for supporting circuitry.

[0033] In some cases, a plane 165 can refer to a group of blocks 170, and in some cases, parallel operations can occur within different planes 165. For example, parallel operations can be performed on memory cells within different blocks 170, so long as the different blocks 170 are in different planes 165. In some cases, individual blocks 170 can be referred to as physical blocks, and a virtual block 180 can refer to a group of blocks 170 within which parallel operations can occur. For example, parallel operations can be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d can collectively be referred to as a virtual block 180. In some cases, a virtual block can include blocks 170 from different memory devices 130 (e.g., including blocks in one or more planes of memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block can have the same block address within their respective planes 165 (e.g., block 170-a can be “block 0” of plane 165-a, block 170-b can be “block 0” of plane 165-b, and so on). In some cases, parallel operations in different planes 165 can be subject to one or more restrictions, such as parallel operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., in relation to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0034] In some cases, a block 170 can include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 can share a common word line (e.g., be coupled with) and memory cells in the same string can share a common digit line (which can alternatively be referred to as a bit line) (e.g., be coupled with).

[0035] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at a page granularity level), but can be erased at a second granularity level (e.g., at a block granularity level). That is, a page 175 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently programmed or read (e.g., programmed or read simultaneously as part of a single programming or reading operation), and a block 170 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erase operation). Additionally, in some cases, NAND memory cells can be erased before they can be overwritten with new data. Thus, for example, in some cases, a used page 175 can not be updated until an entire block 170 containing the page 175 has been erased.

[0036] The system 100 can include any number of non-transitory computer- readable media that support techniques for memory region resizing. For example, the host system 105, the memory system controller 115, or the memory device 130 can include or otherwise have access to one or more non-transitory computer- readable media that store instructions (e.g., firmware) to perform the functions attributed herein to the host system 105, the memory system controller 115, or the memory device 130. For example, such instructions, if executed by the host system 105 (e.g., by the host system controller 106), by the memory system controller 115, or by the memory device 130 (e.g., by the local controller 135), can cause the host system 105, the memory system controller 115, or the memory device 130 to perform one or more associated functions as described herein.

[0037] In some cases, the memory system 110 can utilize the memory system controller 115 to provide a managed memory system, which can include, for example, one or more memory arrays and associated circuitry in combination with a local (e.g., on-die or in-package) controller (e.g., the local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0038] In some examples, data can be transferred between blocks 170 of a memory device 130, such as the memory device 130-a. For example, data can be initially written to a first block 170-a (e.g., an SLC block 170-a) and subsequently transferred to a second block 170-b (e.g., a TLC block 170-b) as part of a destage operation. In some cases, the first block 170-a can include a stale region having a corresponding stale region size. During the destage operation, data stored in the stale region can not be transferred from the first block 170-a to the second block 170-b.

[0039] In some cases, the stale region size can be static (i.e., the stale region size can not change). A static stale region size can result in excess temporary data written during WB mode being stored outside of the stale region. During a flush operation, the excess temporary data can be transferred from the first block 170-a to the second block 170-b.

[0040] The memory system 110 (e.g., via the memory system controller 115 or the local controller 135) can dynamically adjust (e.g., increase or decrease) the stale region size in response to receiving a command to remove temporary data. In some cases, the stale region size can be determined based on an amount of free space in the first block 170-a. Additionally or alternatively, the stale region size can be determined based on a host data size. For example, the stale region size can be determined by comparing a size of data to be deleted (e.g., as indicated in a de-map command) to a threshold. The host data size can indicate an amount of data deleted in the first block 170-a, the second block 170-b, or a combination thereof over a period of time (e.g., an amount of data deleted in a day). In some cases, the stale region size can be adjusted to a default stale region size. In other cases, the stale region size can be adjusted based on a host data size from a previous period (e.g., a host delete data size from a previous day).

[0041] Figure 2 An example of a system 200 that supports techniques for memory region size adjustment in accordance with examples as disclosed herein is described. The system 200 can be an example of the system 100 as described with reference to Figure 1 or aspects thereof. The system 200 can include a memory system 210 configured to store data received from a host system 205 and send the data to the host system 205 if requested by the host system 205 using an access command (e.g., a read command or a write command). The system 200 can implement aspects of the system 100 described with reference to Figure 1 For example, the memory system 210 and the host system 205 can be examples of the memory system 110 and the host system 105, respectively.

[0042] The memory system 210 can include a memory device 240 to store data transferred between the memory system 210 and the host system 205, e.g., in response to receiving an access command from the host system 205, as described herein. The memory device 240 can include a memory device 140 as described with reference to Figure 1The one or more memory devices described. For example, the memory devices 240 can include NAND memory, PCM, self-selecting memory, 3D cross point, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0043] The memory system 210 can include a storage controller 230 for controlling transfer of data to and from the memory devices 240, e.g., for storing data, retrieving data, and determining memory locations in which data is to be stored and from which data is to be retrieved. The storage controller 230 can communicate with the memory devices 240 directly or via a bus (not shown) using protocols specific to each type of memory device 240. In some cases, a single storage controller 230 can be used to control multiple memory devices 240 of the same or different types. In some cases, the memory system 210 can include multiple storage controllers 230, e.g., a different storage controller 230 for each type of memory device 240. In some cases, the storage controller 230 can implement aspects of the local controller 135 as described with reference to Figure 1 Aspects of the local controller 135 described.

[0044] The memory system 210 can additionally include an interface 220 for communicating with the host system 205, and a buffer 225 for temporarily storing data transferred between the host system 205 and the memory devices 240. The interface 220, buffer 225, and storage controller 230 can be used to translate data between the host system 205 and the memory devices 240 (e.g., as shown by the data path 250), and can be collectively referred to as data path components.

[0045] Temporarily storing data using the buffer 225 during transfer can allow data to be buffered while a command is being processed, thereby reducing latency between commands and allowing for any data size associated with a command. This can also allow for handling bursts of commands, and once the burst has stopped, the buffered data can be stored or transmitted (or both). The buffer 225 can include relatively fast memory (e.g., some types of volatile memory, such as SRAM or DRAM), or a hardware accelerator, or both, to allow data to be stored to and retrieved from the buffer 225 quickly. The buffer 225 can include data path switching components for bidirectional data transfer between the buffer 225 and other components.

[0046] The temporary storage of data within the buffer 225 can refer to storage of data in the buffer 225 during execution of an access command. That is, after completion of an access command, the associated data can no longer be maintained in the buffer 225 (e.g., overwritten with data for an additional access command). Further, the buffer 225 can be a non-cached buffer. That is, data can not be read directly from the buffer 225 by the host system 205. For example, a read command can be added to the queue without the operation of matching an address to an address already in the buffer 225 (e.g., without a cache address match or lookup operation).

[0047] The memory system 210 can additionally include a memory system controller 215 for executing commands received from the host system 205 and controlling the data path components when moving data. The memory system controller 215 can be an example of the memory system controller 115 as described with reference to Figure 1 The bus 235 can be used for communication between the system components.

[0048] In some cases, one or more queues (e.g., the command queue 260, the buffer queue 265, and the storage queue 270) can be used to control the processing of access commands and movement of corresponding data. For example, this can be beneficial if more than one access command from the host system 205 is processed in parallel by the memory system 210. As an example of a possible implementation, the command queue 260, the buffer queue 265, and the storage queue 270 are depicted at the interface 220, the memory system controller 215, and the storage controller 230, respectively. However, the queues (if used) can be located anywhere within the memory system 210.

[0049] Data communicated between the host system 205 and the memory device 240 can take a different path in the memory system 210 than non-data information (e.g., commands, status information). For example, system components in the memory system 210 can communicate with each other using the bus 235, while data can use the data path 250 through the data path components instead of the bus 235. The memory system controller 215 can control how and whether data is communicated between the host system 205 and the memory device 240 by communicating with the data path components via the bus 235 (e.g., using a protocol specific to the memory system 210).

[0050] If the host system 205 transmits an access command to the memory system 210, the command can be received by the interface 220, e.g., according to a protocol (e.g., a UFS protocol or an eMMC protocol). Thus, the interface 220 can be considered a front end of the memory system 210. Upon receiving each access command, the interface 220 can communicate the command to the memory system controller 215, e.g., via the bus 235. In some cases, each command can be added to the command queue 260 by the interface 220 to communicate the command to the memory system controller 215.

[0051] The memory system controller 215 can determine that an access command has been received based on a communication from the interface 220. In some cases, the memory system controller 215 can determine that an access command has been received by retrieving a command from the command queue 260. After, e.g., a command has been retrieved from the command queue 260 by the memory system controller 215, the command can be removed from the command queue 260. In some cases, the memory system controller 215 can cause the interface 220 to remove a command from the command queue 260, e.g., via the bus 235.

[0052] Upon determining that an access command has been received, the memory system controller 215 can execute the access command. For a read command, this can mean obtaining data from the memory device 240 and transmitting the data to the host system 205. For a write command, this can mean receiving data from the host system 205 and moving the data to the memory device 240.

[0053] In either case, the memory system controller 215 can use the buffer 225 for, among other things, temporary storage of data received from or sent to the host system 205. The buffer 225 can be considered a middle end of the memory system 210. In some cases, buffer address management (e.g., pointers to address locations in the buffer 225) can be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0054] To handle a write command received from the host system 205, the memory system controller 215 can first determine whether the buffer 225 has sufficient available space to store data associated with the command. For example, the memory system controller 215 can determine, e.g., via firmware (e.g., controller firmware), an amount of space available within the buffer 225 to store data associated with a write command.

[0055] In some cases, a buffer queue 265 can be used to control the flow of commands associated with data stored in the buffer 225, including write commands. The buffer queue 265 can include access commands associated with data currently stored in the buffer 225. In some cases, commands in the command queue 260 can be moved by the memory system controller 215 to the buffer queue 265, and can remain in the buffer queue 265 while the associated data is stored in the buffer 225. In some cases, each command in the buffer queue 265 can be associated with an address at the buffer 225. That is, a pointer can be maintained indicating the location in the buffer 225 where data associated with each command is stored. Using the buffer queue 265, multiple access commands can be received sequentially from the host system 205 and at least portions of the access commands can be processed in parallel.

[0056] If the buffer 225 has sufficient space to store the write data, the memory system controller 215 can cause the interface 220 to transmit an indication of availability to the host system 205 (e.g., a “ready to transfer” indication), for example, in accordance with a protocol (e.g., a UFS protocol or an eMMC protocol). When the interface 220 subsequently receives data associated with a write command from the host system 205, the interface 220 can use the data path 250 to transfer the data to the buffer 225 for temporary storage. In some cases, the interface 220 can obtain a location of the stored data within the buffer 225 from the buffer 225 or the buffer queue 265. The interface 220 can indicate to the memory system controller 215 whether the transfer of data to the buffer 225 has been completed, for example, via the bus 235.

[0057] Once the write data has been stored in the buffer 225 by the interface 220, the data can be transferred out of the buffer 225 and stored in the memory device 240. This can be accomplished using the storage controller 230. For example, the memory system controller 215 can cause the storage controller 230 to retrieve the data from the buffer 225 using the data path 250 and transfer the data to the memory device 240. The storage controller 230 can be considered a back end of the memory system 210. The storage controller 230 can indicate to the memory system controller 215 that the transfer of data to the memory device in the memory device 240 has been completed, for example, via the bus 235.

[0058] In some cases, a store queue 270 can be used to assist in the transfer of write data. For example, the memory system controller 215 can push a write command from the buffer queue 265 (e.g., via the bus 235) to the store queue 270 for processing. The store queue 270 can include an entry for each access command. In some examples, the store queue 270 can additionally include a buffer pointer (e.g., address) that can indicate a location in the buffer 225 where data associated with the command is stored and a store pointer (e.g., address) that can indicate a location in the memory device 240 associated with the data. In some cases, the store controller 230 can obtain a location within the buffer 225 from which to obtain data from the buffer 225, the buffer queue 265, or the store queue 270. The store controller 230 can manage locations within the memory device 240 where data is stored (e.g., perform wear leveling, garbage collection, and the like). Entries can be added to the store queue 270, for example, by the memory system controller 215. Upon completion of the transfer of data, entries can be removed from the store queue 270, for example, by the store controller 230 or the memory system controller 215.

[0059] To process a read command received from the host system 205, the memory system controller 215 can again first determine whether the buffer 225 has sufficient available space to store data associated with the command. For example, the memory system controller 215 can determine, for example, via firmware (e.g., controller firmware), an amount of space available within the buffer 225 to store data associated with the read command.

[0060] In some cases, the buffer queue 265 can be used to assist in the buffer storage of data associated with read commands in a similar manner as discussed above with respect to write commands. For example, if the buffer 225 has sufficient space to store read data, the memory system controller 215 can cause the store controller 230 to retrieve data associated with the read command from the memory device 240 and store the data in the buffer 225 for temporary storage using the data path 250. The store controller 230 can indicate to the memory system controller 215 when the transfer of data to the buffer 225 has been completed, for example, via the bus 235.

[0061] In some cases, the storage queue 270 can be used to assist in the transfer of read data. For example, the memory system controller 215 can push a read command to the storage queue 270 for processing. In some cases, the storage controller 230 can obtain from the buffer 225 or the storage queue 270 a location within the memory device 240 from which to retrieve data. In some cases, the storage controller 230 can obtain from the buffer queue 265 a location within the buffer 225 to store data. In some cases, the storage controller 230 can obtain from the storage queue 270 a location within the buffer 225 to store data. In some cases, the memory system controller 215 can move commands processed by the storage queue 270 back to the command queue 260.

[0062] Once data has been stored in the buffer 225 by the storage controller 230, the data can be transferred out of the buffer 225 and sent to the host system 205. For example, the memory system controller 215 can cause the interface 220 to retrieve data from the buffer 225 using the data path 250 and transmit the data to the host system 205, e.g., according to a protocol (e.g., a UFS protocol or an eMMC protocol). For example, the interface 220 can process a command from the command queue 260 and can indicate to the memory system controller 215 that the data transfer to the host system 205 has completed, e.g., via the bus 235.

[0063] The memory system controller 215 can execute received commands according to an order, e.g., a first-in-first-out order according to the order of the command queue 260. For each command, the memory system controller 215 can cause data corresponding to the command to move into and out of the buffer 225, as discussed above. While data is moved into the buffer 225 and stored within the buffer 225, the command can remain in the buffer queue 265. If processing of the command is complete (e.g., if data corresponding to an access command has been transferred out of the buffer 225), the command can be removed from the buffer queue 265, e.g., by the memory system controller 215. If a command is removed from the buffer queue 265, an address previously storing data associated with that command can be used to store data associated with a new command.

[0064] The memory system controller 215 can additionally be configured for operations associated with the memory device 240. For example, the memory system controller 215 can perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 can issue a command indicating one or more LBAs, and the memory system controller 215 can identify one or more physical block addresses indicated by the LBAs. In some cases, one or more contiguous LBAs can correspond to non-contiguous physical block addresses. In some cases, the storage controller 230 can be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 can perform the functions of the storage controller 230 and the storage controller 230 can be omitted.

[0065] The memory device 240 can include SLC blocks 280 and TLC blocks 290. In some examples, the SLC blocks 280 can include a stale region 285, where the stale region 285 has a corresponding size. In some cases, temporary data associated with a WB or write booster mode from the host system 205 can be initially stored in the stale region 285. The temporary data stored in the stale region 285 can be preserved during a transfer of data (e.g., as part of a flush operation) from the SLC blocks 280 to the TLC blocks 290 via the transfer path 275.

[0066] In some cases, the size of the stale region 285 can be static. A static size can result in excess temporary data written during a WB mode being stored outside of the stale region 285. In some cases, the excess temporary data can be transferred from the SLC blocks 280 to the TLC blocks 290 via the transfer path 275. In some cases, the memory device 240 can receive a command to remove temporary data written during a WB mode (e.g., an unmap command). If the excess temporary data has been transferred from the SLC blocks 280 to the TLC blocks 290, removing the temporary data can include removing data from the TLC blocks 290, which can decrease the efficiency of the memory device and cause unwanted power consumption, among other drawbacks.

[0067] Memory device 240 can dynamically adjust (e.g., increase) the size of stale region 285 in response to receiving a command to remove the temporary data. Adjusting the size of stale region 285 can enable memory device 240 to store additional temporary data in stale region 285, which can reduce the amount of temporary data transferred from SLC block 280 to TLC block 290 via transfer path 275.

[0068] In some cases, the size of stale region 285 can be determined based on the amount of free space in SLC block 280. Additionally or alternatively, the size of stale region 285 can be determined based on a host data size. For example, the size of stale region 285 can be determined by comparing the size of data to be deleted (e.g., as indicated in a de-map command) to a threshold value. The host data size can indicate the amount of data deleted in a period of time (e.g., the amount of data deleted in a day) in SLC block 280, TLC block 290, or a combination thereof. In some cases, the size of stale region 285 can be adjusted to a default size. In other cases, the size of stale region 285 can be adjusted based on a host data size from a previous period (e.g., a host delete data size for a previous day).

[0069] Figure 3 An example of process flow 300 is described in accordance with examples as disclosed herein that support techniques for memory region size adjustment. Process flow 300 can be performed by components of a memory system, such as memory system 110 described with reference to Figure 1 and 2 Process flow 300 can be performed by a controller or a memory device (or both) of a memory system, such as memory system controller 115 or local controller 135, respectively, as described with reference to Figure 1 Process flow 300 can be implemented to reduce latency and power consumption and increase system performance, among other benefits. Aspects of process flow 300 can be implemented by a controller, among other components. Additionally or alternatively, aspects of process flow 300 can be implemented as instructions stored in a memory (e.g., firmware stored in a memory coupled to memory system controller 115 or local controller 135). For example, the instructions, if executed by a controller (e.g., memory system controller 115, local controller 135), can cause the controller to perform the operations of process flow 300. In the following description of process flow 300, the operations can be performed in a different order than shown. For example, certain operations can also be omitted from process flow 300, or other operations can be added to process flow 300.

[0070] The memory system can operate in a WB or write-booster mode. During the WB mode, the memory system can store data from the host in a first block of memory cells (e.g., SLC block) configured to store data written by the host. In some cases, the memory system can store recent data from the host device in a stale region of the first block of memory cells. In some examples, the data stored in the stale region can include temporary data. The temporary data can be removed in response to a command issued periodically (e.g., a daily unmap command).

[0071] At 305, a command can be received. For example, the memory system can receive a command to remove data associated with the first block of memory cells. The command can be an example of an unmap command and can be associated with a WB or write-booster mode of the memory system. The unmap command can include an indication to remove temporary data written to the first block of memory cells during the WB or write-booster mode of the memory system. In some cases, the temporary data can have been transferred (e.g., as part of a clean operation) from the first block of memory cells to a second block of memory cells (e.g., a TLC block). In other cases, the temporary data can have been stored in a stale region and thus remain in the first block of memory cells during the clean operation.

[0072] At 310, in response to receiving the command at 305, it can be determined whether the device free space satisfies a threshold. For example, the controller can determine whether the device free space (i.e., unused space of the memory system) exceeds the threshold based on an amount of space associated with the write-booster or WB mode of the memory system (e.g., write-booster size). In some cases, the threshold can be an integer multiple of the write-booster size, such as three times the write-booster size. The write-booster size can be configured to indicate an amount of data to be written during the WB or write-booster mode. However, in some cases, the write-booster size can exceed an available size for the write-booster (e.g., write-booster available size or region size). For example, data associated with the write-booster can be transferred (e.g., during a clean operation) from the first block of memory cells to a second block of memory cells. Thus, if the size of the data associated with the write-booster on the first block of memory cells exceeds the threshold, the second block of memory cells can not have enough space to store the data associated with the write-booster.

[0073] If at 310 it is determined that the device free space satisfies the threshold, 315 can be performed. At 315, a write booster available size can be set. For example, the controller can adjust the write booster available size to a fraction of the device free space. In some examples, the write booster available size can be set to one third of the device free space, such as when data associated with a write booster is configured to be transferred from a first block of memory cells to a second block of memory cells. That is, the write booster available size can be set to provide enough space to transfer data associated with a write booster from a first block of memory cells to a second block of memory cells.

[0074] If at 310 it is determined that the device free space does not satisfy the threshold, 320 can be performed without first performing 315. At 320, an available region size can be set. For example, the controller can set the available region size based on the device free space, the write booster available size, a default stale region size, or a combination thereof. The available region size can indicate a maximum size available to increase the stale region size. That is, the available region can indicate how much additional space the stale region can occupy. The default stale region size can indicate a starting value for the stale region size. In some cases, the default stale region size can be, for example, 2 GB. In some cases, the available region size can indicate a maximum size available for the stale region. The available region size can be based on, for example, one third of the device free space minus a sum of the write booster available size and the default region size. Additionally or alternatively, the available region size can be updated when a block of memory cells is opened for host writes.

[0075] At 325, a delete data size can be set (e.g., determined, calculated, updated). For example, the memory controller can calculate a daily delete TLC data size. The memory controller can record an amount of data associated with a WB mode that is transferred from a first block of memory cells to a second block of memory cells and subsequently deleted over a set of one or more unmap commands issued in a day. In some examples, the memory controller can calculate a host delete data size, which can include an amount of space corresponding to total data indicated in a command received at 305. Additionally or alternatively, the memory controller can calculate a host delete SLC data size, which can include an amount of space corresponding to data indicated in a command received at 305 that remains in the first block of memory cells. In some examples, the memory controller can determine a last daily delete TLC data size, which can include an amount of data that can be determined to correspond to a daily delete TLC data size for a previous day. In some examples, the delete data size can be updated in response to a command received at 305.

[0076] In some cases, data can be optionally transferred from the first block of memory cells to the second block of memory cells at 330. The transferred data can be different than the data associated with the command received at 305. For example, as part of one or more background operations, the memory system can transfer data that is not stored in the stale region from the first block of memory cells to the second block of memory cells. In some cases, transferring data from the first block of memory cells to the second block of memory cells can be part of a clean-up operation.

[0077] At 335, a determination can be made as to whether the daily delete data size set at 325 satisfies a threshold. For example, the memory controller can determine whether the daily delete TLC data size is greater than the available region size. In some cases, determining that the daily delete TLC data size is greater than the available region size can indicate that the memory system can benefit from a larger stale region size than the current stale region size, as a larger stale region size can mitigate (i.e., reduce) the amount of temporary data transferred from the first block of memory cells to the second block of memory cells and subsequently deleted.

[0078] If, at 335, it is determined that the daily delete data size set at 325 satisfies the threshold, 340 can be performed. At 340, the first region size (i.e., the stale region size) can be adjusted (e.g., set or updated) to the available region size based on determining that the daily delete TLC data size exceeds the threshold group. If, at 335, it is determined that the daily delete data size set at 325 does not satisfy the threshold, 341 can be performed. At 341, the first region size can be updated based on the daily delete data size. For example, the memory controller can update the stale region size based on a determination that the daily delete TLC data size does not exceed the threshold based on a sum of the current stale region size and the daily delete TLC data size.

[0079] In some cases, the daily delete TLC data size can be reset at 345. For example, the memory controller can optionally reset (i.e., set to zero) the daily delete TLC data size based on recognizing a nightly unmap command sequence or a group of unmap command sequences. Resetting the daily delete TLC data size can be part of monitoring the amount of data associated with unmap commands that have been transferred from the SLC block to the TLC block in a period of time (e.g., a day). That is, the daily delete TLC data size can indicate the amount of data associated with unmap commands that have been transferred from the SLC block to the TLC block in a day, and resetting the daily TLC delete data size can enable the controller to maintain an accurate record.

[0080] At 350, a determination can be made as to whether the size of the data indicated in the command received at 305 is greater than or equal to the size of the available region. For example, the memory controller can compare the stale region size set at 340 to the available region size determined at 320. If at 350, it is determined that the size of the data is greater than or equal to the size of the available region, 355 can be performed. At 355, the stale region size can be adjusted (e.g., set, reduced) to the size of the available region. That is, the stale region size can be set to the second region size. If at 350, it is determined that the size of the data is not greater than or equal to the size of the available region, 360 can be performed without first performing 355.

[0081] At 360, the command received at 305 can be executed. For example, the memory controller can execute the unmap command based on the stale region size set at 340 and, in some cases, adjusted at 355. In some examples, executing the unmap command can include removing data (e.g., temporary data) from the first block of memory cells (e.g., SLC block) as indicated in the command. In some cases, executing the unmap command can additionally include removing data (e.g., temporary data) that has been transferred from the first block of memory cells to the second block of memory cells (e.g., TLC block).

[0082] In some examples, the steps of process flow 300 can be performed periodically (e.g., on a nightly basis) in response to a periodic unmap command. Accordingly, one or more parameters, such as the starting stale region size and the daily delete TLC data size, among other examples, can be based on previous iterations of process flow 300. Additionally or alternatively, one or more parameters of process flow 300 can be independent of previous iterations of process flow 300, such as the write booster size and the write booster available size, among other examples.

[0083] Figure 4 An example of a process flow 400 that supports techniques for memory region size adjustment, in accordance with examples as disclosed herein, is illustrated. Process flow 400 can be performed by components of a memory system, such as the memory system 110 described with reference to Figure 1 and 2 Process flow 400 can be performed by a controller or a memory device (or both) of a memory system, such as the memory system controller 115 or the local controller 135, respectively, as described with reference to Figure 1The process flow 400 can be implemented to reduce latency and power consumption and increase system performance, among other benefits. Aspects of the process flow 400 can be implemented by a controller, among other components. Additionally or alternatively, aspects of the process flow 400 can be implemented as instructions stored in a memory (e.g., firmware stored in a memory coupled with a memory system controller 115 or a local controller 135). For example, the instructions, if executed by a controller (e.g., a memory system controller 115, a local controller 135), can cause the controller to perform the operations of the process flow 400. In the following description of the process flow 400, the operations can be performed in a different order than shown. For example, certain operations can also be omitted from the process flow 400, or other operations can be added to the process flow 400.

[0084] The memory system can operate in a WB or write-booster mode. During the WB mode, the memory system can store data from a host in a first block of memory cells (e.g., an SLC block) configured to store data written by the host (i.e., the memory system can store the most recent data from the host device in a stale area). In some examples, the data stored in the stale area can include temporary data. The temporary data can be removed in response to a command issued periodically (e.g., a daily unmap command).

[0085] At 405, a default stale area size can be determined. For example, the default stale area size can be set by a memory controller or otherwise indicated by firmware, a previous iteration of the process 400, or the like. The default stale area size can indicate a starting stale area size for a stale area. In some examples, the default stale area size can be 2 gigabytes (GB).

[0086] At 410, a command can be received. For example, the memory system can receive a command to remove data associated with a block of memory cells. The command can be an example of an unmap command and can be associated with a WB or write-booster mode of the memory system. The unmap command can include an indication to remove temporary data written to the first block of memory cells during the WB or write-booster mode of the memory system. In some cases, the temporary data can have been transferred from the first block of memory cells to a second block of memory cells (e.g., a TLC block) as part of a flush operation. In other cases, the temporary data can be stored in a stale area and thus remain in the first block of memory cells during the flush operation.

[0087] At 415, a deletion data size can be set (i.e., determined, calculated, updated). For example, the memory controller can calculate a daily deletion TLC data size. The memory controller can record an amount of data associated with the WB mode transferred from the first block of memory cells to the second block of memory cells and subsequently deleted over a set of one or more unmap commands issued in a day. In some examples, the memory controller can calculate a host deletion data size, which can include an amount of space corresponding to the total data indicated in the command received at 410. Additionally or alternatively, the memory controller can calculate a host deletion SLC data size, which can include an amount of space corresponding to the data indicated in the command received at 410 that remains in the first block of memory cells. In some examples, the memory controller can determine a last daily deletion TLC data size, which can include an amount of data that can be determined to correspond to a daily deletion TLC data size of a previous day. In some examples, the deletion data size can be updated in response to the command received at 410.

[0088] At 420, a determination can be made as to whether the daily deletion data size set at 415 satisfies a threshold. For example, the memory controller can determine whether the host deletion SLC data size is greater than a threshold (e.g., zero). Additionally, the memory controller can determine whether the host deletion data size exceeds a second threshold (e.g., a threshold greater than zero).

[0089] If at 420, it is determined that the daily deletion data size set at 415 does not satisfy the threshold, 425 can be performed. At 425, the stale region size (i.e., the first region size) can be set (i.e., adjusted to) a default stale region size. If at 420, it is determined that the daily deletion data size set at 415 satisfies the threshold, 430 can be performed. At 430, a determination can be made as to whether the quantity satisfies a threshold. For example, the memory controller can determine whether a quantity based on the stale region size and the last daily deletion TLC data size (e.g., a difference between the stale region size and the last daily deletion TLC data size) exceeds a threshold. In some examples, the threshold can be the size of the default stale region determined at 405. If at 430, it is determined that the quantity does not satisfy the threshold, 425 can be performed, as described herein.

[0090] If at 430, it is determined that the quantity satisfies the threshold, 435 can be performed. At 435, the stale region size (i.e., the first region size) can be set (i.e., calculated, adjusted) to a new size. For example, the memory controller can set the stale region size to a new size based on the current stale region size and the last daily deletion TLC data size (e.g., a difference between the current stale region size and the last daily deletion TLC data size).

[0091] At 440, the stale region size can be adjusted (e.g., adjusted to a second region size) based on the threshold. For example, the memory controller can determine whether the stale region size set at 425 or 435 exceeds a threshold, where the threshold can be the available stale region size (e.g., refer to Figure 3 the discussed available region size). If the stale region size set at 425 or 435 exceeds the threshold, the stale region size can be set (i.e., reduced, adjusted) to the available stale region size.

[0092] In some cases, at 445, the daily deletion TLC data size can be reset. For example, the memory controller can optionally reset (i.e., set to zero) the daily deletion TLC data size based on recognizing a nightly de-map command sequence or a set of de-map command sequences. Resetting the daily deletion TLC data size can be part of monitoring an amount of data associated with de-map commands that have been transferred from the first block of memory cells to the second block of memory cells over a period of time (e.g., a day). That is, the daily deletion TLC data size can indicate an amount of data associated with de-map commands that have been transferred from the first block of memory cells to the second block of memory cells in a day, and resetting the daily deletion TLC data size can allow for maintaining an accurate record.

[0093] At 450, the command received at 410 can be executed. For example, the memory controller can execute the de-map command based on the stale region size set at 425 or 435, and in some cases, adjusted at 440. In some examples, executing the de-map command can include removing data (e.g., temporary data) from the first block of memory cells (e.g., SLC block) as indicated in the command. In some cases, executing the de-map command can additionally include removing data (e.g., temporary data) that has been transferred from the first block of memory cells to the second block of memory cells (e.g., TLC block).

[0094] In some examples, the steps of process flow 400 can be performed periodically (e.g., on a nightly basis) in response to a periodic de-map command. Accordingly, one or more parameters (such as the starting stale region size and the daily deletion TLC data size, among other examples) can be based on a previous iteration of process flow 400. Additionally or alternatively, one or more parameters of process flow 400 can be independent of a previous iteration of process flow 400, such as the available stale region size, among other examples.

[0095] Figure 5 A block diagram 500 showing a memory system 520 that supports techniques for memory region size adjustment in accordance with examples as disclosed herein is shown. The memory system 520 can be as described with reference to Figures 1-4Examples of aspects of the described memory system. The memory system 520, or various components thereof, can be examples of means for performing various aspects of techniques for memory region resizing as described herein. For example, the memory system 520 can include a command manager 525, a region size manager 530, a threshold manager 535, a data transfer manager 540, or any combination thereof. Each of these components can communicate, directly or indirectly (e.g., via one or more buses), with one another.

[0096] The command manager 525 can be configured as, or otherwise support, means for receiving, at a memory system, a command to remove data associated with a block of memory cells. The region size manager 530 can be configured as, or otherwise support, means for setting, based at least in part on receiving the command, a first region size based at least in part on a size of the data, the first region size including a first set of memory cells in the block of memory cells and corresponding to a first amount of space including the data to be removed based at least in part on the received command. The threshold manager 535 can be configured as, or otherwise support, means for determining whether the first region size satisfies a threshold based at least in part on a usable region size corresponding to a second amount of space available for storing data in the block of memory cells. In some examples, the region size manager 530 can be configured as, or otherwise support, means for setting, based at least in part on determining that the first region size satisfies the threshold, a second region size, the second region size including a second set of memory cells in the block of memory cells, where the second region size is less than or equal to the usable region size. In some examples, the command manager 525 can be configured as, or otherwise support, means for executing the received command based at least in part on setting the second region size.

[0097] In some examples, the region size manager 530 can be configured as, or otherwise support, means for setting the usable region size based at least in part on the second amount of space and a third region size corresponding to a third amount of space associated with a write booster at the memory system.

[0098] In some examples, the threshold manager 535 can be configured as, or otherwise support, means for determining whether the second amount of space exceeds a second threshold. In some examples, the region size manager 530 can be configured as, or otherwise support, means for setting the third region size based at least in part on determining that the second amount of space exceeds the second threshold.

[0099] In some examples, to support determining whether the first region size satisfies the threshold, the threshold manager 535 can be configured as, or otherwise support, means for determining whether the size of the data is greater than or equal to the usable region size, where setting the second region size is based at least in part on determining that the size of the data is greater than or equal to the usable region size.

[0100] In some examples, to support determining whether the first region size satisfies the threshold, the threshold manager 535 can be configured as or otherwise support a means for determining whether a size of the data satisfies a second threshold, where setting the second region size is based at least in part on determining that the size of the data satisfies the second threshold.

[0101] In some examples, the second threshold is associated with data stored in the block of memory cells, the second block of memory cells, or both.

[0102] In some examples, the region size manager 530 can be configured as or otherwise support a means for resetting the first region size to a default region size based at least in part on executing the received command.

[0103] In some examples, the data transfer manager 540 can be configured as or otherwise support a means for transferring second data from the block of memory cells to the second block of memory cells after setting the first region size, the second data being different from the data associated with the received command.

[0104] In some examples, the block of memory cells includes single-level cells. In some examples, the second block of memory cells includes triple-level cells.

[0105] In some examples, the received command includes an unmap command.

[0106] Figure 6 A flow diagram illustrating a method 600 that supports techniques for memory region resizing in accordance with examples as disclosed herein is shown. The operations of method 600 can be implemented by a memory system or its components as described herein. For example, the operations of method 600 can be performed by a memory system as described with reference to Figures 1-5 In some examples, a memory system can execute a set of instructions to control the functional elements of a device to perform the described functions. Additionally or alternatively, the memory system can perform aspects of the described functions using special-purpose hardware.

[0107] At 605, the method can include receiving, at a memory system, a command to remove data associated with a block of memory cells. The operations of 605 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 605 can be performed by a command manager 525 as described with reference to Figure 5

[0108] ​At 610, the method can include setting, based at least in part on receiving the command, a first region size based at least in part on a size of the data, the first region size including a first set of memory cells in the block of memory cells and corresponding to a first amount of space including the data to be removed based at least in part on the received command. The operations of 610 can be performed according to examples as disclosed herein. In some examples, aspects of the operations of 610 can be performed by a region size manager 530 as described with reference to Figure 5

[0109] At 615, the method can include determining whether the first region size satisfies a threshold based at least in part on an available region size corresponding to a second amount of space available for storing data in the block of memory cells. The operations of 615 can be performed according to examples as disclosed herein. In some examples, aspects of the operations of 615 can be performed by a threshold manager 535 as described with reference to Figure 5

[0110] At 620, the method can include setting, based at least in part on determining that the first region size satisfies the threshold, a second region size, the second region size including a second set of memory cells in the block of memory cells, wherein the second region size is less than or equal to the available region size. The operations of 620 can be performed according to examples as disclosed herein. In some examples, aspects of the operations of 620 can be performed by a region size manager 530 as described with reference to Figure 5

[0111] At 625, the method can include executing the received command based at least in part on setting the second region size. The operations of 625 can be performed according to examples as disclosed herein. In some examples, aspects of the operations of 625 can be performed by a command manager 525 as described with reference to Figure 5 Figure 5

[0112] ​​​​In some examples, an apparatus as described herein can perform one or more methods, such as method 600. The apparatus can include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving, at a memory system, a command to remove data associated with a block of memory cells; setting, based at least in part on receiving the command, a first region size based at least in part on a size of the data, the first region size including a first set of memory cells in the block of memory cells and corresponding to a first amount of space including data to be removed based at least in part on the received command; determining whether the first region size satisfies a threshold based at least in part on a usable region size corresponding to a second amount of space available for storing data in the block of memory cells; setting, based at least in part on determining that the first region size satisfies the threshold, a second region size, the second region size including a second set of memory cells in the block of memory cells, wherein the second region size is less than or equal to the usable region size; and performing, based at least in part on setting the second region size, the received command.

[0113] Some examples of the method 600 and apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for setting the usable region size based at least in part on the second amount of space and a third region size corresponding to a third amount of space associated with a write boost at the memory system.

[0114] Some examples of the method 600 and apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for determining whether the second amount of space exceeds a second threshold and setting the third region size based at least in part on determining that the second amount of space exceeds the second threshold.

[0115] In some examples of the method 600 and apparatus described herein, determining whether the first region size satisfies the threshold can include operations, features, circuitry, logic, means, or instructions for determining whether the size of the data can be greater than or equal to the usable region size, wherein setting the second region size can be based at least in part on determining that the size of the data can be greater than or equal to the usable region size.

[0116] In some examples of the method 600 and apparatus described herein, determining whether the first region size satisfies the threshold can include operations, features, circuitry, logic, means, or instructions for determining whether the size of the data satisfies a second threshold, wherein setting the second region size can be based at least in part on determining that the size of the data satisfies the second threshold.

[0117] In some examples of the method 600 and the apparatus described herein, the second threshold can be associated with data stored in the block of memory cells, a second block of memory cells, or both.

[0118] Some examples of the method 600 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for resetting the first region size to a default region size based at least in part on executing the received command.

[0119] Some examples of the method 600 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for transferring second data from the block of memory cells to a second block of memory cells after setting the first region size, the second data being different from the data associated with the received command.

[0120] In some examples of the method 600 and the apparatus described herein, the block of memory cells includes single-level cells and the second block of memory cells includes triple-level cells.

[0121] In some examples of the method 600 and the apparatus described herein, the received command includes an unmap command.

[0122] It should be noted that the methods described above describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more of the methods can be combined.

[0123] An apparatus is described. The apparatus can include a memory device; and a controller coupled with the memory device and configured such that the apparatus: receives, at the memory device, a command to remove data associated with a block of memory cells; sets, based at least in part on receiving the command, a first region size based at least in part on a size of the data, the first region size including a first set of memory cells in the block of memory cells and corresponding to a first amount of space including data to be removed based at least in part on the received command; determines whether the first region size satisfies a threshold based at least in part on an available region size corresponding to a second amount of space available for storing data in the block of memory cells; sets, based at least in part on determining that the first region size satisfies the threshold, a second region size, the second region size including a second set of memory cells in the block of memory cells, wherein the second region size is less than or equal to the available region size; and executes the received command based at least in part on setting the second region size.

[0124] In some examples, the device can include setting the available region size based at least in part on the second amount of space and a third region size corresponding to a third amount of space associated with a write boost at the memory device.

[0125] In some examples, the device can include determining whether the second amount of space exceeds a second threshold and setting the third region size based at least in part on the determination that the second amount of space exceeds the second threshold.

[0126] In some examples, the device can include determining whether the size of the data can be greater than or equal to the available region size, wherein setting the second region size can be based at least in part on determining that the size of the data can be greater than or equal to the available region size.

[0127] In some examples, the device can include determining whether the size of the data satisfies a second threshold, wherein setting the second region size can be based at least in part on determining that the size of the data satisfies the second threshold.

[0128] In some examples of the device, the second threshold can be associated with data stored in the block of memory cells, a second block of memory cells, or both.

[0129] In some examples, the device can include resetting the first region size to a default region size based at least in part on executing the received command.

[0130] In some examples, the device can include transferring second data from the block of memory cells to a second block of memory cells after setting the first region size, the second data being different from the data associated with the received command.

[0131] In some examples of the device, the block of memory cells includes single-level cells and the second block of memory cells includes triple-level cells.

[0132] In some examples of the device, the received command includes an unmap command.

[0133] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, such signals can represent a bus of signals, where the bus can have a variety of bit widths.

[0134] The terms "in electronic communication," "in conductive contact," "connected," and "coupled" can refer to a relationship between components that supports the flow of signals between the components. Components are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. The conductive path between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) can be an open circuit or a closed circuit at any given time, based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components, or the conductive path between connected components can be an indirect conductive path that can include intervening components such as switches, transistors, or other components. In some examples, the flow of signals between connected components can be interrupted, such as using one or more intervening components such as switches or transistors, for a period of time.

[0135] The term "coupled" refers to the condition of components moving from an open circuit relationship between the components, in which signals are currently not able to be communicated between the components via a conductive path, to a closed circuit relationship between the components, in which signals are able to be communicated between the components via the conductive path. If a component such as a controller couples other components together, the component initiates a change that allows signals to flow between the other components via a conductive path that previously did not permit the flow of signals.

[0136] The term "isolated" refers to a relationship between components in which signals are currently not able to flow between the components. If there is an open circuit between components, the components are isolated from each other. For example, components that are separated by a switch located between the two components are isolated from each other if the switch is open. If a controller isolates two components, the controller implements a change that prevents signals from flowing between the components using a conductive path that previously permitted the flow of signals.

[0137] The terms "if," "when," "based on," or "based at least in part on" can be used interchangeably. In some examples, the terms "if," "when," "based on," or "based at least in part on" are interchangeable if the terms are used to describe a conditional nature of an action, a process, or a connection between parts of a process.

[0138] The term "in response to" can refer to a condition or action that occurs at least partially (if not entirely) as a result of a prior condition or action. For example, a first condition or action can occur, and as a result of the occurrence of the prior condition or action (whether directly after the first condition or action or after the occurrence of one or more other intervening conditions or actions after the first condition or action), a second condition or action can occur at least partially.

[0139] Additionally, the term "directly responsive to" or "directly responsive" can refer to a condition or action that occurs as a direct result of a prior condition or action. In some examples, a first condition or action can occur, and a second condition or action can occur directly as a result of the prior condition or action occurring, independent of whether other conditions or actions occur. In some examples, a first condition or action can occur, and a second condition or action can occur directly as a result of the prior condition or action occurring, such that no other intervening conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intervening steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being "based on," "based at least in part on," or "responsive to" some other step, action, event, or condition can additionally or alternatively be "directly responsive to" or "directly responsive" to such other condition or action, for example, in alternative examples.

[0140] Devices discussed herein that include a memory array can be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as a silicon-on-glass (SOG) or a silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during initial formation or growth of the substrate, by ion implantation, or by any other doping means.

[0141] Switching components or transistors discussed herein can represent field effect transistors (FETs) and include three-terminal devices that include a source, a drain, and a gate. The terminals can be connected to other electronic elements by conductive materials such as metals. The source and drain can be electrically conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can make the channel electrically conductive. A transistor can be "turned on" or "activated" if a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate. A transistor can be "turned off" or "deactivated" if a voltage less than the threshold voltage of the transistor is applied to the transistor gate.

[0142] The description set forth herein describes example configurations and does not represent all examples that can be practiced under the claims. The term "exemplary" used herein means "serving as an example, instance, or illustration," and not "preferred" or "advantageous over other examples." The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts described herein.

[0143] In the drawings, like reference numbers can indicate similar components or features. Additionally, various components of the same type can be distinguished by following the designation with a hyphen and a second designation that distinguishes among the similar components. If only the first designation is used in the specification, the description is applicable to any of the similar components having the same first designation irrespective of the second designation.

[0144] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

[0145] The various illustrative blocks and components described in connection with the disclosure herein can be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein, for example. The general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine, for example. The processor can be a combination of computing devices working together, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0146] As used herein, including in the claims, “or” as used in a list of items prefaced by “at least one of’ indicates a disjunctive list such that, for example, a list of “at least one of A, B, or C” means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” is not meant to be limiting. For example, an example step that is described as being “based on condition A” can be based on both condition A and condition B, without departing from the scope of the disclosure. In other words, as used herein, the phrase “based on” is intended to be interpreted as “based at least in part on.”

[0147] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0148] The description herein is presented to enable a person of ordinary skill in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is intended to be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus, comprising: a memory device; and a controller coupled with the memory device and configured to cause the apparatus to: receive, at the memory device, a command to remove data associated with a block of memory cells; based at least in part on receiving the command, set a first region size based at least in part on a size of the data, the first region size comprising a first set of memory cells in the block of memory cells and corresponding to a first amount of space comprising data to be removed based at least in part on the received command; determine whether the first region size satisfies a threshold based at least in part on an available region size corresponding to a second amount of space available for storing data in the block of memory cells; based at least in part on determining that the first region size satisfies the threshold, set a second region size, the second region size comprising a second set of memory cells in the block of memory cells, wherein the second region size is less than or equal to the available region size; and based at least in part on setting the second region size, execute the received command.

2. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: based at least in part on the second amount of space and a third region size corresponding to a third amount of space associated with a write boost at the memory device, set the available region size.

3. The apparatus of claim 2, wherein the controller is further configured to cause the apparatus to: determine whether the second amount of space exceeds a second threshold; and based at least in part on determining that the second amount of space exceeds the second threshold, set the third region size.

4. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: determine whether the size of the data is greater than or equal to the available region size, wherein setting the second region size is based at least in part on determining that the size of the data is greater than or equal to the available region size.

5. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: determine whether the size of the data satisfies a second threshold, wherein setting the second region size is based at least in part on determining that the size of the data satisfies the second threshold.

6. The apparatus of claim 5, wherein the second threshold is associated with data stored in the block of memory cells, a second block of memory cells, or both.

7. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: based at least in part on executing the received command, reset the first region size to a default region size.

8. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: after setting the first region size, transfer second data from the block of memory cells to a second block of memory cells, the second data being different from the data associated with the received command.

9. The apparatus of claim 8, wherein: The block of memory cells includes single-level cells; and The second block of memory cells includes triple-level cells.

10. The device of claim 1, wherein the received command comprises an unmap command.

11. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive, at the electronic device, a command to remove data associated with a block of memory cells; based at least in part on receiving the command, set a first region size based at least in part on a size of the data, the first region size comprising a first set of memory cells in the block of memory cells and corresponding to a first amount of space comprising data to be removed based at least in part on the received command; determine whether the first region size satisfies a threshold based at least in part on an available region size corresponding to a second amount of space available for storing data in the block of memory cells; based at least in part on determining that the first region size satisfies the threshold, set a second region size, the second region size comprising a second set of memory cells in the block of memory cells, wherein the second region size is less than or equal to the available region size; and based at least in part on setting the second region size, execute the received command.

12. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: based at least in part on the second amount of space and a third region size corresponding to a third amount of space associated with a write booster at the electronic device, set the available region size.

13. The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: determine whether the second amount of space exceeds a second threshold; and based at least in part on the determination that the second amount of space exceeds the second threshold, set the third region size.

14. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: determine whether the size of the data is greater than or equal to the available region size, wherein setting the second region size is based at least in part on determining that the size of the data is greater than or equal to the available region size.

15. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: determine whether the size of the data satisfies a second threshold, wherein setting the second region size is based at least in part on determining that the size of the data satisfies the second threshold.

16. The non-transitory computer-readable medium of claim 15, wherein the second threshold is associated with data stored in the block of memory cells, a second block of memory cells, or both.

17. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: reset the first region size to a default region size based at least in part on executing the received command.

18. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: after setting the first region size, transfer second data from the block of memory cells to a second block of memory cells, the second data being different from the data associated with the received command.

19. The non-transitory computer-readable medium of claim 18, wherein: the block of memory cells comprises single-level cells; and the second block of memory cells comprises triple-level cells.

20. A method comprising: receiving, at a memory system, a command to remove data associated with a block of memory cells; based at least in part on receiving the command, setting a first region size based at least in part on a size of the data, the first region size comprising a first set of memory cells in the block of memory cells and corresponding to a first amount of space comprising data to be removed based at least in part on the received command; determining whether the first region size satisfies a threshold based at least in part on an available region size corresponding to a second amount of space available for storing data in the block of memory cells; based at least in part on determining that the first region size satisfies the threshold, setting a second region size, the second region size comprising a second set of memory cells in the block of memory cells, wherein the second region size is less than or equal to the available region size; and based at least in part on setting the second region size, executing the received command.

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