Mos capacitor layout and forming method and verification method thereof

Abstract

Embodiments of the present application relate to the field of semiconductor, and particularly relate to a MOS capacitor layout, a forming method thereof and a verification method. The MOS capacitor layout comprises: a working layer, the working layer comprises an active layer, a gate layer, a source layer located on one side of the gate layer, and a drain layer located on the other side of the gate layer, and the gate layer, the source layer and the drain layer are located directly above the active layer; and a capacitor identification layer, the capacitor identification layer covers at least part of the working layer. The embodiments of the present application are beneficial to improving the efficiency of LVS consistency verification.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and in particular to a MOS capacitor layout and a forming method and a verification method thereof. BACKGROUND

[0002] With the construction of integrated circuits becoming more complex and semiconductor manufacturing processes becoming more sophisticated, a large number of semiconductor devices can be integrated in an integrated circuit. The integrated circuit includes a large number of components, such as transistors, resistors, capacitors, etc.

[0003] The capacitor can be composed of one or more MOS (Metal-Oxide-Semiconductor) tubes, and the layout of the MOS tube layout is closely related to the performance of the capacitor. In order to verify whether the layout meets the requirements, layout versus schematic (LVS) consistency verification can be performed to verify whether the layout and the corresponding schematic of the capacitor are the same.

[0004] However, the current LVS verification for MOS capacitor has the problem of low verification efficiency. SUMMARY

[0005] Embodiments of the present application solve the technical problem of providing a MOS capacitor layout and a forming method and a verification method thereof to at least solve the problem of low LVS verification efficiency.

[0006] According to some embodiments of the present application, in one aspect, a MOS capacitor layout is provided, comprising: a working layer, the working layer comprising an active layer, a gate layer, a source layer located on one side of the gate layer, and a drain layer located on the other side of the gate layer, the gate layer, the source layer and the drain layer are located directly above the active layer; a capacitor identification layer, the capacitor identification layer covers at least part of the area of the working layer.

[0007] In addition, the capacitor identification layer covers all areas of the working layer.

[0008] In addition, the capacitor identification layer comprises: a first identification layer, the first identification layer is directly opposite to all areas of the working layer; a second identification layer, the second identification layer is located at the periphery of the working layer.

[0009] In addition, the capacitor identification layer is rectangular.

[0010] In addition, the capacitor identification layer has a first boundary extending in a first direction and a second boundary extending in a second direction, the first direction is perpendicular to the second direction, and the second boundary is connected to one of the first boundaries at both ends; the first boundary is flush with the boundary of the gate layer.

[0011] In addition, the second boundary is located at the periphery of the active layer.

[0012] In addition, the capacitance identification layer is rectangular, and the width-length ratio of the capacitance identification layer is the same as the channel width-length ratio of the MOS transistor corresponding to the working layer.

[0013] According to some embodiments of the present application, another aspect of the present application provides a method for forming a MOS transistor capacitance layout, comprising: establishing a working layer, the working layer comprising an active layer, a gate layer, a source layer located on one side of the gate layer, and a drain layer located on the other side of the gate layer, the gate layer, the source layer and the drain layer being located directly above the active layer; and establishing a capacitance identification layer, the capacitance identification layer covering at least part of the working layer.

[0014] In addition, the method for establishing the capacitance identification layer comprises: obtaining the channel width-length ratio of the MOS transistor capacitance corresponding to the working layer; and based on the channel width-length ratio, establishing the capacitance identification layer in the form of a rectangle, and the width-length ratio of the rectangle is the same as the channel width-length ratio.

[0015] According to some embodiments of the present application, still another aspect of the present application provides a layout principle Figure One consistency verification method, comprising: constructing an equivalent circuit diagram of an equivalent total capacitance of a MOS transistor capacitance; constructing at least two MOS transistor capacitance layouts as described in the above embodiments; based on the capacitance identification layer, identifying all the MOS transistor capacitance layouts; obtaining the actual total capacitance of the capacitance corresponding to all the identified MOS transistor capacitance layouts, and performing consistency verification on the actual total capacitance and the equivalent total capacitance.

[0016] In addition, the method for constructing at least two MOS transistor capacitance layouts comprises: constructing at least two MOS transistor capacitance layouts with different channel width-length ratios.

[0017] In addition, the capacitance identification layer is rectangular, and the width-length ratio of the capacitance identification layer is the same as the channel width-length ratio of the MOS transistor corresponding to the MOS transistor capacitance layout; and identifying all the MOS transistor capacitance layouts comprises: identifying the width-length ratio of the capacitance identification layer corresponding to each MOS transistor capacitance layout, and taking the width-length ratio as the channel width-length ratio of the MOS transistor corresponding to the MOS transistor capacitance layout.

[0018] In addition, the method for constructing an equivalent circuit diagram of an equivalent total capacitance comprises: based on the equivalent total capacitance, generating a single MOS transistor, and the gate of the MOS transistor is connected to a working power supply, and the source and the drain are both connected to ground.

[0019] In addition, the method for obtaining the actual total capacitance comprises: obtaining a layout area of each identified MOS capacitor layout; obtaining a total layout area of all the identified MOS capacitor layouts based on each layout area; and obtaining the actual total capacitance based on the total layout area and a standard capacitance, wherein the standard capacitance is a capacitance value corresponding to a standard MOS capacitor layout having a channel width-length ratio of 1.

[0020] The technical scheme provided by the embodiments of the present application has the following advantages:

[0021] In the technical scheme of the MOS capacitor layout provided by the embodiments of the present application, the capacitor identification layer is arranged to cover at least part of the working layer of the MOS transistor, so that different MOS capacitor layouts can be identified at the same time, thereby shortening the time required for positioning different MOS capacitor layouts, and improving the efficiency of LVS consistency verification. BRIEF DESCRIPTION OF DRAWINGS

[0022] One or more embodiments are illustrated by way of example in the drawings in which like reference numerals indicate like elements, and in which:

[0023] Figure 1 is a circuit schematic diagram;

[0024] Figure 2 is a corresponding MOS transistor circuit layout; Figure 1

[0025] Figure 3 is a schematic diagram of a MOS capacitor layout provided by an embodiment of the present application;

[0026] Figure 4 is another structural schematic diagram of a MOS capacitor layout provided by an embodiment of the present application;

[0027] Figure 5 is a flowchart of a forming method of a MOS capacitor layout provided by an embodiment of the present application;

[0028] Figure 6 is a layout principle provided by an embodiment of the present application Figure One is a flowchart of a consistency verification process provided by an embodiment of the present application;

[0029] Figure 7 is an equivalent circuit diagram provided by an embodiment of the present application;

[0030] Figure 8 ​A structural schematic diagram of a MOS capacitor layout provided by an embodiment of the present application. DETAILED DESCRIPTION

[0031] As can be known from the background, the current LVS consistency verification for MOS capacitor has the problem of low efficiency.

[0032] In order to reasonably utilize the layout space, usually multiple MOS capacitor layouts are laid out, and the channel width-length ratios of the MOS transistors corresponding to each MOS capacitor layout can also be different. Correspondingly, the circuit schematic also includes multiple MOS transistors. Specifically, taking the need to lay out three MOS capacitor layouts as an example, Figure 1 A circuit schematic, Figure 2 corresponding to Figure 1 a MOS transistor circuit layout.

[0033] Referring to Figure 1 , the circuit schematic includes a first MOS transistor 11, a second MOS transistor 12, and a third MOS transistor 13, and the gates of the first MOS transistor 11, the second MOS transistor 12, and the third MOS transistor 13 are all electrically connected to a working power supply VDD, and the drains and the sources are all grounded VSS.

[0034] Referring to Figure 2 , the MOS capacitor layout includes a first layout 10, a second layout 20, and a third layout 30, and the first layout 10, the second layout 20, and the third layout 30 all include an active layer 21, a gate layer 22, a source layer 23 located on one side of the gate layer 22, and a drain layer 24 located on the other side of the gate layer 22; wherein the channel width-length ratio corresponding to the first layout 10 is the same as the channel width-length ratio of the first MOS transistor 11, the channel width-length ratio corresponding to the second layout 20 is the same as the channel width-length ratio of the second MOS transistor 12, and the channel width-length ratio corresponding to the third layout 30 is the same as the channel width-length ratio of the third MOS transistor 13.

[0035] During the consistency verification of the layout schematic, Figure One , the consistency verification of the first layout 10 and the first MOS transistor 11 is needed, the consistency verification of the second layout 20 and the second MOS transistor 12 is needed, and the consistency verification of the third layout 30 and the third MOS transistor 13 is needed. It is not difficult to find that the steps of such consistency verification are tedious, the more the number of MOS capacitor layouts is, the more the number of verification times required for consistency verification is, resulting in low efficiency of consistency verification, and the difficulty of consistency verification also increases with the increase of the number of MOS transistor layouts. In addition, for such consistency verification, when the corresponding circuit schematic is constructed, the same number of MOS transistors as the number of MOS capacitor layouts needs to be constructed, and the channel width-length ratios of different MOS transistors are different, which will also result in a long time to construct the circuit schematic, and accordingly will also affect the efficiency of the consistency verification.

[0036] The MOS capacitor layout provided by the embodiments of the present application includes a capacitor identification layer covering at least part of the working layer, which facilitates simultaneous identification of MOS capacitor layouts in different areas, thereby shortening the time for identifying MOS capacitor layouts and improving the efficiency of LVS verification.

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present application, many technical details are presented to make the readers better understand the present application. However, the technical solutions claimed by the present application can be implemented even without these technical details and based on various changes and modifications of the following embodiments.

[0038] Figure 3 A schematic diagram of the MOS capacitor layout provided by an embodiment of the present application.

[0039] Reference Figure 3 The MOS capacitor layout includes: a working layer 100, the working layer 100 including an active area (AA) layer 101, a gate layer 102, a source layer 103 located on one side of the gate layer 102, and a drain layer 104 located on the other side of the gate layer 102, the gate layer 102, the source layer 103, and the drain layer 104 all being located directly above the active area layer 101; and a capacitor identification layer 110, the capacitor identification layer 110 covering at least part of the working layer 100.

[0040] The capacitor identification layer 110 is arranged such that MOS capacitor layouts in different areas can be identified simultaneously, thereby reducing the time required for extracting parameter information of MOS capacitor layouts in different areas and shortening the time required for layout consistency verification, and improving the efficiency of consistency verification. Figure One

[0041] The MOS capacitor layout provided by the embodiments of the present application will be described in more detail below with reference to the drawings.

[0042] The working layer 100 is used to actually define the MOS capacitor corresponding to the MOS capacitor layout. Specifically, the working layer 100 can define the actual capacitance value of the MOS capacitor.

[0043] ​The active layer 101 can be rectangular in shape, and is used to define the shape and size of the active region of the MOS transistor. The source layer 103 and the drain layer 104 are distributed along the first direction X; the gate layer 102 can also be rectangular in shape, and the gate layer 102 is arranged across the active layer 101 along the second direction Y, so as to define the channel of the MOS transistor, and to ensure that the source layer 103 defines the source and the drain layer. The source layer 103 can be rectangular in shape, and is used to define the first conductive layer electrically connected to the source region of the MOS transistor; the drain layer 104 can also be rectangular in shape, and is used to define the second conductive layer electrically connected to the drain region of the MOS transistor.

[0044] The number of the source layers 103 is N, and the number of the drain layers 104 is also N, where N is an integer greater than or equal to 1. In other embodiments, the number of the source layers 103 and the number of the drain layers 104 can also be 1.

[0045] In some embodiments, the length of the gate layer 102 along the second direction Y can be greater than the length of the active layer 101, so as to avoid unnecessary electrical connection between the source region and the drain region. In other embodiments, the length of the gate layer 102 along the second direction Y can also be equal to the length of the active layer 101.

[0046] In addition, the width of the active layer 101 along the second direction Y is defined as the width W of the channel of the MOS transistor, and the width of the gate layer 102 along the first direction X is defined as the length L of the channel of the MOS transistor, so that the width-to-length ratio of the channel of the MOS transistor is W / L, which is directly related to the actual capacitance of the MOS transistor.

[0047] The capacitance identification layer 110 can be rectangular in shape. The capacitance identification layer 110 can cover all regions of the working layer 100, so that the capacitance identification layer 110 has a relatively large area, and thus the difficulty of identifying the capacitance identification layer 110 can be reduced. It can be understood that in other embodiments, the capacitance identification layer can only cover part of the regions of the working layer, as long as the capacitance identification layer can be identified.

[0048] In some embodiments, the capacitance identification layer 110 can include a first identification layer 111 opposite to all regions of the working layer 100, and a second identification layer 112 located at the periphery of the working layer 100. In this way, the area of the capacitance identification layer 110 is greater than the area of the working layer 100, which is conducive to reducing the difficulty of identifying the capacitance identification layer 110.

[0049] The shape of the first identification layer 111 can be rectangular, and the first identification layer 111 is coincident with the gate layer 102. The shape of the second identification layer 112 can be rectangular, and the second identification layer 112 is not only coincident with the source layer 103 and the drain layer 104, but also located at the periphery of the source layer 103 and the periphery of the drain layer 104. It can be understood that, in other embodiments, the second identification layer 112 can also only include the area coincident with the source layer 103 and the drain layer 104.

[0050] The capacitance identification layer 110 has a first boundary B1 extending along a first direction X and a second boundary B2 extending along a second direction Y. The first direction X can be perpendicular to the second direction Y, and the second boundary B2 is connected with a first boundary B1 at both ends. The first boundary B1 is flush with the boundary of the gate layer 102, that is, the boundary of the first identification layer 111 is flush with the boundary of the gate layer 102. In some embodiments, the second boundary B2 is located at the periphery of the active layer 101, that is, the boundary of the second identification layer 112 is located at the periphery of the active layer 101.

[0051] In some embodiments, the capacitance identification layer 110 is rectangular, and the width-length ratio of the capacitance identification layer 110 is the same as the channel width-length ratio of the MOS transistor corresponding to the work layer 100. In this way, by identifying the width-length ratio of the capacitance identification layer 110 as the channel width-length ratio of the MOS transistor, the time required for identifying the width-length ratio of the MOS transistor corresponding to the MOS transistor layout is saved, which is conducive to further improving the time of LVS consistency verification and further improving the efficiency of LVS consistency verification.

[0052] Figure 4 Another structural schematic diagram of the MOS transistor capacitance layout provided by the embodiments of the present application is shown in FIG. 6. As shown in FIG. 6, the work layer 100 can also be located in the capacitance identification layer 110 in the orthographic projection on the surface where the capacitance identification layer 110 is located, and the width of the work layer 100 along the second direction Y is less than the width of the capacitance identification layer 110. Figure 4

[0053] The MOS transistor capacitance layout provided by the above embodiments is conducive to shortening the time of identifying different MOS transistor capacitance layouts in the LVS consistency verification process, thereby improving the efficiency of LVS consistency verification.

[0054] The embodiments of the present application also provide a forming method of the MOS transistor capacitance layout, which can be used to form the MOS transistor capacitance layout provided by the above embodiments. The forming method of the MOS transistor capacitance layout provided by the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, in the following embodiments, the same or corresponding technical features as those in the foregoing embodiments can refer to the detailed description of the foregoing embodiments, which will not be described herein.

[0055] Figure 5 ​A flowchart of a method for forming a MOS capacitor layout is provided in the embodiments of the present application.

[0056] Referring to Figure 5 , the method for forming a MOS capacitor layout comprises the following steps:

[0057] Referring to Figure 3 and Figure 5 , step S11, a working layer 100 is established, the working layer 100 comprises an active layer 101, a gate layer 102, a source layer 103 located on one side of the gate layer 102, and a drain layer 104 located on the other side of the gate layer 102, the gate layer 102, the source layer 103 and the drain layer 104 are all located directly above the active layer 101.

[0058] Specifically, the active layer 101 and the gate layer 102 are established in sequence, and the gate layer 102 spans the active layer 101 in the second direction Y; in addition, the source layer 103 also has an electrical connection relationship with the active layer 101 located on one side of the gate layer 102, and the drain layer 104 has an electrical connection relationship with the active layer 101 located on the other side of the gate layer 102.

[0059] Referring to Figure 3 and Figure 5 , step S12, a capacitor identification layer 110 is established, the capacitor identification layer 110 covers at least part of the area of the working layer 100.

[0060] In some embodiments, the working layer 100 can be established first, and then the capacitor identification layer 110 is established. In addition, the method for establishing the capacitor identification layer 110 can comprise: obtaining the channel width-length ratio of the MOS capacitor corresponding to the working layer 100; based on the channel width-length ratio, establishing a rectangular capacitor identification layer 110, and the width-length ratio of the rectangle is the same as the channel width-length ratio.

[0061] In other embodiments, the capacitor identification layer 110 can be established first, and then the working layer 100 is established.

[0062] The corresponding relationship between the capacitor identification layer 110 and the working layer 100 can be referred to the detailed description of the foregoing embodiments, which will not be described here.

[0063] Correspondingly, the embodiments of the present application also provide a layout principle Figure One consistency verification method, which can use the MOS capacitor layout provided by the above-mentioned embodiments for LVS consistency verification. The layout principle Figure One consistency verification provided by the embodiments of the present application will be described in detail below, and it should be noted that the same or corresponding technical features in the following embodiments and the foregoing embodiments can refer to the detailed description of the foregoing embodiments, which will not be described here.

[0064] Figure 6 Layout principle provided for the embodiments of the present application Figure One Flowchart of the consistency verification, Figure 7 Equivalent circuit diagram provided for the embodiments of the present application, Figure 8 Structure diagram of the MOS capacitor layout provided for the embodiments of the present application.

[0065] In combination with reference Figure 6 And Figure 7 Step S21, constructing the equivalent circuit diagram of the equivalent capacitance of the MOS capacitor.

[0066] Specifically, when designing the MOS capacitor required by the integrated circuit, the engineer will first construct the equivalent circuit diagram according to the actual total capacitance required by the integrated circuit. The method of constructing the equivalent circuit diagram 200 of the equivalent total capacitance can include: generating a single MOS transistor 201 based on the equivalent total capacitance, the gate of the MOS transistor 201 is connected to the working power supply VDD, and the source and drain are both connected to the ground VSS. In addition, constructing the MOS capacitor also includes designing the equivalent channel width-length ratio of the MOS transistor 201.

[0067] In combination with reference Figure 6 And Figure 8 Step S22, constructing at least two MOS capacitor layouts 300.

[0068] Each MOS capacitor layout 300 has a capacitance identification layer 310. Specifically, based on the equivalent total capacitance and the layout space limitation, the method provided in the foregoing embodiments is used to construct a plurality of MOS capacitor layouts 300. In this way, MOS capacitor layouts of different sizes can be arranged in different areas, so that the layout space is reasonably utilized.

[0069] In some embodiments, the method of constructing at least two MOS capacitor layouts can include: constructing at least two MOS capacitor layouts with different channel width-length ratios. In one example, the method of constructing the MOS capacitor layout includes: constructing a first MOS capacitor layout 301 with a first channel width-length ratio, which can be 2 / 2; constructing a second MOS capacitor layout 302 with a second channel width-length ratio, which can be 4 / 4; and constructing a third MOS capacitor layout 303 with a third channel width-length ratio, which can be 8 / 8.

[0070] In addition, the gate layer of each MOS capacitor layout 300 is electrically connected to the working power supply, and the source layer and the drain layer of each MOS capacitor layout are grounded.

[0071] In combination with reference Figure 6 And Figure 8S23, all MOS capacitor layout 300 is identified based on the capacitance identification layer 310.

[0072] Since each MOS capacitor layout 300 has a capacitance identification layer 310, all MOS capacitor layouts 300 can be identified at the same time by identifying the capacitance identification layer 310, which is beneficial to shorten the time required for positioning the MOS capacitor layout 300.

[0073] In some embodiments, the capacitance identification layer 310 is rectangular, and the aspect ratio of each capacitance identification layer 310 can be the same as the aspect ratio of the channel of the corresponding MOS transistor of the corresponding MOS capacitor layout; identifying all MOS capacitor layouts 300 further includes identifying the aspect ratio of the capacitance identification layer 310 corresponding to each MOS capacitor layout, and taking the aspect ratio as the aspect ratio of the channel of the MOS transistor corresponding to the MOS capacitor layout.

[0074] S24, the actual total capacitance of the capacitance corresponding to all identified MOS capacitor layouts is obtained, and consistency verification is performed on the actual total capacitance and the equivalent total capacitance.

[0075] Specifically, if the actual total capacitance and the equivalent total capacitance are consistent, it indicates that the capacitance of the MOS capacitor layout meets the design requirements. If there is a deviation between the actual total capacitance and the equivalent total capacitance, it indicates that the capacitance of the MOS capacitor layout does not meet the design requirements. It should be noted that the "consistent" described herein includes the case of being exactly the same, and also includes the case that the difference between the actual total capacitance and the equivalent total capacitance is within the tolerance value.

[0076] In some embodiments, the method of obtaining the actual total capacitance can include: obtaining the layout area of each identified MOS capacitor layout; based on each layout area, obtaining the total layout area of all identified MOS capacitor layouts; based on the total layout area and the standard capacitance, obtaining the actual total capacitance, wherein the standard capacitance is the capacitance value corresponding to the standard MOS capacitor layout, and the standard MOS capacitor layout has a channel aspect ratio of 1. Wherein, the total layout area can be determined based on the aspect ratio of the aforementioned identified capacitance identification layer.

[0077] Specifically, the standard MOS capacitor layout has a standard capacitance Cg, each MOS capacitor layout has a corresponding actual capacitance C = AREA * Cg, AREA is the product of the corresponding channel width and length, so the sum of the actual capacitance of all MOS capacitor layouts is the actual total capacitance. And the actual total capacitance is actually the sum of the product of each channel width and length.

[0078] The verification method provided by the above embodiments can identify different MOS capacitor layout at one time, thereby shortening the time of LVS consistency verification and reducing the complexity of LVS consistency verification.

[0079] On the other hand, for the equivalent circuit diagram with only one MOS transistor, different sizes of MOS capacitor layout can be arranged in different regions according to actual layout space, thereby saving layout space, reducing the size of the integrated circuit, meeting the development trend of miniaturization of the integrated circuit, and meanwhile, not increasing the difficulty of LVS consistency verification.

[0080] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present application, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make changes and modifications without departing from the spirit and scope of the present application, and therefore, the protection scope of the present application should be limited by the scope defined in the claims.

Claims

1. A MOSFET capacitor layout, characterized in that, include: The working layer includes an active layer, a gate layer, a source layer located on one side of the gate layer, and a drain layer located on the other side of the gate layer. The gate layer, the source layer, and the drain layer are all located directly above the active layer. A capacitance recognition layer, wherein the capacitance recognition layer covers at least a portion of the working layer; The capacitor identification layer is rectangular, and the aspect ratio of the capacitor identification layer is the same as the aspect ratio of the channel of the MOS transistor corresponding to the working layer.

2. The MOS transistor capacitor layout as described in claim 1, characterized in that, The capacitance recognition layer covers all areas of the working layer.

3. The MOS transistor capacitor layout as described in claim 2, characterized in that, The capacitance recognition layer includes: a first recognition layer, which is directly opposite all areas of the working layer; and a second recognition layer, which is located on the periphery of the working layer.

4. The MOS transistor capacitor layout as described in claim 1 or 2, characterized in that, The capacitance recognition layer is rectangular.

5. The MOS transistor capacitor layout as described in claim 4, characterized in that, The capacitor recognition layer has a first boundary extending along a first direction and a second boundary extending along a second direction, the first direction being perpendicular to the second direction, and the two ends of the second boundary being connected to a first boundary respectively; the first boundary is flush with the boundary of the gate layer.

6. The MOS transistor capacitor layout as described in claim 5, characterized in that, The second boundary is located on the periphery of the active layer.

7. A method for forming a MOS transistor capacitor layout as described in any one of claims 1-6, characterized in that, include: A working layer is established, which includes an active layer, a gate layer, a source layer located on one side of the gate layer, and a drain layer located on the other side of the gate layer. The gate layer, the source layer, and the drain layer are all located directly above the active layer. A capacitance recognition layer is established, which at least covers a portion of the working layer; The method for establishing the capacitance recognition layer includes: Obtain the channel width-to-length ratio of the MOS transistor capacitor corresponding to the working layer; Based on the channel width-to-length ratio, a rectangular capacitor recognition layer is established, and the width-to-length ratio of the rectangle is the same as that of the channel.

8. A method for verifying the consistency of a layout schematic, characterized in that, include: Construct the equivalent circuit diagram of the total equivalent capacitance of the MOSFET capacitor; Construct at least two MOS transistor capacitor layouts as described in any one of claims 1-6; Based on the capacitor identification layer, all the MOS transistor capacitor layouts are identified; Obtain the actual total capacitance of all the capacitors corresponding to the identified MOS transistor capacitor layouts, and verify the consistency between the actual total capacitance and the equivalent total capacitance; The method for constructing at least two MOS transistor capacitor layouts includes: constructing at least two MOS transistor capacitor layouts with different channel width-to-length ratios; The capacitor identification layer is rectangular, and its aspect ratio is the same as the channel aspect ratio of the MOS transistor corresponding to the MOS transistor capacitor layout; identifying all the MOS transistor capacitor layouts includes: Identify the width-to-length ratio of the capacitor identification layer corresponding to each MOS transistor capacitor layout, and use the width-to-length ratio as the channel width-to-length ratio of the MOS transistor corresponding to the MOS transistor capacitor layout.

9. The verification method as described in claim 8, characterized in that, Methods for constructing the equivalent circuit diagram of the equivalent total capacitance include: Based on the equivalent total capacitance, a single MOS transistor is generated, and the gate of the MOS transistor is connected to the operating power supply, while the source and drain are both grounded.

10. The verification method as described in claim 8, characterized in that, The method for obtaining the actual total capacitance includes: Obtain the layout area of ​​each identified MOS transistor capacitor layout; Based on the area of ​​each of the aforementioned layouts, the total area of ​​all identified MOS transistor and capacitor layouts is obtained; Based on the total area of ​​the layout and the standard capacitor, the actual total capacitance is obtained, wherein the standard capacitor is the capacitance value corresponding to the standard MOS transistor capacitor layout, and the standard MOS transistor capacitor layout has a channel width-to-length ratio of 1.

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