An Optimization Method for Grayscale Image Mean Preprocessing

Abstract

This invention provides an optimized method for grayscale image mean preprocessing. For grayscale images, 128 image data points are loaded each time. One register loads 16 8-bit data points, using eight variable registers: vrd0, vrd2, vrd4, vrd6, vrd8, vrd10, vrd12, and vrd14. The loaded register data is then converted to 16 bits, meaning 16 registers are used to store the data. These variable registers are reused, and eight more variable registers are added to generate vrd0, vrd1, ..., vrd12. 5. Use a register `sum_h0` to accumulate 16-bit data. When `sum_h0` accumulates 256 times, shift the data right by 8 bits (equivalent to dividing by 256). Then, use a new register `sum_h1` to accumulate the shifted `sum_h0`, while `sum_h0` is initialized to 0. Then, re-accumulate the newly loaded data. Use `sum_h1` to accumulate the shifted `sum_h0`. When `sum_h1` accumulates 256 times, save the result of `sum_h1` to an array. Finally, accumulate the data in the array again and calculate the average. This optimization improves speed by 40 times.

Description

Technical Field

[0001] This invention relates to the field of image processing technology, and in particular to an optimized method for grayscale image mean preprocessing. Background Technology

[0002] In existing image processing technologies, especially for grayscale images or single-channel images, such as infrared images acquired for liveness detection, which are single-channel grayscale images, some technologies convert color images into single-channel grayscale images as input to accelerate processing. Accumulation and averaging methods are frequently used in the processing, but ordinary addition and averaging are very slow, and the speed of averaging in existing technologies slows down the overall processing speed. The common method on chips is to continuously add the entire image data to a single value before averaging, which is time-consuming and does not utilize SIMD for averaging. Furthermore, no SIMD averaging implementation has been found on other chips. Some other averaging applications use a method of loading 16 8-bit data points, converting the original 8-bit data to 32-bit, then grouping them into sets of 4, accumulating them using SIMD, then loading another 16 data points, converting them to 16 bits again, accumulating them again, and so on, until finally accumulating all the data in each group and then averaging. This method is also very inefficient.

[0003] The following are commonly used terms in the prior art:

[0004] 1. Mean: The mean generally refers to the average. The mean, a statistical term, is a measure of central tendency in a set of data. It is calculated by summing all the data points in a set and dividing by the number of data points. It is an indicator reflecting the central tendency of data. The key to solving word problems involving the mean is determining the "total quantity" and the total number of parts corresponding to that total quantity.

[0005] 2. Grayscale image: An image with only one channel.

[0006] 3. SIMD (Single Instruction Multiple Data) instructions are a type of instruction that performs calculations using a vector-based approach. This means that a single instruction can execute multiple data streams, which can often improve program execution speed. A SIMD instruction can be understood as executing one instruction to perform an operation on an array of a specified size. In a 128-bit SIMD instruction, the array size is defined in 128 bits, storing 16 eight-bit data elements, 4 three-bit data elements, or 8 sixteen-bit data elements. For example, adding two arrays can be done directly with a single SIMD instruction. Summary of the Invention

[0007] To address the problems in the prior art, the purpose of this application is to improve the speed of averaging calculations, achieving a 40-fold improvement.

[0008] Specifically, this invention provides an optimized method for grayscale image mean preprocessing. The method loads 128 image data points at a time for grayscale images. One register can load 16 8-bit data points. Eight variable registers are used: vrd0, vrd2, vrd4, vrd6, vrd8, vrd10, vrd12, and vrd14. The loaded register data is then converted to 16 bits, meaning 16 registers are used to store the data. The variable registers are reused, and eight more variable registers are added, generating vrd0, vrd1, vrd2, vrd3, vrd4, vrd5, vrd6, vrd7, vrd8, and vrd9. The data is stored in registers vrd10, vrd11, vrd12, vrd13, vrd14, and vrd15. A register sum_h0 is used to accumulate 16 bits of data. When sum_h0 accumulates 256 times, the data is right-shifted by 8 bits (equivalent to dividing by 256). A new register sum_h1 is then used to accumulate the shifted sum_h0, while sum_h0 is initialized to 0. New data is then added again. The shifted sum_h0 is then accumulated using sum_h1. When sum_h1 accumulates 256 times, the result is saved to an array. Finally, the data in the array is accumulated again, and the average is calculated.

[0009] The method further includes:

[0010] S1, Initialization and Use of Variable Register Declarations: Let vri0 be the selection register that converts the first 8 data in the 8-bit register into a 16-bit register, and vri1 be the selection register that converts the last 8 data in the 8-bit register into a 16-bit register.

[0011] The preprocessed data is indata, with width and height, and the total number of data is piel_count = width * height;

[0012] Let a data set be vsave[8], a regular temporary variable sum_int with mean value avg, and a calculator count that counts the cumulative sum of sum_h1, initially set to 0;

[0013] S2, load 128 image data into vrd0, vrd1, vrd2, vrd3, vrd4, vrd5, vrd6, vrd7, vrd8, vrd9, vrd10, vrd11, vrd12, vrd13, vrd14, vrd15, and then change the indata pointer, i.e., indata = indata + 128;

[0014] S3 uses a pre-defined selection order to convert data from 8 bits to 16 bits. Since there is no instruction in the instruction set to directly convert 8 bits to 16 bits, an arbitrary value instruction is needed to achieve this function. That is, two selection registers, vri0 and vri1, are set, and the specific selection order is pre-designed.

[0015] S4 uses a register sum_h0 to accumulate 16 bits of data. When the first accumulation needs to be initialized, the data in sum_h0 is 0.

[0016] S5. Repeat steps S2, S3, and S4 until the loop count reaches 256. Then, shift sum_h0, add the processed result to sum_h1, set the data in sum_h0 to 0, and increment count by 1.

[0017] S6. Repeat steps S2, S3, S4, and S5 until the loop count reaches 256. Save sum_h1 to vsave[8], sum the data in vsave[8] to sum_int, and set the data in sum_h1 to 0. Repeat steps S2, S3, S4, and S5 until all data has been calculated.

[0018] S7, calculate the mean: save the data of sum_h1 into vsave[8], sum the data of vsave[8] to sum_int, and the number of times it is accumulated is count. Then the mean is: avg=sum_int / count; sum_h1 is a register that contains 8 16-bit data. Take out the data and put it into array vsave[8]. Accumulate the 8 data in array vsave[8] to sum_int.

[0019] The method is applied to chips with SIMD instructions, and the corresponding instruction set is optimized. The length and width of the target being processed are multiples of 2048. The image mean preprocessing requires an accuracy error within 1. The corresponding instruction set used includes addition instructions, shift instructions, arbitrary value extraction instructions, division instructions, data loading instructions, and data saving instructions.

[0020] In step S2, the indata pointer is modified, further including a data loading instruction. The input is the data to be loaded, currently a pointer to the data indata. Starting from the memory location pointed to by indata (0, 16, ..., 96, 112), 128 bits of data are loaded. If it is 8 bits of data, 16 bits are loaded; if it is 16 bits of data, 8 bits are loaded; if it is 32 bits, 4 bits are loaded.

[0021] vrd0=ingenic_load(indata, 0);

[0022] vrd2=ingenic_load(indata, 16);

[0023] vrd4=ingenic_load(indata, 32);

[0024] vrd6=ingenic_load(indata, 48);

[0025] vrd8=ingenic_load(indata, 64);

[0026] vrd10=ingenic_load(indata, 80);

[0027] vrd12=ingenic_load(indata, 96);

[0028] vrd14=ingenic_load(indata, 112);

[0029] indata = indata + 128.

[0030] Step S3 further includes an arbitrary value selection instruction: selecting 4, 8, or 16 data points from variables vrd0, vrd2, ..., vrd12, vrd14 according to the numbers set by vri1 and vri0. When using this instruction, a permanent register vri1 or vir0 is required to select data at a specific location.

[0031] vrd1=ingenic_choise_h(vrd0, vrd0, vri1);

[0032] vrd0=ingenic_choise_h(vrd0, vrd0, vri0);

[0033] vrd3=ingenic_choise_h(vrd2,vrd2,vri1);

[0034] vrd2=ingenic_choise_h(vrd2,vrd2,vri0);

[0035] vrd5=ingenic_choise_h(vrd4,vrd4,vri1);

[0036] vrd4=ingenic_choise_h(vrd4,vrd4,vri0);

[0037] vrd7=ingenic_choise_h(vrd6,vrd6,vri1);

[0038] vrd6=ingenic_choise_h(vrd6,vrd6,vri0);

[0039] vrd9=ingenic_choise_h(vrd8,vrd8,vri1);

[0040] vrd8=ingenic_choise_h(vrd8,vrd8,vri0);

[0041] vrd11=ingenic_choise_h(vrd10,vrd10,vri1);

[0042] vrd10=ingenic_choise_h(vrd10,vrd10,vri0);

[0043] vrd13=ingenic_choise_h(vrd12,vrd12,vri1);

[0044] vrd12=ingenic_choise_h(vrd12,vrd12,vri0);

[0045] vrd15=ingenic_choise_h(vrd14,vrd14,vri1);

[0046] vrd14=ingenic_choise_h(vrd14,vrd14,vri0)。

[0047] Step S4 further includes an addition instruction. The input variables are sum_h0, vrd0, vrd1, ..., vrd14, vrd15. The output variable is sum_h0, which stores eight int16_t data. sum_h0 and vrd0 ... vrd15 also store eight int16_t data.

[0048] sum_h0=ingenic_add_h(sum_h0, vrd0);

[0049] sum_h0=ingenic_add_h(sum_h0, vrd1);

[0050] sum_h0=ingenic_add_h(sum_h0, vrd2);

[0051] sum_h0=ingenic_add_h(sum_h0, vrd3);

[0052] sum_h0=ingenic_add_h(sum_h0, vrd4);

[0053] sum_h0=ingenic_add_h(sum_h0, vrd5);

[0054] sum_h0=ingenic_add_h(sum_h0, vrd6);

[0055] sum_h0=ingenic_add_h(sum_h0, vrd7);

[0056] sum_h0=ingenic_add_h(sum_h0, vrd8);

[0057] sum_h0=ingenic_add_h(sum_h0, vrd9);

[0058] sum_h0=ingenic_add_h(sum_h0, vrd10);

[0059] sum_h0=ingenic_add_h(sum_h0, vrd11);

[0060] sum_h0=ingenic_add_h(sum_h0, vrd12);

[0061] sum_h0=ingenic_add_h(sum_h0, vrd13);

[0062] sum_h0=ingenic_add_h(sum_h0, vrd14);

[0063] sum_h0=ingenic_add_h(sum_h0, vrd15).

[0064] Step S5 further includes a right shift instruction, which shifts each element in the variable sum_h0 by 8 bits and outputs sum_h1. This instruction performs rounding operations, and then increments count by 1.

[0065] sum_h0=ingenic_shift_right(sum_h0, 8);

[0066] count += 1.

[0067] Therefore, the advantage of this application lies in providing a method for calculating the average of grayscale images. Using a maximum of 16-bit operations, a single SIMD instruction can accumulate 8 data points. This is significantly slower than accumulating 4 data points with a single SIMD instruction using a maximum of 32 bits. In preprocessing, fewer steps are used, with only one step converting 16 8-bit data points into 8 16-bit data points in two registers. Intermediate processing uses shifting instead of mean division; when the number of accumulations reaches 256, a shift operation is performed, effectively averaging the final mean across each 256-bit average, thus achieving a maximum of 16-bit operations and calculating the mean. In data loading, 128 data points are loaded at once, fully utilizing both available registers and bandwidth, improving overall speed. Processing 128 data points is also easier. Furthermore, the corresponding instruction set is optimized, achieving a 40-fold speed improvement. Attached Figure Description

[0068] The accompanying drawings, which are provided to further illustrate the invention and form part of this application, are not intended to limit the scope of the invention.

[0069] Figure 1 This is a flowchart of the method of the present invention. Detailed Implementation

[0070] To better understand the technical content and advantages of the present invention, the present invention will now be described in further detail with reference to the accompanying drawings.

[0071] The overall method or core idea of ​​this application can be implemented on any chip with SIMD instructions. Different chips will have some minor differences, such as variations in individual instructions, different instruction register bit widths, or the use of multiple instructions to implement a single instruction in the method. While the instructions themselves will differ from chip to chip, addition, subtraction, multiplication, and shifting operations are generally the same, but specific chips will have instructions with unique functions. Therefore, the specific chip used to reproduce this invention will be specified.

[0072] The specific embodiments of this application are implemented on Beijing Junzheng T30 and T31 chips, on which the implementation of this method can be completely reproduced.

[0073] like Figure 1 As shown, this invention relates to an optimization method for grayscale image mean preprocessing, the method further comprising:

[0074] S1, Initialization and Use of Variable Register Declarations: Let vri0 be the selection register that converts the first 8 data in the 8-bit register into a 16-bit register, and vri1 be the selection register that converts the last 8 data in the 8-bit register into a 16-bit register.

[0075] The preprocessed data is indata, with width and height, and the total number of data is piel_count = width * height;

[0076] Let a data set be vsave[8], a regular temporary variable sum_int with mean value avg, and a calculator count that counts the cumulative sum of sum_h1, initially set to 0;

[0077] S2, load 128 image data into vrd0, vrd1, vrd2, vrd3, vrd4, vrd5, vrd6, vrd7, vrd8, vrd9, vrd10, vrd11, vrd12, vrd13, vrd14, vrd15, and then change the indata pointer, i.e., indata = indata + 128;

[0078] S3 uses a pre-defined selection order to convert data from 8 bits to 16 bits. Since there is no instruction in the instruction set to directly convert 8 bits to 16 bits, an arbitrary value instruction is needed to achieve this function. That is, two selection registers, vri0 and vri1, are set, and the specific selection order is pre-designed.

[0079] S4 uses a register sum_h0 to accumulate 16 bits of data. When the first accumulation needs to be initialized, the data in sum_h0 is 0.

[0080] S5. Repeat steps S2, S3, and S4 until the loop count reaches 256. Then, shift sum_h0, add the processed result to sum_h1, set the data in sum_h0 to 0, and increment count by 1.

[0081] S6. Repeat steps S2, S3, S4, and S5 until the loop count reaches 256. Save sum_h1 to vsave[8], sum the data in vsave[8] to sum_int, and set the data in sum_h1 to 0. Repeat steps S2, S3, S4, and S5 until all data has been calculated.

[0082] S7, calculate the mean: save the data of sum_h1 into vsave[8], sum the data of vsave[8] to sum_int, and the number of times it is accumulated is count. Then the mean is: avg=sum_int / count.

[0083] Specifically, this embodiment can also be described as follows:

[0084] 1. Usage Requirements. This is used on Beijing Junzheng T30 and T31 chips. Using standard averaging calculations is very slow, severely impacting overall performance. Optimization using the corresponding instruction sets of the T30 and T31 chips achieves a 40-fold speed improvement. The target image dimensions (length x width) are multiples of 2048, and the required precision error for image averaging preprocessing is within 1. The corresponding instruction sets used on the T30 and T31 chips include addition, shift, arbitrary value retrieval, division, and data loading instructions. The instructions are as follows:

[0085] a) Addition instruction:

[0086] vrd = ingenic_add_h(vrs, vrt);

[0087] The input variables are vrs and vrt, and the output variable is vrd. vrd stores 8 int16_t data, and vrs and vrt store 8 int16_t data.

[0088] Equivalent operations:

[0089] vrd0:=vrs0+vrt0;

[0090] vrd1:=vrs1+vrt1;

[0091] ...

[0092] vrd7:=vrs7+vrt7;

[0093] b) Shift instruction: Shifts each element in the variable by i bits. This instruction has rounding capabilities.

[0094] Left shift instruction

[0095] vrd=ingenic_shift_left(vrs, i);

[0096] Right shift instruction

[0097] vrd=ingenic_shift_right(vrs,i);

[0098] c) Arbitrary value selection instruction: Selects 4, 8, or 16 data points from variables vrs and vrt according to the numbers set by vri. When using this instruction, a permanent register vri is required to select the data at a specific location.

[0099] vrd=ingenic_choise_h(vrs, vrt, vri);

[0100] d) Division instruction:

[0101] vrd = ingenic_div_d(vrs, vrt);

[0102] The input variables are vrs and vrt, and the output variable is the vrd register. vrd stores 16 int8_t values, and vrs and vrt each store 16 int8_t values. The result is rounded.

[0103] Equivalent operations:

[0104] vrd0:=vrs0 / vrt0;

[0105] vrd1:=vrs1 / vrt1;

[0106] ...

[0107] vrd7:=vrs7 / vrt7;

[0108] ...

[0109] Vrd15:=vrs15 / vrt15;

[0110] e) Load Data Instruction: The input is the data to be loaded, currently a pointer to the data, `indata`. Starting from the memory location `m` pointed to by `indata`, load 128 bits of data. If the data is 8 bits, load 16 bits; if it's 16 bits, load 8 bits; if it's 32 bits, load 4 bits. The data is loaded into the variable `vrd` register. Here, `m` is calculated in bytes, i.e., 8 bits per unit.

[0111] vrd=ingenic_load(indata, m);

[0112] f) Save data instruction: The register variable vrd contains the data to be saved, and the pointer savedata stores the data. The data in the register is stored starting from the pointer position. 128 bits of data from vrd are stored in savedata.

[0113] ingenic_save(vrd, savedata, m).

[0114] 2. Calculate the mean.

[0115] 1) For grayscale images, we load 128 image data points at a time. One register can load 16 8-bit data points, using 8 variable registers: vrd0, vrd2, vrd4, vrd6, vrd8, vrd10, vrd12, and vrd14. The loaded register data is then converted to 16 bits, meaning 16 registers are used to store the data. These variable registers are reused, adding 8 more variable registers, resulting in vrd0, vrd1, ..., vrd7, vrd8, ..., vrd15. A register sum_h0 is used to accumulate the 16-bit data. When sum_h0 accumulates 256 times, the data is right-shifted by 8 bits (equivalent to dividing by 256). A register sum_h1 is then used to accumulate the shifted sum_h0, while sum_h0 is initialized to 0. The newly loaded data is then re-accumulated. The shifted sum_h0 is summed using sum_h1. When sum_h1 has accumulated 256 times, the result is saved to an array. Finally, the data in the array are summed again, and the average is calculated. The specific implementation is as follows:

[0116] The variable registers used are declared as follows: vrd0, vrd1, ..., vrd7, vrd8, ..., vrd15, sum_h0, sum_h1. Let vri0 be the selection register that converts the first 8 data in the 8-bit register into a 16-bit register, and vri1 be the selection register that converts the last 8 data in the 8-bit register into a 16-bit register. The preprocessed data is indata, the data width is width, the length is height, and the total number of data is piel_count = width * height. Let a data set be vsave[8], a regular temporary variable sum_int with an average value of avg, and a calculator count that counts the cumulative sum_h1, initially set to 0.

[0117] a) Load 128 image data points into vrd0, vrd1, ..., vrd7, vrd8, ..., vrd15. Then modify the indata pointer: indata = indata + 128. Use the load data instruction, inputting the data to be loaded. Currently, the data pointer is indata. Starting from memory locations 0, 16, 32, 48, 64, 80, 96, 112, load 128 bits of data. If it is 8-bit data, load 16 bits; if it is 16-bit data, load 8 bits; if it is 32-bit data, load 4 bits. The data is loaded into registers vrd0, vrd2, ..., vrd12, vrd14, as shown below:

[0118] vrd0=ingenic_load(indata, 0);

[0119] vrd2=ingenic_load(indata, 16);

[0120] vrd4=ingenic_load(indata, 32);

[0121] vrd6=ingenic_load(indata, 48);

[0122] vrd8=ingenic_load(indata, 64);

[0123] vrd10=ingenic_load(indata, 80);

[0124] vrd12=ingenic_load(indata, 96);

[0125] vrd14=ingenic_load(indata, 112);

[0126] indata = indata + 128;

[0127] b) Use the pre-defined selection order to convert data from 8 bits to 16 bits. Since there is no instruction in the instruction set that can directly convert 8 bits to 16 bits, an arbitrary value instruction is needed to achieve this function. This involves setting two selection registers, vri0 and vri1, and pre-designing the specific selection order within them; using an arbitrary value instruction, it is represented as follows:

[0128] vrd1=ingenic_choise_h(vrd0, vrd0, vri1);

[0129] Using the arbitrary value retrieval instruction, select data from variables vrd0 and vrd1 according to the number set by vri1, and store it in vrd1; the following arbitrary value retrieval instructions follow the same pattern and will not be repeated.

[0130] vrd0=ingenic_choise_h(vrd0, vrd0, vri0);

[0131] vrd3=ingenic_choise_h(vrd2, vrd2, vri1);

[0132] vrd2=ingenic_choise_h(vrd2, vrd2, vri0);

[0133] vrd5=ingenic_choise_h(vrd4, vrd4, vri1);

[0134] vrd4=ingenic_choise_h(vrd4, vrd4, vri0);

[0135] vrd7=ingenic_choise_h(vrd6, vrd6, vri1);

[0136] vrd6=ingenic_choise_h(vrd6, vrd6, vri0);

[0137] vrd9=ingenic_choise_h(vrd8, vrd8, vri1);

[0138] vrd8=ingenic_choise_h(vrd8, vrd8, vri0);

[0139] vrd11=ingenic_choise_h(vrd10, vrd10, vri1);

[0140] vrd10=ingenic_choise_h(vrd10, vrd10, vri0);

[0141] vrd13=ingenic_choise_h(vrd12, vrd12, vri1);

[0142] vrd12=ingenic_choise_h(vrd12, vrd12, vri0);

[0143] vrd15=ingenic_choise_h(vrd14, vrd14, vri1);

[0144] vrd14=ingenic_choise_h(vrd14, vrd14, vri0);

[0145] c) Use a register sum_h0 to accumulate 16-bit data. When initializing the first sum, the data in sum_h0 is 0. Use the addition instruction as follows:

[0146] sum_h0=ingenic_add_h(sum_h0, vrd0);

[0147] Using the addition instruction, the input variables are sum_h0 and vrd0. The output variable is sum_h0, which stores 8 int16_t data. Both sum_h0 and vrd0 store 8 int16_t data. The following addition instructions follow the same pattern and will not be repeated.

[0148] sum_h0=ingenic_add_h(sum_h0, vrd1);

[0149] ...

[0150] sum_h0=ingenic_add_h(sum_h0, vrd15);

[0151] d) Repeat steps a), b), and c) until the loop reaches 256 times. Then, shift the data in sum_h0, add the result to sum_h1, set the data in sum_h0 to 0, and increment count.

[0152] sum_h0=ingenic_shift_right(sum_h0, 8);

[0153] count += 1;

[0154] e) Repeat a), b), c), d) until the loop count reaches 256 times, save sum_h1 to vsave[8], sum the data in vsave[8] to sum_int, set the data in sum_h1 to 0, and repeat a), b), c), d) until all data is calculated.

[0155] f) Save sum_h1 to vsave[8], sum the data in vsave[8] to sum_int, and the number of sums is count.

[0156] avg=sum_int / count.

[0157] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the embodiments of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An optimization method for mean pre-processing of gray scale images, characterized in that, The method is for a gray scale image, 128 image data are loaded each time, 16 8-bit data are loaded in a register, 8 variable registers are used, which are vrd0, vrd2, vrd4, vrd6, vrd8, vrd10, vrd12 and vrd14, and then the loaded register data are converted into 16 bits, that is, 16 registers are used to store data, the above variable registers are multiplexed, and 8 variable registers are further added, vrd0, vrd1, vrd2, vrd3, vrd4, vrd5, vrd6, vrd7, vrd8, vrd9, vrd10, vrd11, vrd12, vrd13, vrd14 and vrd15 are generated; a register sum_h0 is used to accumulate 16-bit data, when sum_h0 is accumulated 256 times, the data is right shifted by 8 bits, which is equivalent to division by 256, and then a new register sum_h1 is used to accumulate the shifted sum_h0, and sum_h0 is initialized to 0, and then the new loaded data is re-accumulated; sum_h1 is used to accumulate the shifted sum_h0, and when sum_h1 is accumulated 256 times, the result of sum_h1 is saved in an array; finally, the data of the array is re-accumulated, and the average value is calculated.

2. The optimization method of the gray scale image mean value preprocessing according to claim 1, characterized in that, The method further comprises: S1, initialization and declaration of a variable register used: vri0 is a selection register for converting the first 8 data in an 8-bit register into 16 bits, and vri1 is a selection register for converting the last 8 data in an 8-bit register into 16 bits; The preprocessed data is indata, the data width is width, the data length is height, and the total number of data is piel_count=width*height; A data group is vsave[8], a general temporary variable sum_int, an average value is avg, a calculator count for counting the number of times of sum_h1 accumulation, and count is initially 0; S2, 128 image data are loaded into vrd0, vrd1, vrd2, vrd3, vrd4, vrd5, vrd6, vrd7, vrd8, vrd9, vrd10, vrd11, vrd12, vrd13, vrd14 and vrd15, and then the indata pointer is changed, that is, indata=indata+128; S3, the data is converted from 8 bits to 16 bits using the set selection order, since there is no instruction in the instruction set for directly converting 8 bits to 16 bits, an arbitrary value taking instruction needs to be used to realize this function, that is, two selection registers vri0 and vri1 are set, and the specific selection order in them is designed in advance; S4, a register sum_h0 is used to accumulate 16-bit data, and the data in sum_h0 is 0 when the first accumulation and initialization are needed. S5, repeat steps S2, S3, S4 until the number of cycles reaches 256, then shift sum_h0, and add the result to sum_h1, and set the data in sum_h0 to 0, and count is incremented by 1; S6, repeat steps S2, S3, S4, S5 until the number of cycles reaches 256, then save sum_h1 to vsave[8], sum the data in vsave[8] to sum_int, and set the data in sum_h1 to 0; repeat steps S2, S3, S4, S5 until all data is calculated; S7, average: save the data in sum_h1 to vsave[8], sum the data in vsave[8] to sum_int, and the number of additions is count, then the average is avg=sum_int / count.

3. The optimization method of the gray scale image mean value preprocessing according to claim 2, characterized in that, The method is applied to a chip with simd instructions, and the corresponding instruction set is optimized, the target of the processing has a length*width of 2048 times, the required precision error of image mean preprocessing is within 1, and the corresponding instruction set used includes addition instructions, shift instructions, arbitrary value instructions, division instructions, data loading instructions, and data saving instructions.

4. The optimization method of the gray scale image mean value preprocessing according to claim 3, characterized in that, The addition instructions, shift instructions, arbitrary value instructions, division instructions, data loading instructions, and data saving instructions are as follows: a) addition instruction: as follows: vrd=ingenic_add_h(vrs,vrt); The input variables vrs and vrt are 8 int16_t data, and the output variable vrd is 8 int16_t data, Equivalent operation: vrd0:=vrs0+vrt0; vrd1:=vrs1+vrt1; …… vrd7:=vrs7+vrt7; b) shift instruction: shift each element in the variable by i bits, and the instruction has a rounding operation; Left shift instruction, as follows: vrd=ingenic_shift_left(vrs,i); Right shift instruction, as follows: vrd=ingenic_shift_right(vrs,i); c) arbitrary value instruction: select 4 or 8 or 16 data from variables vrs and vrt according to the number set by vri, and when using the instruction, a permanent register vri is needed to select the specific position of the data, vrd=ingenic_choise_h(vrs,vrt,vri); d) division instruction: as follows: vrd=ingenic_div_d(vrs,vrt); The input variables vrs and vrt are 16 int8_t data, and the output variable vrd is 16 int8_t data, and the result is rounded to the nearest integer; Equivalent operation: vrd0:=vrs0 / vrt0; vrd1 := vrs1 / vrt1; …… vrd7 := vrs7 / vrt7; …… Vrd15 := vrs15 / vrt15; e) Load data instruction: input the data to be loaded, the current data pointer indata, load 128-bit data from the position m in the memory pointed by the data indata, if it is 8-bit data, load 16, if it is 16-bit data, load 8, if it is 32-bit, load 4 data; the data is loaded into the variable vrd register; wherein m is calculated in byte, i.e. 8-bit as a unit, which is represented as follows: vrd = ingenic_load (indata, m); f) Save data instruction: the register variable vrd of the data to be saved, the savedata pointer of the stored data, store the data in the register from the position of the pointer, store the 128-bit data in vrd to savedata, which is represented as follows: ingenic_save (vrd, savedata, m).

5. The optimization method of the gray scale image mean value preprocessing according to claim 4, characterized in that, In step S2, the indata pointer is changed, further comprising a load data instruction, input the data to be loaded, the current data pointer indata, load 128-bit data from the position 0, 16, …… 96, 112 in the memory pointed by the data indata, if it is 8-bit data, load 16, if it is 16-bit data, load 8, if it is 32-bit, load 4 data, which is represented as follows: vrd0 = ingenic_load (indata, 0); vrd2 = ingenic_load (indata, 16); vrd4 = ingenic_load (indata, 32); vrd6 = ingenic_load (indata, 48); vrd8 = ingenic_load (indata, 64); vrd10 = ingenic_load (indata, 80); vrd12 = ingenic_load (indata, 96); vrd14 = ingenic_load (indata, 112); indata = indata + 128.

6. The optimization method of the gray scale image mean value preprocessing according to claim 5, characterized in that, The step S3 further comprises an arbitrary value instruction: select 4 or 8 or 16 data from the variable vrd0, vrd2, ……, vrd12, vrd14 and vrd0, vrd2, ……, vrd12, vrd14 according to the number set by vri1, vri0, when using the instruction, a permanent register vri1 or vri0 is required to occupy the data at the specific position, which is represented as follows: vrd1 = ingenic_choise_h (vrd0, vrd0, vri1); vrd0 = ingenic_choise_h (vrd0, vrd0, vri0); vrd3 = ingenic_choise_h (vrd2, vrd2, vri1) ; vrd2 = ingenic_choise_h (vrd2, vrd2, vri0) ; vrd5 = ingenic_choise_h (vrd4, vrd4, vri1) ; vrd4 = ingenic_choise_h (vrd4, vrd4, vri0) ; vrd7 = ingenic_choise_h (vrd6, vrd6, vri1) ; vrd6 = ingenic_choise_h (vrd6, vrd6, vri0) ; vrd9 = ingenic_choise_h (vrd8, vrd8, vri1) ; vrd8 = ingenic_choise_h (vrd8, vrd8, vri0) ; vrd11 = ingenic_choise_h (vrd10, vrd10, vri1) ; vrd10 = ingenic_choise_h (vrd10, vrd10, vri0) ; vrd13 = ingenic_choise_h (vrd12, vrd12, vri1) ; vrd12 = ingenic_choise_h (vrd12, vrd12, vri0) ; vrd15 = ingenic_choise_h (vrd14, vrd14, vri1) ; vrd14 = ingenic_choise_h (vrd14, vrd14, vri0).

7. The optimization method of the gray scale image mean value preprocessing according to claim 6, characterized in that, The step S4, further comprising addition instruction, input variable sum_h0, vrd0, vrd1, ……vrd14, vrd15 output variable is sum_h0, sum_h0 storage is 8 int16_t data, sum_h0 and vrd0 …… vrd15, storage is 8 int16_t data, indicates as follows: sum_h0 = ingenic_add_h (sum_h0, vrd0) ; sum_h0 = ingenic_add_h (sum_h0, vrd1) ; sum_h0 = ingenic_add_h (sum_h0, vrd2) ; sum_h0 = ingenic_add_h (sum_h0, vrd3) ; sum_h0 = ingenic_add_h (sum_h0, vrd4) ; sum_h0 = ingenic_add_h (sum_h0, vrd5) ; sum_h0 = ingenic_add_h (sum_h0, vrd6) ; sum_h0 = ingenic_add_h (sum_h0, vrd7) ; sum_h0 = ingenic_add_h (sum_h0, vrd8) ; sum_h0 = ingenic_add_h (sum_h0, vrd9) ; sum_h0 = ingenic_add_h (sum_h0, vrd10) ; sum_h0 = ingenic_add_h (sum_h0, vrd11) ; sum_h0 = ingenic_add_h (sum_h0, vrd12) ; sum_h0 = ingenic_add_h (sum_h0, vrd13) ; sum_h0 = ingenic_add_h (sum_h0, vrd14) ; sum_h0 = ingenic_add_h (sum_h0, vrd15). sum_h0 = ingenic_add_h(sum_h0, vrd9); sum_h0 = ingenic_add_h(sum_h0, vrd10); sum_h0 = ingenic_add_h(sum_h0, vrd11); sum_h0 = ingenic_add_h(sum_h0, vrd12); sum_h0 = ingenic_add_h(sum_h0, vrd13); sum_h0 = ingenic_add_h(sum_h0, vrd14); sum_h0 = ingenic_add_h(sum_h0, vrd15).

8. The optimization method of the gray scale image mean value preprocessing according to claim 7, characterized in that, The step S5 further includes a right shift instruction, which shifts each element in the variable sum_h0 by 8 bits, and outputs sum_h1. The instruction has a rounding operation, and count is incremented by 1. The operation is as follows: sum_h0 = ingenic_shift_right(sum_h0, 8); count += 1.

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