wafer mounting stage

Abstract

This invention provides a wafer mounting stage capable of processing wafers at high temperatures and efficiently dissipating heat from the wafers. The wafer mounting stage (10) includes a ceramic substrate (20), a first cooling substrate (30), and a second cooling substrate (50). The ceramic substrate (20) has a wafer mounting surface (22a) and houses a wafer adsorption electrode (25) and a heater electrode (26). The first cooling substrate (30) is bonded to the surface of the ceramic substrate (20) opposite to the wafer mounting surface (22a) via a metal bonding layer (40) and has a first refrigerant flow path (31) capable of switching the supply and cessation of a first refrigerant. The second cooling substrate (50) is mounted on the surface of the first cooling substrate (30) opposite to the metal bonding layer (40) via a space layer (42) capable of supplying heat transfer gas and has a second refrigerant flow path (51) capable of switching the supply and cessation of a second refrigerant.

Description

Technical Field

[0001] This invention relates to a wafer mounting stage. Background Technology

[0002] To perform CVD, etching, and other processes on wafers using plasma, a wafer mounting stage is used. For example, the wafer mounting stage disclosed in Patent Document 1 includes: a metal cooling stage with a refrigerant flow path; a high-frequency transmission power supply connected to the lower surface of the cooling stage; a conductive base disposed on the upper surface of the cooling stage; and an electrostatic chuck metally bonded to the base. The electrostatic chuck contains an adsorption electrode and a heater. The cooling stage and the base are clamped by a metal fastening member via O-rings. The fastening member ensures conductivity between the cooling stage and the base. A heat transfer gas is supplied to the space formed by the cooling stage, the base, and the O-rings.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2017-63011 Summary of the Invention

[0006] The problem that the invention aims to solve

[0007] However, while such a wafer stage is suitable for processing wafers at high temperatures, it is not suitable for efficient heat dissipation from the wafer afterwards.

[0008] This invention was made to solve such a problem, and its main purpose is to balance the processing of wafers at high temperatures and the efficient heat dissipation from the wafers.

[0009] Solution for solving the problem

[0010] The wafer mounting stage of the present invention comprises:

[0011] A ceramic substrate having a wafer mounting surface and an embedded electrostatic electrode and a heater electrode;

[0012] A first cooling substrate, bonded via a metal bonding layer to a surface of the ceramic substrate opposite to the wafer mounting surface, has a first refrigerant flow path capable of switching the supply and stopping of a first refrigerant; and

[0013] The second cooling substrate, which is mounted on the surface opposite to the metal bonding layer in the first cooling substrate through a space layer that allows the supply of heat transfer gas, has a second refrigerant flow path that allows switching of the supply and cessation of the supply of the second refrigerant.

[0014] According to this wafer mounting stage, it is possible to simultaneously process the wafer at high temperatures and efficiently dissipate heat from the wafer. For example, in processes requiring high wafer temperatures, the first refrigerant can be diverted from the first refrigerant flow path of the first cooling substrate, while the second refrigerant can flow through the second refrigerant flow path of the second cooling substrate. As a result, the heat from the wafer, which is heated by energizing the heater electrodes, is less likely to be absorbed by the first cooling substrate, which is closer to the ceramic substrate, and is instead absorbed by the second cooling substrate, which is farther away from the ceramic substrate. Therefore, it is possible to maintain the wafer at a high temperature while processing. Furthermore, for example, in processes requiring high heat dissipation of the wafer, the first refrigerant can be diverted from the first refrigerant flow path of the first cooling substrate. As a result, the heat from the wafer, which is heated by energizing the heater electrodes, is absorbed by the first cooling substrate, which is closer to the ceramic substrate, thus enabling efficient heat dissipation of the wafer. It should be noted that a heat transfer gas is supplied to the space layer when it is desirable to have good thermal conductivity between the first and second cooling substrates.

[0015] In the wafer mounting stage of the present invention, the space layer may be switchable between a vacuum state and a heat transfer gas filling state. If the space layer is made into a vacuum state, the first cooling substrate and the second cooling substrate can be thermally insulated; if the space layer is filled with heat transfer gas, the heat conduction between the first cooling substrate and the second cooling substrate can be improved.

[0016] In the wafer mounting stage of the present invention, the temperature of the first coolant may be lower than the temperature of the second coolant. For example, in processes requiring high heat dissipation of the wafer, the first cooling substrate can more easily capture heat, thus enabling more efficient heat dissipation of the wafer.

[0017] In the wafer mounting stage of the present invention, the first refrigerant flow path may be able to switch the circulation of the first refrigerant and stop the circulation, and the second refrigerant flow path may be able to switch the circulation of the second refrigerant and stop the circulation. For example, in a process requiring high heat dissipation of the wafer, the first refrigerant may circulate in the first refrigerant flow path, and in a process that processes the wafer at high temperatures, the circulation of the first refrigerant in the first refrigerant flow path may be stopped, while the circulation of the second refrigerant in the second refrigerant flow path may be allowed to begin.

[0018] In the wafer mounting stage of the present invention, at least one of the first cooling substrate and the second cooling substrate may also serve as a plasma generating electrode. This simplifies the structure compared to embedding the plasma generating electrode in a ceramic substrate.

[0019] In the wafer mounting stage of the present invention, the difference in the coefficient of thermal expansion between the ceramic substrate and the first cooling substrate may also be 1×10⁻⁶. -6 / K or below. This allows for the suppression of obstacles in the bonding between the ceramic substrate and the first cooling substrate, even when the wafer stage is repeatedly used at high and low temperatures. For example, when the ceramic substrate is made of alumina, the first cooling substrate is preferably made of SiSiCTi or AlSiC.

[0020] In the wafer stage of the present invention, it is preferable that the thickness of the space layer is 0.05 mm or more and 2 mm or less. If the thickness of the space layer is above the lower limit, the in-plane space layer thickness deviation can be controlled, which is preferable in terms of reducing the influence of thermal resistance deviation. If the thickness of the space layer is below the upper limit, it is preferable from the viewpoint of temperature control responsiveness in terms of low thermal resistance.

[0021] In the wafer mounting stage of the present invention, the space layer may also be divided by a sealing ring disposed between the first cooling substrate and the second cooling substrate. In this case, the sealing ring may be a metal ring, a resin ring, or a combination of both. When using both metal and resin rings, the deformation of the resin ring can be limited by the metal ring. The sealing ring may be disposed along the outer edge of the smaller diameter of the first cooling substrate and the second cooling substrate. Additionally, spacers that limit the thickness of the space layer may also be provided in the space layer. This facilitates maintaining the overall thickness of the space layer.

[0022] In the wafer mounting stage of the present invention, the first refrigerant flow path may have a smaller cross-sectional area and a longer flow path length compared to the second refrigerant flow path. This results in better heat dissipation from the first refrigerant flow path. Attached Figure Description

[0023] Figure 1 This is a longitudinal sectional view of the wafer mounting stage 10.

[0024] Figure 2 This is a top view of the wafer mounting stage 10.

[0025] Figure 3 This is a manufacturing process diagram of the wafer mounting stage 10.

[0026] Figure 4 This is a manufacturing process diagram of the wafer mounting stage 10.

[0027] Figure 5 This is an explanatory diagram of the wafer mounting stage 10 when processing wafer W at high temperature.

[0028] Figure 6 This is an explanatory diagram of the wafer mounting stage 10 for efficient heat dissipation from wafer W.

[0029] Symbol Explanation

[0030] 10: Wafer stage; 20: Ceramic substrate; 22: Central portion; 22a: Wafer mounting surface; 23: BS gas passage; 24: Outer periphery; 24a: FR mounting surface; 25: Wafer adsorption electrode; 26: Heater electrode; 27: FR adsorption electrode; 30: Cooling substrate; 30a: Flange; 31: First refrigerant flow path; 32: First refrigerant supply path; 33: BS gas connection path; 36: First refrigerant circulator; 40: Metal bonding layer ; 42: Space layer; 43: Large diameter sealing ring; 44: Small diameter sealing ring; 45: Refrigerant sealing ring; 46-49: Sealing ring; 50: Second cooling substrate; 50a: Second flange; 51: Second refrigerant flow path; 52: Second refrigerant supply path; 53: BS gas connection path; 54: Heat transfer gas supply and exhaust path; 55: First refrigerant connection path; 56: Second refrigerant circulator; 62: Power supply terminal; 63: Power supply rod; 63a: Spring; 64: Supply Electrical terminal; 65: Power supply rod; 65a: Spring; 66: Power supply terminal; 67: Power supply rod; 67a: Spring; 70: Fastening component; 70a: Inner peripheral stepped surface; 70b: Outer peripheral stepped surface; 72: Bolt; 74: Mounting component; 74a: Inner peripheral stepped surface; 76: Bolt; 78: Focusing ring; 80: Chamber; 80a: Nozzle; 81: Setting plate; 82: First refrigerant inlet path; 83: Second refrigerant inlet path; 84: BS gas inlet path; 8 5: Heat transfer gas inlet / outlet; 86: Temperature sensor; 87: High-frequency power supply; 91-95: Sealing ring; 96: BS gas supply source; 97: Switching valve; 98: Heat transfer gas supply source; 99: Vacuum pump; 111: First ceramic molded body; 112: Second ceramic molded body; 113: Third ceramic molded body; 114, 115: Electrode pattern; 115: Electrode pattern; 120: Ceramic sintered body; 122: Joint; 124: Joint; W: Wafer. Detailed Implementation

[0031] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Figure 1 This is a longitudinal sectional view of the wafer stage 10 (a sectional view cut along a plane that includes the central axis of the wafer stage 10). Figure 2 This is a top view of the wafer mounting stage 10. In the following description, terms such as up / down, left / right, and front / back are sometimes used, but these are merely relative positional relationships. Furthermore, in this specification, the symbol “~” indicating a numerical range is used to mean: including the values ​​described before and after it as the lower and upper limits.

[0032] The wafer stage 10 is used to perform CVD, etching, and other processes on the wafer W using plasma, and is fixed on a mounting plate 81 disposed inside a semiconductor process chamber 80. The wafer stage 10 includes a ceramic substrate 20, a first cooling substrate 30, a metal bonding layer 40, a space layer 42, a second cooling substrate 50, and a fastening member 70.

[0033] The ceramic substrate 20 has an outer peripheral portion 24 with an annular focusing ring mounting surface 24a around the outer periphery of the central portion 22 of the circular wafer mounting surface 22a. Hereinafter, the focusing ring is sometimes simply referred to as "FR". A wafer W is mounted on the wafer mounting surface 22a, and a focusing ring 78 is mounted on the FR mounting surface 24a. The ceramic substrate 20 is formed of a ceramic material, such as alumina or aluminum nitride. The FR mounting surface 24a is one step lower than the wafer mounting surface 22a.

[0034] A wafer adsorption electrode 25 and a heater electrode 26 are sequentially housed in the central portion 22 of the ceramic substrate 20, starting from the side closest to the wafer mounting surface 22a. These electrodes 25 and 26 are formed, for example, of materials containing W, Mo, WC, MoC, etc. The wafer adsorption electrode 25 is a unipolar electrostatic electrode in the shape of a disc or a mesh. A layer in the ceramic substrate 20 above the wafer adsorption electrode 25 functions as a dielectric layer. The wafer adsorption electrode 25 is connected to a DC power supply (not shown) for wafer adsorption via a power supply terminal 62 and a power supply rod 63. The upper surface of the power supply terminal 62 is engaged with the lower surface of the wafer adsorption electrode 25, and the lower surface of the power supply terminal 62 is in contact with the upper surface of the power supply rod 63, which is exerted upward force by a spring 63a. The power supply terminal 62 and the power supply rod 63 are inserted in an electrically insulated state into holes that are respectively disposed in the heater electrode 26, the first cooling substrate 30, the metal bonding layer 40, the second cooling substrate 50, and the mounting plate 81, extending vertically. The heater electrode 26 is wired from one end to the other in a single stroke, covering the entire surface of the wafer mounting surface 22a when viewed from above. One end of the heater electrode 26 is connected to a heater power source (not shown) via a power supply terminal 64 and a power supply rod 65. The upper surface of the power supply terminal 64 engages with the lower surface of one end of the heater electrode 26, and the lower surface of the power supply terminal 64 contacts the upper surface of the power supply rod 65, which is exerted upward force by a spring 65a. The power supply terminal 66 and the power supply rod 67 are inserted in an electrically insulated manner into holes that are respectively disposed in the first cooling substrate 30, the metal bonding layer 40, the second cooling substrate 50, and the mounting plate 81, extending vertically. Although not shown, the other end of the heater electrode 26 is also connected to the heater power source via a power supply terminal and a power supply rod, similarly to one end of the heater electrode 26. The central portion 22 of the ceramic substrate 20 has a BS gas passage 23 for supplying back-side gas (BS gas) to the back side of the wafer W. The BS gas passage 23 extends vertically through the central portion 22 of the ceramic substrate 20.

[0035] An FR adsorption electrode 27 is embedded in the outer periphery 24 of the ceramic substrate 20. The FR adsorption electrode 27 is formed, for example, from a material containing W, Mo, WC, MoC, etc. The FR adsorption electrode 27 is a ring-shaped or mesh-shaped unipolar electrostatic electrode. A layer in the ceramic substrate 20 above the FR adsorption electrode 27 functions as a dielectric layer. The FR adsorption electrode 27 is connected to a DC power supply (not shown) for FR adsorption via a power supply terminal 66 and a power supply rod 67. The upper surface of the power supply terminal 66 is engaged with the lower surface of the FR adsorption electrode 27, and the lower surface of the power supply terminal 66 is in contact with the upper surface of the power supply rod 67, which is exerted upward force by a spring 67a. The power supply terminal 66 and the power supply rod 67 are inserted in an electrically insulated state into holes that are respectively disposed in the first cooling substrate 30, the metal bonding layer 40, the second cooling substrate 50, and the mounting plate 81 in the vertical direction.

[0036] The first cooling substrate 30 is a conductive circular plate component containing metal, and has a first flange 30a on its lower side. The first cooling substrate 30 has a first refrigerant flow path 31 inside, through which a first refrigerant can circulate. The first refrigerant flow path 31 is formed from one end to the other in a single stroke, covering the entire surface of the ceramic substrate 20 when viewed from above. One end of the first refrigerant flow path 31 is connected to a first refrigerant supply path 32. The other end of the first refrigerant flow path 31 is connected to a first refrigerant discharge path. The first cooling substrate 30 has a BS gas connection path 33 that communicates with the BS gas passage 23 of the ceramic substrate 20. The BS gas connection path 33 extends vertically through the first cooling substrate 30. The BS gas connection path 33 continuously forms small-diameter holes, tapered holes, and large-diameter holes from the top of the first cooling substrate 30. The diameter of the small-diameter holes is larger than that of the BS gas passage 23. The first cooling substrate 30 is made of a conductive material containing metal. Examples of conductive materials include composite materials and metals. Examples of composite materials include metal composites (also known as metal matrix composites (MMCs)). MMCs include materials containing Si, SiC, and Ti, and materials in which Al and / or Si are impregnated within porous SiC. Materials containing Si, SiC, and Ti are called SiSiCTi; materials in which Al is impregnated within porous SiC are called AlSiC; and materials in which Si is impregnated within porous SiC are called SiSiC. Mo is an example of a metal.

[0037] The metal bonding layer 40 bonds the lower surface of the ceramic substrate 20 to the upper surface of the first cooled substrate 30. The metal bonding layer 40 may be, for example, a layer formed of solder or brazing filler metal. The metal bonding layer may be formed, for example, by TCB (Thermal Compression Bonding). TCB refers to a known method of bonding two components by sandwiching a metal bonding material between them and applying pressure while heating the two components to a temperature below the solidus temperature of the metal bonding material.

[0038] A space layer 42 is disposed between the first cooling substrate 30 and the second cooling substrate 50. The space layer 42 is formed by the lower surface of the first cooling substrate 30, the upper surface of the second cooling substrate 50, and a large-diameter sealing ring 43. The thickness of the space layer 42 is preferably 0.05 mm to 2 mm. The large-diameter sealing ring 43 divides the space layer 42 and is a ring with an outer diameter slightly smaller than the diameter of the lower surface of the first cooling substrate 30. The large-diameter sealing ring 43 can be a metal ring, a resin ring (insulating ring), or a combination of both. When using a metal ring and a resin ring, the deformation of the resin ring can be limited by the metal ring. Spacers that limit the thickness of the space layer 42 may also be provided in the space layer 42. These spacers can be made of metal or resin.

[0039] The second cooling substrate 50 is mounted on the first cooling substrate 30 through a space layer 42. The second cooling substrate 50 is a conductive circular plate component containing metal, and has a second flange 50a on its lower side. The second cooling substrate 50 has a second refrigerant flow path 51 inside, through which a second refrigerant can circulate. The second refrigerant flow path 51 is formed from one end to the other in a single stroke, covering the entire surface of the ceramic substrate 20 when viewed from above. One end of the second refrigerant flow path 51 is connected to a second refrigerant supply path 52. The other end of the second refrigerant flow path 51 is connected to a second refrigerant discharge path. The second cooling substrate 50 has a BS gas connection path 53 that is connected to the BS gas connection path 33 of the first cooling substrate 30. The BS gas connection path 53 is a cylindrical hole that penetrates the second cooling substrate 50 in the vertical direction. The BS gas connection path 33 and the BS gas connection path 53 are hermetically connected by a small-diameter sealing ring 44 disposed between the first cooling substrate 30 and the second cooling substrate 50. Therefore, BS gas communication path 33 and BS gas communication path 53 are not connected to space layer 42. It should be noted that, in this embodiment, as... Figure 1 As shown, the small-diameter sealing ring 44 is configured as a double ring, but it can also be a single ring.

[0040] The second cooling substrate 50 has a heat transfer gas supply and exhaust passage 54 communicating with the space layer 42. The heat transfer gas supply and exhaust passage 54 is a cylindrical hole penetrating the second cooling substrate 50 in the vertical direction. The heat transfer gas supply and exhaust passage 54 is used to fill the space layer 42 with heat transfer gas (e.g., helium) or to create a vacuum in the space layer. The second cooling substrate 50 has a first refrigerant connection passage 55 communicating with a first refrigerant supply passage 32 of the first cooling substrate 30. The first refrigerant connection passage 55 is a cylindrical hole penetrating the second cooling substrate 50 in the vertical direction. The first refrigerant supply passage 32 and the first refrigerant connection passage 55 are hermetically connected by a small-diameter refrigerant sealing ring 45 disposed between the first cooling substrate 30 and the second cooling substrate 50. Therefore, the first refrigerant supply passage 32 and the first refrigerant connection passage 55 are not communicating with the space layer 42. The second cooling substrate 50 is connected to a high-frequency power supply 87 for generating plasma and is used as a high-frequency electrode. The second cooling substrate 50 is made of a conductive material containing metal. Examples of conductive materials include composite materials and metals, but Al and Ti are preferred.

[0041] The fastening member 70 is a ring-shaped, metal component with a generally Z-shaped cross-section, having an inner peripheral stepped surface 70a and an outer peripheral stepped surface 70b. The first cooling substrate 30 and the second cooling substrate 50 are integrated by the fastening member 70. That is, various sealing rings 43 to 49 are disposed between the first cooling substrate 30 and the second cooling substrate 50, the inner peripheral stepped surface 70a of the fastening member 70 is disposed on the first flange 30a of the first cooling substrate 30, and the lower surface of the fastening member 70 is disposed on the second flange 50a of the second cooling substrate 50. Furthermore, bolts 72 are inserted from the lower surface of the second flange 50a and threadedly engaged with threaded holes provided on the lower surface of the fastening member 70. Bolts 72 are installed at multiple locations (e.g., 8 or 12 locations) evenly spaced along the circumference of the second flange 50a. A power supply rod 63 is inserted into the sealing ring 46, a power supply rod 65 is inserted into the sealing ring 47, and a power supply rod 67 is inserted into the sealing ring 48. The inner spaces of each sealing ring 46-48 are not connected to the space layer 42. Sealing rings 44-48 can be metal rings, resin rings, or a combination of both. Additionally, sealing rings 44-48 can also function as spacers limiting the thickness of the space layer 42. The first cooling substrate 30 and the second cooling substrate 50 are integrated via a conductive fastening member 70, thus the first cooling substrate 30 and the second cooling substrate 50 are at the same potential. Since the second cooling substrate 50 functions as a high-frequency electrode, the first cooling substrate 30 also functions as a high-frequency electrode.

[0042] Such a wafer mounting stage 10 is mounted on a mounting plate 81 disposed inside a chamber 80 using a mounting member 74. The mounting plate 81 includes a first refrigerant inlet path 82, a second refrigerant inlet path 83, a BS gas inlet path 84, and a heat transfer gas inlet / outlet path 85. The first refrigerant inlet path 82 is disposed vertically through the mounting plate 81 opposite to the first refrigerant communication path 55, and is airtightly connected to the first refrigerant communication path 55 via a sealing ring 92 between the second cooling substrate 50 and the mounting plate 81. The second refrigerant inlet path 83 is disposed vertically through the mounting plate 81 opposite to the second refrigerant supply path 52, and is airtightly connected to the second refrigerant supply path 52 via a sealing ring 93 between the second cooling substrate 50 and the mounting plate 81. The BS gas inlet path 84 is disposed vertically through the mounting plate 81 opposite to the BS gas communication path 53, and is airtightly connected to the BS gas communication path 53 via a sealing ring 94 between the second cooling substrate 50 and the mounting plate 81. The heat-conducting gas inlet / outlet path 85 is arranged to pass through the mounting plate 81 vertically opposite the heat-conducting gas supply / exhaust path 54, and is airtightly connected to the heat-conducting gas supply / exhaust path 54 through the sealing ring 95 between the second cooling substrate 50 and the mounting plate 81. The mounting plate 81 has through holes for inserting power supply rods 63, 65, and 67 respectively, and a temperature sensor 86 for measuring the temperature of the first cooling substrate 30. The front end (temperature measuring part) of the temperature sensor 86 is exposed in the temperature measuring space surrounded by the first cooling substrate 30, the second cooling substrate 50, and the sealing ring 49. This temperature measuring space is not connected to the space layer 42 and is essentially at the same temperature as the first cooling substrate 30. Between the second cooling substrate 50 and the mounting plate 81, a sealing ring 91 of approximately the same size as the large-diameter sealing ring 43 is arranged along the outer periphery of the second cooling substrate 50.

[0043] A first refrigerant circulator 36 is installed in the first refrigerant inlet path 82. The first refrigerant circulator 36 is a circulation pump with temperature regulation function, introducing first refrigerant adjusted to the desired temperature into the first refrigerant inlet path 82, and then introducing the first refrigerant discharged from the first refrigerant outlet path of the first refrigerant flow path 31 back into the first refrigerant inlet path 82 after adjusting it to the desired temperature. A second refrigerant circulator 56 is installed in the second refrigerant inlet path 83. The second refrigerant circulator 56 is a circulation pump with temperature regulation function, introducing second refrigerant adjusted to the desired temperature into the second refrigerant inlet path 83, and then introducing the second refrigerant discharged from the second refrigerant outlet path of the second refrigerant flow path 51 back into the second refrigerant inlet path 83 after adjusting it to the desired temperature. A BS gas supply source 96 is installed in the BS gas inlet path 84. The BS gas supply source 96 supplies heat transfer gas to the back surface of the wafer W via the BS gas inlet path 84, the BS gas connecting path 53, the BS gas connecting path 33, and the BS gas passage 23. The heat transfer gas inlet / outlet 85 is connected to the heat transfer gas supply source 98 and the vacuum pump 99 via the switching valve 97. The heat transfer gas supply source 98 supplies heat transfer gas to the space layer 42 via the heat transfer gas inlet / outlet 85. The vacuum pump 99 creates a vacuum (reduced pressure) inside the space layer 42 via the heat transfer gas inlet / outlet 85.

[0044] Mounting member 74 is an annular member with a roughly inverted L-shaped cross-section and an inner peripheral stepped surface 74a. The wafer stage 10 and the mounting plate 81 are integrated via mounting member 74. With the inner peripheral stepped surface 74a of mounting member 74 placed on the outer peripheral stepped surface 70b of the fastening member 70 of wafer stage 10, bolts 76 are inserted from the upper surface of mounting member 74, thereby threading into threaded holes provided on the upper surface of mounting plate 81. Bolts 76 are installed at multiple locations (e.g., 8 or 12 locations) evenly spaced along the circumference of mounting member 74. Mounting member 74 and bolts 76 can be made of insulating material or conductive material (metal, etc.).

[0045] Next, use Figure 3 and Figure 4 A manufacturing example of the wafer mounting stage 10 will be described. Figure 3 and Figure 4 This is a manufacturing process diagram of the wafer mounting stage 10. First, disc-shaped first to third ceramic molded bodies 111 to 113 are fabricated by die casting. Electrode paste is then printed on the upper surfaces of the second and third ceramic molded bodies 112 and 113 to form electrode patterns 114 and 115 (see reference). Figure 3(a) The so-called molding method refers to a known method in which a ceramic slurry containing ceramic raw material powder and a molding agent is injected into a molding die, and the molding agent undergoes a chemical reaction within the molding die to mold the ceramic slurry and obtain a molded body. The molding agent can be, for example, a substance containing isocyanate and polyol, which is molded via a urethane reaction. The electrode paste is, for example, a slurry in which ceramic powder is added to conductive materials such as W, Mo, WC, and MoC. The electrode pattern 114 printed on the upper surface of the second ceramic molded body 112 has the same shape as the wafer adsorption electrode 25, and the electrode pattern 115 printed on the upper surface of the third ceramic molded body 113 has a shape that combines the heater electrode 26 and the FR adsorption electrode 27.

[0046] Next, the first ceramic molded body 111, the second ceramic molded body 112 with electrode patterns 114 printed on its upper surface, and the third ceramic molded body 113 with electrode patterns 115 printed on its upper surface are stacked together, and the resulting stacked body is hot-pressed and fired to obtain a ceramic sintered body 120 (see reference). Figure 3 (b) Thus, electrode pattern 114 becomes wafer adsorption electrode 25, and electrode pattern 115 becomes heater electrode 26 and FR adsorption electrode 27.

[0047] Next, the shape and thickness of the obtained ceramic sintered body 120 are adjusted by grinding or sandblasting on both sides, and holes in the vertical direction are formed (holes for inserting power supply terminals 62, 64, 66, BS gas passage 23, etc.) (see reference). Figure 3 (c)).

[0048] Next, power supply terminal 62 is inserted into the hole of ceramic sintered body 120 that communicates with wafer adsorption electrode 25 and is engaged with wafer adsorption electrode 25; power supply terminal 64 is inserted into the hole that communicates with heater electrode 26 and is engaged with heater electrode 26; and power supply terminal 66 is inserted into the hole that communicates with FR adsorption electrode 27 and is engaged with FR adsorption electrode 27. Figure 3 (d) Then, a first cooling substrate 30 is prepared, and a ceramic sintered body 120 is bonded to the first cooling substrate 30 using a metal bonding layer 40 to obtain a bond 122. Figure 3(e)). Holes extending vertically are pre-formed on the first cooling substrate 30 at positions opposite to the power supply terminals 62, 64, and 66 of the ceramic sintered body 120. During bonding, the power supply terminals 62, 64, and 66 are inserted into each hole (an insulating film is formed on the inner wall). Furthermore, during bonding, the BS gas passage 33 of the first cooling substrate 30 is aligned with the BS gas passage 23 of the ceramic substrate 20. When the ceramic sintered body 120 is formed of alumina, the first cooling substrate 30 is preferably formed of SiSiCTi. The coefficient of linear thermal expansion from 40 to 570°C is 7.7 × 10⁻⁶ for alumina. -6 / K, SiSiCTi is 7.8×10 -6 / K.

[0049] For SiSiCTi plates, a powder mixture is prepared, for example, comprising one or more raw materials selected in a manner that contains 39 to 51% by mass of silicon carbide raw material particles with an average particle size of 10 μm or more and 25 μm or less, and containing Ti and Si. For Si and Ti derived from raw materials other than silicon carbide, the mass ratio of Si / (Si+Ti) is 0.26 to 0.54. As raw materials, for example, silicon carbide, metallic Si, and metallic Ti can be used. In this case, it is preferable to mix 39 to 51% by mass of silicon carbide, 16 to 24% by mass of metallic Si, and 26 to 43% by mass of metallic Ti. Next, the obtained powder mixture is formed into a disc-shaped molded body by uniaxial pressure molding, and the molded body is sintered at 1370 to 1460°C by hot pressing under an inactive atmosphere, thereby obtaining the SiSiCTi plate.

[0050] The bonding of the ceramic sintered body 120 and the first cooling substrate 30 is performed using a metal bonding material. For example, TCB bonding is performed by sandwiching a metal bonding material between the alumina ceramic sintered body 120 and the first cooling substrate 30 made of SiSiCTi. Specifically, TCB bonding is performed by pressurizing the laminate of the ceramic sintered body 120 and the first cooling substrate 30 at a temperature below the solidus temperature of the metal bonding material (e.g., a temperature above the solidus temperature minus 20°C and below the solidus temperature), and then returning to room temperature. Thus, the metal bonding material becomes the metal bonding layer 40. As the metal bonding material at this time, Al-Mg based bonding materials and Al-Si-Mg based bonding materials can be used. For example, when using an Al-Si-Mg based bonding material (containing 88.5 wt% Al, 10 wt% Si, and 1.5 wt% Mg, with a solidus temperature of approximately 560°C) for TCB bonding, under a vacuum atmosphere, at a temperature of 540–560°C, the bonding is performed at a pressure of 0.5–2.0 kg / mm². 2The pressure is applied to the ceramic sintered body 120 for several hours. A metal bonding material with a thickness of approximately 100 μm is preferably used.

[0051] Next, steps are formed by cutting the outer periphery of the ceramic sintered body 120 of the joint 122, thereby forming a ceramic substrate 20 having a central portion 22 and an outer peripheral portion 24, resulting in the joint 124. Figure 3 (f) Next, a second cooling substrate 50 is prepared. Sealing rings 43-49 are temporarily fixed to the upper surface of the second cooling substrate 50, and sealing rings 91-95 are temporarily fixed to the lower surface. Using fastening members 70 and bolts 72, the second cooling substrate 50 and the first cooling substrate 30 of the connector 124 are fastened together. Figure 4 (a)). Thus, the wafer mounting stage 10 is obtained. It should be noted that the sealing rings 43-49, 91-95 can be, for example, O-rings made of fluoropolymer resin or silicone resin. Next, a mounting plate 81 is prepared, which has a first refrigerant inlet 82, a second refrigerant inlet 83, a BS gas inlet 84, and a heat transfer gas inlet / outlet 85, and is equipped with a temperature sensor 86 and power supply rods 63, 65, 67. Then, the wafer mounting stage 10 is placed on the mounting plate 81 and fastened with bolts 76 using mounting members 74 (see reference). Figure 4 (b)). In this way, the wafer stage 10 is fixed to the mounting plate 81.

[0052] It should be noted that the exposed surfaces of the metal bonding layer 40, the first cooling substrate 30, and the fastening member 70 are preferably covered with an insulating film. The insulating film can be formed, for example, by spraying ceramic powder. Furthermore, the surfaces forming paths connected to the BS gas passage 23 (through holes in the metal bonding layer 40, BS gas connection paths 33 and 53, and BS gas inlet path 84, etc.) are also preferably covered with an insulating film.

[0053] Next, use Figure 1 An example of the use of the wafer stage 10 will be described. The wafer stage 10 is provided on the mounting plate 81 of the chamber 80 as described above. A nozzle 80a is disposed on the top surface of the chamber 80 to release process gas from a plurality of gas injection holes into the interior of the chamber 80.

[0054] A focusing ring 78 is placed on the FR mounting surface 24a of the wafer mounting stage 10, and a disk-shaped wafer W is placed on the wafer mounting surface 22a. The focusing ring 78 has a step along the inner periphery of its upper end to avoid interference with the wafer W. In this state, a DC voltage is applied to the wafer adsorption electrode 25 to adsorb the wafer W onto the wafer mounting surface 22a, and a DC voltage is applied to the FR adsorption electrode 27 to adsorb the focusing ring 78 onto the FR mounting surface 24a. In addition, BS gas (e.g., helium) is supplied to the back side of the wafer W from the BS gas passage 23, and the heater electrode 26 is energized to control the wafer W to a high temperature (e.g., 400°C). Then, the interior of the chamber 80 is set to a predetermined vacuum atmosphere (or reduced pressure atmosphere), and while process gas is supplied from the nozzle 80a, a high-frequency voltage from the high-frequency power supply 87 is applied to the second cooling substrate 50. As a result, plasma is generated between the first cooling substrate 30 (at the same potential as the second cooling substrate 50) and the nozzle 80a. Then, the high-temperature wafer W is processed using this plasma.

[0055] In such a process that requires high-temperature wafer W, such as Figure 5 As shown, the first refrigerant is not allowed to flow in the first refrigerant flow path 31 of the first cooling substrate 30, but the second refrigerant is allowed to flow in the second refrigerant flow path 51 of the second cooling substrate 50. That is, the operation of the first refrigerant circulator 36 is stopped, thus stopping the circulation of the first refrigerant in the first refrigerant flow path 31, and the second refrigerant circulates in the second refrigerant flow path 51 by operating the second refrigerant circulator 56. In addition, heat transfer gas is supplied to the space layer 42 to improve the thermal conductivity of the space layer 42. As a result, the heat of the wafer W heated by energizing the heater electrode 26 is less likely to be taken away by the first cooling substrate 30 which is close to the ceramic substrate 20, but is taken away by the second cooling substrate 50 which is far away from the ceramic substrate 20. Therefore, it is possible to process the wafer W while maintaining it at a high temperature.

[0056] On the other hand, in processes that require high heat dissipation of the chip W, such as Figure 6As shown, the energization of the heater electrode 26 is stopped, and a DC voltage is applied to the wafer adsorption electrode 25 to adsorb the wafer W onto the wafer mounting surface 22a. A DC voltage is also applied to the FR adsorption electrode 27 to adsorb the focusing ring 78 onto the FR mounting surface 24a. Additionally, BS gas is supplied to the back side of the wafer W from the BS gas passage 23. Then, the first refrigerant is allowed to flow in the first refrigerant flow path 31 of the first cooling substrate 30, while the second refrigerant is prevented from flowing in the second refrigerant flow path 51 of the second cooling substrate 50. That is, the first refrigerant circulator 36 is activated to circulate the first refrigerant in the first refrigerant flow path 31, and the operation of the second refrigerant circulator 56 is stopped to stop the circulation of the second refrigerant in the second refrigerant flow path 51. Furthermore, the space layer 42 is made a vacuum to suppress heat movement from the second cooling substrate 50 to the first cooling substrate 30. Thus, the heat from the high-temperature wafer W is removed by the first cooling substrate 30 near the ceramic substrate 20, thereby enabling efficient heat dissipation of the wafer W. It should be noted that the temperature of the first refrigerant is preferably lower than the temperature of the second refrigerant. For example, the temperature of the first refrigerant can be set to -30°C and the temperature of the second refrigerant can be set to 5°C.

[0057] It should be noted that the focusing ring 78 is also consumed during plasma treatment of the wafer W. However, since the focusing ring 78 is thicker than the wafer W, the focusing ring 78 is replaced after multiple wafers W have been processed.

[0058] The wafer stage 10 of this embodiment described above can simultaneously process the wafer W at high temperatures and efficiently dissipate heat from the wafer W.

[0059] Furthermore, the space layer 42 can switch between a vacuum state and a heat transfer gas filling state. Therefore, if the space layer 42 is set to a vacuum state, the first cooling substrate 30 and the second cooling substrate 50 can be insulated from each other. If the space layer 42 is filled with heat transfer gas, the heat conduction between the first cooling substrate 30 and the second cooling substrate 50 can be improved.

[0060] Furthermore, the temperature of the first refrigerant is lower than that of the second refrigerant. Therefore, in processes requiring high heat dissipation of the wafer W, it is easier to utilize the first cooling substrate 30 to capture heat, thus enabling more efficient heat dissipation of the wafer W.

[0061] Furthermore, the first refrigerant flow path 31 can switch the circulation of the first refrigerant and stop the circulation, and the second refrigerant flow path 51 can switch the circulation of the second refrigerant and stop the circulation. Thus, in processes requiring high heat dissipation of the wafer W, the first refrigerant can circulate in the first refrigerant flow path 31, and in processes where the wafer W is processed at high temperatures, the circulation of the first refrigerant in the first refrigerant flow path 31 can be stopped, while the circulation of the second refrigerant in the second refrigerant flow path 51 can be started.

[0062] Furthermore, the first and second cooling substrates 30 and 50 also serve as electrodes for plasma generation, thus simplifying the structure compared to embedding plasma generation electrodes in the ceramic substrate 20.

[0063] Furthermore, the difference in the coefficients of thermal expansion between the ceramic substrate 20 and the first cooling substrate 30 at temperatures ranging from 40 to 570°C is 1 × 10⁻⁶. -6 Therefore, even with repeated use of the wafer stage 10 at high and low temperatures, obstacles in the bonding between the ceramic substrate 20 and the first cooling substrate 30 can be suppressed. For example, if the ceramic substrate 20 is made of alumina, the first cooling substrate 30 is preferably made of SiSiCTi or AlSiC.

[0064] Furthermore, the thickness of the space layer 42 is preferably 0.05 mm or more and 2 mm or less. If the thickness of the space layer 42 is above the lower limit, the in-plane thickness deviation of the space layer can be controlled, which is preferable in terms of reducing the impact of thermal resistance deviation. If the thickness of the space layer 42 is below the upper limit, it is preferable from the viewpoint of temperature control responsiveness, as the thermal resistance is not large. It is preferable to provide a spacer in the space layer 42 to limit the thickness of the space layer 42. In this way, it is easy to maintain the overall thickness of the space layer 42.

[0065] Furthermore, the large-diameter sealing ring 43 is preferably a component that combines a metal ring and a resin ring (e.g., a component with a metal ring on the outer circumference and a resin ring on the inner circumference; or a component with a resin ring on the outer circumference and a metal ring on the inner circumference). This allows the metal ring to limit the deformation of the resin ring. Additionally, the first refrigerant flow path 31 preferably has a smaller cross-sectional area and a longer flow path length compared to the second refrigerant flow path 51. This improves heat dissipation through the first refrigerant flow path 31.

[0066] It should be noted that the present invention is not limited to any of the above embodiments. It goes without saying that as long as it falls within the technical scope of the present invention, it can be implemented in various ways.

[0067] For example, in the above embodiments, regarding the states of the first and second refrigerant flow paths 31 and 51, and the state of the space layer 42, when the wafer W is processed at high temperature, such as Figure 5As shown, the configuration was set up to efficiently dissipate heat from the chip W, such as Figure 6 The settings are as shown, but are not specifically limited to them. For example, it is also possible to appropriately set whether the first refrigerant circulates in the first refrigerant flow path 31 and whether the second refrigerant circulates in the second refrigerant flow path 51, depending on the situation. The temperatures of the first and second refrigerants can also be appropriately set, depending on the situation. It is also possible to appropriately set whether the space layer 42 is a vacuum or filled with heat transfer gas, depending on the situation.

[0068] In the above embodiment, the heater electrode 26 is wired throughout the central portion 22 of the ceramic substrate 20 when viewed from above. However, the central portion 22 can also be divided into multiple regions and the heater electrode can be wired in each region. In addition, the wafer adsorption electrode 25 and the FR adsorption electrode 27 are unipolar, but bipolar types can also be used.

[0069] In the above embodiments, the through holes of the power supply terminals 62, 64, 66 in the first cooling substrate 30 may also have an insulating film on the inner wall or an insulating tube for inserting the power supply terminals. However, they may also not have such an insulating film or insulating tube, and insulation may be ensured only by the distance between the power supply terminals 62, 64, 66 and the inner wall of the through holes.

[0070] In the above embodiments, the fastening member 70 and the mounting member 74 are set as ring-shaped members, but they can also be circular arc members that divide the ring-shaped member into multiple circular arcs.

[0071] In the above embodiment, the high-frequency power supply is connected to the second cooling substrate 50, but it can also be connected to the first cooling substrate 30. Alternatively, the high-frequency power supply can be either a bias power supply for introducing ions into the wafer W or a source power supply for generating plasma.

[0072] In the above embodiments, a ceramic molded body is produced by molding, but it is not particularly limited to this method. For example, multiple strip-shaped molded bodies can also be stacked to produce a ceramic molded body. Alternatively, it can be replaced with... Figure 3 The first and third ceramic molded bodies 111 and 113 of (a) are used to form a ceramic powder layer between the first and third ceramic sintered bodies, and hot pressing is performed in this state to produce a ceramic sintered body 120 with a built-in wafer adsorption electrode 25, heater electrode 26 and FR adsorption electrode 27.

[0073] In the above embodiment, the second cooling substrate 50 is connected to the high-frequency power supply 87, but alternatively, the first cooling substrate 30 can be connected to the high-frequency power supply 87.

[0074] In the above embodiments, the outer periphery 24 of the ceramic substrate 20 may also contain a heater electrode.

Claims

1. A wafer mounting stage, comprising: A ceramic substrate having a wafer mounting surface and an embedded electrostatic electrode and a heater electrode; A first cooling substrate, bonded via a metal bonding layer to a surface of the ceramic substrate opposite to the wafer mounting surface, has a first refrigerant flow path capable of switching the supply and stopping of a first refrigerant; and The second cooling substrate, mounted on the surface opposite to the metal bonding layer in the first cooling substrate through a space layer capable of supplying heat transfer gas, has a second refrigerant flow path capable of independently switching the supply and cessation of the second refrigerant in conjunction with the supply and cessation of the first refrigerant. The first refrigerant flow path and the second refrigerant flow path are not connected. The second refrigerant is different from the first refrigerant.

2. The wafer mounting stage according to claim 1, wherein, At least one of the first cooling substrate and the second cooling substrate also serves as an electrode for plasma generation.

3. The wafer mounting stage according to claim 1 or 2, wherein, The difference in the coefficient of thermal expansion between the ceramic substrate and the first cooling substrate is 1×10⁻⁶. -6 / K or below.

4. The wafer mounting stage according to claim 1 or 2, wherein, The thickness of the space layer is greater than 0.05 mm and less than 2 mm.

5. The wafer mounting stage according to claim 1 or 2, wherein, The space layer is divided by a sealing ring disposed between the first cooling substrate and the second cooling substrate.

6. The wafer mounting stage according to claim 5, wherein, The sealing ring is a component that combines a metal ring and a resin ring.

7. The wafer mounting stage according to claim 5, wherein, The space layer is provided with a spacer to limit the thickness of the space layer.

8. The wafer mounting stage according to claim 6, wherein, The space layer is provided with a spacer to limit the thickness of the space layer.

9. The wafer mounting stage according to claim 1 or 2, wherein, Compared with the second refrigerant flow path, the first refrigerant flow path has a smaller cross-sectional area and a longer flow path length.

Images