Semiconductor device and method of stacking devices using a support frame

Abstract

A semiconductor device has a first substrate and a first electrical component disposed on the first substrate. A first support frame is disposed on the first substrate. The first support frame has a horizontal support channel extending across the first substrate and a vertical support bracket extending from the horizontal support channel to the first substrate. The first support frame can have a vertical shield bulkhead extending from the horizontal support channel to the first substrate. A sealant is deposited on the first electrical component and the first substrate and around the first support frame. A second electrical component is disposed on the first electrical component. A second substrate is disposed on the first support frame. The second electrical component is disposed on the second substrate. A third substrate is disposed on the second substrate. A second support frame is disposed on the second substrate.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods of stacking devices using support frames. BACKGROUND

[0002] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networking, computing, entertainment, and consumer products.

[0003] Semiconductor devices continue to increase in electrical functionality. More electrical functionality often requires more internal components and more surface area. However, surface area on a PCB is very valuable. A common method to achieve more electrical functionality in a given footprint is to stack semiconductor devices vertically. Semiconductor die stacking requires structural support and vertical electrical interconnection, which is often achieved with conductive vias embedded within encapsulant around the semiconductor die. Conductive vias and encapsulant have limited support capability, poor heat dissipation, and are prone to warpage. BRIEF DESCRIPTION OF DRAWINGS

[0004] Figures la- lc illustrates a semiconductor wafer having multiple semiconductor dies separated by a saw street;

[0005] Figures 2a-2r illustrates a process of forming a semiconductor package having a support frame for structural support;

[0006] Figures 3a-3e illustrates another method of forming a semiconductor package having a support frame for structural support;

[0007] Figures 4a-4b illustrates a second embodiment of a semiconductor package having a support frame;

[0008] Figures 5a-5b illustrates a third embodiment of a semiconductor package having a support frame;

[0009] Figures 6a-6b illustrates a fourth embodiment of a semiconductor package having a support frame; and

[0010] Figure 7 illustrates a PCB having different types of packages mounted to the surface of a printed circuit board (PCB). DETAILED DESCRIPTION

[0011] In the following description of drawings in reference to the drawings, the application is described in one or more embodiments, wherein like numbers represent the same or similar elements. While the application has been described in the best mode contemplated, it is recognized that the application is amenable to alterations, modifications, and substitutions by one of ordinary skill in the art, which are intended to be covered by the following claims and their equivalents. The term "semiconductor die" as used herein refers to both the singular and plural of the word and thus can refer to both a single semiconductor device and multiple semiconductor devices.

[0012] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming a plurality of dies on a surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. The active electrical components, such as transistors and diodes, have a

[0013] Back-end manufacturing refers to the process of cutting or singulating the completed wafers into individual semiconductor dies and packaging the semiconductor dies to form a semiconductor device. To singulate the semiconductor dies, the wafer is scribed and broken along non-functional areas of the wafer called saw streets or scribe lines. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor dies are mounted to a packaging substrate that includes pins or contact pads for interconnection with other system components. The contact pads formed on the semiconductor dies are then connected to the contact pads within the package. The electrical connections can be made with conductive layers, bumps, stud bumps, conductive paste, or wirebonds. A sealant or other molding material is deposited over the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system and the functions of the semiconductor device are made available to other system components.

[0014] Figure la A semiconductor wafer 100 is shown having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or components 104 are formed on the wafer 100 separated by non-active inter-die wafer areas or saw streets 106. The saw streets 106 provide cutting areas to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0015] Figure lb A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or non-active surface 108 and an active surface 110 that includes analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed over the die and electrically interconnected according to the electrical design and function of the die. For example, the circuits can include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog circuits or digital circuits such as digital signal processors (DSPs), application specific integrated circuits (ASICs), memory or other signal processing circuits. The semiconductor die 104 can also include IPDs for RF signal processing such as inductors, capacitors, and resistors.

[0016] A conductive layer 112 is formed on the active surface 110 using PVD, CVD, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. The conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive material. The conductive layer 112 operates as a contact pad that is electrically connected to the circuits on the active surface 110.

[0017] A conductive bump material is deposited on the conductive layer 112 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with or without a flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or leadless solder. The bump material is bonded to the conductive layer 112 using a suitable adhesion or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 114. In one embodiment, the bump 114 is formed on an under bump metallization (UBM) having a wetting layer, barrier layer, and adhesion layer. The bump 114 can also be crimped or thermocompression bonded to the conductive layer 112. The bump 114 represents one type of interconnect structure that can be formed on the conductive layer 112. Interconnect structures can also use wirebonds, conductive adhesive, stud bumps, micro bumps, or other electrical interconnects.

[0018] In Figure lc The semiconductor wafer 100 is singulated into individual semiconductor dies 104 through the scribe lanes 106 using a saw blade or laser cutting tool 118. The individual semiconductor dies 104 can be inspected and electrically tested for identifying KGD after singulation.

[0019] Figures 2a-2rA process of forming a semiconductor package with a support frame for structural support is illustrated. Figure 2a A cross-sectional view of an interconnect substrate or PCB 120 is shown, including conductive layers 122 and insulating layers 124. The conductive layers 122 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. The conductive layers 122 provide horizontal electrical interconnects across the substrate 120, as well as vertical electrical interconnects between the top surface 126 and the bottom surface 128 of the substrate 120. Depending on the design and functionality of the semiconductor die 104 and other electrical components, portions of the conductive layers 122 can be electrically common or electrically isolated. The insulating layers 124 include one or more layers of silicon dioxide (Si02), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta205), aluminum oxide (AI2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials with similar insulating and structural properties. The insulating layers 124 provide isolation between the conductive layers 122.

[0020] In Figure 2b , multiple electrical components 130a-130c are mounted to the surface 126 of the interconnect substrate 120 and electrically and mechanically connected to the conductive layers 122. The electrical components 130a-130c are each positioned on the substrate 120 using a pick-and-place operation. For example, the electrical component 130a can be a semiconductor die 104 from Figure lc , with the active surface 110 and bumps 114 oriented toward the surface 126 of the substrate 120 and electrically connected to the conductive layers 122. The electrical component 130b can be a discrete semiconductor device 134, such as a transistor, diode, capacitor, inductor, or resistor. The terminals 136 of the discrete semiconductor device 134 are electrically connected to the conductive layers 122. The electrical component 130c can be a semiconductor die 140, such that similar to the semiconductor die 104, there are different package types and device functionalities. The bumps 142 on the semiconductor die 140 are electrically connected to the conductive layers 122 on the surface 126. Alternatively, the electrical components 130a-130c can include other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical devices, discrete transistors, diodes, or IPDs. The electrical components 130a-130c are mounted to the interconnect substrate 120 as shown in Figure 2c , with the mechanical and electrical connections of the bumps 114 and 142, terminals 136 to the conductive layers 122.

[0021] Figure 2d A perspective view of a support frame 150 is illustrated. The support frame 150 includes interconnected horizontal support channels 152, vertical support brackets 154, and a center pad 156. Figure 2e is from Figure 2da top view of the support frame 150 having horizontal support channels 152, vertical support brackets 154, and a center pad 156 arranged to provide compartments 158a-158d for electrical components 130a-130c. The horizontal support channels 152 and vertical support brackets 154 can be stamped from sheet metal, similar to a lead frame, and joined together with adhesive. Alternatively, the support frame 150 can be formed from 3D imaging. The support frame 150 can be made from Al, Cu, Sn, Ni, Au, Ag, or other structurally stable materials. Alternatively, the support frame 150 can be carbonyl iron, stainless steel, nickel silver, mild steel, silicon iron steel, polymers, epoxy, and other metals and composites capable of providing structural support for semiconductor packages.

[0022] Figure 2f Another embodiment of the support frame 150 is illustrated having interconnected horizontal support channels 152, vertical support brackets 154, and a center pad 156. Figure 2g is from Figure 2f a top view of the support frame 150 having horizontal support channels 152, vertical support brackets 154, and a center pad 156 arranged to provide compartments 158a-158e for electrical components 130a-130c.

[0023] Figure 2h Yet another embodiment of the support frame 150 is illustrated having interconnected horizontal support channels 152, vertical support brackets 154, and a center pad 156. Figure 2i is from Figure 2h a top view of the support frame 150 having horizontal support channels 152, vertical support brackets 154, and a center pad 156 arranged to provide compartments 158a-158c for electrical components 130a-130c.

[0024] Figure 2j Yet another embodiment of the support frame 150 is illustrated having interconnected horizontal support channels 152, vertical support brackets 154, and a center pad 156 arranged to provide compartments 158a-158d for electrical components 130a-130c. In this case, solid vertical panels or partitions 159 provide RFI / EMI shielded isolation for electrical components 130a-130c in compartments 158a-158d.

[0025] Once the electrical components 130a-130c are mounted to the interconnect substrate 120, the support frame 150 can be mounted to the interconnect substrate. In Figure 2k is from Figure 2dA support frame 150 is positioned on the surface 126 of the interconnect substrate 120. The support frame 150 is shown in cross-section along line 2k-2k from Figure 2k Figure 2d The support frame 150 is lowered to a point where the support brackets 154 contact the surface 126 between the electrical components 130a-130c, as shown in Figure 21 Particularly, the support frame 150 provides structural support for electrical components, substrates, PCBs, and semiconductor packages disposed above the support frame. In addition, the support frame 150 provides isolation between the electrical components 130a-130b and the electrical component 130c from external components. The support frame 150 can also provide vertical electrical interconnections, i.e., through the metallic vertical brackets 154. Figure 2m is a perspective view of the support frame 150 mounted to the interconnect substrate 120 with the electrical components 130a-130c disposed in the compartments 158a-158d. Figure 2n is a perspective view of the support frame 150 from Figure 2j mounted to the interconnect substrate 120 with the electrical components 130a-130c disposed in the compartments 158a-158d and separated by the vertical panel 159 for RFI / EMI isolation and shielding.

[0026] Figure 20 A cross-section of an interconnect substrate or PCB 170 is shown that includes conductive layers 172 and insulating layers 174. The conductive layers 172 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layers 172 provide horizontal electrical interconnections across the substrate 170 as well as vertical electrical interconnections between the top surface 176 and the bottom surface 178 of the substrate 170. Depending on the design and functionality of the semiconductor die 104 and other electrical components, portions of the conductive layers 172 can be electrically common or electrically isolated. The insulating layers 174 include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials with similar insulating and structural properties. The insulating layers 174 provide isolation between the conductive layers 172.

[0027] The interconnect substrate 170 is positioned on the support frame 150 and lowered to a point where the surface 178 contacts the horizontal support channels 152 and the center pad 156 of the support frame 150, as shown in Figure 2p ​The adhesive can be used to bond the interconnect substrate 170 to the support frame 150. Alternatively, the interconnect substrate 170 is bonded by dispensing or flux immersion. Thus, the support frame 150 provides structural support for the interconnect substrate 170 and any electrical components mounted to the interconnect substrate. The support frame 150 can also provide a ground connection between the PCB 170 and the PCB 120 through horizontal support channels 152 and vertical support brackets 154. In one embodiment, each vertical support bracket 154 can be a separate vertical conductive path.

[0028] In Figure 2q In one embodiment, a paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator is used to deposit a sealant or molding compound 180 on the surface 126 of the electrical components 130a-130c and the interconnect substrate 120 and around the support frame 150. The support frame 150 has openings on at least two sides to allow free flow of the sealant 180 across the electrical components 130a-130c and the support frame 150. The sealant 180 can be a polymer composite such as an epoxy with fillers, an epoxy acrylate with fillers, or a polymer with suitable fillers. The sealant 180 is non-conductive, provides structural support, and environmentally protects the semiconductor devices from external elements and contaminants.

[0029] In Figure 2r In one embodiment, an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process is used to deposit a conductive bump material on the conductive layer 122 on the surface 128 of the interconnect substrate 120. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high lead solder, or lead-free solder. The bump material is bonded to the conductive layer 122 using a suitable adhesion or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps 184. In one embodiment, the bumps 184 are formed on a UBM with a wetting layer, a barrier layer, and an adhesion layer. The bumps 184 can also be crimped or thermocompression bonded to the conductive layer 122. The bumps 184 represent one type of interconnect structure that can be formed on the conductive layer 122. Interconnect structures can also use wirebonds, conductive adhesive, stud bumps, micro bumps, or other electrical interconnects.

[0030] Figure 2rsemiconductor package 186 uses support frame 150 for structural support and isolation of electrical components 130a-130c. PCB 170 is stacked on PCB 120 containing electrical components 130a-130c and provides vertical electrical interconnections. Support frame 150 provides rigid structural support for the vertical stacking of PCB 170 and other components while reducing warpage and increasing heat dissipation through semiconductor package 186. Component stacking in a small package footprint increases electrical functionality. Support frame 150 can also provide RFI / EMI shielding for electrical components 130a-130c disposed in individual compartments 158a-158d, see Figure 2j , 2n . Support frame 150 can also provide a ground connection between PCB 170 and PCB 120 and bump 184 through vertical support bracket 154.

[0031] Figures 3a-3e Another process of forming a semiconductor package with a support frame for structural support is illustrated. From Figures 21-2m continuing, a sealant or molding compound 190 is deposited on the surface 126 of electrical components 130a-130c and interconnect substrate 120 and around support frame 150 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator, as shown in Figure 3a . Support frame 150 has openings on at least two sides to allow free flow of sealant 190 across electrical components 130a-130c and support frame 150. Sealant 190 can be a polymer composite such as an epoxy with fillers, an epoxy acrylate with fillers, or a polymer with appropriate fillers. Sealant 190 is electrically non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.

[0032] In Figure 3b , a portion of sealant 190 is removed by a grinder 192 to expose a surface 194 of sealant 194 that is coplanar with a top surface 196 of center pad 156. Grinder 192 planarizes the surface 194 of sealant 190 and the top surface 196 of center pad 156, as shown in Figure 3c .

[0033] Figure 3dA cross-sectional view of an interconnect substrate or PCB 200 is shown that includes conductive layers 202 and insulating layers 204. The conductive layers 202 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. The conductive layers 202 provide horizontal electrical interconnections across the substrate 200 as well as vertical electrical interconnections between the top surface 206 and the bottom surface 208 of the substrate 200. Portions of the conductive layers 202 can be electrically common or electrically isolated depending on the design and function of the semiconductor die 104 and other electrical components. The insulating layers 204 include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials with similar insulating and structural properties. The insulating layers 204 provide isolation between the conductive layers 202.

[0034] The interconnect substrate 200 is positioned on the support frame 150 and the encapsulant 190 and lowered so that the surface 178 contacts the horizontal support channels 152 and the center pad 156 of the support frame 150, similar to Figure 20 and 2p An adhesive can be used to bond the interconnect substrate 200 to the support frame 150. Thus, the support frame 150 provides structural support for the interconnect substrate 200 and any electrical components mounted to the interconnect substrate.

[0035] In Figure 3e , an evaporative, electrolytic plating, electroless plating, ball drop, or screen printing process is used to deposit a conductive bump material on the conductive layer 122 on the surface 128 of the interconnect substrate 120. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder, or lead-free solder. The bump material is bonded to the conductive layer 122 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form the balls or bumps 210. In one embodiment, the bumps 210 are formed on UBMs with a wetting layer, a barrier layer, and an adhesion layer. The bumps 210 can also be crimped or thermocompression bonded to the conductive layer 122. The bumps 210 represent one type of interconnect structure that can be formed on the conductive layer 122. Interconnect structures can also use wirebonds, conductive adhesive, stud bumps, micro bumps, or other electrical interconnections.

[0036] Figure 3esemiconductor package 212 uses support frame 150 for structural support and isolation of electrical components 130a-130c. PCB 200 is stacked on PCB 120 containing electrical components 130a-130c and provides vertical electrical interconnections. Support frame 150 provides rigid structural support for the vertical stacking of PCB 200 and other components while reducing warpage and increasing heat dissipation through semiconductor package 212. Component stacking in a small package footprint increases electrical functionality. Support frame 150 can also provide RFI / EMI shielding for electrical components 130a-130c disposed in individual compartments 158a-158d, see Figure 2j , 2n . Support frame 150 can also provide a ground connection between PCB 200 and PCB 120 and bump 184 through vertical support standoffs 154.

[0037] In another embodiment of forming a semiconductor package with a support frame for structural support, Figure 4a A cross-sectional view of an interconnect substrate or PCB 220 is shown that includes conductive layers 222 and insulating layers 224. Conductive layers 222 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Conductive layers 222 provide horizontal electrical interconnections across substrate 220 and vertical electrical interconnections between top surface 226 and bottom surface 228 of substrate 220. Portions of conductive layers 222 can be electrically common or electrically isolated depending on the design and functionality of semiconductor dies and other electrical components. Insulating layers 224 contain one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials with similar insulating and structural properties. Insulating layers 224 provide isolation between conductive layers 222.

[0038] A plurality of electrical components 230a-230f are mounted to or on the surface 226 of the interconnect substrate 220 and are electrically connected to the conductive layer 222. The electrical components 230a-230f are each positioned on the substrate 220 using a pick and place operation. For example, electrical components 230a and 230b are stacked semiconductor dies, such that similar to semiconductor dies 104, although possibly of different types and functionality. A conductive via 232 extends through the stacked electrical components 230a-230b. A bond wire 234 makes an electrical connection between electrical component 230a and electrical component 230b. Bumps 236 make electrical connections between electrical components 230a-230b and the interconnect substrate 220. Electrical component 230c can be a discrete semiconductor device, such as a transistor, diode, capacitor, inductor, or resistor, electrically connected to the conductive layer 122. Electrical components 230d-230f are stacked semiconductor dies, such that similar to semiconductor dies 104, although possibly of different types and functionality. A conductive via 238 extends through the stacked electrical components 230d-230f. Bumps 239 make electrical connections between electrical components 230d-230f and the interconnect substrate 220 and other interconnect substrates. In one embodiment, electrical components 230d-230f can be embedded stacked PCBs. In another embodiment, the stacked electronic components 230d-230f can be embedded antennas, such as 5G antenna-in-package (AiP).

[0039] A support frame 240 is positioned on the surface 226 of the interconnect substrate 220. The support frame 240 follows the structure and materials of the support frame 150, as in Figures 2d-21 . The support frame 240 is lowered to a point where the support brackets 244 contact the surface 226 between the electrical components 230a-230f, as shown in Figure 4a . Adhesive bonds the support brackets 244 to the surface 226 of the interconnect substrate 220. In particular, the support frame 240 provides structural support for the electrical components, substrates, and semiconductor packages disposed above the support frame. Further, the support frame 240 provides isolation between the electrical components 230a-230c and the electrical components 230d-130f from external components. The support frame 240 can also provide vertical electrical interconnections, i.e., through the metallic vertical brackets 244.

[0040] In Figure 4bIn particular embodiments, a sealant or molding compound 246 is deposited on the surface 226 of the electrical components 230a-230f and the interconnect substrate 220 and around the support frame 240 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. The support frame 240 has openings on at least two sides to allow free flow of the sealant 246 across the electrical components 230a-230f and the support frame 240. The sealant 246 can be a polymer composite such as an epoxy with fillers, an epoxy acrylate with fillers, or a polymer with suitable fillers. The sealant 246 is electrically non-conductive, provides structural support, and environmentally protects the semiconductor devices from external elements and contaminants.

[0041] Similar to Figures 20-2p , an interconnect substrate or PCB 250 is disposed on the support frame 240 and the sealant 246. The conductive layers 252 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive materials. The conductive layers 252 provide horizontal electrical interconnections across the substrate 250 and vertical electrical interconnections between the top surface 256 and the bottom surface 258 of the substrate 250. Depending on the design and functionality of the semiconductor dies and other electrical components, portions of the conductive layers 252 can be electrically common or electrically isolated. The insulating layers 254 include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials with similar insulating and structural properties. The insulating layers 254 provide isolation between the conductive layers 252. Bumps 259 make electrical connections between the electrical components 230a-230b and the conductive layers 252. Bumps 239 make electrical connections between the electrical components 230d-230f and the conductive layers 252. Discrete electrical components 260 can be embedded between the insulating layers 254 and electrically connected to the conductive layers 252. Alternatively, the sealant 246 can be deposited prior to mounting the interconnect structure 250, as in Figures 3a-3c .

[0042] Conductive bump material is deposited on the conductive layer 222 on the surface 228 of the interconnect substrate 220 using evaporation, electroplating, electroless plating, droplet, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, or combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer 222 using a suitable adhesion or bonding process. In one embodiment, the bump material is reflowed by heating it above its melting point to form balls or bumps 262. In one embodiment, bumps 262 are formed on a UBM having a wetting layer, a barrier layer, and an adhesive layer. Bumps 262 can also be press-fitted or thermo-press-fitted to the conductive layer 222. Bumps 262 represent a type of interconnect structure that can be formed on the conductive layer 222. The interconnect structure can also use bonding wires, conductive adhesive, stud bumps, microbumps, or other electrical interconnects.

[0043] Semiconductor package 264 uses support frame 240 for structural support and isolation of electrical components 230a-230f. PCB 250 is mounted on the stacked electrical components 230a-230f and provides vertical electrical interconnects. Support frame 240 provides rigid structural support for PCB 250 and the stacked electrical components 230a-230f, while reducing warpage and increasing heat dissipation through semiconductor package 264. The component stacking increases electrical functionality within a small package footprint. Support frame 240 also provides RFI / EMI shielding for electrical components 230a-230f housed in individual compartments 158a-158d, see [link to documentation]. Figure 2j , 2n The support frame 240 can also provide a grounding connection between the PCB 250 and the PCB 220 and the bump 262 via the vertical support bracket of the support frame 240.

[0044] As Figure 5a Another embodiment of the present invention, from Figure 4b Continuing, the electrical component or semiconductor die 266 is mounted to the surface 256 of the interconnect substrate 250 and electrically connected to the conductive layer 252 using bumps 268, similar to... Figures 2b-2c .

[0045] exist Figure 5bIn this process, a sealant or molding compound 270 is deposited on the semiconductor die 266 and interconnect structure 250 using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable applicators. The sealant 270 can be a polymer composite material, such as a filled epoxy resin, a filled epoxy acrylate, or a polymer with appropriate fillers. The sealant 270 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external components and contaminants.

[0046] Electrical components 230a-230f may include IPDs that are susceptible to or generate EMI, RFI, harmonic distortion, and inter-device interference. For example, the IPDs included within electrical components 230a-230f provide the electrical characteristics required for high-frequency applications, such as resonators, high-pass filters, low-pass filters, band-pass filters, symmetrical Hi-Q resonant transformers, and tuning capacitors. In another embodiment, electrical components 230a-230f include digital circuitry that switches at high frequencies, which may interfere with the operation of the IPDs within the semiconductor package.

[0047] exist Figure 5b In this process, an electromagnetic shielding layer 272 is formed or disposed on the surface 274 of the sealant 270 by conformally applying the shielding material. The shielding layer 272 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Alternatively, the shielding layer 272 may be carbonyl iron, stainless steel, nickel silver, low-carbon steel, ferrosilicon steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference. Furthermore, the shielding layer 272 covers the side surface 276 of the sealant 270 and the side surface of the semiconductor package 279.

[0048] Conductive bump material is deposited on the conductive layer 222 on the surface 228 of the interconnect substrate 220 using evaporation, electroplating, electroless plating, droplet, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, or combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer 222 using a suitable adhesion or bonding process. In one embodiment, the bump material is reflowed by heating it above its melting point to form balls or bumps 278. In one embodiment, the bumps 278 are formed on a UBM having a wetting layer, a barrier layer, and an adhesive layer. The bumps 278 can also be press-fitted or thermo-press-fitted to the conductive layer 222. The bumps 278 represent a type of interconnect structure that can be formed on the conductive layer 222. The interconnect structure can also use bonding wires, conductive adhesive, stud bumps, microbumps, or other electrical interconnects.

[0049] The semiconductor package 279 uses the support frame 240 for structural support and isolation of the electrical components 230a-230f. The PCB 250 is disposed on the stacked electrical components 230a-230f and provides vertical electrical interconnections. The support frame 240 provides rigid structural support for the PCB 250 and the stacked electrical components 230a-230f and semiconductor die 266 while reducing warpage and increasing heat dissipation through the semiconductor package 279. The component stacking increases electrical functionality in a small package footprint. The support frame 240 can also provide RFI / EMI shielding for the electrical components 230a-230f disposed in the individual compartments 158a-158d, see Figure 2j 、 2n . The support frame 240 can also provide a ground connection between the PCB 250 and the PCB 220 and bump 278 through vertical support brackets of the support frame 240.

[0050] As another embodiment in Figure 6a , from Figure 4a continuing, vertical interconnect bumps 280 are formed on the interconnect substrate 220 and electrically connected to the conductive layer 222. The bumps 280 can have an inner core 280a made of a polymeric material, and an outer conductive layer 280b.

[0051] A sealant or molding compound 284 is deposited on the surfaces 226 of the electrical components 230a-230f and the interconnect substrate 220 and around the support frame 240 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. The support frame 240 has openings on at least two sides to allow free flow of the sealant 284 across the electrical components 230a-230f and the support frame 240. The sealant 284 can be a polymeric composite such as an epoxy with fillers, an epoxy acrylate with fillers, or a polymer with appropriate fillers. The sealant 284 is electrically non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.

[0052] Similar to Figures 20-2pAn interconnect substrate or PCB 290 is disposed on the support frame 240 and encapsulant 284. The conductive layers 292 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layers 292 provide horizontal electrical interconnections across the substrate 290 and vertical electrical interconnections between the top surface 296 and the bottom surface 298 of the substrate 290. Depending on the design and functionality of the semiconductor dies and other electrical components, portions of the conductive layers 252 can be electrically common or electrically isolated. The insulating layers 294 include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials with similar insulating and structural properties. The insulating layers 254 provide isolation between the conductive layers 292. Discrete electrical components 300 can be embedded between the insulating layers 294 and electrically connected to the conductive layers 292. Alternatively, the encapsulant 284 can be deposited after the mounting of the interconnect structure 290, as in Figure 2q .

[0053] Similar to Figures 2b-2c , electrical components or semiconductor dies 304 are mounted to the surface 296 of the interconnect substrate 290 and electrically connected to the conductive layers 292 with bumps 308. Conductive vias 310 extend through the semiconductor dies 304 and are electrically connected to the bumps 308.

[0054] In Figure 6b , a plurality of vertical interconnect bumps 312 are formed on the interconnect substrate 290 and electrically connected to the conductive layers 292. The bumps 312 can have an inner core 312a made of a polymeric material and an outer conductive layer 312b. Similar to the support frame 150 in Figures 2d-21 , a support frame 316 is mounted to the interconnect substrate 290. Bumps 318 are formed on the semiconductor dies 304 and electrically connected to the conductive vias 310.

[0055] An encapsulant or molding compound 320 is deposited on the semiconductor dies 304 and bumps 312 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicators. The support frame 316 has openings on at least two sides to allow free flow of the encapsulant 320 across the electrical components 230a-230f and the support frame 316. The encapsulant 320 can be a polymeric composite, such as an epoxy resin with fillers, an epoxy acrylate with fillers, or a polymer with suitable fillers. The encapsulant 320 is electrically non-conductive, provides structural support, and environmentally protects the semiconductor devices from external elements and contaminants.

[0056] Similar to Figures 20-2pAn interconnect substrate or PCB 330 is disposed on the support frame 316 and encapsulant 320. The conductive layers 332 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. The conductive layers 332 provide horizontal electrical interconnects across the substrate 330 and vertical electrical interconnects between the top surface 336 and the bottom surface 338 of the substrate 330. Portions of the conductive layers 332 can be electrically common or electrically isolated depending on the design and function of the semiconductor die and other electrical components. The insulating layers 334 include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials with similar insulating and structural properties. The insulating layers 334 provide isolation between the conductive layers 332.

[0057] A conductive bump material is deposited on the conductive layer 222 on the surface 228 of the interconnect substrate 220 using an evaporation, electroplating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high lead solder, or lead-free solder. The bump material is bonded to the conductive layer 222 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form the balls or bumps 340. In one embodiment, the bumps 340 are formed on UBMs with wetting, barrier, and adhesion layers. The bumps 340 can also be compression or thermocompression bonded to the conductive layer 222. The bumps 340 represent one type of interconnect structure that can be formed on the conductive layer 222. Interconnect structures can also use wirebonds, conductive adhesive, stud bumps, micro bumps, or other electrical interconnects.

[0058] The semiconductor package 330 uses the support frames 240 and 316 for structural support and isolation of the electrical components 230a-230f. The PCB 290 is disposed on the stacked electrical components 230a-230f and provides vertical electrical interconnects. The support frames 240 and 316 provide rigid structural support for the PCB 250 and the stacked electrical components 230a-230f as well as the semiconductor die 304 and the PCB 330 while reducing warpage and increasing heat dissipation through the semiconductor package 342. The stacking of components in a small package footprint increases electrical functionality. The support frames 240 and 316 can also provide RFI / EMI shielding for the electrical components 230a-230f disposed in the individual compartments 158a-158d, see Figure 2j , 2n The support frames 240 and 316 can also provide a ground connection between the PCB 330 and the PCB 290 and the bumps 340 through vertical support brackets of the support frames 240 and 316.

[0059] Figure 7 An electronic device 400 is illustrated with a chip carrier substrate or PCB 402, where multiple semiconductor packages are mounted on a surface of the PCB 402, including semiconductor packages 186, 212, 264, 279, and 330. Depending on the application, the electronic device 400 can have one type of semiconductor package or multiple types of semiconductor packages.

[0060] The electronic device 400 can be a stand-alone system that uses semiconductor packages to perform one or more electrical functions. Alternatively, the electronic device 400 can be a subcomponent of a larger system. For example, the electronic device 400 can be part of a tablet computer, cellular phone, digital camera, communication system, or other electronic device. Alternatively, the electronic device 400 can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor packages can include microprocessors, memory, ASICs, logic circuitry, analog circuitry, RF circuitry, discrete devices, or other semiconductor dies or electrical components. Miniaturization and light weight are critical for market acceptance of products. Distances between semiconductor devices can be reduced to achieve higher densities.

[0061] In Figure 7 The PCB 402 provides a common substrate for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 404 are formed on a surface or within layers of the PCB 402 using evaporation, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. The signal traces 404 provide electrical communication between each of the semiconductor packages, mounted components, and other external system components. The traces 404 also provide power and ground connections to each of the semiconductor packages.

[0062] In some embodiments, the semiconductor device has two levels of packaging. The first level of packaging is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second level of packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device can have only the first level of packaging, where the die is mechanically and electrically mounted directly to the PCB. For illustrative purposes, several types of first level packaging are shown on the PCB 402, including wire bond packaging 406 and flip chip 408. In addition, several types of second level packaging are shown mounted on the PCB 402, including ball grid array (BGA) 410, bump chip carrier (BCC) 412, land grid array (LGA) 416, multi-chip module (MCM) or SIP module 418, quad flat no-lead package (QFN) 420, quad flat package 422, embedded wafer level ball grid array (eWLB) 424, and wafer level chip scale package (WLCSP) 426. In one embodiment, the eWLB 424 is a fan-out wafer level package (Fo-WLP), and the WLCSP 426 is a fan-in wafer level package (Fi-WLP). Any combination of semiconductor packages configured in first and second level packaging styles, as well as other electronic components, can be connected to the PCB 402 depending on system requirements. In some embodiments, the electronic device 400 includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate pre-fabricated components into electronic devices and systems. Because the semiconductor packages include complex functionality, less expensive components and simplified manufacturing processes can be used to manufacture the electronic devices. The resulting devices are less likely to fail and are less expensive to manufacture, resulting in lower costs to the consumer.

[0063] While one or more embodiments of the application have been illustrated and described, as noted above, it will be readily apparent to those of ordinary skill in the art that many modifications, adaptations and variations of such embodiments can be made without departing from the scope of the present application as set forth in the following claims.

Claims

1. A semiconductor device comprising: a first substrate; a first electrical component disposed on the first substrate; a second electrical component disposed on the first substrate; a first support frame disposed on the first substrate around the first and second electrical components, wherein the first support frame comprises, (a) a plurality of horizontal support channels disposed separately from the first substrate, wherein center pads of the plurality of horizontal support channels define a plurality of compartments containing the first and second electrical components, and (b) a plurality of separate vertical support brackets extending from the plurality of horizontal support channels to the first substrate; a sealant deposited on the first and second electrical components and around a portion of the first support frame and the first substrate; and a second substrate disposed on the first support frame.

2. The semiconductor device of claim 1, further comprising a third electrical component disposed on the first electrical component.

3. The semiconductor device of claim 1, wherein the sealant deposited on the first and second electrical components and the first substrate extends to a top of the first support frame.

4. The semiconductor device of claim 1, wherein the first support frame comprises vertical shield partitions extending from the plurality of horizontal support channels to the first substrate.

5. A semiconductor device comprising: a first substrate; a first electrical component disposed on the first substrate; and a second electrical component disposed on the first substrate; a first support frame disposed on the first substrate, wherein the first support frame comprises: a plurality of horizontal support channels extending across the first substrate, wherein center pads of the plurality of horizontal support channels define a plurality of compartments containing the first and second electrical components; and a plurality of separate vertical support brackets extending from the plurality of horizontal support channels to the first substrate. a sealant deposited on the first and second electrical components and around the first support frame.

6. The semiconductor device of claim 5, further comprising:

7. The semiconductor device of claim 5, wherein the first support frame comprises vertical shield partitions extending from the plurality of horizontal support channels to the first substrate. a second substrate disposed on the first support frame.

8. The semiconductor device of claim 5, further comprising: a third substrate disposed on the second substrate.

9. The semiconductor device of claim 8, further comprising:

10. A method of manufacturing a semiconductor device comprising: providing a first substrate; disposing a first electrical component on the first substrate; and disposing a second electrical component on the first substrate; disposing a first support frame on the first substrate, wherein the first support frame comprises: a plurality of horizontal support channels extending across the first substrate, wherein center pads of the horizontal support channels define a plurality of compartments containing the first and second electrical components; and a plurality of separate vertical support brackets extending from the horizontal support channels to the first substrate. depositing a sealant on the first and second electrical components and around the first support frame.

12. The method of claim 10, wherein the first support frame comprises vertical shield partitions extending from the horizontal support channels to the first substrate.

11. The method of claim 10, further comprising: disposing a second substrate on the first support frame. ​ 13. The method of claim 10, further comprising: ​

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