lateral diffused metal oxide semiconductor element

Abstract

A lateral diffusion metal oxide semiconductor element mainly comprises a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a protection ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation surrounding the protection ring.

Description

Technical Field

[0001] This invention relates to a laterally diffused metal-oxide semiconductor device, and more particularly to a laterally diffused metal-oxide semiconductor device having a guard ring surrounding the gate structure. Background Technology

[0002] Laterally diffused metal-oxide semiconductor devices (LDMOS) are widely used in high-voltage operating environments, such as CPU power supply, power management system, DC / DC converter, and high-power or high-frequency power amplifiers, due to their high operating bandwidth and efficiency, as well as their planar structure that is easy to integrate with other integrated circuits.

[0003] However, current laterally diffused metal-oxide-semiconductor (MOSFET) devices typically have excessively large cell areas, resulting in suboptimal on-state breakdown voltage and compatibility. Therefore, improving the cell design of existing laterally diffused MOSFET devices is an important current research topic. Summary of the Invention

[0004] An embodiment of the present invention discloses a laterally diffused metal-oxide-semiconductor device, which mainly includes a first gate structure and a second gate structure extending on a substrate along a first direction, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation surrounding the guard ring.

[0005] Another embodiment of the present invention discloses a laterally diffused metal-oxide-semiconductor device, comprising a first gate structure and a second gate structure extending on a substrate along a first direction, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a first protection region connecting the first source region and the second source region on one side of the first gate structure and the second gate structure, and a second protection region connecting the first source region and the second source region on the other side of the first gate structure and the second gate structure.

[0006] Another embodiment of the present invention discloses a laterally diffused metal-oxide-semiconductor device, which includes a first gate structure and a second gate structure extending on a substrate along a first direction, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, a plurality of guard regions connecting the first source region, the second source region and the guard ring, and a shallow trench isolation surrounding the guard ring. Attached Figure Description

[0007] Figure 1 This is a top view of a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present invention;

[0008] Figure 2 for Figure 1 A schematic cross-section along the tangent AA';

[0009] Figure 3 This is a top view of a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present invention;

[0010] Figure 4 This is a top view of a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present invention;

[0011] Figure 5 This is a top view of a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present invention.

[0012] Explanation of main component symbols

[0013] 12: Base

[0014] 14: P-trap

[0015] 16:N-well

[0016] 18: Shallow trench isolation

[0017] 20: Gate structure

[0018] 22: Gate Structure

[0019] 24: Source Region

[0020] 26: Source Region

[0021] 28: Drain region

[0022] 30: Protective ring

[0023] 32: Contact plug

[0024] 34: Protected Area

[0025] 36: Protected Area

[0026] 38: Protected Area

[0027] 42: Laterally diffused metal-oxide-semiconductor devices

[0028] 44: Laterally diffused metal-oxide-semiconductor devices

[0029] 46: Laterally diffused metal-oxide-semiconductor devices

[0030] 48: Protected Area Detailed Implementation

[0031] Please refer to Figures 1 to 2 , Figures 1 to 2 This is a schematic diagram of a method for fabricating a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present invention, wherein... Figure 1 A top view of a laterally diffused metal-oxide-semiconductor device. Figure 2 Then it is Figure 1 A schematic cross-sectional view along the tangent AA'. (See diagram below.) Figure 1 As shown, a substrate 12 is first provided, and then a first well region (e.g., P-well 14) and a second well region (e.g., N-well 16) are formed within the substrate. A shallow trench isolation (STI) 18 is then formed within the substrate 12. In this embodiment, the substrate 12 is preferably made of a semiconductor material, such as a silicon substrate, an epitaxial silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate. The shallow trench isolation 18 is preferably made of silicon oxide, but is not limited thereto.

[0032] Next, a gate structure 20 is formed on the left side of the substrate 12 and the shallow trench isolation 18, and a gate structure 22 is formed on the right side of the substrate 12 and the shallow trench isolation 18. Preferably, the gate structure 20 is disposed on the middle N-well 16 and the left side P-well 14, while the gate structure 22 is disposed on the middle N-well 16 and the right side P-well 14. In this embodiment, the above-mentioned gate structures 20 and 22 can be fabricated according to the fabrication process requirements using a gate-first fabrication process, a gate-last fabrication process with a high-k first dielectric layer, or a gate-last fabrication process with a high-k last dielectric layer. Taking the gate fabrication process of this embodiment as an example, a gate dielectric layer or dielectric layer, a gate material layer (not shown) and a selective hard mask (not shown) can be sequentially formed on the substrate 12. A patterned photoresist (not shown) is used as a mask to perform a pattern transfer fabrication process. In a single etching or successive etching step, part of the gate material layer and part of the gate dielectric layer are removed. Then the patterned photoresist is stripped to form gate structures 20 and 22 composed of patterned gate dielectric layer and patterned gate material layer on the substrate 12.

[0033] Then, at least one spacer wall (not shown) is formed on the sidewalls of each gate structure 20, 22, and source regions 24 and 26, composed of, for example, N+ regions, drain region 28, composed of N+ regions, and guard ring 30, composed of P+ regions, are formed in the substrate 12 on both sides of the gate structures 20, 22. Source region 24 is located on the left side of gate structure 20, source region 26 is located on the right side of gate structure 22, drain region 28 is located between gate structure 20 and gate structure 22, and guard ring 30, in the cross-sectional view, is located on the left side of gate structure 20 and the right side of gate structure 22, simultaneously contacting adjacent source regions 24 and 26. Subsequently, a metallization fabrication process may be selectively performed to form a metallization layer (not shown) on the surfaces of source regions 24, 26, drain region 28, and guard ring 30.

[0034] In this embodiment, the spacer wall can be a single spacer wall or a composite spacer wall, for example, it may include a bias spacer wall and a main spacer wall. The bias spacer wall and the main spacer wall may contain the same or different materials, and both can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. The source regions 24 and 26, the drain region 28, and the guard ring 30 may contain different dopants depending on the conductivity type of the transistor being disposed, for example, they may contain P-type dopants or N-type dopants.

[0035] Subsequently, an interlayer dielectric layer (not shown) can be selectively formed on the gate structures 20 and 22, and a pattern transfer fabrication process can be performed. For example, a patterned mask can be used to remove a portion of the interlayer dielectric layer next to the gate structures 20 and 22 to form multiple contact holes (not shown) and expose the gate structures 20 and 22, source regions 24 and 26, drain region 28, and the top of the guard ring 30. Then, the required conductive material is filled into each contact hole, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. A planarization process is then performed, for example, by chemical mechanical polishing to remove some of the conductive material to form contact plugs 32 that contact and electrically connect the gate structures 20, 22, the source regions 24, 26, and the drain region 28. This completes the fabrication of a semiconductor element according to an embodiment of the present invention.

[0036] It is worth noting that although the contact plug 32 formed in this embodiment is only disposed on the gate structures 20, 22, the source regions 24, 26, and the drain region 28, but not on the guard ring 30, it is not limited to this. According to other embodiments of the present invention, the contact plug can be disposed on the guard ring 30 at the same time as the contact plug 32 is formed, and this variation is also within the scope of the present invention. It should also be noted that although this embodiment takes a polysilicon gate structure prepared by a gate-first fabrication process as an example, it is not limited to this. According to other embodiments of the present invention, the polysilicon gate can be converted into a metal gate by a metal gate replacement (RMG) fabrication process according to the fabrication process or product requirements. Each metal gate can include elements such as a dielectric layer, a high dielectric constant dielectric layer, a work function metal layer, and a low impedance metal layer.

[0037] If each gate structure is composed of metal gates, the high-dielectric-constant dielectric layer may contain a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), and strontium bismuthtantalate oxide. SrBi₂Ta₂O₉ (SBT), lead zirconate titanate (PbZr) x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1-x The group consisting of TiO3, BST, or combinations thereof.

[0038] The work function metal layer is preferably used to adjust the work function of the metal gate, making it suitable for N-type transistors (NMOS) or P-type transistors (PMOS). If the transistor is an N-type transistor, the work function metal layer can be made of a metal material with a work function of 3.9 eV to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto. If the transistor is a P-type transistor, the work function metal layer can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but is not limited thereto. Another barrier layer (not shown in the figure) can be included between the work function metal layer and the low-impedance metal layer, and the material of the barrier layer can include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. The low-resistance metal layer can be selected from low-resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or combinations thereof. Since the fabrication of the metal gate is a well-known technique in the art, it will not be described in detail here.

[0039] Please refer to again Figure 1 ,from Figure 1 From the top view, gate structure 20 and gate structure 22 preferably extend along a first direction, such as the Y direction, on the substrate 12. Source region 24 extends along the Y direction on one side of gate structure 20 (as shown on the left), source region 26 extends along the Y direction on one side of gate structure 22 (as shown on the right), and drain region 28 extends along the Y direction between gate structure 20 and gate structure 22. Guard ring 30 surrounds gate structure 20 and gate structure 22, and shallow trench isolation 18 surrounds the entire guard ring 30. In this embodiment, guard ring 30 is preferably disposed around source regions 24 and 26 and surrounding source regions 24 and 26, drain region 28, and gate structures 20 and 22. Guard ring 30 preferably directly contacts source regions 24 and 26 on both sides of gate structures 20 and 22 but does not contact drain region 28. It should be noted that, for a simpler representation of the positions of each component, Figure 1 The sidewalls of gate structures 20 and 22 directly contact and align with the sidewalls of drain region 28, but are not limited to this; the sidewalls of gate structures 20 and 22 can also be as follows: Figure 2 The cross-sectional structure is generally not cut flush with the sidewalls of the drain region 28, and these variations are all within the scope of this invention.

[0040] Please continue to refer to Figure 3 , Figure 3 This is a top view of a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present invention. Figure 3As shown, the laterally diffused metal-oxide-semiconductor device mainly includes gate structures 20 and 22 extending along a first direction, such as the Y direction, on the substrate 12. A source region 24 extends along the Y direction on one side of the gate structure 20 (as shown on the left), a source region 26 extends along the Y direction on one side of the gate structure 22 (as shown on the right), and a drain region 28 extends along the Y direction between the gate structures 20 and 22. A guard region 34 connects the source regions 24 and 26 on one side of the gate structures 20 and 22, and the guard region 36 connects the source regions 24 and 26 on the other side of the gate structures 20 and 22. As in the aforementioned embodiment, although the sidewalls of the gate structures 20 and 22 in the figure directly contact and are flush with the sidewall of the drain region 28, this is not limited to this; the sidewalls of the gate structures 20 and 22 can also be as shown... Figure 2 The cross-sectional structure is generally not cut flush with the sidewalls of the drain region 28, and these variations are all within the scope of this invention.

[0041] In this embodiment, the protection region 34 disposed on one side or below the gate structures 20 and 22 preferably presents an approximately U-shape connecting the source region 24 and the source region 26 from an upward viewing angle, while the protection region 36 disposed on the other side or above the gate structures 20 and 22 presents an approximately inverted U-shape connecting the source region 24 and the source region 26 from an upward viewing angle. Each protection region 34 and 36 directly contacts the source region 24 and the source region 26, and the edges of each protection region 34 and 36 are flush with the edges of the source region 24 and the source region 26. As in the aforementioned embodiment, the source region 24, the source region 26, and the drain region 28 preferably each include an N+ region, while the protection region 34 and the protection region 36 each include a P+ region.

[0042] Please continue to refer to Figure 4 , Figure 4 This is a top view of a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present invention. Figure 4 As shown, the laterally diffused metal-oxide-semiconductor device mainly includes gate structure 20 and gate structure 22 extending along a first direction, such as the Y direction, on the substrate 12. Source region 24 extends along the Y direction on one side of gate structure 20 (left side), source region 26 extends along the Y direction on one side of gate structure 22 (right side), drain region 28 extends along the Y direction between gate structure 20 and gate structure 22, guard ring 30 surrounds gate structure 20 and gate structure 22, and multiple guard regions 38 connect source regions 24 and 26 to guard ring 30, and shallow trench isolation 18 surrounds guard ring 30. As in the aforementioned embodiment, although the sidewalls of gate structures 20 and 22 in the figure directly contact and are flush with the sidewalls of drain region 28, this is not limited to this; the sidewalls of gate structures 20 and 22 can also be as shown... Figure 2 The cross-sectional structure is generally not cut flush with the sidewalls of the drain region 28, and these variations are all within the scope of this invention.

[0043] as Figure 1 In this embodiment, the guard ring 30 is preferably disposed around the source regions 24 and 26, surrounding the source regions 24 and 26, the drain region 28, and the gate structures 20 and 22. The guard ring 30 preferably directly contacts the source regions 24 and 26 on both sides of the gate structures 20 and 22 but does not contact the drain region 28. Multiple guard regions 38 are preferably disposed at the four corners of the guard ring 30 and respectively contact the guard ring 30 and the source regions 24 and 26. In other words, this embodiment is approximately... Figure 1 and Figure 3 The variation formed by combining the guard ring and the guard region. It should be noted that although the guard ring 30 and the guard region 38 are separated by a dotted line, they are actually an integral structure because they are both manufactured in the same process. As in the aforementioned embodiment, source region 24, source region 26, and drain region 28 each contain an N+ region, while guard ring 30 and guard region 38 each contain a P+ region.

[0044] Please continue to refer to Figure 5 , Figure 5 This is a top view of a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present invention. Figure 5 As shown, the laterally diffused metal oxide semiconductor device mainly includes three sets of laterally diffused metal oxide semiconductor elements 42, 44, 46 or three sets of laterally diffused metal oxide semiconductor units disposed on the substrate 12. The three sets of laterally diffused metal oxide semiconductor elements 42, 44, 46 are arranged adjacent to each other, and each set of laterally diffused metal oxide semiconductor elements 42, 44, 46 preferably includes various elements of the laterally diffused metal oxide semiconductor element in the aforementioned embodiment.

[0045] For example, each laterally diffused metal-oxide-semiconductor (MOD) element 42, 44, 46 includes a gate structure 20 and a gate structure 22 extending along a first direction, such as the Y direction, on the substrate 12; a source region 24 extending along the Y direction on one side of the gate structure 20 (as shown on the left); a source region 26 extending along the Y direction on one side of the gate structure 22 (as shown on the right); and a drain region 28 extending along the Y direction between the gate structure 20 and the gate structure 22. It should be noted that the source region located between two adjacent MOD elements 42, 44, 46 is preferably a common source region for both MOD elements 42, 44, 46. For example, the source region 24 or 26 between MOD elements 42 and 44, and the source region 24 or 26 between MOD elements 44 and 46, are each a common source region.

[0046] Furthermore, the laterally diffused metal-oxide-semiconductor device of this embodiment also includes a guard ring 30 that surrounds three sets of laterally diffused metal-oxide-semiconductor devices 42, 44, 46, multiple guard regions 48 connecting the source regions 24, 26 and the guard ring 30, and a shallow trench isolation 18 surrounding the guard ring 30. Preferably, the guard ring 30 directly contacts the source regions 24, 26 on both sides of the entire diffused metal-oxide-semiconductor device 42, 46 but does not contact the drain region 28.

[0047] More specifically, the guard ring 30 preferably contacts the source region 24 on the left side of the laterally diffused metal-oxide-semiconductor element 42 and the source region 26 on the right side of the laterally diffused metal-oxide-semiconductor element 46, but does not contact the drain region 28. The guard region 48 further comprises eight guard regions, four of which are preferably located at the four corners of the guard ring 30 and contact the guard ring 30 and the source regions 24 and 26 respectively. The remaining four guard regions 48 are connected to the guard ring 30 and the source regions 24 and 26 on both sides of the intermediate diffused metal-oxide-semiconductor element 44 respectively. As in the aforementioned embodiment, although the guard ring 30 and the guard region 48 are separated by a dotted line, they are actually an integral structure because they are both fabricated in the same process.

[0048] In summary, the present invention is mainly based on the foregoing Figure 1 , Figure 3 as well as Figure 4 The invention discloses at least three layout patterns for laterally diffused metal-oxide-semiconductor (LMDS) devices, which mainly reduce the overall area of ​​each LMDS device, particularly a P-type cell, by setting guard rings and / or guard regions around the gate structure, source region, and drain region. According to a preferred embodiment of the invention, placing the aforementioned guard rings and / or guard regions around and adjacent to or in contact with the source region not only reduces the cell area of ​​existing LMDS devices but also provides better on-state breakdown voltage and compatibility.

[0049] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A laterally diffused metal-oxide-semiconductor device, characterized in that, Include: The first gate structure and the second gate structure extend on the substrate along the first direction; A first source region extends along the first direction on one side of the first gate structure and has a first end and a second end that are far apart from each other in the first direction; The second source region extends along the first direction to one side of the second gate structure; The drain region extends along the first direction between the first gate structure and the second gate structure; A protective ring surrounds the first gate structure and the second gate structure and contacts the first source region, wherein the protective ring and the first end and the second end of the first source region are spaced apart from each other in the first direction; as well as Shallow trench isolation, surrounding the protective ring, In the cross-sectional structure of the laterally diffused metal-oxide-semiconductor device, the first source region is located within the first well region, the second source region is located within the second well region, the drain region is located within the third well region, and the third well region is in direct contact with the first well region and the second well region.

2. The laterally diffused metal-oxide-semiconductor device of claim 1, wherein the first source region comprises an N+ region.

3. The laterally diffused metal-oxide-semiconductor device of claim 1, wherein the second source region comprises an N+ region.

4. The laterally diffused metal-oxide-semiconductor device of claim 1, wherein the drain region comprises an N+ region.

5. The laterally diffused metal-oxide-semiconductor device of claim 1, wherein the guard ring comprises a P+ region.

6. The laterally diffused metal-oxide-semiconductor device of claim 1, wherein the second source region has a third end and a fourth end that are spaced apart from each other in the first direction, the guard ring contacts the second source region, and the guard ring is spaced apart from the third end and the fourth end of the second source region in the first direction.

7. A laterally diffused metal-oxide-semiconductor device, characterized in that, Include: The first gate structure and the second gate structure extend on the substrate along the first direction; The first source region extends along the first direction to one side of the first gate structure; The second source region extends along the first direction to one side of the second gate structure; The drain region extends along the first direction between the first gate structure and the second gate structure; A first protection region connects the first source region and the second source region to one side of the first gate structure and the second gate structure; as well as The second protection region connects the first source region and the second source region to the other side of the first gate structure and the second gate structure.

8. The laterally diffused metal-oxide-semiconductor device of claim 7, wherein the first source region comprises an N+ region.

9. The laterally diffused metal-oxide-semiconductor device of claim 7, wherein the second source region comprises an N+ region.

10. The laterally diffused metal-oxide-semiconductor device of claim 7, wherein the drain region comprises an N+ region.

11. The laterally diffused metal-oxide-semiconductor device of claim 7, wherein the first protection region comprises a P+ region.

12. The laterally diffused metal-oxide-semiconductor device of claim 7, wherein the first protection region comprises a U-shape.

13. The laterally diffused metal-oxide-semiconductor device of claim 7, wherein the second protection region comprises an inverted U-shape.

14. A laterally diffused metal-oxide-semiconductor device, characterized in that, Include: The first gate structure and the second gate structure extend on the substrate along the first direction; The first source region extends along the first direction to one side of the first gate structure; The second source region extends along the first direction to one side of the second gate structure; The drain region extends along the first direction between the first gate structure and the second gate structure; A protective ring surrounds the first gate structure and the second gate structure; Multiple protection regions connect the first source region, the second source region, and the protection ring; as well as Shallow trenches were used to isolate the area, surrounding the protective ring.

15. The laterally diffused metal-oxide-semiconductor device of claim 14, wherein the first source region comprises an N+ region.

16. The laterally diffused metal-oxide-semiconductor device of claim 14, wherein the second source region comprises an N+ region.

17. The laterally diffused metal-oxide-semiconductor device of claim 14, wherein the drain region comprises an N+ region.

18. The laterally diffused metal-oxide-semiconductor device of claim 14, wherein the guard ring comprises a P+ region.

19. The laterally diffused metal-oxide-semiconductor device of claim 14, wherein the plurality of protective regions contact the first source region.

20. The laterally diffused metal-oxide-semiconductor device of claim 14, wherein the plurality of protection regions are located at the corners of the protection ring.

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