Dynamic random access memory and method of manufacturing the same

Abstract

This invention provides a dynamic random access memory (DRAM) and a method for manufacturing the same. The DRAM includes multiple bit line contact structures, multiple bit line structures, multiple first insulating structures, a capacitor contact structure, a first connecting pad, a second insulating structure, and a capacitor structure. The bit line structures extend along a first direction. The first insulating structures extend along a second direction intersecting the first direction. The capacitor contact structures are located between two bit line structures and two pairs of first insulating structures. The first connecting pad is formed on the capacitor contact structure. The second insulating structure surrounds the first connecting pad, and the top width of the second insulating structure is greater than its bottom width. The capacitor structure is formed on the first connecting pad and is electrically connected to the first connecting pad.

Description

Technical Field

[0001] This invention relates to a memory device, and more particularly to a dynamic random access memory and a method of manufacturing the same. Background Technology

[0002] As electronic products become increasingly miniaturized, there is also a growing demand for smaller memory devices. However, with the miniaturization of memory devices, improving their performance and yield has become more challenging.

[0003] For example, in dynamic random access memory (DRAM), the bit line structure has sidewall spacers formed of nitride / oxide / nitride. During wet etching, because oxides are less resistant to wet etching than nitrides, the tops of the oxides in the sidewall spacers are often damaged, leading to thinning or even complete removal of the sidewall spacers (i.e., the top surface of the sidewall spacers is lower than the top surface of the capping layer above the conductive structure). If the tops of the sidewall spacers in the bit line structure are completely removed, the top of the capping layer in the bit line structure is exposed, potentially causing the capping layer to deform (e.g., giving it a rounded top surface). This results in the tops of the interconnect pads on both sides of the bit line structure becoming wider than expected. In other words, the distance between the tops of adjacent interconnect pads becomes closer. This increases the risk of short circuits in the memory device, thus reducing product performance and yield. As memory devices become smaller, the distance between adjacent interconnect pads decreases, making the aforementioned short circuit problem even more severe. Summary of the Invention

[0004] This invention provides a dynamic random access memory and its manufacturing method, which can reduce the risk of short circuits and facilitate miniaturization.

[0005] An embodiment of the present invention discloses a dynamic random access memory (DRAM), comprising: a plurality of bit line contact structures formed on a substrate; a plurality of bit line structures formed on the plurality of bit line contact structures and extending along a first direction; a plurality of first insulating structures formed on the substrate and extending along a second direction intersecting the first direction; a capacitor contact structure located between adjacent plurality of bit line structures and adjacent plurality of first insulating structures; a first connection pad formed on the capacitor contact structure; a second insulating structure surrounding the first connection pad, wherein the top width of the second insulating structure is greater than the bottom width; and a capacitor structure formed on the first connection pad and electrically connected to the first connection pad.

[0006] An embodiment of the present invention discloses a method for manufacturing a dynamic random access memory (DRAM), comprising: forming a plurality of bit line contact structures on a substrate; forming a plurality of bit line structures on the plurality of bit line contact structures, wherein each bit line structure extends along a first direction; forming a plurality of first insulating structures on the substrate, wherein each first insulating structure extends along a second direction intersecting the first direction; forming a capacitor contact structure between adjacent bits and adjacent first insulating structures; forming a first connection pad on the capacitor contact structure; forming a second insulating structure surrounding the first connection pad, wherein the top width of the second insulating structure is greater than the bottom width; and forming a capacitor structure on the first connection pad and electrically connected to the first connection pad.

[0007] In the dynamic random access memory and its manufacturing method provided in this embodiment of the invention, the risk of short circuits can be reduced by forming a second insulating structure surrounding the first connection pad. Furthermore, by making the top width of the second insulating structure greater than the bottom width, a suitable contact impedance can be achieved between the first connection pad and the capacitor structure, and the parasitic capacitance between the bit line structure and the first connection pad can be reduced. Thus, performance and yield can be improved. Attached Figure Description

[0008] Figure 1 This is a top view schematic diagram of DRAM according to some embodiments of the present invention.

[0009] Figures 2A to 2G A DRAM according to an embodiment of the present invention follows the process at various stages as follows: Figure 1 A schematic diagram of the cross section drawn by section line AA'.

[0010] Figure 3 For some embodiments of the present invention, DRAM follows the path shown below. Figure 1 A schematic diagram of the cross section drawn using the section line BB' shown.

[0011] Figure 4 This is a cross-sectional schematic diagram of DRAM according to other embodiments of the present invention.

[0012] Figure 5 This is a cross-sectional schematic diagram of DRAM according to other embodiments of the present invention.

[0013] Figure 6 This is a cross-sectional schematic diagram of DRAM according to other embodiments of the present invention.

[0014] Symbol explanation:

[0015] 100: DRAM

[0016] 102:Substrate

[0017] 104: Bit line contact structure

[0018] 105: Contact Area

[0019] 106: Insulation Pattern

[0020] 108: Conductive Structure

[0021] 110: Insulating cover layer

[0022] 112: Spacer layer

[0023] 112a: First spacer layer

[0024] 112b: Second spacer layer

[0025] 112c: Third spacer layer

[0026] 114: First contact component

[0027] 115: Notch

[0028] 116: Buffer layer

[0029] 118: Second contact component

[0030] 118a: Conductive liner

[0031] 118b: Conductive layer

[0032] 119: Capacitor contact structure

[0033] 120: First material layer

[0034] 120a: Overhanging section

[0035] 120b: Gradual narrowing section

[0036] 120b': Remaining first material layer

[0037] 120c: Horizontal section

[0038] 122: First connecting pad

[0039] 122a: Upper part

[0040] 122b: Lower part

[0041] 124: Second insulating material

[0042] 126: Air gap

[0043] 128: Interlayer dielectric layer

[0044] 130: Capacitor Structure

[0045] 132: First insulation structure

[0046] 140: Second insulation structure

[0047] 200:DRAM

[0048] 240: Second insulation structure

[0049] 300: DRAM

[0050] 340: Second insulation structure

[0051] 400: DRAM

[0052] 440: Second insulation structure

[0053] H1: First Height

[0054] H2: Minimum thickness

[0055] H3: Third Height

[0056] H4: Fourth Height

[0057] W1: First width

[0058] W2: Maximum distance

[0059] W3: Third width

[0060] W4: Width

[0061] W5: Width

[0062] W6: Sixth Width

[0063] W7: Thickness Detailed Implementation

[0064] To make the above and other objects, features, and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Furthermore, repeated reference numerals and / or words may be used in different embodiments of the present invention. These repeated numerals or words are for simplification and clarity purposes and are not intended to limit the relationship between the various embodiments and / or the described appearance structures. Here, the terms "about" or "approximately" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%. The quantities given here are approximate quantities, meaning that the meaning of "about" or "approximately" may be implied unless otherwise specified.

[0065] This invention provides a dynamic random access memory (DRAM) and its manufacturing method. For the sake of simplicity, Figure 1 Only the contact structure 104, insulation pattern 106, insulation cover layer 110, insulation spacer 112, first connecting pad 122, first insulation structure 132, and second insulation structure 140 are shown. Please also refer to... Figure 1 and Figure 2AAn insulating pattern 106 and a bit line contact structure 104 are formed alternately on a substrate 102. The bit line contact structure 104 is configured to electrically connect the substrate 102 to a subsequently formed bit line structure.

[0066] The substrate 102 may be made of silicon, silicon-containing semiconductors, silicon-on-insulator (SOI), other suitable materials, or combinations thereof. In this embodiment, the substrate 102 is a silicon substrate. In some embodiments, shallow trench isolation structures and buried word lines may be formed in the substrate 102. In some embodiments, other structures may also be formed in the substrate 102. For example, p-type well regions, n-type well regions, or conductive regions may be formed in the substrate 102 by a placement process. For the sake of simplicity, the shallow trench isolation structures, buried word lines, and other structures described above are not illustrated in the figures, and the structures in the substrate 102 and their formation methods will not be described in detail here.

[0067] The material of the insulating pattern 106 may include oxides, nitrides, oxynitrides, carbides, other suitable insulating materials, or combinations thereof. In this embodiment, the insulating pattern 106 is silicon nitride. In other embodiments, the insulating pattern 106 is a bilayer structure formed of silicon oxide and silicon nitride formed on the silicon oxide. The material of the bit line contact structure 104 may include doped polysilicon, other suitable conductive materials, or combinations thereof. In order to adjust the work function and resistance value within a suitable range, the material of the bit line contact structure 104 may be different from the material of the conductive structure 108 of the subsequently formed bit line structure. For example, the material of the bit line contact structure 104 may be doped polysilicon.

[0068] Next, a conductive structure 108 is formed on the insulating pattern 106 and the bit line contact structure 104, and an insulating capping layer 110 is formed on the conductive structure 108. The plurality of insulating capping layers 110 are formed on the substrate 102 in parallel with each other, and each insulating capping layer 110 extends along the first direction D1.

[0069] In some embodiments, the conductive structure 108 may be formed of a single material. In such embodiments, the material of the conductive structure 108 may include tungsten, aluminum, copper, gold, silver, the alloys described above, or other suitable metallic materials. In other embodiments, the conductive structure 108 includes a first conductive layer and a second conductive layer formed on the first conductive layer. In such embodiments, the material of the first conductive layer may include titanium, titanium nitride, tungsten nitride, tantalum, tantalum nitride, other suitable conductive materials, or combinations thereof. The material of the second conductive layer may include tungsten, aluminum, copper, gold, silver, the alloys described above, other suitable metallic materials, or combinations thereof. In this embodiment, the conductive structure 108 is formed of tungsten. The material of the insulating capping layer 110 may include oxides, nitrides, oxynitrides, other suitable insulating materials, or combinations thereof. In this embodiment, the insulating capping layer 110 is silicon nitride. The conductive structure 108 and the insulating capping layer 110 may each be formed independently by a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, other suitable deposition processes, or combinations thereof.

[0070] Next, insulating spacers 112 are compliantly formed on the sidewalls of the bit line contact structure 104, the insulating pattern 106, the conductive structure 108, and the insulating capping layer 110. In this specification, the conductive structure 108, the insulating capping layer 110, and the insulating spacers 112 are collectively referred to as bit line structures. In some embodiments, a first spacer layer 112a, a second spacer layer 112b, and a third spacer layer 112c may be formed sequentially to form the insulating spacers 112. The first spacer layer 112a, the second spacer layer 112b, and the third spacer layer 112c may each be formed independently by a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or a combination thereof, and the insulating spacers 112 may be formed using any known etching process after the deposition process to expose the top surfaces of the substrate 102 and the insulating capping layer 110. The first spacer layer 112a, the second spacer layer 112b, and the third spacer layer 112c may each independently comprise oxides, nitrides, oxynitrides, carbides, other suitable insulating materials, or combinations thereof.

[0071] In this embodiment, the first spacer layer 112a and the third spacer layer 112c are nitrides, and the second spacer layer 112b is an oxide. During the fabrication of the insulating spacer 112 in this embodiment, because the removal rate of the second spacer layer 112b is high and the thickness of the third spacer layer 112c is thin, the top surfaces of the second spacer layer 112b and the third spacer layer 112c are lower than the top surface of the first spacer layer 112a. In other embodiments, the top surface of the insulating spacer 112 is lower than the top surface of the insulating capping layer 110, that is, the insulating spacer 112 exposes the top sidewall of the insulating capping layer 110, and the insulating capping layer 110 has a rounded top surface.

[0072] Please refer to the following at the same time Figure 1 , Figure 2A and Figure 3 After the insulating spacer 112 is formed, a plurality of first insulating structures 132 are formed on the substrate 102. These first insulating structures 132 are formed parallel to each other on the substrate 102, and each first insulating structure 132 extends along a second direction D2 intersecting the first direction D1. Herein, a contact area 105 is defined between two adjacent insulating cap layers 110 and two adjacent first insulating structures 132. Specifically, a contact area 105 is defined between two insulating spacers 112 disposed on different insulating cap layers 110 and two adjacent first insulating structures 132. Furthermore, the contact area 105 is a recessed area compared to the insulating cap layers 110 and the first insulating structures 132.

[0073] Next, a capacitor contact structure 119 electrically connected to the substrate 102 is formed in the contact area 105, and the top surface of the capacitor contact structure 119 is lower than the top surface of the insulating capping layer 110. In this embodiment, the capacitor contact structure 119 includes a first contact member 114, a buffer layer 116, and a second contact member 118 sequentially formed on the substrate 102. The step of forming the first contact member 114 includes, for example, forming a conductive material on the substrate 102 and etching back a portion of the conductive material to form the first contact member 114 in the contact area 105. The material of the first contact member 114 may be the same as or similar to the material of the bit line contact structure 104. In this embodiment, in order to adjust the work function and resistance value within a suitable range, the material of the first contact member 114 is doped polysilicon.

[0074] The top surface of the second contact member 118 is lower than the top surface of the insulating capping layer 110. In this embodiment, the second contact member 118 includes a conductive liner 118a and a conductive layer 118b. The steps of forming the second contact member 118 may include compliantly forming a conductive liner material covering the buffer layer 116 in the contact area 105. Next, a conductive material is formed on the conductive liner material. Subsequently, the conductive liner material and the conductive layer material are partially removed by an etch-back process. The material of the buffer layer 116 is, for example, a metal silicide. The conductive liner material may include titanium, titanium nitride, tungsten nitride, tantalum, tantalum nitride, or a combination thereof. The conductive layer material may include tungsten, aluminum, copper, gold, silver, the alloys mentioned above, other suitable metallic materials, or a combination thereof. Through the capacitive contact structure 119, the substrate 102 can be electrically connected to the subsequently formed capacitor structure 130 (shown in the figure). Figure 2G middle).

[0075] Please refer to Figure 2BA first material layer 120 of uneven thickness is formed on the insulating cap layer 110, the insulating spacer 112, and the capacitor contact structure 119. A protruding portion 120a of the first material layer 120 is formed on the top of the insulating cap layer 110. A tapered portion 120b of the first material layer 120 is formed on the sidewall of the insulating spacer 112. A horizontal portion 120c of the first material layer 120 is formed on the top surface of the capacitor contact structure 119. The maximum thickness of the protruding portion 120a is greater than the maximum thickness of the tapered portion 120b. This embodiment, by using a first material layer 120 with the protruding portion 120a, can help improve yield, which will be discussed in detail below.

[0076] In one embodiment, to efficiently form the first material layer 120 having the overhanging portion 120a, the first material layer 120 can be formed using a method with poor step coverage, such as plasma-enhanced chemical vapor deposition. In one embodiment, the first material layer 120 is not completely removed in subsequent processes, and the remaining first material layer 120 becomes part of the subsequently formed second insulating structure. The first material layer 120 may include a first insulating material, such as an oxide, nitride, oxynitride, other suitable insulating materials, or combinations thereof. In this embodiment, the first material layer 120 includes an oxide.

[0077] Please refer to Figure 2C A first etching process is performed to partially remove the first material layer 120 and expose the top surface of the capacitor contact structure 119. More specifically, after the first etching process, the horizontal portion 120c of the first material layer 120 is completely removed, exposing the top surface of the second contact member 118. The first etching process may be an isotropic etching process, such as a wet etching process.

[0078] Please refer to Figure 2D A first connecting pad 122 is formed on the capacitor contact structure 119, and the top surface of the first connecting pad 122 is coplanar with the top surface of the insulating capping layer 110. The step of forming the first connecting pad 122 may include depositing a conductive material on the first material layer 120 and the capacitor contact structure 119 to fill the contact area 105. Subsequently, a planarization process is performed to make the top surfaces of the first material layer 120, the insulating capping layer 110, and the first connecting pad 122 coplanar. The conductive material may include tungsten, aluminum, copper, gold, silver, alloys of the above, other suitable metallic materials, or combinations thereof. In this embodiment, the conductive material is tungsten.

[0079] Please refer to Figure 2EA second etching process is performed to remove the first material layer 120 and form a notch 115 exposing the insulating spacer 112. In this embodiment, the second etching process removes the overhanging portion 120a of the first material layer 120, and the notch 115 further exposes the tapered portion 120b of the first material layer 120.

[0080] Please refer to Figure 2F The recess 115 is filled with a second insulating material 124, and the top surface of the second insulating material 124, the top surface of the insulating capping layer 110, and the top surface of the first connecting pad 122 are coplanar. To protect the first material layer 120 from subsequent etching processes, the second insulating material 124 may be different from the material of the first material layer 120. The second insulating material 124 may include oxides, nitrides, or oxynitrides. In this embodiment, the second insulating material 124 is a nitride. The second insulating material 124 can be formed by a suitable deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, and combinations thereof.

[0081] Please refer to the following at the same time Figure 1 and Figure 2F In this embodiment, the narrowing portion 120b of the first material layer 120 and the second insulating material 124 form a second insulating structure 140 surrounding the first connecting pad 122. This second insulating structure 140 is formed between the first connecting pad 122 and the insulating capping layer 110. The top width of the second insulating structure is greater than the bottom width. The second insulating structure 140 in this embodiment can help improve yield, which will be discussed in detail below.

[0082] Please refer to Figure 2G After the second insulating structure 140 is formed, an interlayer dielectric layer 128 is formed on the substrate 102. Next, a third etching process is performed on the interlayer dielectric layer 128 to form a plurality of openings exposing the first connection pad 122. Then, a capacitor structure 130 is formed in these openings of the interlayer dielectric layer 128. The capacitor structure 130 can be electrically connected to the capacitor contact structure 119 through the first connection pad 122.

[0083] In this embodiment, the material of the interlayer dielectric layer 128 is different from the material of the second insulating material 124, so that during the third etching process, the removal rate of the interlayer dielectric layer 128 is much greater than the removal rate of the second insulating material 124. This prevents conductive material in the capacitor structure 130 from forming at the location originally intended to be filled into the second insulating structure 140, thereby preventing short circuits. Furthermore, during the third etching process, the second insulating material 124 prevents the etching solution from entering the substrate 102 through the tapered portion 120b and the second spacer layer 112b. This further improves the yield of the DRAM 100. In some embodiments, during the third etching process, the ratio R1 / R2 of the removal rate R1 of the interlayer dielectric layer 128 to the removal rate R2 of the second insulating material 124 is 1.5-20. The material of the interlayer dielectric layer 128 may include oxides, nitrides, oxynitrides, or combinations thereof. In this embodiment, the interlayer dielectric layer 128 is an oxide.

[0084] The configuration range of capacitor structure 130 may not completely overlap with the configuration range of the first connection pad 122. In this embodiment, one capacitor structure 130 is disposed on the first connection pad 122, the second insulating structure 140, and the insulating capping layer 110. The capacitor structure 130 can be formed using existing methods, which will not be detailed here. After forming the capacitor structure 130, other existing processes can be performed to complete the DRAM 100. For simplicity, these other existing processes will not be detailed here.

[0085] Please refer to the following at the same time Figure 1 , Figure 2G and Figure 3 In some embodiments of the present invention, the DRAM 100 includes a substrate 102, a bit line contact structure 104, a bit line structure, a first insulating structure 132, a capacitor contact structure 119, a first connection pad 122, a second insulating structure 140, and a capacitor structure 130. The bit line structure includes a conductive structure 108, an insulating capping layer 110, and an insulating spacer 112.

[0086] Bit line contact structure 104, conductive structure 108, and insulating capping layer 110 are sequentially formed on substrate 102. The bit line structure extends along a first direction D1. A first insulating structure 132 extends along a second direction D2 intersecting the first direction D1. A capacitor contact structure 119, a first connecting pad 122, and a second insulating structure 140 are located between two adjacent bit line structures and two adjacent first insulating structures 132. Insulating spacers 112 are formed on the sidewalls of each of the bit line contact structure 104, conductive structure 108, and insulating capping layer 110. A first connecting pad 122 is formed on the capacitor contact structure 119. Each second insulating structure 140 surrounds a first connecting pad 122. The top surface of the second insulating structure 140 is flush with the top surface of the first connecting pad 122, and the second insulating structure 140 has a width that gradually narrows downwards. A capacitor structure 130 is formed on the first connecting pad 122 and electrically connected to the first connecting pad 122. For further details regarding DRAM100, please refer to the foregoing description of the manufacturing method; therefore, they will not be repeated here.

[0087] In the DRAM 100 provided in this embodiment, by making the top of the first connection pad 122 narrower and configuring a second insulating structure 140 around the first connection pad 122, the risk of short circuits can be reduced, and the parasitic capacitance between the conductive structure 108 and the first connection pad 122 can also be reduced. Therefore, the write speed can be improved, and performance and yield can be enhanced.

[0088] In some embodiments, the second insulating structure 140 includes a first portion and a second portion. The first portion extends upward from the top surface of the capacitive contact structure 119 and gradually widens. The second portion extends downward from the top surface of the first connecting pad 122 and gradually narrows. Figure 2F In the illustrated embodiment, the first portion of the second insulating structure 140 includes a first material layer 120, and the second portion of the second insulating structure 140 includes a second insulating material 124.

[0089] like Figure 2FAs shown, the top surface of the second insulating structure 140 has a first width W1. The surface of the first portion of the second insulating structure 140 has a maximum distance W2 with the surface of the third spacer layer 112c. The top surface of the insulating cover layer 110 has a sixth width W6. In this embodiment, the distance between the top portions of two adjacent first connecting pads 122 is the sixth width W6 plus twice the first width W1 plus twice the thickness W7 of the first spacer layer 112a (i.e., W6 + 2 * W1 + 2 * W7). In some embodiments, the ratio W1 / W2 of the first width W1 to the maximum distance W2 is 1.5-10.0. This allows for an appropriate distance between the top portions of two adjacent first connecting pads 122, providing suitable contact resistance between the first connecting pads 122 and the capacitor structure 130, and reducing the parasitic capacitance between the conductive structure 108 and the first connecting pads 122, thereby improving yield and performance.

[0090] Furthermore, in some other embodiments, a second connecting pad (not shown) electrically connected to the first connecting pad 122 may be formed on the first connecting pad 122 before the capacitor structure 130 is formed. In such embodiments, the second connecting pad and the first connecting pad 122 may be staggered. By forming the second portion of the second insulating structure 140 described in this embodiment, it is possible to effectively prevent one second connecting pad from being electrically connected to two adjacent first connecting pads 122 simultaneously, thereby reducing the risk of short circuits and improving performance and yield.

[0091] In this embodiment, the first connection pad 122 includes an upper portion 122a and a lower portion 122b. Since the first connection pad 122 is in contact with and surrounded by the second insulating structure 140, the upper portion 122a of the first connection pad 122 has a width that gradually narrows upwards, and the lower portion 122b of the first connection pad 122 also has a width that gradually narrows upwards. Furthermore, the width of the bottom surface of the first connection pad 122 can be less than or equal to the width of the top surface of the capacitor contact structure 119. The width W5 of the bottom surface of the first connection pad 122 can be greater than the width W4 of the top surface of the first connection pad 122. Through the first connection pad 122 of this embodiment, excessive contact resistance between the first connection pad 122 and the capacitor contact structure 119 can be avoided, and the risk of short circuits between two adjacent first connection pads 122 can be reduced. This further improves the performance and yield of the DRAM 100.

[0092] like Figure 2FAs shown, the first connecting pad 122 has a third width W3 at the junction of the upper portion 122a and the lower portion 122b. The top surface of the first connecting pad 122 has a width W4. In some embodiments, the ratio W3 / W4 of the third width W3 to the width W4 is 1.1-2.5. This allows the first connecting pad 122 to have a suitable resistance value, ensuring an appropriate distance between the top portions of two adjacent first connecting pads 122 and preventing gaps from forming in the first connecting pad 122, thereby more effectively improving yield and performance.

[0093] Please refer to Figure 2A and Figure 2B In this embodiment, the conductive liner 118a can improve the adhesion between the conductive layer 118b and the third spacer layer 112c. Furthermore, by forming the second insulating structure 140 on the second contact member 118, peeling or delamination of the conductive layer 118b can also be avoided.

[0094] Furthermore, in this embodiment, the adhesive force between the first connecting pad 122 and the second contact member 118 is greater than the adhesive force between the first connecting pad 122 and the second insulating structure 140, and the width of the bottom surface of the first connecting pad 122 is less than or equal to the width of the top surface of the second contact member 118. This effectively prevents peeling or delamination of the first connecting pad 122, thereby further improving the yield of the DRAM 100.

[0095] like Figure 2F As shown, the second insulating structure 140 has a first height H1. The combined height of the first connecting pad 122 and the second contact member 118 is a third height H3. To facilitate the formation of the overhanging portion 120a of the first material layer 120 and to avoid peeling or delamination of the conductive layer 118b, in some embodiments, after the back etching process, the top surface of the second contact member 118 may be flush with or lower than the top surface of the second spacer layer 112b or the third spacer layer 112c. Furthermore, in some embodiments, the ratio H3 / H1 of the third height H3 to the first height H1 is 1.5-5, thereby improving yield.

[0096] In this embodiment, the first portion of the second insulating structure 140 (i.e., the narrowing portion 120b of the first material layer 120) includes oxide to reduce the parasitic capacitance between the conductive structure 108 and the first connecting pad 122. Furthermore, the width of the first portion of the second insulating structure 140 may be smaller than the width of the second portion to reduce the resistance value of the first connecting pad 122. This further improves performance.

[0097] like Figure 2FAs shown, the second portion of the second insulating structure 140 has a minimum thickness H2. In order to effectively prevent the etching solution of the third etching process from damaging the components (e.g., the second spacer layer 112b and the substrate 102) under the second portion of the second insulating structure 140, reduce the parasitic capacitance between the conductive structure 108 and the first connection pad 122, and facilitate miniaturization, in some embodiments, the ratio H1 / H2 of the first height H1 to the minimum thickness H2 is 1.5-10.0.

[0098] Figure 4 The DRAM200 shown is Figure 2F The DRAM100 shown is similar, therefore the same reference numerals are used to represent the same components, the difference being... Figure 4 The first part of the second insulating structure 240 is formed by the air gap 126. For simplicity, regarding the same as... Figure 2F The components and their manufacturing processes shown in the diagram will not be described in detail here.

[0099] The second insulating structure 240 can be formed through the following process steps. In the second etching process, the first material layer 120 is completely removed, forming an opening that exposes the sidewalls of the first connecting pad 122. The upper portion of this opening is a notch 115 exposing the top of the insulating spacer 112, and the lower portion is used to form an air gap 126. Then, a second insulating material 124 is formed in the notch 115. In this embodiment, the first material layer 120 is completely removed as a sacrificial layer.

[0100] In this embodiment, a method with poor step coverage (e.g., plasma-enhanced chemical vapor deposition) can be selected to deposit the second insulating material 124, thereby forming the second insulating material 124 in the notch 115 and forming an air gap 126 under the second insulating material 124.

[0101] In this embodiment, the first portion of the second insulating structure 240 includes an air gap 126, and the second portion of the second insulating structure 240 includes a second insulating material 124. Compared to the case where the first portion of the insulating structure is formed with an oxide, using an air gap 126 as the first portion can further reduce the parasitic capacitance between the conductive structure 108 and the first connecting pad 122. In this way, performance can be further improved.

[0102] like Figure 4 As shown, the second insulating structure 240 has a first height H1. The second contact member 118 has a fourth height H4. In some embodiments, the ratio H1 / H4 of the first height H1 to the fourth height H4 is 0.5-10.0, thereby preventing peeling or delamination of the second contact member 118 and facilitating the formation of the overhanging portion 120a of the first material layer 120, thereby improving yield.

[0103] In this embodiment, the first material layer 120 may include oxides, nitrides, oxynitrides, carbon-based materials (e.g., graphite or other carbides), polysilicon, or combinations thereof. Therefore, the process flexibility is high. Furthermore, in this embodiment, materials that are easier to form the overhanging portions 120a can be selected, or materials with a higher removal rate during the second etching process can be selected to fabricate the first material layer 120, thus helping to shorten manufacturing time and improve yield.

[0104] Figure 5 The illustrated DRAM300 and Figure 2F The DRAM100 shown is similar, therefore the same reference numerals are used to represent the same components, the difference being... Figure 5 The second insulating structure 340 is formed solely of the first material layer 120. For simplicity, regarding the same as... Figure 2F The components and their manufacturing processes shown in the diagram will not be described in detail here.

[0105] In this embodiment, by means of... Figure 2D The steps shown form the second insulating structure 340. Therefore, in forming such a structure... Figure 2D Following the structure shown, the following can be omitted: Figure 2E and Figure 2F The steps described are not directly performed as follows. Figure 2G The described steps simplify the process and reduce production time and cost. In this embodiment, the first material layer 120 is a nitride. The material of the first material layer 120 is different from that of the interlayer dielectric layer, so that during the third etching process, the removal rate of the interlayer dielectric layer is much greater than the removal rate of the second insulating structure 340. This prevents conductive material in the capacitor structure from forming at the locations originally intended to be filled into the second insulating structure 340, thereby preventing short circuits. Furthermore, during the third etching process, the second insulating structure 340 prevents the etching solution from penetrating and entering the substrate 102.

[0106] Figure 6 The DRAM400 shown is Figure 2F The DRAM100 shown is similar, therefore the same reference numerals are used to represent the same components, the difference being... Figure 6 The illustrated second insulating structure 440 includes a first portion, a second portion, and a third portion. The first portion extends upward from the top surface of the capacitor contact structure 119. The second portion extends downward from the top surface of the first connecting pad 122. The third portion is located between the first and second portions. For simplicity, regarding the same... Figure 2F The components and their manufacturing processes shown in the diagram will not be described in detail here.

[0107] The second insulating structure 440 can be formed through the following process steps. It can be formed as follows: Figure 2DFollowing the illustrated structure, a second etching process is performed to partially remove the first material layer 120 and form a recess 115 exposing a portion of the sidewall of the first bonding pad 122. Then, a second insulating material 124 is deposited in the recess 115, but the second insulating material 124 does not completely fill the recess 115. If a method with poor step coverage (e.g., plasma-enhanced chemical vapor deposition) is selected to deposit the second insulating material 124, the second insulating material 124 can be formed in the upper portion of the recess 115, and an air gap 126 can be formed in the lower portion of the recess 115. This forms an air gap 126 between the remaining first material layer 120b' and the second insulating material 124.

[0108] In this embodiment, the first portion of the second insulating structure 440 includes the remaining first material layer 120b'. The second portion of the second insulating structure 440 includes a second insulating material 124. The third portion of the second insulating structure 440 includes an air gap 126. The second insulating material 124 is different from the first material layer 120. The first material layer 120 may include oxides, nitrides, oxynitrides, other suitable insulating materials, or combinations thereof. The second insulating material 124 may include oxides, nitrides, oxynitrides, carbides, or other suitable insulating materials. In this embodiment, the first material layer 120 is an oxide, and the second insulating material 124 is a nitride. In this embodiment, the first portion of the second insulating structure 440 is an oxide, and the third portion is an air gap. Therefore, the parasitic capacitance between the conductive structure 108 and the first connection pad 122 can be reduced, thereby improving the performance of the memory device.

[0109] In summary, in the DRAM manufacturing method provided by the embodiments of the present invention, a first material layer with a protruding portion is formed to cover and enclose the top portion of the insulating capping layer, thereby reducing the risk of short circuits in the memory device and improving yield. Furthermore, the second insulating structure surrounding the first connection pad comprises a low-dielectric-constant material to reduce the parasitic capacitance between the bit line and the first connection pad, and improve the performance of the memory device.

[0110] Although the present invention has been disclosed above with reference to several preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make any modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the foregoing claims.

Claims

1. A dynamic random access memory, characterized in that, include: Multiple bit line contact structures are formed on a substrate; Multiple bit line structures are formed on the bit line contact structure and extend along a first direction; Multiple first insulating structures are formed on the substrate and extend along a second direction intersecting the first direction; A capacitive contact structure is formed on the substrate and located between the adjacent bit line structure and the adjacent first insulating structure; A first connection pad is formed on the capacitor contact structure; A second insulating structure surrounds the first connecting pad, and the top width of the second insulating structure is greater than the bottom width; and A capacitor structure is formed on and electrically connected to the first connecting pad, wherein a top surface of the second insulating structure is flush with a top surface of the first connecting pad and a top surface of the bit line structure.

2. The dynamic random access memory according to claim 1, characterized in that, The second insulation structure includes: A first portion extends upward from a top surface of the capacitor contact structure, wherein the first portion has a width that gradually narrows downward; and A second portion extends downward from the top surface of the first connecting pad, wherein the second portion has a width that gradually narrows downward, wherein the top surface of the second insulating structure has a first width W1, wherein the surface of the first portion of the second insulating structure has a maximum distance W2 between the surface of the sidewall of the bit line structure, and wherein the ratio (W1 / W2) of the first width W1 to the maximum distance W2 is 1.5-10.

0.

3. The dynamic random access memory according to claim 2, characterized in that, The first part includes a first insulating material, and the second part includes a second insulating material, wherein the second insulating material is different from the first insulating material.

4. The dynamic random access memory according to claim 2, characterized in that, The first portion includes an air gap, and the second portion includes an insulating material.

5. The dynamic random access memory according to claim 2, characterized in that, The first part and the second part comprise the same insulating material.

6. The dynamic random access memory according to claim 2, characterized in that, The second insulating structure has a first height H1, the second portion has a minimum thickness H2, and the ratio (H1 / H2) of the first height H1 to the minimum thickness H2 is 1.5-10.

0.

7. The dynamic random access memory according to claim 2, characterized in that, The second insulating structure further includes a third portion located between the first portion and the second portion, the first portion including a first insulating material, the second portion including a second insulating material, the third portion including an air gap, and the second insulating material being different from the first insulating material.

8. The dynamic random access memory according to claim 1, characterized in that, The bitline structure includes: A conductive structure is formed on the bit line contact structure; An insulating capping layer is formed on the conductive structure; An insulating spacer is located between the conductive structure and the capacitor contact structure, and includes: A first spacer layer is formed on one sidewall of the insulating cap layer and one sidewall of the conductive structure; A second spacer layer is formed on the first spacer layer, wherein a top surface of the second spacer layer is lower than a top surface of the first spacer layer; and A third spacer layer is formed on the second spacer layer, wherein a top surface of the third spacer layer is lower than the top surface of the first spacer layer.

9. The dynamic random access memory according to claim 1, characterized in that, The width of a bottom surface of the first connecting pad is greater than the width of a top surface of the first connecting pad, and the ratio of the width of the junction between the lower and upper portions of the first connecting pad to the width of the top surface of the first connecting pad is 1.1-2.

5.

10. A method for manufacturing a dynamic random access memory, characterized in that, include: Multiple bit line contact structures are formed on a substrate; Multiple bit line structures are formed on the bit line contact structure, wherein each bit line structure extends along a first direction; A plurality of first insulating structures are formed on the substrate, wherein each of the first insulating structures extends along a second direction intersecting the first direction; A capacitive contact structure is formed on the substrate, wherein the capacitive contact structure is located between an adjacent bit line structure and an adjacent first insulating structure. A first connection pad is formed on the capacitor contact structure; A second insulating structure is formed around the first connecting pad, wherein the top width of the second insulating structure is greater than the bottom width; as well as A capacitor structure is formed on the first connecting pad and electrically connected to the first connecting pad, wherein a top surface of the second insulating structure is flush with a top surface of the first connecting pad and a top surface of the bit line structure.

11. The method for manufacturing a dynamic random access memory according to claim 10, characterized in that, Forming the second insulating structure and forming the first connecting pad include: A first material layer of non-uniform thickness is formed on the bit line structure and the capacitor contact structure, wherein the first material layer includes a first insulating material; A first etching process is performed to partially remove the first material layer and expose a top surface of the capacitor contact structure; A conductive material is deposited on the first material layer and the capacitor contact structure; A planarization process is performed to make a top surface of the first material layer coplanar with a top surface of the conductive material, wherein the conductive material forms the first connection pad after the planarization process; A second etching process is performed to remove a portion of the first material layer and form a notch adjacent to the first bonding pad; and A second insulating material is formed in the notch, wherein the second insulating material is different from the first insulating material. One top surface of the second insulating structure is flush with one top surface of the first connecting pad.

12. The method for manufacturing a dynamic random access memory according to claim 11, characterized in that, The notch is formed by removing a protruding portion of the first material layer using the first etching process.

13. The method of manufacturing a dynamic random access memory according to claim 11, wherein the second insulating material fills the notch, and the remaining first material layer and the second insulating material form the second insulating structure.

14. The method for manufacturing a dynamic random access memory according to claim 11, characterized in that, The second insulating material does not completely fill the notch, but forms an air gap in the notch and is located between the first material layer and the second insulating material, wherein the remaining first material layer, the second insulating material and the air gap form the second insulating structure.

15. The method for manufacturing a dynamic random access memory according to claim 10, characterized in that, Forming the second insulating structure and forming the first connecting pad include: A first material layer of uneven thickness is formed on the bit line structure and the capacitor contact structure; A first etching process is performed to partially remove the first material layer and expose a top surface of the capacitor contact structure; A conductive material is deposited on the first material layer and the capacitor contact structure; A planarization process is performed to make a top surface of the first material layer coplanar with a top surface of the conductive material; After the planarization process, the conductive material forms the first connection pad, and the first connection pad is in direct contact with the capacitor contact structure. A second etching process is performed to completely remove the first material layer and form an opening exposing the sidewalls of the first bonding pad; and A second insulating structure is formed in the opening, wherein the material of the second insulating structure is different from the material of the first material layer.

16. The method for manufacturing a dynamic random access memory according to claim 15, characterized in that, Forming the second insulating structure in the opening includes forming an insulating material, wherein the insulating material does not completely fill the opening, but forms an air gap in the opening and is located below the insulating material, wherein the insulating material and the air gap form the second insulating structure.

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