Bonding pads for semiconductor die assemblies and associated methods and systems

Abstract

Bonding pads for semiconductor die assemblies and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes a first semiconductor die including a first bonding pad on a first side of the first semiconductor die. The semiconductor die assembly further includes a second semiconductor die including a second bonding pad on a second side of the second semiconductor die. The first bonding pad is aligned with and bonded to the second bonding pad at a bonding interface between the first and second bonding pads, and at least one of the first and second bonding pads includes a first metal and a second metal different from the first metal. Further, the first metal is located at the bonding interface, and the second metal has a first thickness that is at least one fourth of a second thickness corresponding to the first or second bonding pad.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor die assemblies, and more specifically, to bonding pads for semiconductor die assemblies and associated methods and systems. Background Technology

[0002] Semiconductor packages typically comprise semiconductor dies (e.g., memory chips, microprocessor chips, imager chips) mounted on a substrate and housed within a protective cover (e.g., encapsulation material). The semiconductor die may contain functional features, such as memory cells, processor circuitry, or imager devices, and bonding pads electrically connected to these functional features. The bonding pads may be electrically connected to corresponding conductive structures on the substrate, which may couple to terminals outside the protective cover, allowing the semiconductor die to be connected to higher-level circuitry.

[0003] Market pressures are increasingly driving semiconductor manufacturers to reduce the size of semiconductor packages to fit the space constraints of electronic devices. In some semiconductor packages, direct chip attachment methods (e.g., flip-chip bonding between a semiconductor die and a substrate) can be used to reduce the package's coverage area. This direct chip attachment method involves directly connecting multiple conductive pillars electrically coupled to the semiconductor die to corresponding conductive structures (e.g., conductive bumps) on the substrate. In this regard, bonding structures can be formed over individual conductive pillars to bond the conductive pillars to their corresponding conductive structures—for example, forming a connector structure that includes conductive pillars, bonding structures, and conductive bumps. Furthermore, encapsulation materials can be applied to protect the semiconductor die. Summary of the Invention

[0004] One aspect of this disclosure provides a semiconductor die assembly comprising: a first semiconductor die including a first bonding pad on a first side of the first semiconductor die; and a second semiconductor die including a second bonding pad on a second side of the second semiconductor die; wherein the first bonding pad is aligned with and bonded to the second bonding pad at a bonding interface between the first bonding pad and the second bonding pad; and at least one of the first and second bonding pads includes a first copper layer having a first crystallographic orientation and a second copper layer having a second crystallographic orientation having a second crystallographic orientation different from the first crystallographic orientation, the first copper layer being located at the bonding interface.

[0005] Another aspect of this disclosure provides a method comprising: forming an opening in a dielectric material such that a bottom surface of the opening exposes a conductive structure contained in the dielectric material; partially filling the opening with a first copper having a generally first crystallographic orientation, wherein the first copper is connected to the conductive structure and includes a first top surface above and parallel to the bottom surface of the opening; and filling the opening with a second crystallographic orientation having a generally different crystallographic orientation from the first crystallographic orientation, wherein the second copper contacts the first top surface of the first copper and includes a second top surface that is generally flush with the surface of the dielectric material.

[0006] Another aspect of this disclosure provides a semiconductor die assembly comprising: a logic die including a first side and a second side opposite to the first side, wherein: the first side includes an integrated circuit system and a conductive structure coupled thereto; and the second side includes a first bonding pad operably coupled to the conductive structure via a through-substrate via (TSV) extending through the logic die; and a memory die bonded at the second side of the logic die, the memory die including a front side having a memory array and a second bonding pad operably coupled to the memory array, wherein: individual second bonding pads are aligned with and bonded to a corresponding first bonding pad at a bonding interface between the memory die and the logic die; and both the first and second, or both the first and second bonding pads, include a first copper layer having a first crystallographic orientation primarily and a second copper layer having a second crystallographic orientation primarily different from the first crystallographic orientation, the first copper layer being located at the bonding interface. Attached Figure Description

[0007] The following diagrams will help to better understand many aspects of this technology. The components in the diagrams are not necessarily drawn to scale. Instead, the focus is on clearly illustrating the principles of this technology.

[0008] Figure 1 This is a diagram of an interface wafer with a stack of semiconductor dies according to an embodiment of the present technology.

[0009] Figures 2A to 2C This describes the stages of the process for a core semiconductor die according to embodiments of the present technology.

[0010] Figure 3 This is a diagram illustrating a portion of an interface chip according to an embodiment of the present technology.

[0011] Figure 4A and 4B This describes the stages of a process for forming a semiconductor die assembly according to embodiments of the present technology.

[0012] Figure 5This is a diagram of a semiconductor die assembly according to an embodiment of the present technology.

[0013] Figure 6A The process steps for forming a bonding pad according to embodiments of the present technology are described.

[0014] Figure 6B This is a diagram of bonding pads that are joined together according to an embodiment of the present technology.

[0015] Figure 7 This is a block diagram illustrating, schematically, a system comprising a semiconductor die assembly configured according to embodiments of the present technology.

[0016] Figure 8 This is a flowchart of a method for forming a bonding pad according to an embodiment of the present technology. Detailed Implementation

[0017] The following describes specific details of several embodiments relating to bonding pads and associated systems and methods for semiconductor die assemblies. Wafer-level packaging (WLP) can provide a scaling form factor for semiconductor die assemblies (semiconductor device assemblies). WLP technology utilizes an interface wafer to which semiconductor dies or stacks of semiconductor dies (e.g., active dies, known-good dies, memory dies) are attached. Individual semiconductor dies (or stacks of semiconductor dies) are aligned with and electrically connected to corresponding interface dies of the interface wafer. The interface die may comprise semiconductor dies of a different type than the semiconductor dies (e.g., logic dies controlling the semiconductor dies) or an interposer die having a redistribution layer (RDL) configured to route electrical signals between the semiconductor dies (or stacks of semiconductor dies) and higher-level circuitry (e.g., host devices external to logic dies and / or memory dies).

[0018] After the semiconductor dies (or stacks of semiconductor dies) have been attached to an interface wafer, which may be called a chip-on-wax (CoW), an encapsulation material (e.g., molding compound, epoxy molding compound (EMC)) can be placed over the interface wafer, immersing the semiconductor dies (or stacks of semiconductor dies) in the encapsulation material. The encapsulation material is then cured at high temperature to harden it and provide protection for the semiconductor dies. Excess encapsulation material on the semiconductor dies (or stacks of semiconductor dies) can be removed using a polishing process. The process step of using an encapsulation material to protect the semiconductor dies can be called a molding process. Following the molding process, one or more dicing processes can be performed to dic (e.g., cut, separate) the individual semiconductor die assemblies along the scribing lines of the interface wafer.

[0019] For certain semiconductor die assemblies, the semiconductor die is attached to the interface wafer by forming a junction structure between the semiconductor die and the interface wafer (or the interface die of the interface wafer). This involves, for example, forming conductive pillars on the semiconductor die, forming conductive bumps on the interface die, and connecting the conductive pillars to the conductive bumps using solder. The distance between the semiconductor die and the interface die is referred to as the bonding line thickness (BLT), which is related to the total height of the junction structure. Similarly, semiconductor dies can be connected to each other to create a stack of semiconductor dies by forming junction structures between two or more semiconductor dies (e.g., memory dies). In some cases, the semiconductor die assembly contains an interface die carrying a stack of semiconductor dies (e.g., 4, 8, 12, or even more). Therefore, the total BLT limits the number of semiconductor dies that can be accommodated in the semiconductor die assembly while meeting the height specifications of the semiconductor die assembly.

[0020] Connector structures between semiconductor dies (or between a semiconductor die and an interface die) can be eliminated by utilizing a direct bonding scheme (also known as a zero-BLT configuration). Therefore, direct bonding can facilitate a reduction in the overall height of the semiconductor die assembly or an increase in the number of semiconductor dies while meeting the height requirements of the semiconductor die assembly. Typically, a direct bonding scheme involves two or more different materials (e.g., a conductive material and a dielectric material surrounding the conductive material) directly bonded to corresponding counterparts. In other words, respectively, the conductive material of the first semiconductor die is bonded to the corresponding conductive material of the second semiconductor die, and the dielectric material of the first semiconductor die is bonded to the corresponding dielectric material of the second semiconductor die. In this way, the direct bonding scheme can form an interconnect (with a zero-BLT conductive path) between the conductive materials of the first and second semiconductor dies, while the surrounding dielectric material provides electrical isolation and structural support for the interconnect.

[0021] Therefore, direct bonding can be referred to as combined bonding, hybrid bonding, or similar. Generally, the direct bonding process involves two stages. First, two dies / wafers (e.g., a top die / wafer and a bottom die / wafer) are attached together, such that the dielectric materials of the top and bottom dies / wafers are bonded to each other. In some embodiments, the surfaces to be bonded are activated (e.g., using a plasma treatment process) to facilitate surface bonding. Furthermore, the bonding pads (containing conductive material) of the top and bottom dies are aligned facing each other to form a conductive path therebetween, as described in more detail below. Additionally, the bonding pads may be recessed relative to the surfaces of the dielectric materials (e.g., bonding interfaces, mating interfaces), allowing the bonding of the dielectric materials to be achieved without interference from protruding bonding pads.

[0022] Subsequently, the bonding die / wafer is annealed at a high temperature (e.g., post-bonding annealing), allowing the conductive materials of the top and bottom dies to expand toward each other within an open space defined by the recesses and the dielectric material surrounding the bonding pads (e.g., due to a mismatch in the coefficients of thermal expansion (CTE) between the conductive and dielectric materials). When the surfaces of the top and bottom conductive materials come into contact, the conductive materials interleave (e.g., via atomic migration (hybridization, diffusion) from one conductive material to another) to form a permanent bond—e.g., a metallurgical bond. Once a bond is formed between the conductive pads, the conductive materials do not separate (or break) when the bonded die / wafer reaches the ambient or operating temperature of the semiconductor die assembly.

[0023] Direct bonding offers various advantages for semiconductor device assemblies. For example, it eliminates yield, reliability, and / or performance issues associated with forming junction structures. Furthermore, bonding pads can be produced using various process steps used in manufacturing semiconductor devices (e.g., processes for forming copper interconnects, chemical mechanical polishing, wet / dry etching processes), allowing for scalable pad spacing to achieve fine-pitch semiconductor die stacking. Additionally, by increasing the number of memory dies in the semiconductor device assembly—for example, due to zero BLT—the memory capacity of the semiconductor device assembly can be increased while maintaining the same package height.

[0024] One of the challenges associated with direct bonding schemes may be the thermal cycling associated with annealing bonded dies / wafers (e.g., dies / wafers attached to each other using dielectric layers) to form a metallurgical bond between the bonding pads during post-bonding annealing. In some cases, post-bonding annealing temperatures range from approximately 350°C to 450°C. In some embodiments, lowering the post-bonding annealing temperature may be beneficial given certain materials used during the direct bonding process steps—e.g., adhesive materials used to attach wafers (e.g., semiconductor wafers containing memory dies, interface wafers containing logic dies) to a carrier substrate. Alternatively, the post-bonding annealing temperature may be limited to avoid additional thermal cycling on semiconductor dies (e.g., dynamic random access memory (DRAM) products) that have already undergone their processing. In some cases, additional thermal cycling may have undesirable effects on the semiconductor dies.

[0025] This technology is designed to facilitate bonding between bonding pads in a direct bonding scheme. More specifically, this technology is suitable for post-bonding annealing processes at relatively low temperatures (e.g., about 200°C or lower). For example, the bonding pads may comprise composite conductive materials that are different from each other (two or more conductive materials other than the conductive material used as a backing material for the bonding pads, e.g., a composite metal structure). In this regard, a conductive material exhibiting a relatively higher diffusivity at the annealing temperature (e.g., the post-bonding annealing temperature) may be placed at the bonding interface (mating interface) of the bonding pads. Thus, at least due to the higher diffusivity, the bonding strength between the bonding pads can be enhanced—e.g., promoting grain growth across the bonding interface, improving the mixing of conductive materials across the bonding interface, avoiding the formation of micropores at the bonding interface, etc. In some embodiments, such conductive materials comprise copper. In some embodiments, the copper primarily has a (111) crystallographic orientation, which may also be referred to as nanotwinned copper (e.g., NT-Cu(111)).

[0026] Furthermore, the remaining portion of the bonding pads away from the bonding interface may contain a conductive material different from that of nanotwinned copper—for example, copper without a specific predominant crystallographic orientation or copper with a predominant crystallographic orientation different from (111), such as (100) or (110) crystallographic orientations. NT-Cu (111) has a higher diffusivity (e.g., approximately three (3) times the diffusivity compared to copper with other crystallographic configurations), which facilitates bonding between bonding pads at relatively low post-bonding annealing temperatures (e.g., approximately 200°C or lower), for example by suppressing the formation of copper-to-copper recessed pores. Thus, bonding pads containing NT-Cu (111) at the mating interface are suitable for direct bonding processes using relatively low post-bonding annealing temperatures—e.g., chip-to-wafer (C2W) direct bonding schemes, face-to-back (F2B) direct bonding schemes.

[0027] The term "semiconductor device or die" generally refers to a solid-state device comprising one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, microprocessors, diodes, and the like. Such semiconductor devices may include integrated circuits or components, data storage elements, processing components, and / or other features fabricated on a semiconductor substrate. Furthermore, the term "semiconductor device or die" may refer to a finished device or an assembly or other structure at various processing stages prior to becoming a finished device. Depending on its context, the term "substrate" may refer to a wafer-level substrate or a single-cut die-level substrate. Additionally, a substrate may comprise a semiconductor wafer, a package support substrate, an interposer, a semiconductor device or die, or the like. Those skilled in the art will recognize that appropriate steps of the methods described herein can be performed at the wafer or die level.

[0028] Furthermore, unless the context otherwise indicates, conventional semiconductor manufacturing techniques can be used to form the structures disclosed herein. For example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, plating, and / or other suitable techniques can be used to deposit materials. Similarly, plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques can be used to remove materials. Some techniques can be combined with photolithography processes. Those skilled in the art will also understand that the techniques may have additional embodiments and can be implemented without reference to this document. Figures 2A to 5 The described techniques are practiced in the context of several details of the embodiments described.

[0029] As used herein, the terms “vertical,” “lateral,” “downward,” “upward,” “above,” and “below” can refer to the relative orientation or position of features in a semiconductor die assembly given the orientations shown in the figures. For example, “above” or “topmost” can refer to a feature positioned closer to the top of the page than another feature. However, these terms should be interpreted broadly to include semiconductor devices having other orientations. Furthermore, the terms “front,” “back,” “top,” “bottom,” “above,” “below,” and the like (if present) in the specification and claims are for descriptive purposes and are not necessarily used to describe permanent relative positions. It should be understood that the terms thus used are interchangeable where appropriate, such that embodiments of the invention described herein can, for example, operate on orientations other than those described or otherwise. Unless otherwise stated, terms such as “first” and “second” are used to arbitrarily distinguish elements described by such terms. Therefore, these terms are not necessarily intended to indicate time priority or other priorities for such elements. The term “coupling,” as used herein, is not intended to be limited to direct coupling or mechanical coupling.

[0030] Figure 1 This is a diagram of an interface substrate 105 (or interface wafer) having a stack of semiconductor dies 110 according to an embodiment of the present technology. Given the single-cut individual semiconductor dies 110 (or stacks of semiconductor dies 110) aligned and attached to corresponding interface dies 106 of the interface substrate 105, the interface substrate 105 carrying the stack of semiconductor dies 110 may be referred to as a reconstructed wafer (or CoW as described above). Although the present technology is described herein with semiconductor device assemblies comprising stacks of semiconductor dies (e.g., stacks of semiconductor dies 110) attached to interface dies (e.g., interface dies 106), it should be understood that the principles of the present technology are not limited thereto. For example, a semiconductor device assembly according to the present technology may comprise a single semiconductor die (e.g., a memory die) attached (or bonded) to an interface die.

[0031] In some embodiments, interface die 106 is a semiconductor die (e.g., a logic die, a controller die) that differs from the type and stack of semiconductor dies 110 (e.g., a memory die, a DRAM product). The logic die may be configured to exchange electrical signals with semiconductor die 110 and higher-level circuitry coupled to the logic die (e.g., a host device external to a semiconductor device assembly). In some embodiments, interface die 106 is an interposer die having various conductive structures (e.g., redistribution layers, pathways, interconnects) configured to route electrical signals between the stack of semiconductor dies 110 and higher-level circuitry—e.g., a central processing unit (CPU) coupled to the stack of semiconductor dies 110 via the interposer die.

[0032] The stack of semiconductor dies 110 comprises semiconductor dies 110 stacked one on top of the other. Each semiconductor die 110 in the stack has a front side facing the interface die 106, which may be referred to as the active side of the semiconductor die having a memory array, an integrated circuit coupled to the memory array, bonding pads coupled to the integrated circuit, etc., and a rear side opposite the front side. As described in more detail herein, the rear side of the semiconductor die 110 may include bonding pads configured to attach to (or bond to) bonding pads of another die (or wafer). Furthermore, the semiconductor die 110 may include a through-substrate via (TSV) extending through the semiconductor die 110, configured to couple bonding pads on the front side to bonding pads on the rear side. The uppermost semiconductor die 110 in the stack may be referred to as the top die, and one or more semiconductor dies 110 located between the top die and the interface die 106 may be referred to as the core die.

[0033] Similarly, logic die 106 includes a front side (e.g., the active side of a logic die having various integrated circuits, bonding pads, and / or conductive structures coupled to integrated circuits) and a rear side opposite the front side. The conductive structures on the front side may include redistribution layers and vias, as well as conductive pillars / pads and / or terminals (e.g., balls in a ball grid array (BGA)) configured to couple to a higher level of circuitry—e.g., a central processing unit (CPU). The rear side of logic die 106 may include bonding pads configured to attach to (or bond to) bonding pads of another die (e.g., semiconductor die 110). Furthermore, logic die 106 may include TSVs extending through logic die 106, configured to couple bonding pads on the front side to bonding pads on the rear side.

[0034] In some embodiments, after front-side wafer processing (e.g., forming bonding pads coupled to the integrated circuit), an adhesive material is used to temporarily attach the core wafer (wafer containing the core die) to a carrier wafer (or substrate) – for example, with the front side of the core wafer facing the carrier wafer. Subsequently, the core wafer may be thinned to expose the TSV of the core die from the back side. Various structures are formed on the back side of the thinned core die / wafer to facilitate core die stacking – for example, depositing a dielectric layer to protect the back side of the core die, forming bonding pads connected to the exposed surfaces of the TSV, etc. In some embodiments, the adhesive material may constrain the temperature of the deposited dielectric layer (and / or the annealing of the bonding pads). The core die is then diced and stacked together with the top die on interface substrate 105 (e.g., using process steps for direct bonding) to produce a reconstructed wafer, as shown in [the original text]. Figure 1 As explained in [the document]. However, the top die of the stack may be thicker than the core die and may not have a backside conductive structure (or TSV).

[0035] The process steps for fabricating semiconductor dies to stack one on top of the other (e.g., forming bonding pads and / or conductive structures coupled to an integrated circuit on the front side of the wafer, temporarily attaching the wafer to a carrier substrate, thinning the wafer from the back side, forming conductive pads on the back side, etc.) can be applied to the interface substrate 105, such that suitable conductive structures for stacking the semiconductor dies can be formed on the front and back sides of the interface die 106. Thus, the interface substrate 105 can correspond to an interface wafer that has undergone the process steps described above—for example, thinned and containing suitable conductive structures for stacking on the front and back sides. Figure 1 The diagram also depicts scribe lines 115 (which may be referred to as scribe lines, cut lines, or the like) on the interface substrate 105 between the stacks of semiconductor dies 110 (e.g., horizontal scribe lines 115a along the x-direction and vertical scribe lines 115b along the y-direction). In some embodiments, individual semiconductor die assemblies are slit along the scribe lines after the CoW molding process is completed.

[0036] Figures 2A to 2C This describes the stages of a process for a core semiconductor die (or a core wafer containing a core semiconductor die) according to embodiments of the present technology. Figure 2A This illustrates a cross-sectional view of a portion of the core semiconductor die (e.g., the core DRAM die of a core wafer) after various structures have been formed following the completion of front-end processing. For example, Figure 2AThe semiconductor die 210 (which may be an example of or include aspects of semiconductor die 110) is described, having a front side 211 and a rear side 212 opposite to the front side 211. The front side 211 of the semiconductor die 210 includes an integrated circuit 215 (e.g., a memory array, peripheral circuitry operatively coupled to the memory array, etc.), an interconnect layer 220 (e.g., one or more dielectric layers including conductive traces and pathways) coupled to the integrated circuit 215, and a through-substrate via 225 (TSV). The interconnect layer 220 is further coupled to TSV pads 226 and probe pads 230. The semiconductor die 210 also includes dummy pads 227 that can be isolated (e.g., electrically isolated from the integrated circuit 215) or connected to a ground plane of the semiconductor die 210. In some embodiments, pads 226, 227, and 230 comprise Al (or an AlCu alloy).

[0037] After pads 226, 227, and 230 have been formed on interconnect layer 220, dielectric layer 235 (e.g., silicon oxide (SiOx) deposited at approximately 375°C) may be formed. Depending on the aspect ratio provided by pads 226, 227, and 230, one or more air gaps 245 may exist in dielectric layer 235. Subsequently, dielectric layer 240 (e.g., silicon carbon nitride (SiCN) deposited at approximately 350°C) may be formed on dielectric layer 235. Bonding pads 245 and 250 are then formed in dielectric layers 235 and 240. Individual bonding pads 245 and 250 comprise conductive pads 246 (e.g., TaN) and metal 247 (e.g., copper). Metal 247 may comprise two or more metals (other than conductive pads 246) with different material properties, as referenced. Figure 6A and 6B More detailed description.

[0038] Bond pad 245 is coupled to TSV 225 via TSV pad 226 and interconnect layer 220, while bond pad 250 is not connected to any electrically active and / or functional components of semiconductor die 210. Therefore, bond pad 250 may be referred to as a dummy bond pad, while bond pad 245 may be referred to as an active bond pad. Bond pad 250 (or a plurality of bond pads 250 distributed throughout semiconductor die 210) provides the required process uniformity for bond pad 245 to meet the following requirements: for example, preventing the surface of bond pad 245 from protruding above the surface of dielectric layer 240, and ensuring that depressions (recesses and / or etching) of metal (e.g., copper) below the surface of dielectric layer 240 are within acceptable limits—for example, after a chemical mechanical polishing (CMP) process step. This requirement for bond pads 245 and 250 facilitates proper bonding of front side 211 to other semiconductor dies (or logic dies).

[0039] Figure 2BThis diagram illustrates a cross-sectional view of the semiconductor die 210 after TSV 225 has been exposed from the rear side 212. In this regard, the semiconductor die 210 has been temporarily attached to a carrier substrate 265 using an adhesive material 260, with the front side 211 of the semiconductor die 210 facing the carrier substrate 265. Subsequently, a backside polishing process (or CMP process) has been performed to expose the TSV 225 from the rear side 212. In some embodiments, a portion of the TSV 225 may protrude from the rear side 212, and a dielectric layer 270 (e.g., silicon nitride (SiN) deposited at approximately 180°C) may be formed to cover the rear side of the semiconductor die 210. Thereafter, a portion of the dielectric layer 270 over the TSV 225 may be removed (e.g., polished) to expose the TSV 225, as... Figure 2B Described in the text.

[0040] Figure 2C This illustrates a cross-sectional view of the semiconductor die 210 after various structures have been formed following the subsequent back-end processing. For example, Figure 2C The diagram describes dielectric layer 275 (e.g., SiOx deposited at approximately 180°C), dielectric layer 280 (e.g., SiN or SiCN deposited at approximately 180°C), and bonding pads 285 and 290 formed in dielectric layers 275 and 280. Similar to bonding pads 245 and 250, bonding pad 290 may be referred to as a dummy bonding pad, while bonding pad 285 may be referred to as an active bonding pad. Bonding pad 285 is coupled to bonding pad 245 via a TSV 225 extending through semiconductor die 210. In some embodiments, bonding pads 285 and 290 have the same structural configuration as bonding pads 245 and 250. For example, individual bonding pads 285 and 290 include a conductive pad 246 (e.g., TaN) and a metal (e.g., copper) comprising two or more metals (other than the conductive pad 246) with different material properties, as referenced. Figure 6A and 6B More detailed description.

[0041] It should be noted that, given the adhesive material 260, the temperature of various process steps performed on the back side 212 can be constrained (limited). For example, the temperatures at which dielectric layers 270, 275, and 280 are formed are lower than the temperatures at which dielectric layers 235 and 240 are formed. In such cases... Figure 2C After the subsequent processing as shown, the semiconductor die 210 can be diced and detached from the carrier substrate 265 (e.g., by removing the adhesive material 260), allowing the semiconductor die 210 to be attached to the interface die 106 (and / or stacked on top of each other to form a stack of semiconductor dies 210) to form a reference. Figure 1 The aforementioned CoW.

[0042] Figure 3This diagram illustrates a cross-sectional view of a portion of the interface die 310 (which may be an example of or include an aspect of the interface die 106) of an interface wafer (e.g., interface substrate 105) after various structures have been formed following the completion of front-side and back-side processing. Thus, the interface die 310 can be considered as a part of the interface wafer (e.g., interface substrate 105) after the front-side and back-side processing has been completed and various structures have been formed. Figure 2C The semiconductor die 210 described herein is at the same stage. For example, interface die 310 includes a front side 311 and a rear side 312 opposite to the front side 311. The front side 311 of interface die 310 includes various integrated circuits 315 (e.g., logic circuit systems), interconnect layers 320 (e.g., one or more dielectric layers including conductive traces and vias) coupled to integrated circuits 315, and TSV 325. Interconnect layer 320 is further coupled to TSV pad 326 and probe pad 330. In some embodiments, TSV pad 326, dummy pad 327, and probe pad 330 comprise Al (or an AlCu alloy). TSV pad 326 may be further coupled to conductive pad 394, which is coupled to copper pad 395. In some embodiments, solder bumps 396 are formed on copper pad 395. In some embodiments, conductive pad 394 comprises aluminum, while solder bumps 396 comprise a SnAg alloy.

[0043] The front side 311 of the interface die 310 can be temporarily attached to the carrier substrate 365 using an adhesive material 360, allowing reference to be performed on the rear side 312 of the interface die 310. Figure 2B and 2C The backside processing is described. Therefore, the interface die 310 has been thinned from the backside (e.g., using a backside polishing process) to expose the TSV 325. Subsequently, dielectric layers 370 (e.g., SiN deposited at approximately 180°C), 375 (e.g., silicon oxide deposited at approximately 180°C), and 380 (e.g., SiCN or SiN deposited at approximately 180°C) are formed on the backside. Bonding pads 385 (active bonding pads) and 390 (dummy bonding pads) are formed in dielectric layers 380 and 375. In some embodiments, bonding pads 385 and 390 have the same structural configuration as bonding pads 245 and 250. For example, individual bonding pads 385 and 390 comprise conductive pads (e.g., conductive pad 246) and metals (e.g., copper) containing two or more metals with different material properties (other than conductive pad 246), as referenced. Figure 6A and 6B More detailed description.

[0044] Figure 4A and 4B This describes the stages of a process for forming a semiconductor die assembly according to embodiments of the present technology. Figure 4A Explain semiconductor dies (e.g., Figure 2CThe semiconductor die 210 depicted in the image is attached to the interface die of the interface wafer (e.g., Figure 3 The interface wafer 310 depicted is attached to the carrier substrate 365 via an adhesive material 360. In this regard, the front side 211 of the semiconductor wafer 210 and the rear side of the interface wafer 310 can be treated with an isoplasma process to promote bonding between the dielectric layer 240 of the semiconductor wafer 210 (e.g., SiCN deposited at approximately 350°C) and the dielectric layer 380 of the interface wafer 310 (e.g., SiCN or SiN deposited at approximately 180°C) at the bonding interface 450. It should be noted that due to the recesses of the metal surfaces, the surfaces of the bonding pads (e.g., the metal surfaces of bonding pads 245 and 385) may not be fully bonded together (e.g., interfacial) at this stage. For example, Figure 4A This indicates that the gap 460 is formed by the depression.

[0045] Figure 4B This describes a semiconductor die 210 attached to interface die 310 after a thermal annealing step (e.g., at approximately 200°C or lower for approximately 2 hours). During the thermal annealing step, the metals (e.g., copper) of bonding pads 245 and 385 expand toward each other within an open space defined by grooves and dielectric layers 240 and 380 surrounding bonding pads 245 and 385 (e.g., due to CTE mismatch between the metal and dielectric materials). When the surfaces of the top and bottom metals contact, the metals interlock (e.g., via atomic migration (or mixing) from one metal to another to form a permanent bond—e.g., a metallurgical bond). Thus, the metals (e.g., copper) of bonding pads 245 and 385 form a continuous metal structure (e.g., without gaps across the bonding interface 450—e.g., after the thermal annealing step). For example, Figure 4B This indicates that the gap 460 is removed during the hot annealing step.

[0046] Figure 5 This is a diagram of a semiconductor die assembly 501 according to an embodiment of the present technology. The semiconductor die assembly 501 includes an interface die (e.g., interface die 310) directly bonded to a stack of semiconductor dies at a bonding interface 450a. The stack of semiconductor dies includes core semiconductor dies 210a and 210b (e.g., semiconductor die 210) and a top semiconductor die 505, each of which is directly bonded to each other at bonding interfaces 450b and 450c.

[0047] The top semiconductor die 505 includes aspects of semiconductor die 210. For example, the top semiconductor die 505 includes an integrated circuit 215 and an interconnect layer 220 coupled to the integrated circuit 215 and TSV 225. The interconnect layer 220 is further coupled to TSV pad 226 and probe pad 230. Additionally, the top semiconductor die 505 includes bonding pads 245 and 250 formed in dielectric layers 235 and 240. In some embodiments, TSV 225 is omitted for the top semiconductor die 505. In some embodiments, the top semiconductor die 505 is thicker than the core semiconductor dies 210a and 210b because the top semiconductor die 505 may not need to be thinned from the back side.

[0048] As in Figure 5 The semiconductor die assembly 501 is depicted as being temporarily attached to a carrier substrate 365 using an adhesive material 360. In some embodiments, a molding process step may be performed to provide protection for the semiconductor die assembly 501. Subsequently, individual semiconductor die assemblies 501 may be individually cut and detached from the carrier substrate 365. Although the semiconductor die assembly 501 illustrates a stack of semiconductor dies having three (3) semiconductor dies bonded to an interface die 310 (i.e., core semiconductor dies 210a and 210b and a top semiconductor die 505), the art is not limited thereto. For example, the stack of semiconductor dies may contain 8, 12, 16, 32 or even more semiconductor dies (e.g., memory dies).

[0049] Figure 6A The process steps for forming a bonding pad according to embodiments of the present technology are described. Figure 6A Figures 610 to 635 contain details illustrating several stages used to form individual mating pads (e.g., mating pads 245, 285, and 385). It should be understood that, although... Figure 6A The various structures depicted are related to the process steps used to form bonding pads (e.g., bonding pads 285 and 385) on the back side of a semiconductor die, but the process steps are applicable to forming bonding pads on the front side of a semiconductor die (e.g., bonding pad 245). For example, bonding pad 685 depicted in FIG. 635 may correspond to bonding pads 285 and / or 385 of semiconductor dies 210 and 310, respectively, while the same process steps may be used to form bonding pad 245 of semiconductor die 210.

[0050] Figure 610 depicts an opening 670 formed in the dielectric material 650 and conductive pads 671 formed on the sidewalls and bottom surfaces of the opening 670 and on the surface of the dielectric material 650 (e.g., reference). Figure 2AThe TaN pad 246 is described. The opening 670 may have a circular, elliptical, or rectangular coverage area, etc. The bottom surface of the opening 670 exposes a conductive structure 660, a portion of which is contained within a dielectric material 650. In this manner, the conductive pad 671 contacts the conductive structure 660. Figure 610 also illustrates a substrate 665, which may be an example of a substrate (e.g., a silicon substrate) of the semiconductor die 210 (or interface die 310) or contain aspects thereof.

[0051] The dielectric material 650 may be a composite dielectric layer. In the embodiment illustrated in FIG610, the dielectric material 650 comprises three (3) dielectric layers 651, 652 and 653, which may be used as a reference. Figure 2C Dielectric layers 270, 275, and 280 (or referenced) are described. Figure 3 Examples of or aspects thereof are described for dielectric layers 370, 375, and 380. In other embodiments, for example, when bonding pads (e.g., bonding pad 245) are formed on the front side of a semiconductor die, dielectric material 650 may include reference... Figure 2A The dielectric layers 235 and 240 are described. Furthermore, in the embodiment illustrated in FIG. 610, the conductive structure 660 may be an example of TSV 225 (or TSV 325) or include aspects thereof. In other embodiments, for example, when a bonding pad (e.g., bonding pad 245) is formed on the front side of a semiconductor die, the conductive structure 660 may be as described in reference... Figure 2A The TSV pad 226 described may include instances or aspects thereof.

[0052] Figure 615 depicts a first metal 675 formed in the opening 670 and above the conductive pad 671. In some embodiments, the first metal 675 comprises copper, which can be plated onto the conductive pad 671 using a plating solution (e.g., using an electroplating process step). Figure 620 depicts the first metal 675 above the conductive pad 671 (e.g., excess portion of the first metal 675) having been removed. In some embodiments, a CMP process step is used to remove excess portion of the first metal 675 and stop on the conductive pad 671. Figure 625 depicts a portion of the first metal 675 in the opening 670 having been removed. In some embodiments, a wet and / or plasma etching process step for selectively removing the first metal 675 can be used to partially remove the first metal 675 in the opening 670.

[0053] In some embodiments, a bottom-up deposition process step that selectively forms a first metal 675 in the opening 670 can be used to partially fill the opening 670 with the first metal 675, instead of the process steps described with reference to Figures 615 (e.g., copper plating step), 620 (e.g., CMP process step), and 625 (e.g., wet / plasma etching process step). In this respect, the bottom-up deposition process step can selectively form the first metal 675 (e.g., copper) on a first portion of the conductive pad 671 corresponding to the bottom surface of the opening 670, but not on a second portion of the conductive pad 671 corresponding to the sidewall surface of the opening 670 (or on the conductive pad 671 above the surface of the dielectric material 650).

[0054] Figure 625 depicts a first metal 675 partially filling an opening 670, wherein the first metal 675 has a first top surface above and parallel to the bottom surface of the opening 670. In some embodiments, the first top surface corresponds to at least one-quarter (denoted as "D" in Figure 625) of the depth of the opening 670—for example, one-third, half, two-thirds, or the like—such that the remaining portion of the opening 670 may be filled with a second metal 680, as described with reference to Figures 630 and 635. In this respect, the depth of the opening 670 approximately corresponds to the thickness of a bonding pad (e.g., bonding pad 685) formed in the opening 670.

[0055] Figure 630 depicts a second metal 680 formed in the opening 670 (in contact with the first metal 675) and on the conductive pad 671. In some embodiments, the second metal 680 comprises copper, which can be plated using a plating solution (e.g., using an electroplating process step). In some embodiments, the copper corresponding to the second metal 680 may have different properties (e.g., different crystallographic orientations) than the copper corresponding to the first metal 675, as described in more detail below.

[0056] Figure 635 depicts a second metal 680 (e.g., excess portion of the second metal 680) removed above the conductive pad 671. Additionally, the conductive pad 671 is removed from the surface of the dielectric layer 653. In some embodiments, a CMP process step may be used to remove excess portion of the second metal 680 and the conductive pad 671 before stopping on the dielectric layer 653. As depicted in Figure 635, the top surface of the second metal 680 may generally be flush with the surface of the dielectric material 650. For example, the second metal 680 does not protrude above the top surface of the dielectric material 650 (e.g., dielectric layer 653). In the embodiment illustrated in Figure 635, as a result of the CMP process, the second metal 680 may be recessed relative to the top surface of the dielectric material 650 (denoted as "R" in Figure 635). It should be understood that Figure 635, which depicts the bonding pad 685, is not drawn to scale - for example, the width of the bonding pad 685 may vary from 0.2 to 10 micrometers (μm), while the recess (R) may range from less than 5 nanometers (nm).

[0057] In some embodiments, the copper filling the opening 670 comprises multiple grains, each having a different size and material properties from the others. Depending on the process conditions for forming the copper (e.g., plating solution, temperature, copper backing layer formed thereon, annealing conditions after copper formation), the copper grains may contain a distribution of certain crystallographic orientations—e.g., (100), (110), (111), or similar. For example, more than half of the copper grains corresponding to the second metal 680 may have a (111) crystallographic orientation—that is, the copper is predominantly or substantially (111) crystallographically oriented. Copper with a (111) crystallographic orientation may be referred to as nanotwins (e.g., NT-copper (111)), which can promote the bonding (intercalation) of copper during direct bonding processes (including relatively low post-bonding annealing temperatures (e.g., approximately 200°C or lower)). For example, nanotwins can promote grain growth across the bonding interface, mixing of copper atoms across the bonding interface, and reduction of microporosity formation at the bonding interface, etc. In some cases, nanotwins may include a seed layer configured to promote nanotwin formation—for example, a strongly (111) oriented seed layer, with more than 90% of the surface of the seed layer in a (111) crystallographic orientation.

[0058] In contrast to copper corresponding to the second metal 680, copper corresponding to the first metal 675 may have a dominant crystallographic orientation different from the (111) orientation, such as (100) or (110) orientation—for example, more than half of its copper grains have a crystallographic orientation different from the (111) orientation. In some cases, copper corresponding to the first metal 675 may not have a particular dominant (or principal) crystallographic orientation—for example, the copper grains of the first metal 675 have various crystallographic orientations, making it impossible to determine a dominant or principal crystallographic orientation. Although the foregoing examples of the dominant (or principal) crystallographic orientation of copper provide that more than half of the copper grains have certain crystallographic orientations, the art is not limited thereto. For example, the dominant (or principal) crystallographic orientation of copper may be determined based on 60%, 70%, 80%, or even more of the copper grains having a particular crystallographic orientation.

[0059] Figure 6B This is a diagram of bonding pads that are joined together according to an embodiment of the present technology. Figure 6B This illustrates that bonding pad 685 (on the bottom semiconductor die) contacts (directly bonds) another bonding pad 690 (on the top semiconductor die), which can be used as a reference. Figure 2A The described example of or includes aspects of the bonding pad 245. The bonding pad 690 may have been formed by the process steps described with reference to Figures 610-635. For example, the bonding pad 690 includes a first metal 675 and a second metal 680. Furthermore, the bonding pad 690 is coupled to the TSV pad 226, as referenced... Figure 2A describe.

[0060] Across the bonding interface 450, a second metal 680 from bonding pads 685 and 690 forms a single block of second metal 680 (e.g., a continuous sheet of second metal 680, primarily having copper with a (111) crystallographic orientation), which provides a conductive path between conductive structure 660 (or TSV 225, 325) and TSV pad 226, and a mechanical connection between bonding pads 685 and 690. Furthermore, a dielectric layer 653 (or 280) directly bonded to dielectric layer 240 provides additional bonding strength between the top and bottom dies.

[0061] although Figure 6BThe invention depicts both bonding pads 685 and 690, which include a first metal 675 and a second metal 680 (e.g., a composite metal structure), but is not limited thereto. For example, in some embodiments, one of bonding pads 685 or 690 comprises only the first metal 675 (while the other bonding pad comprises a composite metal structure). In such embodiments, the first metal 675 and the second metal 680 are bonded to each other at a bonding interface 450 to provide a conductive path between the conductive structure 660 (or TSV 225, 325) and the TSV pad 226. In some embodiments, one of bonding pads 685 or 690 comprises only the second metal 680 (while the other bonding pad comprises a composite metal structure). In some embodiments, both bonding pads 685 and 690 comprise only the second metal 680 (neither bonding pad 685 nor bonding pad 690 comprises a composite metal structure).

[0062] Figure 6B To further illustrate, the two dielectric layers are bonded to each other at a bonding interface 450—for example, dielectric layer 653 (or 280) is bonded to dielectric layer 240. As described herein, dielectric layer 653 (or 280) can be deposited at a relatively lower process temperature than dielectric layer 240 (e.g., during process steps forming various structures on the front side of a semiconductor die) (e.g., during process steps forming various structures on the back side of a semiconductor die). In some embodiments, an adhesive material 260 (or 360) present during the deposition of dielectric layer 653 (or 280) limits the process temperature of dielectric layer 653 (or 280), as referenced. Figure 2C Description. In this respect, the only difference between dielectric layers 653 (or 280) and 240 may be the deposition temperature—for example, about 180°C versus about 350°C. In some embodiments, dielectric layers 653 (or 280) and 240 may have the same material composition—for example, SiCN. In some embodiments, dielectric layers 653 (or 280) and 240 may have different material compositions—for example, SiCN versus SiN.

[0063] refer to Figure 5 The described semiconductor die assembly 501 can be incorporated into any of numerous larger and / or more complex systems, a representative example of which is... Figure 7The system 770 is schematically shown in the diagram. System 770 may include a semiconductor die assembly 501, a power supply 772, a driver 774, a processor 776, and / or other subsystems or components 778. The semiconductor die assembly 501 may include features generally similar to those of the bonding pads described above—for example, bonding pads 685 and 690. In other words, the semiconductor die assembly 501 includes bonding pads that are bonded to each other, wherein at least one of the bonding pads includes a first metal and a second metal different from the first metal. Furthermore, the first metal is located at the bonding interface, and the second metal has a first thickness corresponding to at least one-quarter of the second thickness of the first or second bonding pad. Given the increased number of memory dies (e.g., DRAM dies) that can be accommodated in a package due to a zero-BLT configuration, the semiconductor die assembly 501 may include increased memory (or storage) capacity for a given package height.

[0064] The resulting system 770 can perform any of a wide variety of functions, such as memory storage, data processing, and / or other suitable functions. Therefore, a representative system 770 may include, but is not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, and apparatus. Components of system 770 may be housed in a single unit or distributed over multiple interconnected units (e.g., via a communication network). Components of system 770 may also include remote devices and any of a wide variety of computer-readable media.

[0065] Figure 8 This is a flowchart 800 of a method for forming an bonding pad according to an embodiment of the present technology. Flowchart 800 may include, as referenced... Figure 6A Aspects of the methods described.

[0066] The method includes forming an opening in a dielectric material such that the bottom surface of the opening exposes a conductive structure contained within the dielectric material (box 810). The method further includes partially filling the opening with a first copper having a generally first crystallographic orientation, wherein the first copper is connected to the conductive structure and includes a first top surface above and parallel to the bottom surface of the opening (box 815). The method further includes filling the opening with a second crystallographic orientation having a generally different crystallographic orientation from the first, wherein the second copper contacts the first top surface of the first copper and includes a second top surface that is generally flush with the surface of the dielectric material (box 820).

[0067] In some embodiments, the second crystallographic orientation corresponds to the (111) orientation. In some embodiments, the method further includes forming conductive pads at the surface of the dielectric material, at the sidewall surfaces of the opening, and at the bottom surface of the opening before partially filling the opening with the first copper, wherein the first copper is connected to the conductive structure through the conductive pads. In some instances, partially filling the opening with the first copper includes forming the first copper on a first portion of the conductive pad corresponding to the bottom surface of the opening, without forming the first copper on a second portion of the conductive pad corresponding to the sidewall surfaces of the opening.

[0068] In some embodiments, partially filling an opening with first copper comprises: forming first copper on a conductive pad such that the first copper fills the opening; removing a first portion of the first copper above a plane corresponding to the surface of the dielectric material; and removing a second portion of the first copper from the opening portion. In some instances, filling an opening with second copper comprises: forming second copper above a first top surface of the first copper and above a surface of the dielectric material such that the second copper fills the opening; and removing a portion of the second copper above a plane corresponding to the surface of the dielectric material.

[0069] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are feasible. Furthermore, embodiments from two or more of the methods can be combined. In addition, specific embodiments of the technology have been described herein for illustrative purposes, but various modifications can be made without departing from this disclosure.

[0070] The devices discussed herein (including semiconductor devices) can be formed on a semiconductor substrate or die (e.g., silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc.). In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate can be controlled by doping with various chemical species (including, but not limited to, phosphorus, boron, or arsenic). Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0071] As used herein, the word "or," as in the claims, as in a list of items (e.g., a list of items preceded by phrases such as "at least one of" or "one or more of"), indicates an inclusive list such that (e.g.) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a set of closed conditions. For example, an example step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be understood in the same manner as the phrase "at least partially based on".

[0072] As can be understood from the foregoing, specific embodiments of the invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the invention. Rather, numerous specific details have been discussed in the foregoing description to provide a thorough and feasible description of embodiments of the present technology. However, those skilled in the art will recognize that this disclosure may be practiced without one or more of these specific details. In other instances, well-known structures or operations typically associated with memory systems and devices have not been shown or described in detail so as not to obscure other aspects of the present technology. In general, it should be understood that various other devices, systems, and methods, in addition to the specific embodiments disclosed herein, may also be within the scope of the present technology.

Claims

1. A semiconductor die assembly comprising: A first semiconductor die, which includes a first bonding pad on a first side of the first semiconductor die; and A second semiconductor die, comprising a second bonding pad on a second side of the second semiconductor die; wherein: The first bonding pad is aligned with and bonded to the second bonding pad at the bonding interface between the first bonding pad and the second bonding pad; and At least one of the first and second bonding pads includes a first copper layer having a first crystallographic orientation and a second copper layer having a second crystallographic orientation different from the first crystallographic orientation, the first copper layer being located at the bonding interface, wherein the first bonding pad is connected to a through-substrate via (TSV) of a conductive structure extending through the first semiconductor die and configured to couple the first bonding pad to a third side of the first semiconductor die, the third side being opposite to the first side.

2. The semiconductor die assembly according to claim 1, wherein the first crystallographic orientation corresponds to the (111) orientation.

3. The semiconductor die assembly of claim 1, wherein the second copper layer has a first thickness of at least one-quarter of the second thickness corresponding to the first or second bonding pad.

4. The semiconductor die assembly according to claim 1, wherein: The first side of the first semiconductor die includes a first dielectric material surrounding the first bonding pad, the first dielectric material being formed at a first temperature; The second side of the second semiconductor die includes a second dielectric material surrounding the second bonding pad, the second dielectric material being formed at a second temperature higher than the first temperature; and The first and second dielectric materials are bonded at the bonding interface.

5. The semiconductor die assembly of claim 4, wherein the first and second dielectric materials correspond to silicon carbon nitride.

6. The semiconductor die assembly of claim 1, wherein the first and / or second semiconductor dies exchange electrical signals with a device outside the semiconductor die assembly via the conductive structure.

7. The semiconductor die assembly of claim 1, wherein the second bonding pad is connected to a second through-substrate via (TSV) extending through the second semiconductor die and configured to couple the second bonding pad to a third bonding pad on a fourth side of the second semiconductor die, the fourth side being opposite to the second side.

8. The semiconductor die assembly according to claim 7, wherein: The fourth side of the second semiconductor die includes a first dielectric material surrounding the third bonding pad, the first dielectric material being formed at a first temperature; and The second side of the second semiconductor die includes a second dielectric material surrounding the second bonding pad, the second dielectric material being formed at a second temperature above the first temperature.

9. The semiconductor die assembly according to claim 7, wherein: The third bonding pad is configured to bond at the second bonding interface to the fourth bonding pad of the third semiconductor die of the semiconductor die assembly; and At least one of the third and fourth bonding pads comprises a third copper layer having a predominantly first crystallographic orientation and a fourth copper layer having a predominantly second crystallographic orientation, the third copper layer being located at the second bonding interface.

10. The semiconductor die assembly according to claim 1, wherein: The first semiconductor die corresponds to a logic die or an interposer die; and The second semiconductor die corresponds to a memory die.

11. A semiconductor die assembly comprising: A logic die, comprising a first side and a second side opposite to the first side, wherein: The first side includes an integrated circuit system and a conductive structure coupled thereto; and The second side includes a first bonding pad operably coupled to the conductive structure via a through-substrate via (TSV) extending through the logic die; and A memory die, bonded at the second side of the logic die, the memory die including a front side having a memory array and a second bonding pad operatively coupled to the memory array, wherein: Individual second bonding pads are aligned with and bonded to the corresponding first bonding pads at the bonding interface between the memory die and the logic die; and Both the first and second, or the first and second bonding pads, comprise a first copper layer having a first crystallographic orientation and a second copper layer having a second crystallographic orientation different from the first crystallographic orientation, with the first copper layer located at the bonding interface.

12. The semiconductor die assembly of claim 11, wherein: The memory die includes a third bonding pad disposed on a rear side of the memory die opposite to the front side, the third bonding pad being coupled to the second bonding pad via a through-substrate via (TSV) extending through the memory die. The third bonding pad is surrounded by a first dielectric material formed at a first temperature; and The second bonding pad is surrounded by a second dielectric material formed at a second temperature higher than the first temperature.

13. The semiconductor die assembly of claim 12, wherein the memory die is a first memory die, and the semiconductor die assembly further comprises: A second memory die includes a fourth bonding pad at the front side of the second memory die, the second memory die having a second memory array operatively coupled to the fourth bonding pad, wherein: Individual third bonding pads are aligned with and bonded to the corresponding fourth bonding pads at the second bonding interface between the first and second memory dies, and Both the third and fourth, or the third and fourth bonding pads, comprise a third copper layer having a predominantly first crystallographic orientation and a fourth copper layer having a predominantly second crystallographic orientation, the third copper layer being located at the second bonding interface.

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