Data Transmission Circuit and Memory

Abstract

The present application relates to a data transmission circuit and a memory, including a sense amplifier circuit, a first sub-discharge path, a second sub-discharge path, and a discharge adjustment unit. The sense amplifier circuit is configured to generate an amplified signal based on the signals at its first end and second end; the first sub-discharge path is configured to discharge the first end to the discharge end according to the signal of the first data line in a read state; the second sub-discharge path is configured to discharge the second end to the discharge end according to the discharge adjustment signal in a read state; the discharge adjustment unit is electrically connected to both the second sub-discharge path and the control signal, and is not electrically connected to the first sub-discharge path, and is configured to generate the discharge adjustment signal according to the control signal to adjust the discharge capacity of the second sub-discharge path. The present application improves the anti-interference ability and data transmission efficiency of the data transmission circuit.

Description

Technical Field

[0001] This application relates to the field of semiconductor memory technologies, and particularly to a data transmission circuit and a memory. Background Art

[0002] Semiconductor memory devices are typically arranged as large two-dimensional arrays composed of memory cells. The memory cells in each row can be selected by a row line (word line), and the memory cells in each column can be selected by a column line (bit line). The memory cells located at the intersection of the word line and the bit line are used to store corresponding information and are electrically connected to corresponding sense amplifiers. The sense amplifiers are used to read the information stored in the memory cells, amplify it, and then output it.

[0003] However, in traditional semiconductor memory devices, the data transmission circuit is affected by noise signals, resulting in the accuracy of the actually transmitted signal being lower than expected. Summary of the Invention

[0004] Based on this, a data transmission circuit and a memory with stronger anti-interference ability and higher data transmission efficiency are provided.

[0005] To achieve the above and other objectives, one aspect of this application provides a data transmission circuit, including a sense amplifier circuit, a first sub-discharge path, a second sub-discharge path, and a discharge adjustment unit. The sense amplifier circuit is used to generate an amplified signal according to the signals at its first end and second end; the first sub-discharge path is electrically connected to both the first end of the sense amplifier circuit and a first data line, and is used to discharge the first end to a discharge end according to the signal of the first data line in a read state; the second sub-discharge path is electrically connected to both the second end of the sense amplifier circuit and a discharge adjustment signal, and is used to discharge the second end to the discharge end according to the discharge adjustment signal in a read state; the discharge adjustment unit is electrically connected to both the second sub-discharge path and a control signal, and is not electrically connected to the first sub-discharge path, and is used to generate the discharge adjustment signal according to the control signal to adjust the discharge ability of the second sub-discharge path.

[0006] In the data transmission circuit in the above embodiment, by setting the discharge adjustment unit to be electrically connected to both the second sub-discharge path and the control signal, and not electrically connected to the first sub-discharge path, the discharge adjustment unit generates a discharge adjustment signal according to the control signal to adjust the discharge ability of the second sub-discharge path, improving the data transmission efficiency of the data transmission circuit and avoiding the influence of the impedance and noise signals provided by the circuit connected via the first data line and the first sub-discharge path on the sense amplifier circuit.

[0007] In one embodiment, the control signal includes a first sub-control signal, and the discharge regulation signal includes a first sub-discharge regulation signal; the discharge regulation unit includes a first sub-discharge regulation circuit, and the first sub-discharge regulation circuit is electrically connected to both the first sub-control signal and the first end of the second sub-discharge path, and is configured to provide the first sub-discharge regulation signal to the second sub-discharge path according to the first sub-control signal, regulate the discharge capacity of the second sub-discharge path, improve the data transmission efficiency of the data transmission circuit, and avoid the influence of the impedance and noise signals provided by the circuit connected to the first sub-discharge path via the first data line on the sense amplifier circuit.

[0008] In one embodiment, the control signal further includes a second sub-control signal, and the discharge regulation signal further includes a second sub-discharge regulation signal; the discharge regulation unit further includes a second sub-discharge regulation circuit, and the second sub-discharge regulation circuit is electrically connected to both the second sub-control signal and the second end of the second sub-discharge path, and is configured to provide the second sub-discharge regulation signal to the second sub-discharge path according to the second sub-control signal, cooperate with the first sub-discharge regulation signal to regulate the discharge capacity of the second sub-discharge path, improve the data transmission efficiency of the data transmission circuit, and avoid the influence of the impedance and noise signals provided by the circuit connected to the first sub-discharge path via the first data line on the sense amplifier circuit.

[0009] In one embodiment, the first sub-discharge regulation circuit includes a first transistor, a second transistor, and a first energy storage unit. The first transistor is configured such that: the source electrode is electrically connected to a first voltage, and the gate electrode is electrically connected to the first sub-control signal; the second transistor is configured such that: the source electrode is electrically connected to a second voltage, the drain electrode is electrically connected to both the drain electrode of the first transistor and the first end of the second sub-discharge path, and the gate electrode is electrically connected to the first sub-control signal; the first energy storage unit is electrically connected to both the drain electrode of the first transistor and the drain electrode of the second transistor. By providing the first energy storage unit to store the energy released by the first sub-discharge regulation circuit, the discharge efficiency of the first sub-discharge regulation circuit is improved, and the influence of the impedance and noise signals provided by the circuit connected to the first sub-discharge path via the first data line on the sense amplifier circuit is avoided.

[0010] In one embodiment, the second sub-discharge regulating circuit includes a third transistor, a fourth transistor, and a second energy storage unit. The third transistor is configured such that its source electrode is electrically connected to a first voltage, and its gate electrode is electrically connected to the second sub-control signal. The fourth transistor is configured such that its source electrode is electrically connected to a second voltage, its drain electrode is electrically connected to both the drain electrode of the third transistor and the second end of the second sub-discharge path, and its gate electrode is electrically connected to the second sub-control signal. The second energy storage unit is electrically connected to both the drain electrode of the third transistor and the drain electrode of the fourth transistor. By providing the second energy storage unit to store the energy released by the second sub-discharge regulating circuit, the discharge efficiency of the second sub-discharge regulating circuit is improved, and the influence of the impedance and noise signals provided by the circuit connected to the first data line and the first sub-discharge path on the sense amplifier circuit is avoided.

[0011] In one embodiment, the first energy storage unit includes a first MOS transistor and / or a capacitor. The first MOS transistor is configured such that its source electrode and drain electrode are both electrically connected to a first voltage node, and its gate electrode is electrically connected to the drain electrode of the first transistor, the drain electrode of the second transistor, and the first end of the second sub-discharge path. The capacitor is configured such that its first end is electrically connected to the first voltage node, and its second end is electrically connected to the drain electrode of the first transistor, the drain electrode of the second transistor, and the first end of the second sub-discharge path.

[0012] In one embodiment, the first voltage node is grounded; or the first voltage node is electrically connected to a first controllable voltage output unit. Wherein, the first controllable voltage output unit is configured to provide a controllable voltage to the first voltage node according to the received first sub-control signal to regulate the driving voltage of the sense amplifier circuit.

[0013] In one embodiment, the first controllable voltage output unit includes a first NOR gate. The first NOR gate is configured such that its output terminal is electrically connected to the first voltage node, its first input terminal is electrically connected to the first sub-control signal, and its second input terminal is electrically connected to both the first sub-discharge path and the second sub-discharge path.

[0014] In one embodiment, the sense amplifier circuit includes an amplification unit and an output circuit. The amplification unit is electrically connected to the discharge ends of the first sub-discharge path and the second sub-discharge path; the output circuit is electrically connected to the equalization signal, the first end of the sense amplifier circuit, the second end of the sense amplifier circuit, the second data line, and the second complementary data line; wherein, the sense amplifier circuit is configured to output the amplified signal to the second data line and the second complementary data line according to the equalization signal, the signal provided by the first sub-discharge path, and the signal provided by the second sub-discharge path, and the second data line and the second complementary data line transmit data that are inverted with respect to each other. The amplification unit amplifies the data read by it, and the output circuit is provided to output the amplified comparison result, thereby improving the noise immunity of the transmitted data.

[0015] In one embodiment, the sense amplifier circuit further includes a pre-charge module. The pre-charge module is electrically connected to the third end and the fourth end of the sense amplifier circuit and is configured to perform pre-charging.

[0016] In one embodiment, the output circuit further includes a first sub-output circuit and a second sub-output circuit. The first sub-output circuit is electrically connected to the second end of the sense amplifier circuit, the second data line, and the second complementary data line and is configured to output the amplified signal; the second sub-output circuit is electrically connected to the first end of the sense amplifier circuit, the second data line, and the second complementary data line and is configured to output the amplified signal and match the output load of the amplification unit.

[0017] In one embodiment, the output circuit further includes a first switch unit and a second switch unit. The first end of the sense amplifier circuit is electrically connected to the equalization signal via the first switch unit; the second end of the sense amplifier circuit is electrically connected to the equalization signal via the second switch unit.

[0018] In one embodiment, the data transmission circuit further includes a discharge end control circuit. The discharge end control circuit is electrically connected to the discharge ends of the first sub-discharge path and the second sub-discharge path and is configured to provide a driving voltage to the first sub-discharge path and the second sub-discharge path according to the received read enable signal and the complementary equalization signal to control the discharge capabilities of the first sub-discharge path and the second sub-discharge path, wherein the complementary equalization signal is an inverted signal of the equalization signal.

[0019] In one embodiment, the data transmission circuit further includes a write circuit. The write circuit is electrically connected to the second data line, the write enable signal, the equalization signal, and the first data line. The write circuit is configured to write data to the first data line according to the write enable signal and the equalization signal.

[0020] In one embodiment, the amplification unit includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The fifth transistor is configured such that its source is electrically connected to a third voltage. The sixth transistor is configured such that its source is electrically connected to a second voltage node and its drain is electrically connected to the drain of the fifth transistor. The seventh transistor is configured such that its source is electrically connected to the third voltage, its drain is electrically connected to the gate of the fifth transistor, and its gate is electrically connected to the drain of the fifth transistor. The eighth transistor is configured such that its source is electrically connected to a third voltage node, its drain is electrically connected to both the drain of the seventh transistor and the gate of the sixth transistor, and its gate is electrically connected to the drain of the fifth transistor. A latch is formed by arranging the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor. The latch can amplify and latch the data read via the first data line and then output it, so as to improve the noise immunity of the output data.

[0021] In one embodiment, the first sub-output circuit includes a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor. The ninth transistor is configured such that its source is electrically connected to a third voltage, its drain is electrically connected to a second complementary data line, and its gate is electrically connected to the drain of the seventh transistor. The tenth transistor is configured such that its drain is electrically connected to the drain of the ninth transistor, and its gate is electrically connected to both the drain of the seventh transistor and the gate of the ninth transistor. The eleventh transistor is configured such that its source is grounded, its drain is electrically connected to the source of the tenth transistor, and its gate is electrically connected to the second data line. The twelfth transistor is configured such that its source is electrically connected to the third voltage, its drain is electrically connected to both the second complementary data line and the drain of the ninth transistor, and its gate is electrically connected to the second data line.

[0022] In one embodiment, the second sub-output circuit includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor. The thirteenth transistor is configured such that: its source is electrically connected to a third voltage, its drain is electrically connected to the second data line, and its gate is electrically connected to the drain of the fifth transistor; the fourteenth transistor is configured such that: its drain is electrically connected to the drain of the thirteenth transistor, and its gate is electrically connected to both the drain of the fifth transistor and the gate of the thirteenth transistor; the fifteenth transistor is configured such that: its drain is electrically connected to the source of the fourteenth transistor, and its gate is electrically connected to the second complementary data line; the sixteenth transistor is configured such that: its source is grounded, its drain is electrically connected to the source of the fifteenth transistor, and its gate is electrically connected to a reset signal; the seventeenth transistor is configured such that: its source is electrically connected to the third voltage, its drain is electrically connected to the second data line, and its gate is electrically connected to both the second complementary data line and the gate of the fifteenth transistor; the eighteenth transistor is configured such that: its source is electrically connected to the third voltage, its drain is electrically connected to the second data line, and its gate is electrically connected to both the reset signal and the gate of the sixteenth transistor.

[0023] In one embodiment, the output circuit further includes a first inverter, a second NOR gate, a second inverter, and a third NOR gate. The first inverter is configured such that: its input terminal is electrically connected to the drain of the seventh transistor; the second NOR gate is configured such that: its first input terminal is electrically connected to the output terminal of the first inverter, its second input terminal is electrically connected to the second complementary data line, and its output terminal is electrically connected to the second data line; the second inverter is configured such that: its input terminal is electrically connected to the drain of the fifth transistor; the third NOR gate is configured such that: its first input terminal is electrically connected to the second data line, its second input terminal is electrically connected to the output terminal of the second inverter, and its output terminal is electrically connected to the second complementary data line. This embodiment can make the output loads at the first end and the second end of the sense amplifier circuit more balanced, so as to improve the sensitivity of the sense amplifier circuit.

[0024] In one embodiment, the write circuit includes a nineteenth transistor, a twentieth transistor, a fourth NOR gate, a fifth NOR gate, a first NAND gate, a first AND gate, and a third inverter. The nineteenth transistor is configured such that its source is electrically connected to a third voltage, and its drain is electrically connected to the first data line. The twentieth transistor is configured such that its source is grounded, and its drain is electrically connected to both the drain of the nineteenth transistor and the first data line. The fourth NOR gate is configured such that its output terminal is electrically connected to the gate of the nineteenth transistor. The fifth NOR gate is configured such that its output terminal is electrically connected to the gate of the twentieth transistor. The first NAND gate is configured such that its output terminal is electrically connected to the first input terminal of the fifth NOR gate. The first input terminal is electrically connected to the write enable signal, and the second input terminal is electrically connected to the equalization signal. The first AND gate is configured such that its output terminal is electrically connected to the second input terminal of the fourth NOR gate. The first input terminal is electrically connected to the write enable signal, and the second input terminal is electrically connected to both the second input terminal of the fifth NOR gate and the second data line. The third inverter is configured such that its output terminal is electrically connected to the first input terminal of the fourth NOR gate, and its input terminal is electrically connected to the equalization signal.

[0025] Another aspect of the present application provides a memory, including the data transmission circuit described in any embodiment of the present application, capable of controlling the discharge regulation of the second sub-discharge path through a control signal to adjust the discharge capacity, improve the data transmission efficiency of the data transmission circuit, and avoid the influence of the impedance and noise signals provided by the circuit connected to the first data line and the first sub-discharge path on the sense amplifier circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0027] Figure 1 It is a schematic circuit diagram of a data transmission circuit provided in the first embodiment of the present application;

[0028] Figure 2a It is a schematic circuit diagram of a data transmission circuit provided in the second embodiment of the present application;

[0029] Figure 2b It is a schematic circuit diagram of a data transmission circuit provided in the third embodiment of the present application;

[0030] Figure 2c For Figure 2a a circuit schematic diagram of

[0031] Figure 2d A Figure 2b schematic diagram of a circuit;

[0032] Figure 2e Another Figure 2a schematic diagram of a circuit;

[0033] Figure 2f Another Figure 2b schematic diagram of a circuit;

[0034] Figure 3 Schematic diagram of the circuit principle of a data transmission circuit provided in the fourth embodiment of the present application;

[0035] Figure 4a Schematic diagram of the circuit principle of a data transmission circuit provided in the fifth embodiment of the present application;

[0036] Figure 4b Schematic diagram of the circuit principle of a data transmission circuit provided in the sixth embodiment of the present application;

[0037] Figure 4c Schematic diagram of the circuit principle of a data transmission circuit provided in the seventh embodiment of the present application;

[0038] Figure 4d Schematic diagram of the circuit principle of a data transmission circuit provided in the eighth embodiment of the present application;

[0039] Figure 5a Partial circuit schematic diagram of a data transmission circuit provided in an embodiment of the present application;

[0040] Figure 5b Partial circuit schematic diagram of the output circuit in a data transmission circuit provided in an embodiment of the present application;

[0041] Figure 5c Partial circuit schematic diagram of the output circuit in a data transmission circuit provided in another embodiment of the present application;

[0042] Figure 5d Schematic diagram of the write circuit in a data transmission circuit provided in an embodiment of the present application;

[0043] Description of reference numerals:

[0044] 10. Sensing and amplifying circuit; 21. First sub-discharge path; 22. Second sub-discharge path; 30. Discharge adjustment unit; 31. First sub-discharge adjustment circuit; 32. Second sub-discharge adjustment circuit; 311. First energy storage unit; 321. Second energy storage unit; 312. First controllable voltage output unit; 322. Second controllable voltage output unit; 11. Amplifying unit; 12. Output circuit; 13. Pre-charging module; 121. First sub-output circuit; 122. Second sub-output circuit; 123. First switch unit; 124. Second switch unit; 23. Discharge terminal control circuit; 40. First data line; 50. Write circuit. Detailed implementation manners

[0045] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application. Additionally, certain terms used throughout the specification and the following claims refer to specific elements. Those skilled in the art will understand that manufacturers may use different names to refer to elements. This document does not intend to distinguish elements with different names but the same functions. In the following description and embodiments, the terms "comprising" and "including" are used in an open-ended manner and should thus be interpreted as "including, but not limited to...". Similarly, the term "connected" is intended to express an indirect or direct electrical connection. Accordingly, if a device is connected to another device, the connection can be accomplished through a direct electrical connection or through an indirect electrical connection via other devices and connectors.

[0047] It should be understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0048] As an example, please refer to Figure 1, in an embodiment of the present application, a data transmission circuit is provided, which includes a sense amplifier circuit 10, a first sub-discharge path 21, a second sub-discharge path 22, and a discharge adjustment unit 30. The sense amplifier circuit 10 is configured to generate an amplified signal based on the signals at its first terminal 1 and second terminal 2. The first sub-discharge path 21 is electrically connected to both the first terminal 1 of the sense amplifier circuit 10 and the first data line 40, and is used to discharge the first terminal 1 of the sense amplifier circuit 10 according to the signal of the first data line 40 in the read state. The second sub-discharge path 22 is electrically connected to both the second terminal 2 of the sense amplifier circuit 10 and the discharge adjustment signal YIO_REF, and is used to discharge the second terminal 2 of the sense amplifier circuit 10 according to the discharge adjustment signal YIO_REF in the read state. The discharge adjustment unit 30 is electrically connected to both the second sub-discharge path 22 and the control signal CM_SESA, and is not electrically connected to the first sub-discharge path 21, and is used to generate the discharge adjustment signal YIO_REF according to the control signal CM_SESA to adjust the discharge capacity of the second sub-discharge path 22.

[0049] Please continue to refer to Figure 1 , by setting that the discharge adjustment unit 30 is electrically connected to both the second sub-discharge path 22 and the control signal CM_SESA, and is not electrically connected to the first sub-discharge path 21, the discharge adjustment unit 30 generates the discharge adjustment signal YIO_REF according to the control signal CM_SESA to adjust the discharge capacity of the second sub-discharge path 22, improve the data transmission efficiency of the data transmission circuit, and avoid the influence of the impedance and noise signals provided by the circuit connected to the first data line 40 and the first sub-discharge path 21 on the sense amplifier circuit 10.

[0050] As an example, please refer to Figure 2a , in an embodiment of the present application, the control signal CM_SESA includes a first sub-control signal CM_SESA<0>, and the discharge adjustment signal YIO_REF includes a first sub-discharge adjustment signal YIO_REF<0>. The discharge adjustment unit 30 includes a first sub-discharge adjustment circuit 31. The first sub-discharge adjustment circuit 31 is electrically connected to both the first sub-control signal CM_SESA<0> and the first terminal 1 of the second sub-discharge path 22, and is used to provide the first sub-discharge adjustment signal YIO_REF<0> to the second sub-discharge path 22 according to the first sub-control signal CM_SESA<0> to adjust the discharge capacity of the second sub-discharge path 22, improve the data transmission efficiency of the data transmission circuit, and avoid the influence of the impedance and noise signals provided by the circuit connected to the first data line 40 and the first sub-discharge path 21 on the sense amplifier circuit 10.

[0051] As an example, please refer to Figure 2b, in an embodiment of the present application, the control signal CM_SESA further includes a second sub-control signal CM_SESA<1>, and the discharge regulation signal YIO_REF further includes a second sub-discharge regulation signal YIO_REF<1>; the discharge regulation unit 30 further includes a second sub-discharge regulation circuit 32, and the second sub-discharge regulation circuit 32 is electrically connected to both the second sub-control signal CM_SESA<1> and the second end 2 of the second sub-discharge path 22, and is configured to provide the second sub-discharge regulation signal YIO_REF<1> to the second sub-discharge path 22 according to the second sub-control signal CM_SESA<1>, cooperate with the first sub-discharge regulation signal YIO_REF<0> to adjust the discharge capacity of the second sub-discharge path 22, improve the data transmission efficiency of the data transmission circuit, and avoid the influence of the impedance and noise signals provided by the circuit connected to the first sub-discharge path 21 via the first data line 40 on the sense amplifier circuit 10.

[0052] As an example, please refer to Figure 2c , in an embodiment of the present application, the first sub-discharge regulation circuit 31 includes a first transistor M1, a second transistor M2, and a first energy storage unit 311. The first transistor M1 is configured such that: the source is electrically connected to the first voltage VCCZ, and the gate is electrically connected to the first sub-control signal CM_SESA<0>; the second transistor M2 is configured such that: the source is electrically connected to the second voltage VSSZ, the drain is electrically connected to both the drain of the first transistor M1 and the first end 1 of the second sub-discharge path 22, and the gate is electrically connected to the first sub-control signal CM_SESA<0>; the first energy storage unit 311 is electrically connected to both the drain of the first transistor M1 and the drain of the second transistor M2. By providing the first energy storage unit 311 to store the energy released by the first sub-discharge regulation circuit 31, the discharge efficiency of the first sub-discharge regulation circuit 31 is improved, and the influence of the impedance and noise signals provided by the circuit connected to the first sub-discharge path 21 via the first data line 40 on the sense amplifier circuit 10 is avoided.

[0053] As an example, please refer to Figure 2d, in an embodiment of the present application, the second sub-discharge adjustment circuit 32 includes a third transistor M3, a fourth transistor M4, and a second energy storage unit 321. The third transistor M3 is configured such that: the source is electrically connected to the first voltage VCCZ, and the gate is electrically connected to the second sub-control signal CM_SESA<1>; the fourth transistor M4 is configured such that: the source is electrically connected to the second voltage VSSZ, the drain is electrically connected to both the drain of the third transistor M3 and the second end 2 of the second sub-discharge path 22, and the gate is electrically connected to the second sub-control signal CM_SESA<1>; the second energy storage unit 321 is electrically connected to both the drain of the third transistor M3 and the drain of the fourth transistor M4. By providing the second energy storage unit 321 to store the energy released by the second sub-discharge adjustment circuit 32, the discharge efficiency of the second sub-discharge adjustment circuit 32 is improved, and the influence of the impedance and noise signals provided by the circuit connected to the first sub-discharge path 21 via the first data line 40 on the sense amplifier circuit 10 is avoided.

[0054] As an example, please refer to Figure 2e , in an embodiment of the present application, the first energy storage unit 311 includes a first MOS transistor MOS1, and the first MOS transistor MOS1 is configured such that: both the source and the drain are electrically connected to the first voltage node, and the gate is electrically connected to the drain of the first transistor M1, the drain of the second transistor M2, and the first end 1 of the second sub-discharge path 22.

[0055] As an example, please continue to refer to Figure 2e , in an embodiment of the present application, the first energy storage unit 311 includes a capacitor (not shown), and the capacitor is configured such that: the first end is electrically connected to the first voltage node I, and the second end is electrically connected to the drain of the first transistor M1, the drain of the second transistor M2, and the first end 1 of the second sub-discharge path 22.

[0056] As an example, please continue to refer to Figure 2e , in an embodiment of the present application, the first voltage node I is electrically connected to the first controllable voltage output unit 312; wherein, the first controllable voltage output unit 312 is used to provide a controllable voltage to the first voltage node according to the received first sub-control signal CM_SESA<0> to adjust the driving voltage of the first energy storage unit 311. In other embodiments of the present application, the first voltage node I can also be set to be grounded.

[0057] As an example, please refer to Figure 2f , in an embodiment of the present application, the first controllable voltage output unit 312 includes a first nor gate Nor1, and the first nor gate Nor1 is configured such that: the output end is electrically connected to the first voltage node I, the first input end is electrically connected to the first sub-control signal CM_SESA<0>, and the second input end is electrically connected to both the first sub-discharge path 21 and the second sub-discharge path 22.

[0058] As an example, please continue to refer to Figure 2f , in an embodiment of the present application, the second energy storage unit 321 includes a second MOS transistor MOS2, and the second MOS transistor MOS2 is configured such that: both the source and the drain are electrically connected to the voltage node N, and the gate is electrically connected to the drain of the third transistor M3, the drain of the fourth transistor M4, and the second end 2 of the second sub-discharge path 22. The voltage node N is electrically connected to the output end of the second controllable voltage output unit 322; wherein, the second controllable voltage output unit 322 is configured to provide a controllable voltage to the voltage node N according to the received second sub-control signal CM_SESA<1> to adjust the driving voltage of the second energy storage unit 321. It can be set that the second controllable voltage output unit 322 includes a NOR gate Nor2', and the NOR gate Nor2' is configured such that: the output end is electrically connected to the voltage node N, the first input end is electrically connected to the second sub-control signal CM_SESA<1>, and the second input end is electrically connected to both the first sub-discharge path 21 and the second sub-discharge path 22.

[0059] As an example, please refer to Figure 3 , in an embodiment of the present application, the sense amplifier circuit 10 includes an amplification unit 11 and an output circuit 12. The amplification unit 11 is electrically connected to both the first sub-discharge path 21 and the second sub-discharge path 22; the output circuit 12 is electrically connected to the equalization signal EQ, the first end 1 of the sense amplifier circuit 10, the second end 2 of the sense amplifier circuit 10, the second data line Data, and the second complementary data line Data_; wherein, the sense amplifier circuit 10 is configured to output amplified signals to the second data line Data and the second complementary data line Data_ according to the equalization signal EQ, the signal provided by the first sub-discharge path 21, and the signal provided by the second sub-discharge path 22, and the second data line Data and the second complementary data line Data_ transmit data that are inverted with each other. The amplification unit 11 amplifies the data read by it, and the output circuit 12 is set to output the amplified comparison result to improve the noise immunity of the transmitted data.

[0060] As an example, please refer to Figure 4a , in an embodiment of the present application, the sense amplifier circuit 10 further includes a pre-charge module 13. The pre-charge module 13 is electrically connected to both the third end 3 and the fourth end 4 of the sense amplifier circuit 10 and is used for pre-charging.

[0061] As an example, please refer to Figure 4b, in an embodiment of the present application, the output circuit 12 further includes a first sub-output circuit 121 and a second sub-output circuit 122. The first sub-output circuit 121 is electrically connected to the second terminal 2 of the sense amplifier circuit 10, the second data line Data, and the second complementary data line Data_, and is configured to output an amplified signal. The second sub-output circuit 122 is electrically connected to the first terminal 1 of the sense amplifier circuit 10, the second data line Data, and the second complementary data line Data_, and is configured to output an amplified signal and match the output load of the amplification unit 11.

[0062] As an example, please continue to refer to Figure 4b , in an embodiment of the present application, the output circuit 12 further includes a first switch unit 123 and a second switch unit 124. The first terminal 1 of the sense amplifier circuit 10 is electrically connected to the equalization signal via the first switch unit 123. The second terminal 2 of the sense amplifier circuit 10 is electrically connected to the equalization signal via the second switch unit 124.

[0063] As an example, please refer to Figure 4c , in an embodiment of the present application, the data transmission circuit further includes a discharge terminal control circuit 23. The discharge terminal control circuit 23 is electrically connected to the discharge terminals of the first sub-discharge path 21 and the second sub-discharge path 22, and is configured to provide a driving voltage to the first sub-discharge path 21 and the second sub-discharge path 22 according to the received read enable signal YIO_EN and the complementary equalization signal EQN to control the discharge capabilities of the first sub-discharge path 21 and the second sub-discharge path 22, where the complementary equalization signal EQN and the equalization signal EQ are anti-phase signals of each other.

[0064] As an example, please refer to Figure 4d , in an embodiment of the present application, the data transmission circuit further includes a write circuit 50. The write circuit 50 is electrically connected to the second data line Data, the write enable signal WrEn, the equalization signal EQ, and the first data line 40. The write circuit 50 is configured to write data to the first data line 40 according to the write enable signal WrEn and the equalization signal EQ.

[0065] As an example, please refer to Figure 5a, in an embodiment of the present application, the amplification unit 11 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The fifth transistor M5 is configured such that its source is electrically connected to the third voltage VCC; the sixth transistor M6 is configured such that its source is electrically connected to the second voltage node a, and its drain is electrically connected to the drain of the fifth transistor M5; the seventh transistor M7 is configured such that its source is electrically connected to the third voltage VCC, its drain is electrically connected to the gate of the fifth transistor M5, and its gate is electrically connected to the drain of the fifth transistor M5; the eighth transistor M8 is configured such that its source is electrically connected to the third voltage node b, its drain is electrically connected to both the drain of the seventh transistor M7 and the gate of the sixth transistor M6, and its gate is electrically connected to the drain of the fifth transistor M5. A latch is formed by arranging the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8. The latch can amplify and latch the data read via the first data line 40, such as the global data line YIO, and then output it to improve the noise immunity of the output data.

[0066] As an example, please continue to refer to Figure 5a , in an embodiment of the present application, the first sub-discharge path 21 includes a transistor Q1, a transistor Q2, a transistor Q3, and a transistor Q4. The transistor Q1 is configured such that its source is electrically connected to the fourth voltage node Com, its drain is electrically connected to the second voltage node a, and its gate is electrically connected to the global data line YIO; the transistor Q2 is configured such that its source is electrically connected to the fourth voltage node Com, its drain is electrically connected to the second voltage node a, and its gate is electrically connected to the global data line YIO; the transistor Q3 is configured such that its source is electrically connected to the fourth voltage node Com, its drain is electrically connected to the second voltage node a, and its gate is electrically connected to the global data line YIO; the transistor Q4 is configured such that its source is electrically connected to the fourth voltage node Com, its drain is electrically connected to the second voltage node a, and its gate is electrically connected to the global data line YIO. The second sub-discharge path 22 includes a transistor Q5, a transistor Q6, a transistor Q7, and a transistor Q8. The transistor Q5 is configured such that its source is electrically connected to the fourth voltage node Com, its drain is electrically connected to the third voltage node b, and its gate is electrically connected to the fourth voltage VSS; the transistor Q6 is configured such that its source is electrically connected to the fourth voltage node Com, its drain is electrically connected to the third voltage node b, and its gate is electrically connected to the third voltage VCC; the transistor Q7 is configured such that its source is electrically connected to the fourth voltage node Com, its drain is electrically connected to the third voltage node b, and its gate is electrically connected to the second sub-discharge adjustment signal YIO_REF<1>; the transistor Q8 is configured such that its source is electrically connected to the fourth voltage node Com, its drain is electrically connected to the third voltage node b, and its gate is electrically connected to the first sub-discharge adjustment signal YIO_REF<0>.

[0067] As an example, please continue to refer to Figure 5a, in an embodiment of the present application, the first switch unit 123 includes a transistor Q9, the second switch unit 124 includes a transistor Q10, and a first end 1 of the sense amplifier circuit 10 is electrically connected to the equalization signal EQ via the transistor Q9; a second end 2 of the sense amplifier circuit 10 is electrically connected to the equalization signal EQ via the transistor Q10.

[0068] As an example, please continue to refer to Figure 5a , in an embodiment of the present application, it may be set that the precharge module 13 includes a transistor Q11, a transistor Q12, and a transistor Q13. The transistor Q11 is configured such that: its source is electrically connected to the third voltage VCC, its drain is electrically connected to the drain of the fifth transistor M5, and its gate is electrically connected to the equalization signal EQ; the transistor Q12 is configured such that: its source is electrically connected to the third voltage VCC, its drain is electrically connected to the drain of the seventh transistor M7, and its gate is electrically connected to the equalization signal EQ; the transistor Q13 is configured such that: its source is electrically connected to the drain of the transistor Q12, its drain is electrically connected to the drain of the transistor Q13, and its gate is electrically connected to the equalization signal EQ.

[0069] As an example, please continue to refer to Figure 5a , in an embodiment of the present application, the discharge terminal control circuit 23 includes a NAND gate NAnd2, an inverter Inv4, and an inverter Inv5. The NAND gate NAnd2 is configured such that: its first input terminal is electrically connected to the read enable signal YIO_EN, and its second input terminal is electrically connected to the complementary equalization signal EQN; the input terminal of the inverter Inv4 is electrically connected to the output terminal of the NAND gate NAnd2; the input terminal of the inverter Inv5 is electrically connected to the output terminal of the inverter Inv4, and the output terminal of the inverter Inv5 is electrically connected to the fourth voltage node Com.

[0070] As an example, please refer to Figure 5b , in an embodiment of the present application, the first sub-output circuit 121 includes a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12. The ninth transistor M9 is configured such that: its source is electrically connected to the third voltage VCC, its drain is electrically connected to the second complementary data line Data_, and its gate is electrically connected to the drain of the seventh transistor M7; the tenth transistor M10 is configured such that: its drain is electrically connected to the drain of the ninth transistor M9, and its gate is electrically connected to both the drain of the seventh transistor M7 and the gate of the ninth transistor M9; the eleventh transistor M11 is configured such that: its source is grounded, its drain is electrically connected to the source of the tenth transistor M10, and its gate is electrically connected to the second data line Data; the twelfth transistor M12 is configured such that: its source is electrically connected to the third voltage VCC, its drain is electrically connected to both the second complementary data line Data_ and the drain of the ninth transistor M9, and its gate is electrically connected to the second data line Data.

[0071] As an example, please continue to refer toFigure 5b In one embodiment of the present application, the second sub-output circuit 122 includes a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, and an eighteenth transistor M18. The thirteenth transistor M13 is configured such that its source is electrically connected to the third voltage VCC, its drain is electrically connected to the second data line Data, and its gate is electrically connected to the drain of the fifth transistor M5. The fourteenth transistor M14 is configured such that its drain is electrically connected to the drain of the thirteenth transistor M13, and its gate is electrically connected to both the drain of the fifth transistor M5 and the gate of the thirteenth transistor M13. The fifteenth transistor M15 is configured such that its drain is electrically connected to the source of the fourteenth transistor M14, and its gate is electrically connected to the second complementary data line Data_. The sixteenth transistor M16 is configured such that its source is grounded, its drain is electrically connected to the source of the fifteenth transistor M15, and its gate is electrically connected to the reset signal Rst. The seventeenth transistor M17 is configured such that its source is electrically connected to the third voltage VCC, its drain is electrically connected to the second data line Data, and its gate is electrically connected to both the second complementary data line Data_ and the gate of the fifteenth transistor M15. The eighteenth transistor M18 is configured such that its source is electrically connected to the third voltage VCC, its drain is electrically connected to the second data line Data, and its gate is electrically connected to both the reset signal Rst and the gate of the sixteenth transistor M16. In this embodiment, the second data line Data can be set as the local data line LIO, and the second complementary data line Data_ can be set as the complementary local data line LIO_. Here, the local data line LIO and the complementary local data line LIO_ transmit data that are inverted with respect to each other.

[0072] As an example, please refer to Figure 5c In one embodiment of the present application, the output circuit further includes a first inverter Inv1, a second nor gate Nor2, a second inverter Inv2, and a third nor gate Nor3. The first inverter Inv1 is configured such that its input terminal is electrically connected to the drain of the seventh transistor M7. The second nor gate Nor2 is configured such that its first input terminal is electrically connected to the output terminal of the first inverter Inv1, its second input terminal is electrically connected to the second complementary data line Data_, and its output terminal is electrically connected to the second data line Data. The second inverter Inv2 is configured such that its input terminal is electrically connected to the drain of the fifth transistor M5. The third nor gate Nor3 is configured such that its first input terminal is electrically connected to the second data line Data, its second input terminal is electrically connected to the output terminal of the second inverter Inv2, and its output terminal is electrically connected to the second complementary data line Data_. This embodiment makes the output load of the first end 1 of the sense amplifier circuit 10 and the output load of the second end 2 of the sense amplifier circuit 10 more balanced, so as to improve the sensitivity of the sense amplifier circuit 10.

[0073] As an example, please refer to Figure 5d, in an embodiment of the present application, the write circuit 50 includes a nineteenth transistor M19, a twentieth transistor M20, a fourth NOR gate Nor4, a fifth NOR gate Nor5, a first NAND gate NAnd1, a first AND gate And1, and a third inverter Inv3. The nineteenth transistor M19 is configured such that its source is electrically connected to the third voltage VCC, and its drain is electrically connected to the first data line 40, for example, the global data line YIO. The twentieth transistor M20 is configured such that its source is grounded, and its drain is electrically connected to both the drain of the nineteenth transistor M19 and the first data line 40. The fourth NOR gate Nor4 is configured such that its output terminal is electrically connected to the gate of the nineteenth transistor M19. The fifth NOR gate Nor5 is configured such that its output terminal is electrically connected to the gate of the twentieth transistor M20. The first NAND gate NAnd1 is configured such that its output terminal is electrically connected to the first input terminal of the fifth NOR gate Nor5, its first input terminal is electrically connected to the write enable signal, and its second input terminal is electrically connected to the equalization signal. The first AND gate And1 is configured such that its output terminal is electrically connected to the second input terminal of the fourth NOR gate Nor4, its first input terminal is electrically connected to the write enable signal, and its second input terminal is electrically connected to both the second input terminal of the fifth NOR gate Nor5 and the second data line Data. The third inverter Inv3 is configured such that its output terminal is electrically connected to the first input terminal of the fourth NOR gate Nor4, and its input terminal is electrically connected to the equalization signal.

[0074] In an embodiment of the present application, a memory is provided, including the data transmission circuit in any embodiment of the present application, which can control the discharge regulation of the second sub-discharge path 22 through the control signal CM_SESA to adjust the discharge capacity, improve the data transmission efficiency of the data transmission circuit, and avoid the influence of the impedance and noise signals provided by the circuit connected to the first sub-discharge path 21 via the first data line 40 on the sense amplifier circuit 10.

[0075] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation to the present invention.

[0076] Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0077] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0078] The above-described embodiments merely represent several implementation manners of the present invention. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all fall within the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.

Claims

1. A data transmission circuit, characterized in that, Including: A sense amplifier circuit for generating an amplified signal based on the signals at its first terminal and second terminal; A first sub-discharge path electrically connected to both the first terminal and the first data line, for discharging the first terminal to a discharge terminal according to the signal on the first data line in a read state; A second sub-discharge path electrically connected to both the second terminal and a discharge adjustment signal, for discharging the second terminal to the discharge terminal according to the discharge adjustment signal in a read state; A discharge adjustment unit electrically connected to both the second sub-discharge path and a control signal, and not electrically connected to the first sub-discharge path, for generating the discharge adjustment signal according to the control signal to adjust the discharge capacity of the second sub-discharge path; The control signal includes a first sub-control signal, and the discharge adjustment signal includes a first sub-discharge adjustment signal; the discharge adjustment unit includes: A first sub-discharge adjustment circuit electrically connected to both the first sub-control signal and the first terminal of the second sub-discharge path, for providing the first sub-discharge adjustment signal to the second sub-discharge path according to the first sub-control signal; The first sub-discharge adjustment circuit includes: A first transistor configured such that its source is electrically connected to a first voltage, and its gate is electrically connected to the first sub-control signal; A second transistor configured such that its source is electrically connected to a second voltage, its drain is electrically connected to both the drain of the first transistor and the first terminal of the second sub-discharge path, and its gate is electrically connected to the first sub-control signal; A first energy storage unit electrically connected to both the drain of the first transistor and the drain of the second transistor.

2. The data transmission circuit according to claim 1, wherein The control signal further includes a second sub-control signal, and the discharge adjustment signal further includes a second sub-discharge adjustment signal; the discharge adjustment unit further includes: A second sub-discharge adjustment circuit electrically connected to both the second sub-control signal and the second terminal of the second sub-discharge path, for providing the second sub-discharge adjustment signal to the second sub-discharge path according to the second sub-control signal.

3. The data transmission circuit according to claim 2, wherein The second sub-discharge adjustment circuit includes: A third transistor configured such that its source is electrically connected to a first voltage, and its gate is electrically connected to the second sub-control signal; A fourth transistor configured such that its source is electrically connected to a second voltage, its drain is electrically connected to both the drain of the third transistor and the second terminal of the second sub-discharge path, and its gate is electrically connected to the second sub-control signal; A second energy storage unit electrically connected to both the drain of the third transistor and the drain of the fourth transistor.

4. The data transmission circuit according to claim 1, characterized in that The first energy storage unit includes: A first MOS transistor configured such that its source and drain are both electrically connected to a first voltage node, and its gate is electrically connected to the drain of the first transistor, the drain of the second transistor, and the first terminal of the second sub-discharge path; and / or A capacitor configured such that its first terminal is electrically connected to the first voltage node, and its second terminal is electrically connected to the drain of the first transistor, the drain of the second transistor, and the first terminal of the second sub-discharge path.

5. The data transmission circuit according to claim 4, wherein: The first voltage node is grounded; or The first voltage node is electrically connected to the first controllable voltage output unit; Wherein, the first controllable voltage output unit is configured to provide a controllable voltage to the first voltage node according to the received first sub-control signal.

6. The data transmission circuit according to claim 5, characterized in that The first controllable voltage output unit includes: A first NOR gate, configured such that: the output terminal is electrically connected to the first voltage node, the first input terminal is electrically connected to the first sub-control signal, and the second input terminal is electrically connected to the discharge terminals of both the first sub-discharge path and the second sub-discharge path.

7. The data transmission circuit according to any one of claims 1-2, characterized in that The sense amplifier circuit includes: An amplification unit, electrically connected to the discharge terminals of both the first sub-discharge path and the second sub-discharge path; An output circuit, electrically connected to the equalization signal, the first terminal of the sense amplifier circuit, the second terminal of the sense amplifier circuit, the second data line, and the second complementary data line; Wherein, the sense amplifier circuit is configured to output the amplified signal to the second data line and the second complementary data line according to the equalization signal, the signal provided by the first sub-discharge path, and the signal provided by the second sub-discharge path, and the second data line and the second complementary data line transmit data that are inverted with respect to each other.

8. The data transmission circuit according to claim 7, characterized in that The sense amplifier circuit further includes: A pre-charge module, electrically connected to the third terminal and the fourth terminal of the sense amplifier circuit, for pre-charging.

9. The data transmission circuit according to claim 8, characterized in that, The output circuit further includes: A first sub-output circuit, electrically connected to the second terminal of the sense amplifier circuit, the second data line, and the second complementary data line, for outputting the amplified signal; A second sub-output circuit, electrically connected to the first terminal of the sense amplifier circuit, the second data line, and the second complementary data line, for outputting the amplified signal and matching the output load of the amplification unit.

10. The data transmission circuit according to claim 9, characterized in that The output circuit further includes: A first switch unit, the first terminal of the sense amplifier circuit is electrically connected to the equalization signal via the first switch unit; A second switch unit, the second terminal of the sense amplifier circuit is electrically connected to the equalization signal via the second switch unit.

11. The data transmission circuit according to any one of claims 1-2, characterized in that, Further included: A discharge terminal control circuit, electrically connected to the discharge terminals of both the first sub-discharge path and the second sub-discharge path, for providing a drive voltage to the first sub-discharge path and the second sub-discharge path according to the received read enable signal and complementary equalization signal to control the discharge capabilities of the first sub-discharge path and the second sub-discharge path, wherein the complementary equalization signal and the equalization signal are signals that are inverted with respect to each other.

12. The data transmission circuit according to any one of claims 1-2, characterized in that, Further included is a write circuit, the write circuit is electrically connected to the second data line, the write enable signal, the equalization signal, and the first data line, and the write circuit is configured to write data to the first data line according to the write enable signal and the equalization signal.

13. The data transmission circuit according to claim 10, wherein The amplification unit includes: A fifth transistor, configured such that: the source is electrically connected to the third voltage; A sixth transistor, configured such that: the source is electrically connected to the second voltage node, and the drain is electrically connected to the drain of the fifth transistor; The seventh transistor is configured such that its source is electrically connected to the third voltage, its drain is electrically connected to the gate of the fifth transistor, and its gate is electrically connected to the drain of the fifth transistor; The eighth transistor is configured such that its source is electrically connected to the third voltage node, its drain is electrically connected to both the drain of the seventh transistor and the gate of the sixth transistor, and its gate is electrically connected to the drain of the fifth transistor.

14. The data transmission circuit according to claim 13, wherein The first sub-output circuit includes: The ninth transistor is configured such that its source is electrically connected to the third voltage, its drain is electrically connected to the second complementary data line, and its gate is electrically connected to the drain of the seventh transistor; The tenth transistor is configured such that its drain is electrically connected to the drain of the ninth transistor, and its gate is electrically connected to both the drain of the seventh transistor and the gate of the ninth transistor; The eleventh transistor is configured such that its source is grounded, its drain is electrically connected to the source of the tenth transistor, and its gate is electrically connected to the second data line; The twelfth transistor is configured such that its source is electrically connected to the third voltage, its drain is electrically connected to both the second complementary data line and the drain of the ninth transistor, and its gate is electrically connected to the second data line.

15. The data transmission circuit according to claim 14, wherein The second sub-output circuit includes: The thirteenth transistor is configured such that its source is electrically connected to the third voltage, its drain is electrically connected to the second data line, and its gate is electrically connected to the drain of the fifth transistor; The fourteenth transistor is configured such that its drain is electrically connected to the drain of the thirteenth transistor, and its gate is electrically connected to both the drain of the fifth transistor and the gate of the thirteenth transistor; The fifteenth transistor is configured such that its drain is electrically connected to the source of the fourteenth transistor, and its gate is electrically connected to the second complementary data line; The sixteenth transistor is configured such that its source is grounded, its drain is electrically connected to the source of the fifteenth transistor, and its gate is electrically connected to the reset signal; The seventeenth transistor is configured such that its source is electrically connected to the third voltage, its drain is electrically connected to the second data line, and its gate is electrically connected to both the second complementary data line and the gate of the fifteenth transistor; The eighteenth transistor is configured such that its source is electrically connected to the third voltage, its drain is electrically connected to the second data line, and its gate is electrically connected to both the reset signal and the gate of the sixteenth transistor.

16. The data transmission circuit according to claim 13, wherein The output circuit further includes: The first inverter is configured such that its input terminal is electrically connected to the drain of the seventh transistor; The second NOR gate is configured such that its first input terminal is electrically connected to the output terminal of the first inverter, its second input terminal is electrically connected to the second complementary data line, and its output terminal is electrically connected to the second data line; The second inverter is configured such that its input terminal is electrically connected to the drain of the fifth transistor; The third NOR gate is configured such that its first input terminal is electrically connected to the second data line, its second input terminal is electrically connected to the output terminal of the second inverter, and its output terminal is electrically connected to the second complementary data line.

17. The data transmission circuit according to claim 12, wherein The write circuit includes: The nineteenth transistor is configured such that its source is electrically connected to the third voltage, and its drain is electrically connected to the first data line; The twentieth transistor is configured such that its source is grounded, and its drain is electrically connected to the drain of the nineteenth transistor and the first data line; The fourth NOR gate is configured such that its output terminal is electrically connected to the gate of the nineteenth transistor; The fifth NOR gate is configured such that its output terminal is electrically connected to the gate of the twentieth transistor; The first NAND gate is configured such that its output terminal is electrically connected to the first input terminal of the fifth NOR gate, its first input terminal is electrically connected to the write enable signal, and its second input terminal is electrically connected to the equalization signal; The first AND gate is configured such that its output terminal is electrically connected to the second input terminal of the fourth NOR gate, its first input terminal is electrically connected to the write enable signal, and its second input terminal is electrically connected to the second input terminal of the fifth NOR gate and the second data line; The third inverter is configured such that its output terminal is electrically connected to the first input terminal of the fourth NOR gate, and its input terminal is electrically connected to the equalization signal.

18. A memory, characterized in that, Comprising the data transmission circuit according to any one of claims 1-17.

Images