Semiconductor device and method for manufacturing the same

Abstract

Embodiments relate to a semiconductor device and a manufacturing method thereof. The semiconductor device of the embodiments includes a semiconductor portion, first to third electrodes, and first and second control electrodes. The semiconductor portion is provided between the first and second electrodes and has first and second trenches on the second electrode side. The first and second control electrodes are provided in the first and second trenches, respectively, and the third electrode is provided in the first trench. The first control electrode is positioned between the second electrode and the third electrode. First and second insulating portions are provided on both sides of the third electrode in a first direction from the first control electrode toward the second control electrode, and a gate insulating film is provided on both sides of the first control electrode. A first width obtained by adding the widths of the first and second insulating portions and the third electrode in the first direction is wider than a second width obtained by adding the widths of the first control electrode and the gate insulating film in the first direction.

Description

[0001] This application claims priority based on Japanese Patent Application No. 2021-133192 (filed on August 18, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] The implementation methods relate to semiconductor devices and methods of manufacturing the same. Background Technology

[0003] Semiconductor devices used in power control are required to reduce on-resistance. For example, in a MOS transistor with a trench gate structure, it is preferable to increase the gate channel density by narrowing the spacing between the gate electrodes. This reduces the channel resistance and thus the on-resistance. Summary of the Invention

[0004] The embodiments provide a semiconductor device capable of high-density gate channels and a method for manufacturing the same.

[0005] The semiconductor device according to the embodiment includes a semiconductor portion, first to third electrodes, and first and second control electrodes. The semiconductor portion includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a third semiconductor layer of the first conductivity type. The first electrode is disposed on the back side of the semiconductor portion, and the second electrode is disposed on the surface side of the semiconductor portion. The third electrode is disposed in a first trench disposed on the surface side of the semiconductor portion, located between the first electrode and the second electrode, and electrically insulated from the semiconductor portion by a first insulating film. The first control electrode is disposed in the first trench, located between the second electrode and the third electrode, and electrically insulated from the third electrode by a second insulating film, electrically insulated from the second electrode by a third insulating film, and electrically insulated from the semiconductor portion by a fourth insulating film. The second control electrode is disposed on the surface side of the semiconductor portion in a second trench adjacent to the first trench, and electrically insulated from the semiconductor portion by a fifth insulating film. The first semiconductor layer extends between the first electrode and the second electrode. The second semiconductor layer is disposed between the first semiconductor layer and the second electrode, facing the first control electrode through the fourth insulating film, and facing the second control electrode through the fifth insulating film. The third semiconductor layer is partially disposed between the second semiconductor layer and the second electrode. The second electrode is electrically connected to the second semiconductor layer and the third semiconductor layer. The first trench and the second trench extend from the surface of the semiconductor portion into the first semiconductor layer, and the spacing between the first trench and the first electrode is narrower than the spacing between the second trench and the first electrode. The third electrode in the first trench faces the first semiconductor layer through the first insulating film. In a first direction from the first control electrode toward the second control electrode, the first insulating film includes a first portion and a second portion respectively disposed on both sides of the third electrode, and the fourth insulating film includes a first portion and a second portion respectively disposed on both sides of the first control electrode in the first direction. The first width obtained by adding the widths of the first portion, the second portion, and the third electrode in the first direction of the first insulating film is wider than the second width obtained by adding the widths of the first portion, the second portion, and the first control electrode in the first direction of the fourth insulating film. Attached Figure Description

[0006] Figure 1 This is a schematic cross-sectional view showing the semiconductor device involved in the implementation.

[0007] Figure 2 (a) and Figure 2(b) is a schematic diagram showing the semiconductor device involved in the embodiment.

[0008] Figure 3 (a)~ Figure 12 (b) is a schematic cross-sectional view showing the manufacturing process of the semiconductor device involved in the embodiment.

[0009] Figure 13 This is a schematic cross-sectional view of a semiconductor device involved in a variation of the implementation. Detailed Implementation

[0010] Hereinafter, the embodiments will be described with reference to the accompanying drawings. The same reference numerals will be used for the same parts in the drawings, and detailed descriptions will be omitted where appropriate; different parts will be described. Note that the drawings are schematic or conceptual, and are not limited to the fact that the relationship between the thickness and width of each part, or the ratio of the sizes between parts, must be the same as in reality. Furthermore, even when representing the same parts, there may be cases where the dimensions and ratios are shown differently depending on the accompanying drawings.

[0011] Furthermore, the X, Y, and Z axes shown in each figure are used to explain the configuration and structure of each part. The X, Y, and Z axes are orthogonal to each other, representing the X, Y, and Z directions, respectively. Sometimes, the Z direction is used as the top and its opposite as the bottom for illustration.

[0012] Figure 1 This is a schematic cross-sectional view showing the semiconductor device 1 according to the embodiment. The semiconductor device 1 is a MOS transistor having a trench gate structure.

[0013] Semiconductor device 1 includes a semiconductor section 10, a first electrode 20, a second electrode 30, a third electrode 40, a first control electrode 50, and a second control electrode 60. The semiconductor section 10 is, for example, silicon.

[0014] A first electrode 20 is disposed on the back side of the semiconductor section 10. The first electrode 20 is, for example, a drain electrode. The first electrode 20 is, for example, a metal layer including aluminum (Al), nickel (Ni), etc.

[0015] A second electrode 30 is disposed on the surface side of the semiconductor portion 10. The second electrode 30 is, for example, a source electrode. The second electrode 30 includes, for example, a first metal layer 33 and a second metal layer 35. The first metal layer 33 is disposed between the semiconductor portion 10 and the second metal layer 35.

[0016] The first metal layer 33 has, for example, a stacked structure comprising titanium nitride (TiN) and tungsten (W) (not shown). The titanium nitride layer is disposed between the semiconductor portion 10 and the tungsten layer. The second metal layer 35 comprises, for example, aluminum.

[0017] The semiconductor section 10 includes a first trench TR1 and a second trench TR2. The first trench TR1 and the second trench TR2 are disposed on the surface side of the semiconductor section 10 facing the second electrode 30. The first trench TR1 and the second trench TR2 are disposed in adjacent positions. The distance between the first trench TR1 and the first electrode 20 is shorter than the distance between the second trench TR2 and the first electrode 20.

[0018] The third electrode 40 and the first control electrode 50 are disposed inside the first trench TR1. The first control electrode 50 is disposed between the second electrode 30 and the third electrode 40. The third electrode 40 is, for example, a field plate electrically connected to the second electrode 30. The first control electrode 50 is, for example, a gate electrode. The third electrode 40 and the first control electrode 50 are, for example, polycrystalline silicon with conductivity.

[0019] The third electrode 40 is electrically insulated from the semiconductor section 10 through the first insulating film 43. The first control electrode 50 is electrically insulated from the third electrode 40 through the second insulating film 45. Furthermore, the first control electrode 50 is electrically insulated from the second electrode 30 through the third insulating film 53. Additionally, the first control electrode 50 is electrically insulated from the semiconductor section 10 through a fourth insulating film 55. The fourth insulating film 55 is, for example, a gate insulating film. The first insulating film 43, the second insulating film 45, the third insulating film 53, and the fourth insulating film 55 are, for example, silicon oxide films.

[0020] The second control electrode 60 is disposed inside the second trench TR2. The second control electrode 60 is disposed between the semiconductor portion 10 and the second electrode 30. The second control electrode 60 is electrically insulated from the semiconductor portion 10 by a fifth insulating film 65. The second control electrode 60 is electrically insulated from the second electrode by another third insulating film 53. The second control electrode 60 is, for example, a gate electrode. The third electrode 40 is not disposed inside the second trench TR2. The second control electrode 60 is, for example, conductive polysilicon. The fifth insulating film 65 is, for example, a silicon oxide film.

[0021] The semiconductor section 10 includes, for example, a first semiconductor layer 11 of a first conductivity type, a second semiconductor layer 13 of a second conductivity type, a third semiconductor layer 15 of a first conductivity type, and a fourth semiconductor layer 17 of a first conductivity type. Hereinafter, the first conductivity type will be described as n-type and the second conductivity type as p-type.

[0022] The first semiconductor layer 11 extends between the first electrode 20 and the second electrode 30. The first semiconductor layer 11 is, for example, an n-type drift layer. The first trench TR1 and the second trench TR2 extend from the surface of the semiconductor portion 10 opposite to the second electrode 30 into the first semiconductor layer 11.

[0023] A second semiconductor layer 13 is disposed between the first semiconductor layer 11 and the second electrode 30. Alternatively, the second semiconductor layer 13 is disposed between the first trench TR1 and the second trench TR2. The second semiconductor layer 13 is, for example, a p-type diffusion layer. The second semiconductor layer 13 is opposite to the first control electrode 50 through a fourth insulating film 55. Alternatively, the second semiconductor layer 13 is opposite to the second control electrode 60 through a fifth insulating film 65.

[0024] A third semiconductor layer 15 is disposed between the second semiconductor layer 13 and the second electrode 30. Alternatively, the third semiconductor layer 15 is disposed between the first trench TR1 and the second trench TR2. The third semiconductor layer 15 is, for example, an n-type source layer. The third semiconductor layer 15 includes a portion that is in contact with the fourth insulating film 55 and a portion that is in contact with the fifth insulating film 65.

[0025] A fourth semiconductor layer 17 is disposed between the first electrode 20 and the first semiconductor layer 11. The fourth semiconductor layer 17 is, for example, an n-type drain layer. The fourth semiconductor layer 17 includes a first conductivity type impurity with a higher concentration than the first conductivity type impurity in the first semiconductor layer 11, and is electrically connected to the first electrode 20.

[0026] like Figure 1 As shown, the first metal layer 33 of the second electrode 30 has, for example, a contact portion 33c extending from the surface of the third insulating film 53 into the third semiconductor layer 15. The second electrode 30 is electrically connected to the second semiconductor layer 13 and the third semiconductor layer 15 via the contact portion 33c.

[0027] In the semiconductor device 1 according to the embodiment, the third electrode 40 is embedded in the first semiconductor layer 11 and electrically insulated from the first semiconductor layer 11 by a first insulating film 43. For example, in a first direction (X direction) from the first control electrode 50 toward the second control electrode 60, the first insulating film 43 includes portions located on both sides of the third electrode 40.

[0028] The first width WF, obtained by adding the portions of the first insulating film 43 disposed on both sides of the third electrode 40 and the width of each of the third electrode 40 in the X direction, is wider than the second width WG, obtained by adding the widths of the first control electrode 50 and the fourth insulating film 55 disposed on both sides of the first control electrode 50 in the X direction.

[0029] like Figure 1 As shown, the third electrode 40 has, for example, a rectangular cross-section, a constant width in the X direction, and extends along the Z direction. The first width WF of the third electrode 40 at its upper end, which is opposite to the first control electrode 50 and separated by the second insulating film 45, is the same as the first width WF at its lower end, which is opposite to the first electrode 20 and separated by the first semiconductor layer 11 and the fourth semiconductor layer 17.

[0030] The implementation is not limited to this example; the third electrode 40 may also have a tapered cross-section with a decreasing width in the X direction (-Z direction) from the second electrode 30 toward the first electrode 20. In other words, the third electrode 40 has its widest first width WF at least at the end opposite the first control electrode 50, separated by the second insulating film 45.

[0031] Others, such as Figure 1 As shown, the semiconductor section 10 also has another first trench TR1 adjacent to the second trench TR2. The second trench TR2 is disposed between the first trench TR1 and the other first trench TR1. Other third electrodes 40 and other first control electrodes 50 are disposed inside the other first trench TR1.

[0032] The first semiconductor layer 11 includes a first region 11a disposed between the first trench TR1 and other first trenches TR1. A second control electrode 60 is disposed between the first region 11a of the first semiconductor layer 11 and the second electrode 30. The width of the first region 11a in the X direction is wider than the width of the second control electrode 60 in the X direction.

[0033] For example, if the voltage applied between the first electrode 20 and the second electrode 30 becomes higher, it requires an increase in the insulation withstand voltage between the first semiconductor layer 11 and the third electrode 40. Therefore, it is preferable to increase the thickness of the first insulating film 43.

[0034] On the other hand, if the spacing between adjacent first control electrodes is narrowed to increase the gate channel density, the spacing between adjacent third electrodes 40 becomes narrower. Therefore, the first region 11a of the first semiconductor layer 11 becomes narrower, narrowing the path of current flowing between the first electrode 20 and the second electrode 30 via the first region 11a, resulting in increased on-resistance. If the thickness of the first insulating film 43 is increased, the width of the first region 11a in the X direction becomes further narrower, leading to an increase in on-resistance.

[0035] In the semiconductor device 1 according to the embodiment, by providing a second control electrode 60 between adjacent first control electrodes 50, the gate channel density can be increased and the channel resistance reduced without narrowing the spacing between adjacent third electrodes 40.

[0036] Others, such as Figure 1 As shown, the second insulating film 45 includes a first portion having a first width WF and a second portion having a second width WG. In the second insulating film 45, the first portion is configured to be continuously connected to the second portion. The boundary line between the first portion and the second portion in the second insulating film 45 is located in the Z direction at a horizontal plane lower than the horizontal plane of the bottom surface of the trench TR2. As a result, the spacing between the trench TR1 and the trench TR2 becomes wider, which can reduce the channel resistance.

[0037] Furthermore, in this embodiment, the first width WF in the first trench TR1 is controlled such that the width of the first region 11a of the first semiconductor layer 11 in the X direction is wider than the width of the second control electrode 60 in the X direction. This prevents an increase in the on-resistance of the semiconductor device 1.

[0038] Furthermore, the second control electrode 60 involved in the implementation is not limited to the example described above. For example, multiple second control electrodes 60 may be provided between adjacent first control electrodes 50.

[0039] Figure 2 (a) and Figure 2 (b) is a schematic cross-sectional view of the semiconductor device 1 according to the embodiment. Figure 2 (a) is a top view showing the surface side of semiconductor device 1. Figure 2 (b) is along Figure 2 A cross-sectional view of line AA shown in (a).

[0040] like Figure 2 As shown in (a), the semiconductor device 1 further includes control pads 70 and control wiring 70e. The control pads 70 and control wiring 70e are disposed on the surface side of the semiconductor portion 10, for example, via a third insulating film 53. The control pads 70 and control wiring 70e are electrically insulated from the semiconductor portion 10 by the third insulating film 53. Furthermore, the control pads 70 and control wiring 70e are configured to be separate from the second electrode 30 and electrically insulated from the second electrode 30.

[0041] Control wiring 70e is connected to control pad 70. Control wiring 70e is configured to extend from control pad 70 along second electrode 30. Second electrode 30 has, for example, an extension 30e extending along the outer edge of semiconductor portion 10. Control wiring 70e extends between the main portion of second electrode 30 and extension 30e.

[0042] like Figure 2 As shown in (b), the control wiring 70e has the same stacked structure as the second electrode 30. The control wiring 70e is electrically connected to the first control electrode 50 via a contact portion 70g extending into the third insulating film 53. The control wiring 70e is also electrically connected to the second control electrode 60 in the same way.

[0043] The extension 30e of the second electrode 30 is electrically connected to the third electrode 40 via a contact portion 30f extending into the third insulating film 53. In other words, the second electrode 30 is electrically connected to the third electrode 40 via the extension 30e having the contact portion 30f.

[0044] Next, refer to Figure 3 (a)~ Figure 12 (b) describes the manufacturing method of semiconductor device 1. Figure 3 (a)~ Figure 12 (b) is a schematic cross-sectional view showing the manufacturing process of the semiconductor device 1 according to the embodiment.

[0045] like Figure 3 As shown in (a), a first trench TR1 is formed on the surface side of the semiconductor wafer 100. The first trench TR1 is formed by selectively etching the semiconductor wafer using the insulating film 101 as a mask after forming an insulating film 101 on the surface of the semiconductor wafer 100. A plurality of first trenches TR1 are provided along the surface of the semiconductor wafer 100.

[0046] Semiconductor wafer 100 is, for example, a silicon wafer of a first conductivity type. Semiconductor wafer 100 has, for example, a structure in which a first semiconductor layer 11 is epitaxially grown on a substrate (not shown) of the first conductivity type, which becomes a fourth semiconductor layer 17. Insulating film 101 is, for example, a silicon oxide film. Insulating film 101 is formed, for example, by thermal oxidation of semiconductor wafer 100. Semiconductor wafer 100 is etched, for example, using anisotropic RIE (Reactive Ion Etching).

[0047] like Figure 3 As shown in (b), insulating films 103, 105, and 107 are formed in the residual space inside the first trench TR1. Insulating films 103, 105, and 107 cover the inner surface of the first trench TR1. Insulating film 103 is, for example, a silicon oxide film, formed by thermal oxidation of the semiconductor wafer 100 exposed on the inner surface of the first trench TR1. Insulating film 105 is, for example, a silicon nitride film. Insulating film 107 is, for example, a silicon oxide film. Insulating films 105 and 107 are deposited on the surface side of the semiconductor wafer 100, for example, using CVD (Chemical Vapor Deposition).

[0048] like Figure 4 As shown in (a), insulating films 103, 105, and 107 are selectively removed. For example, anisotropic RIE is used to selectively remove portions of insulating films 103, 105, and 107 formed on the bottom surface of the first trench TR1, exposing a portion of the semiconductor wafer 100. At this time, portions of insulating films 105 and 107 formed on insulating film 101 are also removed.

[0049] like Figure 4As shown in (b), the first trench TR1 extends along its depth direction (-Z direction) by etching the semiconductor wafer 100 exposed on the bottom surface of the first trench TR1. For example, an anisotropic RIE is used to etch the semiconductor wafer 100.

[0050] like Figure 5 As shown in (a), the semiconductor wafer 100 is etched at the extension Tre of the first trench TR1, expanding the extension Tre. For example, CDE (Chemical Dry Etching) is used to isotropically etch the semiconductor wafer 100.

[0051] Among them, through Figure 4 (b) and Figure 5 In the process shown in (a), insulating films 101, 103, 105 and 107 function as anti-etching films.

[0052] like Figure 5 As shown in (b), a first insulating film 43 is formed to cover the inner surface of the extension portion TRe of the first trench TR1. The first insulating film 43 is formed to leave a desired space inside the extension portion TRe. The first insulating film 43 is, for example, a silicon oxide film. The first insulating film 43 is formed by thermal oxidation of the semiconductor wafer 100 exposed on the inner surface of the extension portion TRe of the first trench TR1.

[0053] By forming the first insulating film 43, the extended portion Tre of the first trench TR1 has a further expanded first width WF. Furthermore, the insulating film 105 inhibits thermal oxidation of the upper portion of the first trench TR1. As a result, the first width WF becomes wider than the width WI of the upper portion of the first trench TR1. The insulating film 107 is removed in a wet process prior to the formation of the first insulating film 43.

[0054] like Figure 6 As shown in (a), a conductive film 110 is formed on the surface side of the semiconductor wafer 100. The interior of the first trench TR1 is filled with the conductive film 110. The conductive film 110 is, for example, polycrystalline silicon with conductivity. For example, the conductive film 110 is formed using CVD.

[0055] like Figure 6 As shown in (b), the conductive film 110 is removed by leaving a portion of the extension Tre of the first trench TR1 buried within it. The portion of the extension Tre of the conductive film 110 buried within it becomes an electrode (third electrode 40) embedded in the first semiconductor layer 11. For example, the conductive film 110 is removed by wet etching. In this process, the insulating film 105 is removed together with the conductive film 110.

[0056] like Figure 7 As shown in (a), an insulating film 113 is formed on the surface side of the semiconductor wafer 100. The space in the first trench TR1 after the removal of the conductive film 110 is filled by the insulating film 113. The insulating film 113 is, for example, a silicon oxide film formed using CVD.

[0057] like Figure 7 As shown in (b), a second trench TR2 is formed between adjacent first trenches TR1. The second trench TR2 is formed, for example, by using an anisotropic RIE of the etch mask 115. The second trench TR2 is formed, for example, to extend from the surface of the insulating film 113 into the semiconductor wafer 100. The second trench TR2 is formed such that its bottom surface is located, for example, above the upper end of the third electrode 40 in the Z direction.

[0058] like Figure 8 As shown in (a), an insulating film 117 is formed on the surface side of the semiconductor wafer 100. The second trench TR2 is filled by the insulating film 117. The insulating film 117 is, for example, a silicon oxide film formed using CVD.

[0059] like Figure 8 As shown in (b), the insulating films 113 and 117 are removed by leaving the portion that filled the first trench TR1 and the second trench TR2. The insulating films 113 and 117 are removed, for example, by CMP (Chemical Mechanical Polishing) and wet etching.

[0060] like Figure 9 As shown in (a), a second semiconductor layer 13 is formed on the surface side of the semiconductor wafer 100. The second semiconductor layer 13 is formed, for example, by ion implantation of a second conductivity type impurity such as boron (B) into the surface side of the semiconductor wafer 100. The second conductivity type impurity ion implanted into the semiconductor wafer 100 is activated and diffused by heat treatment. The second semiconductor layer 13 is configured such that the boundary line between the first semiconductor layer 11 and the second semiconductor layer 13 is located at a horizontal plane shallower than the bottom surface of the second trench TR2.

[0061] like Figure 9 As shown in (b), the second semiconductor layer 13 is exposed by removing insulating films 101, 103, 113, and 117. A portion of each of the insulating films 103 and 113 remains in the first trench TR1. The insulating film 117 formed inside the second trench TR2 is completely removed.

[0062] like Figure 10As shown in (a), a fourth insulating film 55 and a fifth insulating film 65 are formed inside the first trench TR1 and the second trench TR2, respectively. The fourth insulating film 55 and the fifth insulating film 65 are formed by thermal oxidation of the exposed portion of the semiconductor wafer 100. The fourth insulating film 55 and the fifth insulating film 65 are, for example, silicon oxide films.

[0063] like Figure 10 As shown in (b), a conductive film 120 is formed on the surface side of the semiconductor wafer 100. A first trench TR1 and a second trench TR2 are filled with the conductive film 120. The conductive film 120 is, for example, polycrystalline silicon with conductive properties. For example, the conductive film 120 is formed using CVD.

[0064] like Figure 11 As shown in (a), a first control electrode 50 and a second control electrode 60 are formed inside the first trench TR1 and the second trench TR2, respectively. The first control electrode 50 and the second control electrode 60 retain portions of the conductive film 120 (refer to) formed inside the first trench TR1 and the second trench TR2. Figure 10 (b) is removed to form the conductive film 120, for example, by isotropic etching via CDE.

[0065] like Figure 11 As shown in (b), a third semiconductor layer 15 is formed on the surface side of the semiconductor wafer 100. The third semiconductor layer 15 is formed, for example, by ion implantation of a first conductivity type impurity such as phosphorus (P). The ion-implanted first conductivity type impurity is activated by heat treatment. The third semiconductor layer 15 is formed on the second semiconductor layer 13.

[0066] like Figure 12 As shown in (a), a third insulating film 53 is formed on the first control electrode 50 and the second control electrode 60. The third insulating film 53 is, for example, a silicon oxide film. For example, the third insulating film 53 is formed on the surface side of the semiconductor wafer 100 using CVD.

[0067] Furthermore, a contact trench CT is formed that connects the surface of the third insulating film 53 to the second semiconductor layer 13. For example, an anisotropic RIE is used to form the contact trench CT.

[0068] like Figure 12 As shown in (b), a second electrode 30 is formed on the surface side of the semiconductor wafer 100. The second electrode 30 is formed by sequentially depositing a first metal layer 33 and a second metal layer 35 on a third insulating film 53. The first metal layer 33 has, for example, a stacked structure comprising titanium nitride (TiN) and tungsten (W). The first metal layer 33 is formed, for example, using sputtering and CVD. The second metal layer 35 comprises, for example, aluminum (Al) and is formed using sputtering.

[0069] The contact trench CT is filled with a first metal layer 33. The portion of the first metal layer 33 extending into the interior of the contact trench CT is electrically connected, for example, to a second semiconductor layer 13 and a third semiconductor layer 15.

[0070] Furthermore, the back side of the semiconductor wafer 100 is thinned to a predetermined wafer thickness by, for example, grinding or polishing. Then, a first electrode 20 is formed on the back side of the semiconductor wafer 100, completing the semiconductor device 1. The first electrode 20 has, for example, a stacked structure including nickel (Ni) and aluminum (Al). For example, the first electrode 20 is formed using a sputtering method.

[0071] Figure 13 This is a partial cross-sectional view schematically illustrating a modified embodiment of the semiconductor device 2. In the semiconductor device 2, a third electrode 40 and a first control electrode 50 are also disposed inside the first trench TR1. A second control electrode 60 is disposed inside the second trench TR2. The third electrode 40 is not disposed inside the second trench TR2.

[0072] In the first trench TR1, the first width WF obtained by adding the widths of the third electrode 40 and the portions of the first insulating film 43 located on both sides of it in the X direction is wider than the second width WG obtained by adding the widths of the first control electrode 50 and the fourth insulating film 55 located on both sides of it in the X direction.

[0073] A third electrode 40 is disposed in the first semiconductor layer 11. The first control electrode 50 is configured such that the spacing Dsg between it and the third electrode 40 is widened. The spacing Dsg is, for example, wider than the second width WG. This reduces the parasitic capacitance between the third electrode 40 and the first control electrode 50. For example, Figure 6 In the manufacturing process shown in (a) and (b), by increasing the etching amount of the conductive film 110 to lower the upper end of the third electrode 40, the spacing Dsg can be widened.

[0074] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention and are included in the scope of the invention and its equivalents as described in the technical solution.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, A trench is formed on a semiconductor wafer, leaving a first space inside the trench. An insulating etch-resistant film is formed covering the interior of the trench. A portion of the semiconductor wafer is exposed on the bottom surface of the trench by selectively removing a portion of the etch-resistant film formed on the bottom surface of the trench. The semiconductor wafer is etched into the depth direction of the trench using the first space within the trench, extending the trench along the depth direction. Isotropic etching is performed on the semiconductor wafer exposed in the extended portion of the trench, laterally expanding the extended portion intersecting the depth direction. A second space is left inside the extended portion by thermal oxidation of the semiconductor wafer exposed in the extended portion of the trench, and a first insulating film is formed covering the inner surface of the extended portion. A conductive component is formed to fill the first and second spaces of the trench. The conductive component is removed such that a portion of it remains in the second space, forming an embedded electrode as part of the conductive component. An insulating component is formed in the third space after the conductive component inside the trench is removed. A second insulating film, including the residue of the insulating component and the residue of the resist film, is formed on the embedded electrode by removing a portion of the insulating component and at least a portion of the resist film from the opening side of the trench. In the fourth space inside the trench after the at least a portion of the resist film and a portion of the insulating component are removed, a first control electrode is formed on the second insulating film. The trench includes two adjacent first trenches. The first control electrode is disposed inside the two adjacent first trenches. A second control electrode is formed inside the second trench between the two adjacent first trenches. The resist film includes a first film formed on the semiconductor wafer, a second film formed on the first film, and a third film formed on the second film. The third film is removed after the extension portion of the trench is formed and before the first insulating film is formed. During the removal of the conductive component, the second film is removed. The second insulating film includes a portion of the first film.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After thermal oxidation of a portion of the semiconductor wafer exposed in the fourth space, the first control electrode is formed in the fourth space.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The first and third films of the etching resist film each comprise silicon oxide, and the second film comprises silicon nitride.

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