A current-modulated column-level single-slope analog-to-digital converter

Abstract

The present invention discloses a current modulation column-level single-slope analog-to-digital converter, which relates to the technical field of analog-to-digital converters and includes an inverter, a voltage modulator, a pull-up circuit, a pull-down circuit, a current-voltage conversion circuit, a differential amplification circuit, and a bias circuit. Since the pull-up circuit and the pull-down circuit are exactly the same as the inverter in the present invention, when the static operating current of the inverter in the column circuit fluctuates due to process, power supply voltage, and temperature, the inverter current modulation circuit can stabilize the inverter current and the operating point of the array of inverters. The inverter is less affected by process, power supply voltage, and temperature, and the static operating point is more stable, improving the accuracy of the column-level single-slope analog-to-digital converter using an inverter-structured comparator, thereby enabling applications in high-precision scenarios.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital converters, and particularly to a current-modulated column-level single-slope analog-to-digital converter. Background Art

[0002] Low-power CMOS image sensors are the core technologies for visual information acquisition and transmission that require battery power supply in the fields of Internet of Things, 5G mobile terminal devices, artificial intelligence, etc. At present, CMOS image sensors mainly adopt a column-parallel architecture, and the main power consumption source of the column-parallel architecture is the column-level analog-to-digital converter (ADC) of the core module. There are four common types of column-level ADCs: single-slope ADC, cyclic ADC, successive approximation ADC, and delta modulation ADC. Among them, the single-slope ADC contains only one comparator and one counter per column, and has the lowest power consumption. Therefore, the column-level single-slope ADC architecture is widely used in low-power CMOS image sensors.

[0003] The comparator in the column-level single-slope ADC can be implemented by an inverter structure. The inverter structure is simple, and the comparator no longer consumes current after flipping, so the power consumption is low. However, the static operating point of the inverter is prone to fluctuate due to process, power supply voltage, and temperature, which will cause the flip point of the inverter to deviate, reducing the accuracy of the column-level single-slope ADC and making it difficult to achieve applications in high-precision scenarios. Summary of the Invention

[0004] The embodiments of the present invention provide a current-modulated column-level single-slope analog-to-digital converter, which solves the technical problem of low accuracy of the column-level single-slope ADC using a comparator with an inverter structure in the prior art, improves the accuracy of the column-level single-slope ADC using a comparator with an inverter structure, and can achieve applications in high-precision scenarios.

[0005] The present invention provides the following technical solutions through an embodiment of the present invention:

[0006] A current-modulated column-level single-slope analog-to-digital converter includes an inverter, a voltage modulator, a pull-up circuit, a pull-down circuit, a current-voltage conversion circuit, a differential amplifier circuit, and a bias circuit;

[0007] The output ends of the differential amplifier circuit are respectively connected to the input end of the voltage modulator and the power supply end of the pull-up circuit. The output end of the voltage modulator is connected to the power supply end of the inverter. The voltage modulator is used to increase its output after its input increases and decrease its output after its input decreases;

[0008] The pull-up circuit is exactly the same as the pull-up network of the inverter, and the pull-down circuit is exactly the same as the pull-down network of the inverter. The output end of the pull-up circuit is connected to the output end of the pull-down circuit through the current-voltage conversion circuit. The common end of the output end of the pull-up circuit and the current-voltage conversion circuit is connected to the non-inverting input end of the differential amplifier circuit. The common end of the output end of the pull-down circuit and the current-voltage conversion circuit is connected to the inverting input end of the differential amplifier circuit;

[0009] The common end of the output end of the pull-down circuit and the current-voltage conversion circuit is also connected to the input end of the bias circuit. The output end of the bias circuit is respectively connected to the input end of the pull-up circuit and the input end of the pull-down circuit. The bias circuit is used to output a low level when its input is a low level and output a high level when its input is a high level.

[0010] Preferably, the current-voltage conversion circuit includes a first resistor, and two ends of the first resistor are respectively connected to the output end of the pull-up circuit and the output end of the pull-down circuit.

[0011] Preferably, the bias circuit includes a first operational amplifier. The common end of the output end of the pull-down circuit and the current-voltage conversion circuit is connected to the non-inverting input end of the first operational amplifier. The inverting input end of the first operational amplifier is connected to a first reference voltage. The output end of the first operational amplifier is respectively connected to the input end of the pull-up circuit and the input end of the pull-down circuit.

[0012] Preferably, the differential amplifier circuit includes an instrumentation amplifier and a second operational amplifier;

[0013] The common end of the output end of the pull-up circuit and the current-voltage conversion circuit is connected to the non-inverting input end of the instrumentation amplifier. The common end of the output end of the pull-down circuit and the current-voltage conversion circuit is connected to the inverting input end of the instrumentation amplifier. The output end of the instrumentation amplifier is connected to the inverting input end of the second operational amplifier. The non-inverting input end of the second operational amplifier is connected to a second reference voltage. The output end of the second operational amplifier is respectively connected to the power supply end of the pull-up circuit and the input end of the voltage modulator.

[0014] Preferably, the voltage modulator includes a third operational amplifier, a fifth MOS transistor, a second resistor circuit, and a third resistor circuit. The fifth MOS transistor is a PMOS;

[0015] The output terminal of the differential amplifier circuit is connected to the non-inverting input terminal of the third operational amplifier. The output terminal of the third operational amplifier is connected to the gate of the fifth MOS transistor. The output terminal of the third operational amplifier is its negative terminal. The bias power supply is grounded through the fifth MOS transistor, the second resistor circuit, and the third resistor circuit connected in series in sequence. The common terminal of the second resistor circuit and the third resistor circuit is connected to the inverting input terminal of the third operational amplifier. The common terminal of the fifth MOS transistor and the second resistor circuit is connected to the power supply terminal of the inverter.

[0016] Preferably, the second resistor circuit includes a resistor R2.

[0017] Preferably, the third resistor circuit includes a resistor R3.

[0018] Preferably, the pull-up circuit includes a third MOS transistor. The third MOS transistor is a PMOS transistor. The source, gate, and drain of the third MOS transistor are the power supply terminal, input terminal, and output terminal of the pull-up circuit respectively.

[0019] Preferably, the pull-down circuit includes a fourth MOS transistor. The fourth MOS transistor is an NMOS transistor. The gate and drain of the fourth MOS transistor are the input terminal and output terminal of the pull-down circuit respectively. The source of the fourth MOS transistor is grounded.

[0020] Preferably, the current modulation column-level single-slope analog-to-digital converter further includes a ramp generator, a first capacitor circuit, a second capacitor circuit, a reset switch, an N-bit counter, and an N-bit register, where N is a positive integer;

[0021] The external column analog signal is input to the input terminal of the inverter through the first capacitor circuit. The output terminal of the ramp generator is connected to the input terminal of the inverter through the second capacitor circuit. The two ends of the reset switch are respectively connected to the input terminal of the inverter and the output terminal of the inverter. The output terminal of the inverter is connected to the input terminal of the N-bit counter. The output terminal of the N-bit counter is connected to the N-bit register.

[0022] One or more technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages:

[0023] Since the pull-up circuit and the pull-down circuit are exactly the same as the inverter, when the static operating current of the inverter in the column circuit fluctuates due to process, power supply voltage, and temperature, the inverter current modulation circuit can stabilize the inverter current, stabilize the operating point of the array inverter. The inverter is less affected by process, power supply voltage, and temperature, and the static operating point is more stable, improving the accuracy of the column-level single-slope analog-to-digital converter using the inverter structure comparator, so as to realize the application in high-precision occasions. Description of the Drawings

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0025] Figure 1 It is a schematic structural diagram of the inverter current modulation circuit of the present invention;

[0026] Figure 2 It is a schematic structural diagram of the column circuit of the present invention;

[0027] Figure 3 It is a circuit diagram of the column circuit of the present invention;

[0028] Figure 4 It is a circuit diagram of the inverter current modulation circuit of the present invention. Specific embodiments

[0029] The embodiments of the present invention provide a current modulation column-level single-slope analog-to-digital converter, which solves the technical problem of low accuracy of the column-level single-slope ADC using an inverter-structured comparator in the prior art.

[0030] The technical solution of the embodiments of the present invention to solve the above technical problem is generally as follows:

[0031] A current modulation column-level single-slope analog-to-digital converter, as Figure 1 shown, includes an inverter, a voltage modulator, a pull-up circuit, a pull-down circuit, a current-voltage conversion circuit, a differential amplifier circuit, and a bias circuit;

[0032] The output terminals of the differential amplifier circuit are respectively connected to the input terminal of the voltage modulator and the power supply terminal of the pull-up circuit. The output terminal of the voltage modulator is connected to the power supply terminal of the inverter. The voltage modulator is used to increase its output after its input increases and decrease its output after its input decreases;

[0033] The pull-up circuit is exactly the same as the pull-up network of the inverter, and the pull-down circuit is exactly the same as the pull-down network of the inverter. The output terminal of the pull-up circuit is connected to the output terminal of the pull-down circuit through the current-voltage conversion circuit. The common terminal of the output terminal of the pull-up circuit and the current-voltage conversion circuit is connected to the non-inverting input terminal of the differential amplifier circuit, and the common terminal of the output terminal of the pull-down circuit and the current-voltage conversion circuit is connected to the inverting input terminal of the differential amplifier circuit;

[0034] The common terminal of the output terminal of the pull-down circuit and the current-voltage conversion circuit is also connected to the input terminal of the bias circuit. The output terminal of the bias circuit is respectively connected to the input terminals of the pull-up circuit and the pull-down circuit. The bias circuit is used to output a low level when its input is at a low level and output a high level when its input is at a high level.

[0035] To better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings of the specification and specific embodiments.

[0036] First, it should be noted that the term "and / or" appearing in this article is merely a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.

[0037] In this embodiment, as Figure 2 shown, the current modulation column-level single-slope analog-to-digital converter further includes a ramp generator, a first capacitor circuit, a second capacitor circuit, a reset switch, an N-bit counter, and an N-bit register, where N is a positive integer; an external column analog signal is input to the input terminal of an inverter through the first capacitor circuit, the output terminal of the ramp generator is connected to the input terminal of the inverter through the second capacitor circuit, both ends of the reset switch are respectively connected to the input terminal of the inverter and the output terminal of the inverter, the output terminal of the inverter is connected to the input terminal of the N-bit counter, and the output terminal of the N-bit counter is connected to the N-bit register. The first capacitor circuit, the second capacitor circuit, the inverter, the reset switch, the N-bit counter, and the N-bit register constitute a column circuit in the column-level single-slope analog-to-digital converter. The column-level single-slope analog-to-digital converter includes multiple column circuits, and each column circuit is respectively used to receive one column analog signal among the column analog signals, convert it into a digital code value, and then output it. The first capacitor circuit and the second capacitor circuit are circuits composed of capacitors for charging and discharging. The first capacitor circuit or the second capacitor circuit may include one capacitor or may include multiple capacitors connected in series or in parallel. The voltage modulator is used to provide the power supply voltage Vdd_inv of the inverters in all column circuits, the ramp generator is used to provide the ramp signal Vramp required for analog-to-digital conversion of all column circuits, and the inverter is used to compare the power supply voltage Vdd_inv with the ramp signal Vramp.

[0038] Specifically, as Figure 3As shown, RST is a reset switch; the first capacitor circuit may only include capacitor C1, and the second capacitor circuit may only include capacitor C2; the inverter includes a first MOS transistor M1 and a second MOS transistor M2, the first MOS transistor M1 is a PMOS, and the second MOS transistor M2 is an NMOS. The column analog signal Vpixel input externally is connected to the gates of the first MOS transistor M1 and the second MOS transistor M2 simultaneously through the capacitor C1, the output terminal of the ramp generator is connected to the gates of the first MOS transistor M1 and the second MOS transistor M2 simultaneously through the capacitor C2, the output terminal of the voltage modulator is grounded through the series-connected first MOS transistor M1 and second MOS transistor M2, the common terminal of the first MOS transistor M1 and the second MOS transistor M2 is connected to the first end of the reset switch RST and the input terminal of the N-bit counter simultaneously, and the second end of the reset switch RST is connected to the gates of the first MOS transistor M1 and the second MOS transistor M2 simultaneously. Among them, the drain of the first MOS transistor M1 is connected to the drain of the second MOS transistor M2, the source of the second MOS transistor M2 is grounded, the gates of the first MOS transistor M1 and the second MOS transistor M2 are the input terminals of the inverter, the common terminal of the drain of the first MOS transistor M1 and the drain of the second MOS transistor M2 is the output terminal of the inverter, and the source of the first MOS transistor M1 is the power supply terminal of the inverter. The pull-up network of the inverter includes the first MOS transistor M1, the pull-down network includes the second MOS transistor M2 and the source of the second MOS transistor M2 is grounded. When the input of the inverter is at a high level, the second MOS transistor M2 conducts, and the input terminal of the N-bit counter is grounded, and the inverter outputs a low level; when the input of the inverter is at a low level, the first MOS transistor M1 conducts, the input terminal of the N-bit counter is connected to the output terminal of the voltage modulator, and the inverter outputs a high level.

[0039] The working principle of one column circuit in this embodiment is as follows: First, in the pixel reset voltage output stage, at this time, the Vpixel voltage is the pixel reset voltage Vrst, the reset switch RST is closed, and the inverter is reset. Figure 3 The voltage at point Vi is the inverter reset voltage Vcm, and the Vramp voltage is the ramp reset voltage Vramp0; then, in the pixel signal voltage output stage, at this time, the Vpixel voltage is the pixel signal voltage Vsig, the reset switch RST is disconnected, the Vramp voltage rises in a ramp. Since point Vi is floating, according to the principle of charge conservation, there is

[0040] (Vcm - Vrst)C1 + (Vcm - Vramp0)C2 = (Vi - Vsig)C1 + (Vi - Vramp)C2;

[0041] It can be obtained that

[0042] When When the driving input voltage Vi of the two MOS transistors is greater than the inverter reset voltage Vcm, the second MOS transistor M2 is turned on, the output Vo is grounded and the voltage is zero, the inverter flips, the N-bit counter stops counting, and the count value at this time is saved to the N-bit register as the N-bit quantization code value of the column pixel signal. The column-level single-slope analog-to-digital converter can also be implemented using an operational amplifier structure. However, it takes 2 N clock cycles to complete the quantization of the N-bit code value. The operational amplifier type comparator consumes static current throughout the 2 N clock cycle quantization process, so the power consumption is relatively high. The comparator in the column-level single-slope analog-to-digital converter implemented by the inverter structure as described above no longer consumes current after the comparator flips. The power consumption of each column circuit is low. Compared with the traditional operational amplifier type comparator, the power consumption of each column circuit is reduced and the structure is simple. As the pixel array increases, the power consumption reduction effect will be more significant. From the working principle of the column circuit, when there is a deviation in the flip point of the inverter, the N-bit counter will count more or less, resulting in a deviation in the quantization code value. Since the static operating point of the inverter is easily affected by process, power supply voltage, and temperature and fluctuates, the flip point of the inverter will deviate.

[0043] In this embodiment, the voltage modulator, the pull-up circuit, the pull-down circuit, the current-voltage conversion circuit, the differential amplification circuit, and the bias circuit together constitute an inverter current modulation circuit. As Figure 4 shown, the voltage modulator includes a third operational amplifier U3, a fifth MOS transistor M5, a second resistor circuit, and a third resistor circuit. The fifth MOS transistor M5 is a PMOS; the current-voltage conversion circuit, the second resistor circuit, or the third resistor circuit can each include only one resistor, or can include multiple resistors connected in series or parallel. Preferably, the current-voltage conversion circuit includes a first resistor R1, the second resistor circuit includes a resistor R2, and the third resistor circuit includes a resistor R3; the bias circuit includes a first operational amplifier U1; the differential amplification circuit includes an instrumentation amplifier and a second operational amplifier U2. The instrumentation amplifier can also be replaced by a differential amplifier; if the inverter includes a first MOS transistor M1 and a second MOS transistor M2, then the pull-up circuit includes a third MOS transistor M3. The third MOS transistor M3 is a PMOS and has the same size as the first MOS transistor M1. The pull-down circuit includes a fourth MOS transistor M4. The fourth MOS transistor M4 is an NMOS and the source of the fourth MOS transistor M4 is grounded. The fourth MOS transistor M4 has the same size as the second MOS transistor M2.

[0044] The output terminal of the second operational amplifier U2 is respectively connected to the source of the third MOS transistor M3 and the non-inverting input terminal of the third operational amplifier U3. The output terminal of the third operational amplifier U3 is connected to the gate of the fifth MOS transistor M5. The output terminal of the third operational amplifier U3 is its negative terminal. The bias power supply is connected to the source of the fifth MOS transistor M5. The drain of the fifth MOS transistor M5 is grounded through the series-connected resistor R2 and resistor R3. The common terminal of resistor R2 and resistor R3 is connected to the inverting input terminal of the third operational amplifier U3. The common terminal of the drain of the fifth MOS transistor M5 and resistor R2 is connected to the source of the first MOS transistor M1. The two ends of the first resistor R1 are respectively connected to the drain of the third MOS transistor M3 and the drain of the fourth MOS transistor M4. The common terminal of the drain of the third MOS transistor M3 and the first resistor R1 is connected to the non-inverting input terminal of the instrumentation amplifier. The common terminal of the drain of the fourth MOS transistor M4 and the first resistor R1 is connected to the inverting input terminal of the instrumentation amplifier. The output terminal of the instrumentation amplifier is connected to the inverting input terminal of the second operational amplifier U2. The non-inverting input terminal of the second operational amplifier U2 is connected to the second reference voltage Vref2. The common terminal of the drain of the fourth MOS transistor M4 and the first resistor R1 is also connected to the non-inverting input terminal of the first operational amplifier U1. The inverting input terminal of the first operational amplifier U1 is connected to the first reference voltage Vref1. Among them, the output terminal of the second operational amplifier U2 is the output terminal of the differential amplifier circuit. The non-inverting input terminal of the third operational amplifier U3 is the input terminal of the voltage modulator. The source of the third MOS transistor M3 is the power supply terminal of the pull-up circuit. The common terminal of the drain of the fifth MOS transistor M5 and resistor R2 is the output terminal of the voltage modulator. The drain of the third MOS transistor M3 is the output terminal of the pull-up circuit. The drain of the fourth MOS transistor M4 is the output terminal of the pull-down circuit. The non-inverting input terminal of the first operational amplifier U1 is the input terminal of the bias circuit. The output terminal of the first operational amplifier U1 is the output terminal of the bias circuit. The gate of the third MOS transistor M3 is the input terminal of the pull-up circuit. The gate of the fourth MOS transistor M4 is the input terminal of the pull-down circuit.

[0045] For the bias circuit, when its input is at a high level, the first operational amplifier U1 outputs a high level; when its input is at a low level, the first operational amplifier U1 outputs a low level. For the differential amplifier circuit, when the difference between the two differential input voltages of the instrumentation amplifier increases, the output of the second operational amplifier U2 decreases. For the voltage modulator, when its input increases, the output of the third operational amplifier U3 decreases, the gate voltage of the fifth MOS transistor M5 decreases, the conduction degree of the fifth MOS transistor M5 increases, the output current of the fifth MOS transistor M5 increases, and the power supply voltage Vdd_inv of the inverter increases; when its input decreases, the output of the third operational amplifier U3 increases, the gate voltage of the fifth MOS transistor M5 increases, the conduction degree of the fifth MOS transistor M5 decreases, the output current of the fifth MOS transistor M5 decreases, and the power supply voltage Vdd_inv of the inverter decreases.

[0046] In this embodiment, since the pull-up circuit and the pull-down circuit are exactly the same as the inverter, when the static operating currents of the first MOS transistor M1 and the second MOS transistor M2 in the column circuit inverter fluctuate, the third MOS transistor M3 and the fourth MOS transistor M4 also fluctuate synchronously. When the static operating currents of the first MOS transistor M1 and the second MOS transistor M2 increase, Figure 4 the difference between Vrp and Vrn increases. The instrumentation amplifier amplifies this difference and inputs it to the inverting input terminal of the second operational amplifier U2. The output voltage Vdd_loop of the second operational amplifier U2 decreases. After being modulated by the voltage modulator, Vdd_inv also decreases, forming a negative feedback, thereby reducing the inverter current and stabilizing the inverter current. Similarly, when the static operating currents of the first MOS transistor M1 and the second MOS transistor M2 decrease, Figure 4 the difference between Vrp and Vrn decreases. The output voltage Vdd_loop of the second operational amplifier U2 increases. After being modulated by the voltage modulator, Vdd_inv also increases, forming a negative feedback, thereby increasing the inverter current and stabilizing the inverter current. In this way, when the static operating current of the inverter in the column circuit fluctuates due to process, power supply voltage, and temperature, the inverter current modulation circuit can stabilize the inverter current, stabilize the operating point of the array inverter. The inverter is less affected by process, power supply voltage, and temperature, and the static operating point is more stable, so that it can be applied to high-precision occasions. In addition, since the inverter current modulation circuit is used to provide the power supply voltage Vdd_inv for the inverters in all column circuits, all column circuits share one inverter current modulation circuit, and the power consumption of the inverter current modulation circuit can be ignored compared with the power consumption of all column circuits, and the power consumption is basically not increased.

[0047] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0048] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. A current-modulated column-level single-slope analog-to-digital converter, characterized in that It includes an inverter, a voltage modulator, a pull-up circuit, a pull-down circuit, a current-voltage conversion circuit, a differential amplifier circuit, and a bias circuit; The output ends of the differential amplifier circuit are respectively connected to the input end of the voltage modulator and the power supply end of the pull-up circuit. The output end of the voltage modulator is connected to the power supply end of the inverter. The voltage modulator is configured to increase its output after its input increases and decrease its output after its input decreases; The pull-up circuit is exactly the same as the pull-up network of the inverter. The pull-down circuit is exactly the same as the pull-down network of the inverter. The output end of the pull-up circuit is connected to the output end of the pull-down circuit through the current-voltage conversion circuit. The common end of the output end of the pull-up circuit and the current-voltage conversion circuit is connected to the non-inverting input end of the differential amplifier circuit. The common end of the output end of the pull-down circuit and the current-voltage conversion circuit is connected to the inverting input end of the differential amplifier circuit; The common end of the output end of the pull-down circuit and the current-voltage conversion circuit is also connected to the input end of the bias circuit. The output end of the bias circuit is respectively connected to the input end of the pull-up circuit and the input end of the pull-down circuit. The bias circuit is configured to output a low level when its input is at a low level and output a high level when its input is at a high level.

2. The current modulation column-level single-slope analog-to-digital converter according to claim 1, wherein The current-voltage conversion circuit includes a first resistor, and two ends of the first resistor are respectively connected to the output end of the pull-up circuit and the output end of the pull-down circuit.

3. The current modulation column-level single-slope analog-to-digital converter according to claim 1, wherein The bias circuit includes a first operational amplifier. The common end of the output end of the pull-down circuit and the current-voltage conversion circuit is connected to the non-inverting input end of the first operational amplifier. The inverting input end of the first operational amplifier is connected to a first reference voltage. The output end of the first operational amplifier is respectively connected to the input end of the pull-up circuit and the input end of the pull-down circuit.

4. The current modulation column-level single-slope analog-to-digital converter according to claim 1, characterized in that The differential amplifier circuit includes an instrumentation amplifier and a second operational amplifier; The common end of the output end of the pull-up circuit and the current-voltage conversion circuit is connected to the non-inverting input end of the instrumentation amplifier. The common end of the output end of the pull-down circuit and the current-voltage conversion circuit is connected to the inverting input end of the instrumentation amplifier. The output end of the instrumentation amplifier is connected to the inverting input end of the second operational amplifier. The non-inverting input end of the second operational amplifier is connected to a second reference voltage. The output end of the second operational amplifier is respectively connected to the power supply end of the pull-up circuit and the input end of the voltage modulator.

5. The current modulation column-level single-slope analog-to-digital converter according to claim 1, wherein The voltage modulator includes a third operational amplifier, a fifth MOS transistor, a second resistor circuit, and a third resistor circuit. The fifth MOS transistor is a PMOS; The output end of the differential amplifier circuit is connected to the non-inverting input end of the third operational amplifier. The output end of the third operational amplifier is connected to the gate of the fifth MOS transistor. The output end of the third operational amplifier is its negative terminal. The bias power supply is grounded through the fifth MOS transistor, the second resistor circuit, and the third resistor circuit connected in series in sequence. The common end of the second resistor circuit and the third resistor circuit is connected to the inverting input end of the third operational amplifier. The common end of the fifth MOS transistor and the second resistor circuit is connected to the power supply end of the inverter.

6. The current modulation column-level single-slope analog-to-digital converter according to claim 5, characterized in that, The second resistor circuit includes a resistor R2.

7. The current modulation column-level single-slope analog-to-digital converter according to claim 5, wherein The third resistor circuit includes a resistor R3.

8. The current modulation column-level single-slope analog-to-digital converter according to claim 1, wherein The pull-up circuit includes a third MOS transistor, the third MOS transistor is a PMOS, and the source, gate, and drain of the third MOS transistor are the power supply terminal, input terminal, and output terminal of the pull-up circuit, respectively.

9. The current modulation column-level single-slope analog-to-digital converter according to claim 1, wherein The pull-down circuit includes a fourth MOS transistor, the fourth MOS transistor is an NMOS, the gate and drain of the fourth MOS transistor are the input terminal and output terminal of the pull-down circuit, respectively, and the source of the fourth MOS transistor is grounded.

10. The current modulation column-level single-slope analog-to-digital converter according to claim 1, wherein It further includes a ramp generator, a first capacitor circuit, a second capacitor circuit, a reset switch, an N-bit counter, and an N-bit register, where N is a positive integer; The external column analog signal is input into the input terminal of the inverter through the first capacitor circuit, the output terminal of the ramp generator is connected to the input terminal of the inverter through the second capacitor circuit, both ends of the reset switch are respectively connected to the input terminal of the inverter and the output terminal of the inverter, the output terminal of the inverter is connected to the input terminal of the N-bit counter, and the output terminal of the N-bit counter is connected to the N-bit register.

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