Method for increasing intrinsic threshold voltage of boundary virtual memory array

Abstract

The present invention discloses a method for increasing the intrinsic threshold voltage (Vth) of a dummy memory array. During the fabrication of a border dummy memory array, a main memory array, a decoder, and peripheral components on a substrate, the method further includes performing an additional implantation process on the border dummy memory array to increase the well concentration of the border dummy memory array to a greater concentration than that of the main memory array. Alternatively, during the fabrication of the decoder or peripheral components, the additional implantation process can be performed on the border dummy memory array, which would not otherwise receive implantation, thereby achieving a greater well concentration in the border dummy memory array than that of the main memory array and saving photomasks.

Description

Technical Field

[0001] The present invention relates to an improvement in the manufacturing process of a memory array, and more particularly to a method for increasing the intrinsic threshold voltage Vth of a boundary virtual memory array. Background Art

[0002] A memory array typically consists of a main memory array and a peripheral dummy memory array. These are semiconductor components manufactured using the same process and design. However, due to manufacturing process factors, the dimensions of some semiconductor components at the memory array's perimeter, such as the height of the shallow trench isolation structures and the height of the polysilicon layer, may not match the required dimensions. Therefore, these perimeters are designated as dummy memory arrays to avoid impacting memory operation.

[0003] In other words, no matter what operation the main memory array performs, the boundary dummy memory array is always performing an erase operation. As the number of erase operations accumulates, the intrinsic threshold voltage Vth of the boundary dummy memory array gradually decreases, resulting in an over-erase phenomenon.

[0004] The over-erase phenomenon can cause threshold leakage current, which affects the PGM and read operations of the main memory array. Summary of the Invention

[0005] The present invention provides a method for increasing the intrinsic threshold voltage (Vth) of a dummy memory array. The method can make the doping concentration of the well region of the boundary dummy memory array greater than the doping concentration of the well region of the main memory array, thereby increasing the intrinsic threshold voltage (Vth) of the dummy memory array and thereby reducing the critical leakage therein.

[0006] The method of increasing the intrinsic threshold voltage Vth of a virtual memory array of the present invention includes fabricating a boundary virtual memory array, a main memory array, a decoder, and a peripheral element on a substrate, wherein the well region of the boundary virtual memory array and the well region of the main memory array are formed using the same fabrication process, and the method further includes at least one of the following steps: (1) during the fabrication of the decoder, a first implantation fabrication process is simultaneously performed on the substrate within the decoder region and the well region of the boundary virtual memory array to form the well region of the decoder and to make the doping concentration of the well region of the boundary virtual memory array greater than the doping concentration of the well region of the main memory array. (2) during the fabrication of the peripheral element, a second implantation fabrication process is simultaneously performed on the substrate within the peripheral element region and the well region of the boundary virtual memory array to form the well region of the peripheral element and to make the doping concentration of the well region of the boundary virtual memory array greater than the doping concentration of the well region of the main memory array. (3) a third implantation fabrication process is performed on the well region of the boundary virtual memory array to make the doping concentration of the well region of the boundary virtual memory array greater than the doping concentration of the well region of the main memory array.

[0007] In one embodiment of the present invention, the boundary virtual memory array is formed around the main memory array.

[0008] In one embodiment of the present invention, the decoder includes a row decoder and a column decoder.

[0009] In one embodiment of the present invention, the first implantation process may be performed before forming the well region of the boundary dummy memory array.

[0010] In one embodiment of the present invention, the second implantation process may be performed before or after forming the well region of the boundary dummy memory array.

[0011] In one embodiment of the present invention, the third implantation process may be performed before or after forming the well region of the boundary dummy memory array.

[0012] In one embodiment of the present invention, the channel doping concentration in the well region of the boundary dummy memory array is more than twice the doping concentration in the well region of the main memory array.

[0013] Based on the above, the present invention achieves a higher well concentration in the boundary dummy memory array than in the (main) memory array by performing an additional implantation process on the boundary dummy memory array, or by performing an additional implantation process on the boundary dummy memory array, which would not otherwise receive implantation, during the fabrication of decoders or peripheral components. Due to the increased well concentration, the intrinsic threshold voltage (Vth) of the boundary dummy memory array also increases. Once the intrinsic threshold voltage (Vth) of the boundary dummy memory array increases, the erase time of the boundary dummy memory array is delayed, resulting in a later erasure time. This mitigates the over-erase phenomenon in this region, reduces leakage, and thus improves PGM operation.

[0014] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a diagram of a process for increasing the intrinsic threshold voltage Vth (Intrinsic Vth) of a boundary virtual memory according to an embodiment of the present invention;

[0016] Figure 2 is an IV curve diagram of the boundary virtual memory array and the main memory array in the present invention;

[0017] Figure 3 is a schematic top view of a semiconductor wafer;

[0018] Figure 4 is a schematic top view of a semiconductor device according to an embodiment of the present invention;

[0019] Figures 5A to 5F It is along Figure 4 Schematic diagram of the cross-sectional manufacturing process of the semiconductor device along the line segment V-V'.

[0020] Explanation of symbols

[0021] 30: Chip

[0022] 300: tube core

[0023] 302: surrounding areas

[0024] 400:Semiconductor device

[0025] 402: Main memory array

[0026] 404: Boundary Virtual Memory Array

[0027] 406: Row Decoder

[0028] 408: Column Decoder

[0029] 500: Base

[0030] 502: Main array area

[0031] 504: Virtual array area

[0032] 506: decoder area

[0033] 508, 510, 512: well region

[0034] 514: Gate structure

[0035] 516: tunneling dielectric layer

[0036] 518: first gate layer

[0037] 518a: floating gate

[0038] 520: intergate dielectric layer

[0039] 522: second gate layer

[0040] 522a: control gate

[0041] 524:Isolation Structure

[0042] 526: Source / drain region

[0043] 528: spacer

[0044] 530: dielectric layer

[0045] 532: Contact window

[0046] 534:Metal connection

[0047] G: Gate

[0048] S100, S102, S104, S106, S108, S110, S112: Steps DETAILED DESCRIPTION

[0049] The following examples are listed and illustrated in detail with reference to the accompanying drawings. However, these examples are not intended to limit the scope of the present invention. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, identical components will be designated by the same reference numerals throughout the following description.

[0050] Furthermore, terms such as "including," "comprising," and "having" used herein are open-ended, meaning "including but not limited to." Furthermore, terms such as "first," "second," and "third" are used herein to describe various areas and / or steps, but these areas and / or steps should not be limited by these terms. These terms are used solely to distinguish one area from another, or to separate one step from another, and do not indicate a sequential order.

[0051] Figure 1 FIG. 1 is a flowchart of a process for increasing the intrinsic threshold voltage Vth (Intrinsic Vth) of a boundary virtual memory according to an embodiment of the present invention.

[0052] Please refer to Figure 1 , step S100 is to produce a boundary dummy memory array on the substrate. Step S102 is to produce a main memory array on the substrate. In one embodiment, the above-mentioned boundary dummy memory array is formed around the above-mentioned main memory array, and step S100 and step S102 are usually performed simultaneously to produce a boundary dummy memory array and a main memory array with the same element design on the substrate. For example, the well region of the boundary dummy memory array and the well region of the main memory array are formed using the same photomask and implantation process, and the doping concentrations of the two well regions are almost the same. Moreover, after the well region is formed, both step S100 and step S102 also include other implantation processes, such as a field isolation implantation process, a channel implantation process, etc., to form a channel and a field isolation region in the well region of the boundary dummy memory array and the well region of the main memory array, respectively.

[0053] Step S104 involves fabricating a decoder on the substrate, wherein the decoder includes a row decoder and a column decoder. In one embodiment, the decoder is formed around the boundary dummy memory. Step S106 involves fabricating peripheral components, such as peripheral circuits and passive components, on the substrate.

[0054] It should be noted that the production sequence and detailed steps of step S100, step S102, step S104 and step S108 can refer to the existing technology. The present invention does not limit the order of these steps. For example, step S100, step S102 and step S106 may cover some film layers and semiconductor manufacturing processes that are produced at the same time.

[0055] Step S108 involves performing a first implantation process. This is performed simultaneously on the substrate within the decoder region and the well region of the border dummy memory array during the fabrication of the decoder. This process forms the well region of the decoder and increases the doping concentration of the well region of the border dummy memory array to a greater degree than that of the well region of the main memory array. Furthermore, because step S100 includes performing other implantation processes, such as a channel implantation process, on the border dummy memory array region, the channel doping concentration within the well region of the border dummy memory array is, for example, more than twice that of the well region of the main memory array. Furthermore, the first implantation process of step S108 can be performed before forming the well region of the border dummy memory array.

[0056] Step S110 is to perform a second implantation process, which is an implantation process performed simultaneously on the substrate within the region of the peripheral element and the well region of the boundary dummy memory array during the fabrication of the peripheral element. This allows the formation of the well region of the peripheral element, and makes the doping concentration of the well region of the boundary dummy memory array greater than the doping concentration of the well region of the main memory array. Moreover, because step S100 includes performing other implantation processes such as a channel implantation process on the region of the boundary dummy memory array, the channel doping concentration within the well region of the boundary dummy memory array is, for example, more than twice the doping concentration of the well region of the main memory array. In one embodiment, the second implantation process of step S110 can be performed before forming the well region of the boundary dummy memory array; in another embodiment, the second implantation process of step S110 can be performed after forming the well region of the boundary dummy memory array.

[0057] Step S112 involves performing a third implantation process, which is an additional implantation process performed on the well region of the border dummy memory array to increase the doping concentration of the well region of the border dummy memory array to a greater concentration than that of the well region of the main memory array. That is, in steps S100 and S102, the well region of the border dummy memory array and the well region of the main memory array are formed using the same photomask and implantation process. At this stage, the doping concentrations of the two well regions are nearly identical. However, after step S112, the doping concentration of the well region of the border dummy memory array increases. Furthermore, because step S100 includes performing other implantation processes, such as a channel implantation process, on the border dummy memory array region, the channel doping concentration within the well region of the border dummy memory array is, for example, more than twice that of the well region of the main memory array. In one embodiment, the third implantation process of step S112 can be performed before forming the well region of the border dummy memory array; in another embodiment, the third implantation process of step S112 can be performed after forming the well region of the border dummy memory array.

[0058] It should be noted that steps S108, S110, and S112 above all perform additional implantation processes on the well region of the border dummy memory array to increase its doping concentration. Therefore, at least one, two, or all of these steps can be selected and added to step S100 of fabricating the border dummy memory array, as needed. That is, step S112 can be added to step S100 of fabricating the border dummy memory array, eliminating the need to implant the well region of the border dummy memory array during steps S108 and S110. Alternatively, step S108 can be added to step S100 of fabricating the border dummy memory array, eliminating the need to implant the well region of the border dummy memory array during step S110, and so on. In another embodiment, steps S108 and S110 can be performed during step S100 of fabricating the border dummy memory array, while step S112 is omitted. This significantly increases the doping concentration of the well region of the border dummy memory array without requiring an additional photomask.

[0059] go through Figure 1 After the method is improved, the IV curves of the boundary virtual memory array and the main memory array are shown as follows: Figure 2 shown.

[0060] exist Figure 2 In the example, the boundary dummy memory array, which should originally have an IV curve similar to that of the main memory array, has its IV curve shifted to the right by increasing the doping concentration of the well region of the boundary dummy memory array. This, in turn, raises the intrinsic threshold voltage (Vth) of the boundary dummy memory array. Once the intrinsic threshold voltage (Vth) of the boundary dummy memory array is increased, the erase timing of the boundary dummy memory array is delayed, thereby mitigating over-erase in that region and reducing leakage in the boundary dummy memory array, thereby ensuring current stability during PGM operation.

[0061] In the following embodiment, step S108 is used to increase the doping concentration of the well region of the boundary dummy memory array to a greater level than that of the well region of the main memory array. The memory array is exemplified by a NOR Flash memory. However, the present invention is not limited thereto, and the memory array may also be another type of memory array, such as a NAND Flash memory.

[0062] Figure 3 The figure is a top view of a semiconductor wafer 30. The wafer 30 is divided into a plurality of dies 300. Each die 300 may include a region having a semiconductor device 400 and a peripheral region 302. The peripheral region 302 generally has peripheral components such as circuits and passive components.

[0063] Figure 4 yes Figure 3 FIG. 4 is a top view of a semiconductor device 400 including a main memory array 402, a border dummy memory array 404, a row decoder 406, and a column decoder 408. The border dummy memory array 404 surrounds the main memory array 402, and the decoders (row decoder 406 and column decoder 408) surround the border dummy memory 404.

[0064] Figures 5A to 5F It is along Figure 4 Schematic diagram of the cross-sectional manufacturing process of the semiconductor device along the line segment V-V'.

[0065] Please refer to Figure 5A The substrate 500 is divided into a main array area 502, a dummy array area 504 and a decoder area 506. The main array area 502 corresponds to Figure 4 The virtual array area 504 corresponds to the area of ​​the main memory array 402. Figure 4 The decoder area 506 corresponds to the boundary of the virtual memory array 404. Figure 4 Then, an implantation process is performed to form a well region 508 in the substrate 500 between the dummy array region 504 and the decoder region 506. This implantation process is equivalent to Figure 1 In step S108 , a well region 508 of the decoder region 506 is formed, and an ion implantation is first performed on the dummy array region 504 .

[0066] Next, please refer to Figure 5B , another implantation process is performed to form well regions 510 in the substrate 500 in the main array region 502 and the dummy array region 504. Because the dummy array region 504 has undergone two implantation processes, the doping concentration of the well region 512 in the dummy array region 504 is approximately the sum of the doping concentration of the well region 510 in the main array region 502 and the doping concentration of the well region 508 in the decoder region 506. Therefore, the doping concentration of the well region 512 in the dummy array region 504 is greater than the doping concentration of the well region 510 in the main array region 502. After forming the well regions 510 and 512, other implantation processes, such as a field isolation implantation process and a channel implantation process, may be performed to form a channel (not shown) and a field isolation region (not shown) in the well region 512 of the dummy array region 504 and the well region 510 of the main array region 502, respectively. Therefore, the channel doping concentration in the well region 512 of the dummy array region 504 is, for example, more than twice the doping concentration in the well region 510 of the main array region 502.

[0067] Afterwards, please refer to Figure 5CA gate structure 514 is formed on the substrate 500. The fabrication process, for example, involves first forming a tunneling dielectric layer 516 and a first gate layer 518. After defining the first gate layer 518, an intergate dielectric layer 520 (e.g., an ONO layer) and a second gate layer 522 are then formed. Furthermore, the parameters of the various layers in the gate structure 514 within the main array region 502 and the dummy array region 504 are substantially the same, but the gate structure 514 in the decoder region 506 is slightly different from those in the main array region 502 and the dummy array region 504. For example, the tunneling dielectric layer 516 in the decoder region 506 is thicker (serving as a gate dielectric layer), and the gate dielectric layer 520 is first removed from the region where the decoder gate G is to be formed, allowing contact between the first gate layer 518 and the second gate layer 522.

[0068] Next, please refer to Figure 5D By etching, the control gate 522a, inter-gate dielectric layer 520, floating gate 518a and tunnel dielectric layer 516 in the main array area 502 and the dummy array area 504 are simultaneously defined, as well as the gate G and gate dielectric layer 516' of the decoder area 506. Then, an isolation structure 524 (such as STI) is formed on the substrate 500 to separate the decoder (such as Figure 4 Column decoder 408) and memory array (such as Figure 4 However, the present invention is not limited thereto, and the isolation structure 524 may be formed earlier than the etching step, or after the well region 512 is formed.

[0069] Then, please refer to Figure 5E , source / drain regions 526 are formed in the substrate 500 , and spacers 528 are formed on the sidewalls of the gate G and the gate structure 514 .

[0070] Afterwards, please refer to Figure 5F , forming a dielectric layer 530 covering the entire surface, and then forming contact windows 532 and metal wiring 534 connecting to the source / drain regions 526. The completed boundary dummy memory array has the same basic design as the main memory array above the substrate 500. The difference is that the doping concentration of the well region 512 is greater than that of the well region 510. This can increase the intrinsic threshold voltage Vth of the boundary dummy memory array and alleviate the over-erase phenomenon.

[0071] In summary, the method of the present invention increases the well concentration of the boundary dummy memory array, thereby increasing its intrinsic threshold voltage (Vth), thereby delaying the erase time of the boundary dummy memory array and mitigating the over-erase phenomenon of the boundary dummy memory array. This reduces leakage in the boundary dummy memory array and ensures current stability during PGM operation. Regarding the method of increasing the well concentration of the boundary dummy memory array, in addition to simply performing an additional implantation process on the boundary dummy memory array, the implantation process can also be performed simultaneously during implantation processes in other areas of the boundary dummy memory array (for example, during the fabrication of a decoder or peripheral components), where the ion implantation process is not originally performed. This not only increases the well concentration of the boundary dummy memory array, but also eliminates the need for additional photomasks and exposure and development processes.

[0072] Although the present invention is disclosed in conjunction with the above embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the attached claims.

Claims

1. A method for increasing the intrinsic threshold voltage of a boundary dummy memory, comprising fabricating a boundary dummy memory array, a main memory array, a decoder, and peripheral components on a substrate, wherein a well region of the boundary dummy memory array and a well region of the main memory array are formed using the same fabrication process, and the method further comprises at least one of the following steps: During the fabrication of the decoder, a first implantation process is simultaneously performed on the substrate within the decoder region and the well region of the boundary dummy memory array to form the well region of the decoder and to make the doping concentration of the well region of the boundary dummy memory array greater than the doping concentration of the well region of the main memory array; During the fabrication of the peripheral element, a second implantation process is simultaneously performed on the substrate within the region of the peripheral element and the well region of the boundary dummy memory array to form the well region of the peripheral element and to make the doping concentration of the well region of the boundary dummy memory array greater than the doping concentration of the well region of the main memory array; A third implantation process is performed on the well region of the boundary dummy memory array to make the doping concentration of the well region of the boundary dummy memory array greater than the doping concentration of the well region of the main memory array.

2. The method of increasing the intrinsic threshold voltage of a boundary virtual memory according to claim 1, wherein the boundary virtual memory array is formed around the main memory array.

3. The method of increasing the intrinsic threshold voltage of a boundary virtual memory as claimed in claim 1, wherein the decoder comprises a row decoder and a column decoder. 4 . The method of claim 1 , wherein the first implantation process is performed before forming the well region of the boundary dummy memory array. 5 . The method of increasing the intrinsic threshold voltage of a boundary virtual memory according to claim 1 , wherein the second implantation process is performed before forming the well region of the boundary virtual memory array. 6 . The method of claim 1 , wherein the second implantation process is performed after forming the well region of the boundary dummy memory array. 7 . The method of claim 1 , wherein the third implantation process is performed before forming the well region of the boundary dummy memory array.

8. The method of increasing the intrinsic threshold voltage of a boundary virtual memory according to claim 1, wherein the third implantation process is performed after forming the well region of the boundary virtual memory array.

9. The method of claim 1, wherein the channel doping concentration in the well region of the boundary dummy memory array is more than twice the doping concentration in the well region of the main memory array.

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