A method for data and resource sharing of a multi-core architecture

Abstract

The application discloses a data and resource sharing method of a multi-core architecture, data interaction between multiple chips is controlled through an HXM (Hardware eXternal Memory) hardware module, a memory mapping mechanism is adopted, data spaces of multiple microcontrollers are divided into corresponding regions, one master controller and multiple slave controllers are composed, and direct access can be realized through an address bus, access efficiency is improved, and software transplantation and expansion are facilitated; multiple microcontrollers are interconnected through a serial bus (such as an SPI, an I2C, a UART and the like), especially, an SPI bus is implemented, handshake request signals and response signals are realized in cooperation with Req and Ack signals defined by the HXM module, and the address and data lines of a traditional memory parallel bus are reduced, and too many IO pin resources are occupied.

Description

Technical Field

[0001] This invention belongs to the technical field of data sharing, and particularly relates to a data and resource sharing method for a multi-core architecture. Background Technology

[0002] With the rapid development of the Internet of Things (IoT) and the Internet of Vehicles (IoV), the demands for data processing volume and computing power are increasing, and the peripheral resources processed by microprocessors can sometimes become extremely complex. Especially during product upgrades, insufficient resources often lead to the predicament of having to completely redesign the product.

[0003] Microcontrollers play a central role in embedded systems. The entire system's control logic, computing power, data throughput, and real-time response are all related to the microcontroller's resources and computing power. Currently, the design and definition of microcontrollers cannot match the high clock speeds and abundant resources of application processors. Therefore, in practical applications, it is common to encounter situations where the selected microcontroller's resources are insufficient, such as insufficient SRAM, insufficient I / O count, or insufficient number of certain peripheral ports. Furthermore, microcontrollers from different manufacturers are designed and used in different ways, including significant differences in processor architecture, register definitions, and functionality. This often forces embedded developers to start from scratch when crossing platforms or chip series, increasing workload considerably and introducing project risks and uncertainties. Summary of the Invention

[0004] The purpose of this invention is to provide a data and resource sharing method for multi-chip architectures, which solves the problem in complex embedded systems where the computing power of a single microcontroller is insufficient for application requirements, or the number of I / O pins and peripheral interfaces of a single microcontroller is insufficient, or the storage resources of a single microcontroller are limited. This allows embedded developers to easily expand the data space and resources of systems developed on the same platform, adapting to more complex application scenarios.

[0005] To solve the above problems, the technical solution of the present invention is as follows:

[0006] A data and resource sharing method for a multi-core architecture includes:

[0007] Data sharing between different chips can be achieved through the HXM module:

[0008] Configure the master HXM module in the master chip and the slave HXM module in the slave chip;

[0009] The CPU and DMA in the main chip directly access the SRAM and peripheral registers in the slave chip through the main HXM module, thereby expanding the SRAM and peripheral resources of the main chip.

[0010] The slave HXM module is in an idle state by default. When the master HXM module initiates a read / write request, the slave HXM module enters the Cmd state, receives read / write instructions from the master chip, and determines whether the current operation is a read or write operation. The slave HXM module then enters the address check state, receives the address from the master chip, and matches it with the address range in the pre-stored state table. If the accessed range is not in the Lock_S state, the slave HXM module enters the Data state; otherwise, it enters the Hold state. In the Data state, if it is a read operation, data is prepared and sent via the bus; if it is a write operation, data is received via the bus and stored in the target area. Data reception and transmission continue until the master HXM module withdraws the request signal.

[0011] According to one embodiment of the present invention, the HXM module includes a register module, an address translation module, a permission management module, a state machine module, a bus interface module, and a communication interface module;

[0012] The register module is used to define the functions and parameter configurations of the HXM module;

[0013] The address translation module is used for address mapping and chip select control;

[0014] The access control module is used for handling access conflicts in the data sharing area;

[0015] The state machine module is used for the work scheduling of the HXM module;

[0016] The bus interface module is used for data communication within the chip;

[0017] The communication interface module is used for data communication with external chips.

[0018] According to one embodiment of the present invention, the address translation module includes a Region area, an SPI area, and an I2C area;

[0019] The Region area is used to store the address space of the master chip accessing the slave chip;

[0020] The SPI area is used to store the SPI chip select signal corresponding to the address space of the Region.

[0021] The I2C area is used to store device addresses corresponding to different slave chip address spaces;

[0022] The chip address, SPI chip select signal, and device address are configured through the register module;

[0023] When the master chip initiates an access to the slave chip through the bus interface module, the address translation module matches the slave chip address in the Region area according to the access address. If the match is successful, the corresponding SPI chip select signal is selected.

[0024] According to an embodiment of the present invention, the permission management module pre-stores a status table, the status table including address, length, control and access permission fields;

[0025] Here, address and length represent the starting address and length of the access control area;

[0026] The access permissions include an accessed state and an unaccessed state. The change of access permissions is controlled by the Req signal initiated by the main chip and also by the Take signal initiated by the slave chip.

[0027] According to one embodiment of the present invention, the change of access permissions is implemented in the form of a state machine, which includes three states: Free, Lock_M, and Lock_S.

[0028] If the current area's access permission is in the Free state, when the master chip's Req request is responded to by the slave chip, the Free state enters the Lock_M state, indicating that the current area is locked by the master chip, and the Busy signal outputs 1 to indicate that it is in a busy state.

[0029] When the processor of the chip initiates a Take lock request, the Free state enters the Lock_S state, indicating that the current area is locked by the chip, and the Status signal outputs 1 to indicate that it is in a busy state.

[0030] In other cases, the Free state remains unchanged.

[0031] According to one embodiment of the present invention, if the access permission of the current region is in the Lock_M state, the Req request of the main chip is revoked and the current region enters the Free state from the Lock_M state.

[0032] If the current region's access permission is in the Lock_S state, a release request is initiated from the chip, and the current region transitions from the Lock_S state to the Free state.

[0033] According to one embodiment of the present invention, the chip supports one-step locking and two-step locking;

[0034] The step lock is to initiate a read operation on the specified register, the hardware triggers the Take=1 signal, and the Status signal returns to the Lock_S state;

[0035] The two-step lock refers to a write operation of 1 to the Lock / Free register, which triggers the Take=1 signal in the hardware, and then a read operation is initiated to the Lock / Free register. The Status signal returns to the Lock_S state.

[0036] According to an embodiment of the present invention, when the main chip initiates a read / write operation through the bus, the main HXM module enters the address mapping state from the idle state; if the target address matches the region in the pre-stored address, the Req signal is set to 1 and enters the Cmd state; otherwise, the Req signal is set to 0 and the module returns to the idle state.

[0037] In the Cmd state, the main HXM module initiates corresponding read / write commands based on the read / write operation and enters the Addr state;

[0038] The Addr state switches the master HXM module to either Data or Hold state based on the Ack signal from the slave chip. When the target area of ​​the slave chip is idle, the master HXM module enters the Data state; otherwise, the master HXM module enters the Hold state.

[0039] Because the present invention adopts the above technical solution, it has the following advantages and positive effects compared with the prior art:

[0040] 1) In one embodiment of the present invention, the data and resource sharing method of the multi-chip architecture controls the data interaction between multiple chips through the HXM (Hardware Extra-Tertiary Memory) hardware module. It adopts a memory mapping mechanism to divide the data space of multiple microcontrollers into corresponding regions, consisting of one master controller and multiple slave controllers. It can be directly accessed through the address bus, which improves access efficiency and facilitates software portability and expansion. Multiple microcontrollers are interconnected through a serial bus (such as SPI, I2C, UART, etc.). In particular, the implementation of the SPI bus, together with the Req and Ack signals defined by the HXM module, performs handshake request and response signals, reducing the excessive IO pin resources occupied by the huge address and data lines of the traditional memory parallel bus.

[0041] 2) In one embodiment of the present invention, the data and resource sharing method of the multi-core architecture is based on the memory access protocol of the SPI bus, which enables software to directly access the data space of other microcontrollers through addresses, just like accessing the microcontroller's own memory or registers, thereby achieving the purpose of data and resource sharing and expansion.

[0042] 3) In one embodiment of the present invention, the data and resource sharing method of the multi-core architecture supports master and slave modes, can be directly mounted on the bus, supports CPU and DMA access, and supports arbitration mechanism when multiple parties access simultaneously; the data space between different microcontrollers supports mutex lock function, adopts Lock_M and Lock_S hardware dual lock implementation, supports hardware module and bus access, supports one-step lock and two-step lock, and supports interrupt mechanism for mutex lock state change. Attached Figure Description

[0043] Figure 1 This is an overall functional block diagram of the multi-core architecture in one embodiment of the present invention;

[0044] Figure 2 This is a logic block diagram of the HXM module in one embodiment of the present invention;

[0045] Figure 3 This is a schematic diagram of an address translation module in one embodiment of the present invention;

[0046] Figure 4 This is a schematic diagram of the permission management module in one embodiment of the present invention;

[0047] Figure 5 This is a schematic diagram of the state machine of the permission management module in one embodiment of the present invention;

[0048] Figure 6 This is a schematic diagram of the main mode state machine of the HXM module in one embodiment of the present invention;

[0049] Figure 7 This is a schematic diagram of the HXM module slave state machine in one embodiment of the present invention. Detailed Implementation

[0050] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a more detailed explanation of the data and resource sharing method for a multi-core architecture proposed in this invention. The advantages and features of this invention will become clearer from the following description and claims.

[0051] In traditional multi-chip applications, multiple chips interconnect via master-slave communication interfaces. Parallel ports offer high access efficiency, but few chips simultaneously support master-slave mode and consume significant I / O resources. Serial communication requires software overhead for scheduling, resulting in lower access efficiency and real-time performance. Data interaction between multiple chips requires software-defined communication protocols to parse the actual transmitted data, increasing system design complexity. In scenarios involving data sharing between different chips, software is needed to resolve conflicts when the same storage space is accessed by different processors at different times, impacting system efficiency and real-time responsiveness. Typically, the complexity of a system with multiple chips working collaboratively is several times higher than that with a single chip, thus affecting system development difficulty and stability. How to make multi-chip collaboration simpler and more efficient has become a growing concern for embedded developers.

[0052] This embodiment provides a data and resource sharing method for multi-chip architectures. In complex embedded systems, when the computing power of a single microcontroller is insufficient for application requirements, or the number of I / O pins, peripheral interfaces, or storage resources of a single microcontroller are insufficient, embedded developers can easily expand the data space and resources of systems developed on the same platform to adapt to more complex application scenarios.

[0053] Specifically, such as Figure 1 As shown, in this embodiment, data sharing between different chips is mainly achieved through the HXM (Hardware eXternal Memory) hardware module in a multi-chip architecture. Chip IC1 serves as the master system chip, chip IC2 as the slave system chip, and multiple slave system chips such as IC3 and IC4 can also be connected. The entire system adopts a one-master-multiple-slave architecture. The HXM module in the master system chip is configured in master mode, and the HXM modules in the slave system chips are configured in slave mode. The CPU1 and DMA1 of the master system chip IC1 can directly access the SRAM2 and peripheral registers in the slave system chip IC2 through the HXM module, allowing the master system chip to easily expand its SRAM and peripheral resources.

[0054] like Figure 2As shown, the HXM (Hardware eXternal Memory) hardware module mainly consists of a register module, an address translation module, a locker module, a state machine module, a bus interface module, and an SPI interface module. The register module defines the main functional configuration of the HXM module; the address translation module is responsible for address mapping and chip select control; the locker module is responsible for handling access conflicts in shared areas; the state machine module is responsible for controlling the overall module's work scheduling; and the bus interface and SPI interface are the internal and external data communication modules, respectively.

[0055] The bus interface is responsible for data exchange with the CPU and is designed primarily according to the buses supported by the processor, such as AHB, APB, and AXI of the AMBA bus. Since the HXM module is directly connected to the CPU bus, it supports both CPU and DMA access modes, in conjunction with the access control module (…). Figure 5 (Details will be provided later), supporting interlocking and arbitration mechanisms for simultaneous access by multiple parties. The communication interface module is responsible for the interface with external chips. It is recommended to choose an interface protocol with high transmission rate and low I / O resources, such as SPI used in this solution, which supports 4-wire transmission mode. This also applies to other commonly used interfaces, such as UART and I2C.

[0056] The register module primarily defines the functions and parameter configurations of the HXM. Other modules initialize and operate based on the parameters configured in the register module. The register module mainly includes parameters such as the address mapping range, the corresponding chip select signal, the corresponding device address, the interlock address and length, the HXM module's master / slave mode, startup, interrupt configuration, etc.

[0057] like Figure 3As shown, the address translation module is illustrated, with each row representing the address mapping relationship of a slave chip. Region represents the address space of the master chip accessing the slave chip; SPI represents the SPI chip select signal corresponding to the address space of the Region, which can support a total of m peripheral slave chips, CS[0], CS[1], ..., CS[m]; I2C represents the device address corresponding to different slave chip address spaces during I2C communication when SPI is not used as the communication interface. This device address is configurable. The slave chip address, chip select signal, and device address can all be configured through the register module. When the master chip initiates an access through the bus module, the address translation module matches the slave chip address of the Region based on the access address. After successful matching, the corresponding SPI chip select signal will be selected. By converting the read and write access of the target address initiated by the bus end into the corresponding SPI interface's CMD, Addr, and Data() functions, the hardware is transformed into the corresponding SPI interface's CMD, Addr, and Data() functions. Figure 6 (This will be explained in detail later), which allows software to directly access the data space of other microcontrollers through addresses, just like accessing the microcontroller's own memory or registers, thus achieving the purpose of data and resource sharing and expansion.

[0058] Figure 4 This is a schematic diagram of the access control module. Each HXM module on the slave chip side has a status table containing four fields: address (Addr), length (Len), control (Ctrl), and access permissions (Lock / Free). Each row represents the access status of a region. Lock indicates that the region is being accessed, and Free indicates that the region is not being accessed. That is, each region corresponds to one Lock / Free access control module, and there are a total of n modules. Addr and Len represent the starting address and length of the access control region, respectively. The boundary of Addr will be aligned with the unit represented by Len. For example, if Len is set to 1KB, the lower 10 bits of Addr will not participate in address matching, that is, Addr[9:0] will not participate in address matching, and only the bits above Addr

[10] will be matched. The Lock / Free access permission transition is controlled by the Req and Ack signals from the master chip and the Take signal from the slave chip. Busy and Status represent the access permissions (Lock / Free) status of the master chip and the slave chip, respectively. The Req and Ack signals are handshake signals from the main chip, initiated and responded to by the HXM module hardware on the main chip side; while the Take signal is initiated from the chip software, that is, the processor accesses the HXM module on the slave chip side for control through the bus.

[0059] Changes in Lock / Free access permissions, such as Figure 5As shown in the state machine, the state machine is divided into three states: Free, Lock_M, and Lock_S. Free indicates that the corresponding area is in an idle state and is not locked. When the request initiated by the master chip (Req=1) is responded to by the slave chip (Ack=1), the Free state enters the Lock_M state, indicating that the area is locked by the master chip, and the Busy signal outputs 1 to indicate that it is in a busy state. When the slave chip's processor initiates a lock request (Take=1), the Free state enters the Lock_S state, indicating that the area is locked by the slave chip, and the Status signal outputs 1 to indicate that it is in a busy state. In other cases, the Free state remains Free.

[0060] If the current region access permission is in the Lock_M state, the Lock_M state will enter the Free state when the main chip's request is revoked (Req=0); otherwise, the Lock_M state will continue to remain in the Lock_M state.

[0061] If the current area access permission is in the Lock_S state, when a release request (Take=0) is initiated from the chip, the Lock_S state will enter the Free state; otherwise, the Lock_S state will continue to remain in the Lock_S state.

[0062] The slave processor supports one-step and two-step locking. One-step locking involves initiating a read operation to the specified register Ctrl, triggering the Take=1 signal in hardware, and simultaneously returning the Lock_S status to the slave processor via the Ctrl register. Two-step locking involves writing 1 to the Lock / Free register, triggering the Take=1 signal in hardware, and then initiating a read operation to the Lock / Free register, returning the Lock_S status.

[0063] Two-step lock operation is intuitive, while one-step lock execution is more efficient and adaptable to different software needs. Changes in both the Busy and Status signals can be configured with interrupt responses, allowing software to respond promptly to and process data area status updates. The design separates Lock_M and Lock_S states, and transitions between them must pass through the Free state. This ensures that access from both master chips does not conflict and that state switching is performed safely through the Free state.

[0064] Figure 6 This describes the state machine of the HXM module on the main chip, illustrating its operation when in master mode. When the main chip initiates a read / write operation (R / W) via the bus, the state machine transitions from the idle state to the address mapping state; if the target address matches... Figure 3If the region in the address translation module matches, the Req signal is set to 1 and the system enters the Cmd state; otherwise, the Req signal is set to 0 and the state machine returns to the Idle state. In the Cmd state, a corresponding read / write instruction is initiated based on the read / write operation (R / W), and then the system enters the Addr state. In the Addr state, based on the Ack signal from the chip, if the region is in the Free state (i.e., Ack = 1), the system enters the Data state; otherwise (Ack = 0), it enters the Hold state. The Hold state remains until the Ack signal becomes 1, after which the system enters the Data state. In the Data state, if it is a read operation (R), data is acquired via SPI or another bus; if it is a write operation (W), data is sent via SPI or another bus. The unit for data reception and transmission is bytes. If there is subsequent continuous data to be read or written (i.e., a single bus operation initiates multiple byte operations), the Continue signal is 1, and the system will continue to remain in the Data state for data transmission and reception; otherwise, the read / write operation is completed, and the Data state transitions to the Idle state. If the address of a bus operation exceeds the region boundary set by the chip, it will be automatically split and return to the Idle state. The part that crosses the region will go through the address mapping and Req / Ack handshake negotiation stage again.

[0065] Figure 7 This describes the state machine of the HXM module at the chip level, i.e., the working principle of the HXM module when it is in slave mode. The slave chip is in an idle state by default. When the master chip initiates a read / write request (Req=1), it enters the Cmd state. The Cmd state receives the read / write command from the master chip, determines whether the operation is a read (R) or write (W), and then enters the address check state. The address check state receives the address from the master chip and compares it with... Figure 4 The address regions in the status table are matched for permissions, and the result is fed back to the Ack signal. If the accessed region is not in the Lock_S state (Status=0), it enters the Data state; otherwise (Status=1), it enters the Hold state. The Hold state will remain until the Status signal becomes 0, at which point it will enter the Data state again. In the Data state, if it is a read operation (R), the SPI or other bus prepares and sends the data; if it is a write operation (W), the SPI or other bus receives the data and stores it in the target region. Data reception and transmission will continue until the master chip requests cancellation (Req=0), at which point the state machine returns to the Idle state. The slave chip's HXM module has the function of initiating bus read and write, so it can directly access the slave chip's SRAM region or peripheral register REG region, thereby realizing data space expansion, including data interaction and data sharing, and also realizing the ability to control other slave chip peripherals.

[0066] The following functions can be achieved through the data and resource sharing methods of the multi-core architecture described above:

[0067] 1. Multiple microcontrollers are processed by the same system, which is equivalent to multiple microcontrollers being combined into a multi-core chip, resulting in greater flexibility;

[0068] 2. Data exchange and sharing between multiple microcontrollers is more convenient. Through the memory mapping mechanism, data can be accessed directly by address. The software can be used as another SRAM memory in the same chip, which is convenient for the business logic control of single system software.

[0069] 3. Through direct access, the master chip can easily read and write the peripheral registers of the slave chip, and can also notify the controller of the slave chip through data structures, thus realizing flexible expansion of peripheral resources and I / O resources;

[0070] 4. When data sharing encounters access conflicts, the hardware sets up a mutex lock, eliminating the need for additional processing logic in the software and improving the efficiency of data access.

[0071] 5. This method features low software overhead and requires fewer hardware pins, making it suitable for various application areas such as product function upgrades, enhanced computing power, and expanded I / O resources. Furthermore, for microcontrollers, it eliminates the need to design multiple products in the same series, enabling a multi-core architecture to meet the diverse product development needs across high, medium, and low-end applications.

[0072] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, if these changes fall within the scope of the claims of the present invention and their equivalents, they shall still fall within the protection scope of the present invention.

Claims

1. A data and resource sharing method for a multi-core architecture, characterized in that, include: Data sharing between different chips can be achieved through the HXM module: Configure the master HXM module in the master chip and the slave HXM module in the slave chip; The CPU and DMA in the main chip directly access the SRAM and peripheral registers in the slave chip through the main HXM module, thereby expanding the SRAM and peripheral resources of the main chip. The slave HXM module is in an idle state by default. When the master HXM module initiates a read or write request, the slave HXM module enters the Cmd state, receives read and write instructions from the master chip, and determines whether the current operation is a read or write operation. The slave HXM module then enters the address check state, receives the address from the master chip, and matches it with the address range in the pre-stored state table. If the accessed range is not in the Lock_S state, the slave HXM module enters the Data state; otherwise, it enters the Hold state. In the Data state, if it is a read operation, data is prepared and sent via the bus; if it is a write operation, data is received via the bus and stored in the target area. Data reception and transmission continue until the master HXM module withdraws the request signal. The HXM module includes a register module, an address translation module, a permission management module, a state machine module, a bus interface module, and a communication interface module. The register module is used to define the functions and parameter configurations of the HXM module; The address translation module is used for address mapping and chip select control; The access control module is used for handling access conflicts in the data sharing area; The state machine module is used for the work scheduling of the HXM module; The bus interface module is used for data communication within the chip; The communication interface module is used for data communication with external chips.

2. The data and resource sharing method for a multi-core architecture as described in claim 1, characterized in that, The address translation module includes a Region area, an SPI area, and an I2C area; The Region area is used to store the address space of the master chip accessing the slave chip; The SPI area is used to store the SPI chip select signal corresponding to the address space of the Region. The I2C area is used to store device addresses corresponding to different slave chip address spaces; The chip address, SPI chip select signal, and device address are configured through the register module; When the master chip initiates an access to the slave chip through the bus interface module, the address translation module matches the slave chip address in the Region area according to the access address. If the match is successful, the corresponding SPI chip select signal is selected.

3. The data and resource sharing method for a multi-core architecture as described in claim 1, characterized in that, The permission management module pre-stores a status table, which includes address, length, control, and access permission fields. Here, address and length represent the starting address and length of the access control area; The access permissions include an accessed state and an unaccessed state. The change of access permissions is controlled by the Req signal initiated by the main chip and also by the Take signal initiated by the slave chip.

4. The data and resource sharing method for a multi-core architecture as described in claim 3, characterized in that, The change of access permissions is implemented in the form of a state machine, which includes three states: Free, Lock_M, and Lock_S. If the current area's access permission is in the Free state, when the master chip's Req request is responded to by the slave chip, the Free state enters the Lock_M state, indicating that the current area is locked by the master chip, and the Busy signal outputs 1 to indicate that it is in a busy state. When the processor of the chip initiates a Take lock request, the Free state enters the Lock_S state, indicating that the current area is locked by the chip, and the Status signal outputs 1 to indicate that it is in a busy state. In other cases, the Free state remains unchanged.

5. The data and resource sharing method for a multi-core architecture as described in claim 4, characterized in that, If the current region's access permission is in the Lock_M state, the main chip's Req request is revoked, and the current region transitions from the Lock_M state to the Free state. If the current region's access permission is in the Lock_S state, a release request is initiated from the chip, and the current region transitions from the Lock_S state to the Free state.

6. The data and resource sharing method for a multi-core architecture as described in claim 4, characterized in that, The chip supports both one-step and two-step locking; The step lock is to initiate a read operation on the specified register, triggering the Take=1 signal in the hardware, while the Status signal returns to the Lock_S state; The two-step lock refers to a write operation of 1 to the Lock / Free register, which triggers the Take=1 signal in the hardware, and then a read operation is initiated to the Lock / Free register. The Status signal returns to the Lock_S state.

7. The data and resource sharing method for a multi-core architecture as described in claim 1, characterized in that, When the main chip initiates a read / write operation via the bus, the main HXM module enters the address mapping state from the idle state; if the target address matches the region in the pre-stored address, the Req signal is set to 1 and the module enters the Cmd state; otherwise, the Req signal is set to 0 and the module returns to the idle state. In the Cmd state, the master HXM module initiates a corresponding read / write command based on the read / write operation and enters the Addr state; in the Addr state, the master HXM module switches between the Data state and the Hold state based on the Ack signal given by the slave chip; when the target area of ​​the slave chip is idle, the master HXM module enters the Data state. Otherwise, the main HXM module enters the Hold state.

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