substrate structure

Abstract

A substrate structure includes a first electrical contact pad formed on an insulating layer of a substrate body. The first electrical contact pad includes a first pad portion disposed on the insulating layer and at least one first protrusion embedded in the insulating layer, such that the first pad portion is electrically connected to a circuit layer in the insulating layer via a conductive blind via, and the first protrusion is not electrically connected to the circuit layer. The design of the first protrusion is such that the surfaces of the metal layers formed on the insulating layer meet the requirement of being coplanar.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a substrate structure. Background Technology

[0002] In the early development of semiconductor packaging, lead frames were used as carriers for active components, primarily due to their advantages of lower manufacturing costs and higher reliability. However, with the rapid development of the electronics industry, electronic products have become increasingly thinner and smaller in form, and more focused on high performance, high functionality, and high speed. Therefore, to meet the demands for high integration and miniaturization in semiconductor devices, current packaging processes are increasingly replacing lead frames with packaging substrates featuring high-density and fine-pitch circuitry.

[0003] like Figure 1 As shown, a conventional packaging substrate 1 includes a substrate body 10, and a first electrical contact pad 11 and a metal block 12 disposed on the substrate body 10. The substrate body 10 has multiple insulating layers 101 and multiple circuit layers 100, and a second electrical contact pad 102 is formed on the outermost circuit layer 100. Each circuit layer 100 (including the second electrical contact pad 102) is electrically connected to each other via multiple conductive blind vias 103. The first electrical contact pad 11 is disposed on the outermost insulating layer 101 of the substrate body 10 and is electrically connected to the circuit layer 100 via the conductive blind via 103. The metal block 12 is disposed on the outermost insulating layer 101 of the substrate body 10 and is not electrically connected to the circuit layers 100 within the insulating layer 101.

[0004] In a typical fan-out redistribution layer (RDL) process, the conductive blind vias 103 in each layer have slightly concave end faces due to their aspect ratio. Therefore, with each additional layer, the height of the end face of the conductive blind via 103 will be lower than the surface of the insulating layer 101 where it is buried. Consequently, when fabricating the outermost wiring, it will affect the coplanarity of the outermost metal layer surface. That is, the topography effect occurs in the continuous stacked blind via regions (such as the range of the second electrical contact pad 102) and the non-continuous stacked blind via regions (such as the range of the metal block 12 and the first electrical contact pad 11). This coplanarity will determine the chip bonding yield in the subsequent die placement process. For example, when the packaging substrate 1 is a three-layer RDL specification, the coplanarity specification of the outermost metal layer surface (i.e. the metal block 12, the first electrical contact pad 11 and the second electrical contact pad 102) can meet the requirements, that is, the height difference between the metal block 12 (highest surface) and the second electrical contact pad 102 (lowest surface) is less than 2.5 micrometers (um), so the predetermined chip bonding yield can be maintained in the subsequent die placement process.

[0005] However, in the existing packaging substrate 1, if a six-layer RDL process is used, the coplanarity of the metal block 12, the first electrical contact pad 11, and the second electrical contact pad 102 will differ too much. This will cause the coplanarity specifications of the outermost metal layer surface (i.e., the metal block 12, the first electrical contact pad 11, and the second electrical contact pad 102) to not meet the requirements (e.g., the height difference h between the surface of the highest metal block 12 and the surface of the lowest second electrical contact pad 102 is 4 micrometers, which is greater than 2.5 micrometers). This will result in poor chip bonding yield in the subsequent die placement process, for example, causing solder non-wetting.

[0006] Therefore, overcoming the problems of the existing technology has become an urgent issue that needs to be addressed. Summary of the Invention

[0007] In view of the various shortcomings of the prior art, the present invention provides a substrate structure that enables the surfaces of the metal layers formed on the insulating layer to achieve coplanarity.

[0008] The substrate structure of the present invention includes: a substrate body comprising at least one insulating layer and a plurality of circuit layers bonded to the insulating layer, wherein a plurality of conductive blind vias electrically connecting the plurality of circuit layers are formed in the insulating layer; and a first electrical contact pad disposed on the insulating layer, wherein the first electrical contact pad comprises a first pad portion disposed on the insulating layer and at least one first protrusion embedded in the insulating layer, wherein the first pad portion is electrically connected to the circuit layer via the conductive blind vias, and the first protrusion is not electrically connected to the circuit layer.

[0009] In the aforementioned substrate structure, the first protrusion and the first pad are integrally formed, and the first protrusion does not contact the circuit layer.

[0010] In the aforementioned substrate structure, the substrate body further comprises at least one second electrical contact pad located on the insulating layer, such that the second electrical contact pad and the first electrical contact pad are located on the same surface of the insulating layer, and the second electrical contact pad is electrically connected to the circuit layer via the conductive blind via. For example, the volume of the second electrical contact pad and the conductive blind via it is equal to the volume of the first electrical contact pad and the conductive blind via it.

[0011] In the aforementioned substrate structure, the aspect ratio of the first protrusion is smaller than the aspect ratio of the conductive blind via.

[0012] The aforementioned substrate structure also includes a metal block formed on the insulating layer, which is not electrically connected to the circuit layer. For example, the metal block includes a second pad portion disposed on the insulating layer and at least one second protrusion embedded in the insulating layer, and the second protrusion is not electrically connected to the circuit layer. Furthermore, the second protrusion and the second pad portion are integrally formed, and the second protrusion does not contact the circuit layer. The aspect ratio of the second protrusion is smaller than the aspect ratio of the conductive blind via. The volume of the metal block is equal to the volume of the first electrical contact pad and the conductive blind via connected to it.

[0013] As can be seen from the above, in the substrate structure of the present invention, the first electrical contact pad includes a first protrusion embedded in the insulating layer (or the metal block includes a second protrusion embedded in the insulating layer) so that the coplanarity of the metal layer surfaces (i.e., the metal block, the first electrical contact pad, and the second electrical contact pad) located on the same insulating layer meets the requirements, so that the predetermined chip bonding yield can be maintained in the subsequent die placement process. In other words, compared with the prior art, the substrate structure of the present invention can maintain the coplanarity of the outermost metal surface in the multilayer circuit structure, thereby improving the chip bonding yield of the subsequent process. Attached Figure Description

[0014] Figure 1 This is a cross-sectional schematic diagram of an existing packaging substrate.

[0015] Figure 2 This is a cross-sectional schematic diagram of the substrate structure of the present invention.

[0016] Figures 3A to 3C for Figure 2 A top cross-sectional view of the metal block in different embodiments of the substrate structure.

[0017] Explanation of reference numerals in the attached figures

[0018] 1: Packaging substrate

[0019] 10,20:Substrate body

[0020] 100, 200: Line layer

[0021] 101, 201: Insulation layer

[0022] 102,202: Second electrical contact pad

[0023] 103, 203: Conductive blind vias

[0024] 11,21: First electrical contact pad

[0025] 12,22: Metal Block

[0026] 2: Substrate Structure

[0027] 202a: concave part

[0028] 210: First pad

[0029] 211: First convex part

[0030] 220: Second pad

[0031] 221: Second convex part

[0032] A: First Area

[0033] B: Second Area

[0034] C: Third Region

[0035] h,t: height difference. Detailed Implementation

[0036] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0037] It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives achieved by the invention, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention's implementation.

[0038] Figure 2 This is a cross-sectional schematic diagram of the substrate structure 2 of the present invention. Figure 2 As shown, the substrate structure 2 includes a substrate body 20, and at least one first electrical contact pad 21 and at least one metal block 22 disposed on the substrate body 20.

[0039] The substrate body 20 is, for example, a package substrate with a core layer and a circuit structure or a coreless circuit structure. It forms multiple (at least three, such as six) circuit layers 200 on multiple insulating layers 201, such as fan-out redistribution layers (RDLs). A second electrical contact pad 202 is formed on the outermost circuit layer 200, and each circuit layer 200 (including the second electrical contact pad 202) is electrically connected to each other through multiple conductive blind vias 203.

[0040] In this embodiment, the substrate body 20 defines a first region A, a second region B, and a third region C, such that the first electrical contact pad 21 is located in the first region A, the second electrical contact pad 202 is located in the second region B, and the metal block 22 is located in the third region C. For example, the second region B is a continuous stack of multiple blind via regions, and the first region A and the third region C are non-continuous stacks of multiple blind via regions. Therefore, in the second region B, the circuit layer 200 below the second electrical contact pad 202 forms a recess 202a on the surface corresponding to the conductive blind via 203.

[0041] Furthermore, the material forming each of the circuit layers 200 is copper, and each of the insulating layers 201 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or a solder resist such as green paint or ink.

[0042] The first electrical contact pad 21 is disposed on the outermost insulating layer 201 of the substrate body 20 and is electrically connected to the circuit layer 200 via the conductive blind hole 203.

[0043] In this embodiment, the first electrical contact pad 21 includes a first pad portion 210 disposed on the insulating layer 201 and at least one first protrusion 211 embedded in the insulating layer 201, and the first protrusion 211 is not electrically connected to the circuit layer 200. For example, the first protrusion 211 is a column, which is integrally formed with the first pad portion 210, and the first protrusion 211 does not contact the circuit layer 200 in the insulating layer 201. Specifically, during manufacturing, a plurality of openings are first formed on the insulating layer 201, and then the first protrusion 211 and conductive blind vias 203 are formed in the openings by electroplating, and the first pad portion 210 is formed on the insulating layer 201, so as to integrally form the first electrical contact pad 21 including the first protrusion 211 and the first pad portion 210 and the conductive blind via 203.

[0044] Furthermore, the volume of the second electrical contact pad 202 and the conductive blind hole 203 connected thereto is equal to the volume of the first pad portion 210 and the conductive blind hole 203 connected thereto and the first protrusion 211.

[0045] Furthermore, the aspect ratio of the first protrusion 211 is smaller than that of the conductive blind hole 203. For example, the aspect ratio of the first protrusion 211 is less than 1, and the aspect ratio of the conductive blind hole 203 is equal to 1.

[0046] The metal block 22 is disposed on the outermost insulating layer 201 of the substrate body 20 and is not electrically connected to the circuit layer 200 in the insulating layer 201.

[0047] In this embodiment, the metal block 22 includes a second pad 220 disposed on the insulating layer 201 and at least one second protrusion 221 embedded in the insulating layer 201, and the second protrusion 221 is not electrically connected to the circuit layer 200. For example, the second protrusion 221 is a column (such as...). Figure 2 As shown), ring (such as) Figure 3A or Figure 3B As shown), walls (such as) Figure 3C (As shown) or other shapes, which are integrally formed with the second pad portion 220, and the second protrusion 221 does not contact the circuit layer 200 in the insulating layer 201. Specifically, during manufacturing, an opening is first formed on the insulating layer 201, and then the second protrusion 221 and the second pad portion 220 are formed in the opening by electroplating, so as to integrally form a second electrical contact pad 22 including the second protrusion 221 and the second pad portion 220.

[0048] Furthermore, the surfaces of the metal block 22, the first electrical contact pad 21, and the second electrical contact pad 202 are approximately at the same height relative to the surface of the outermost insulating layer 201, i.e., they are coplanar. For example, when the substrate structure 2 is a six-layer RDL, the surfaces of the outermost metal layer (i.e., the surfaces of the metal block 22, the first electrical contact pad 21, and the second electrical contact pad 202) are still coplanar, meaning the height difference t between the surface of the metal block 22 and the surface of the second electrical contact pad 202 is less than 2.5 micrometers (µm). Here, coplanarity means that the height difference t of the outermost metal surface is less than 2.5 micrometers.

[0049] Furthermore, the volume of the second pad 220 and the second protrusion 221 connected thereto is equal to the volume of the first pad 210 and the conductive blind hole 203 connected thereto and the first protrusion 211.

[0050] Furthermore, the aspect ratio of the second protrusion 221 is smaller than that of the conductive blind hole 203. For example, the aspect ratio of the second protrusion 221 is less than 1, and the aspect ratio of the conductive blind hole 203 is equal to 1.

[0051] Therefore, the substrate structure 2 of the present invention is mainly designed through the first protrusion 211 (or the second protrusion 221) so that the metal block 22, the first electrical contact pad 21 (and the conductive blind via 203 connected thereto) and the second electrical contact pad 202 (and the conductive blind via 203 connected thereto) on the outermost insulating layer 201 can be electroplated to the same volume, so that the coplanarity of the metal layer surface (i.e. the surface of the metal block 22, the surface of the first electrical contact pad 21 and the surface of the second electrical contact pad 202) meets the requirements. Therefore, in the subsequent die placement process, the predetermined chip bonding yield can be maintained. Therefore, compared with the prior art, if a six-layer RDL process is used, the metal block 22, the first electrical contact pad 21 and the second electrical contact pad 202 of the present invention are still coplanar, so as to improve the chip bonding yield in the subsequent die placement process, for example, to avoid the problem of non-wetting of solder.

[0052] It should be understood that, through the design of the protrusion, the metal surfaces of the same layer can be made to be coplanar, so the metal block 22, the first electrical contact pad 21 and the second electrical contact pad 202 can be formed on any insulating layer 201 as required, and are not limited to the outermost insulating layer 201.

[0053] In summary, the substrate structure of the present invention, through the first electrical contact pad including a first protrusion embedded in the insulating layer (or the metal block including a second protrusion embedded in the insulating layer), ensures that the coplanarity of the metal layer surfaces (i.e., the surface of the metal block, the surface of the first electrical contact pad, and the surface of the second electrical contact pad) located on the same insulating layer meets the requirements, so as to maintain a predetermined chip bonding yield in the subsequent die placement process. In other words, the substrate structure of the present invention can maintain the coplanarity of the outermost metal surface in a multilayer circuit structure, thereby improving the chip bonding yield in the subsequent die placement process.

[0054] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the claims.

Claims

1. A substrate structure, characterized in that, include: The substrate body includes at least one insulating layer and a plurality of circuit layers bonded to the insulating layer, and a plurality of conductive blind vias electrically connecting the plurality of circuit layers are formed in the insulating layer. At least one first electrical contact pad is disposed on the insulating layer, and the first electrical contact pad includes a first pad portion disposed on the insulating layer and at least one first protrusion embedded in the insulating layer, wherein the first pad portion is electrically connected to the circuit layer via the conductive blind via, and the first protrusion is not electrically connected to the circuit layer; and A metal block formed on the insulating layer, wherein the volume of the metal block is equal to the volume of the first electrical contact pad and the conductive blind hole connected thereto.

2. The substrate structure as described in claim 1, characterized in that, The first protrusion and the first pad are integrally formed, and the first protrusion does not contact the circuit layer.

3. The substrate structure as described in claim 1, characterized in that, The substrate body also has at least one second electrical contact pad located on the insulating layer, such that the second electrical contact pad and the first electrical contact pad are located on the same surface of the insulating layer, and the second electrical contact pad is electrically connected to the circuit layer via the conductive blind via.

4. The substrate structure as described in claim 3, characterized in that, The volume of the second electrical contact pad and the conductive blind hole connected thereto is equal to the volume of the first electrical contact pad and the conductive blind hole connected thereto.

5. The substrate structure as described in claim 1, characterized in that, The aspect ratio of the first protrusion is smaller than that of the conductive blind hole.

6. The substrate structure as described in claim 1, characterized in that, The metal block is not electrically connected to the circuit layer.

7. The substrate structure as described in claim 6, characterized in that, The metal block includes a second pad portion disposed on the insulating layer and at least one second protrusion embedded in the insulating layer, wherein the second protrusion is not electrically connected to the circuit layer.

8. The substrate structure as described in claim 7, characterized in that, The second protrusion and the second pad are integrally formed, and the second protrusion does not contact the circuit layer.

9. The substrate structure as described in claim 7, characterized in that, The aspect ratio of the second protrusion is smaller than that of the conductive blind hole.

Images