A driving circuit for a display panel, a display device and an electronic device

Abstract

The present disclosure relates to a driving circuit, a display device and an electronic device for a display panel. The driving circuit includes: a timing control module, a pixel driving module, and at least two row buffer modules; the timing control module is used to sequentially control at least two row buffer modules, and update the pixel data stored inside the row buffer module according to at least two first pixel data; according to a preset algorithm, at least one row buffer module corresponding to the current moment is determined and driven, and a set of target pixel data is output to the pixel driving module; the pixel driving module is used to generate and output the second pixel data corresponding to each set of target pixel data to the display panel according to at least two sets of target pixel data output by at least two row buffer modules. The driving circuit provided by the present disclosure enables the display panel to support the display of input images of multiple resolutions.

Description

Technical Field

[0001] The present disclosure relates to the field of display panels, and in particular to a driving circuit of a display panel, a display device, and an electronic device. Background Art

[0002] With the continuous development of communication technology, the speed of display device replacement is getting faster and faster, and the resolution of display devices is also constantly improving. In existing display devices, display devices generally do not support the conversion of multiple resolutions, resulting in that when the resolution of the image input to the display device is different from the screen resolution of the display device, the display device cannot drive the screen of the display device to display the corresponding image according to the data of the input image.

[0003] In view of this, the present disclosure provides a driving circuit for a display panel to solve the problem that existing display devices cannot support the display of input images with multiple resolutions. Summary of the invention

[0004] According to one aspect of the present disclosure, a driving circuit of a display panel is provided, the driving circuit comprising: a timing control module, a pixel driving module, and at least two row buffer modules; the input end of each row buffer module is electrically connected to the timing control module, and the output end of each row buffer module is electrically connected to the pixel driving module; the timing control module is used to control the at least two row buffer modules in sequence, and update the pixel data stored inside the row buffer modules according to at least two first pixel data; according to a preset algorithm, determine and drive at least one row buffer module corresponding to the current moment, and output a set of target pixel data to the pixel driving module; wherein the first pixel data corresponds to a row of pixels in an input image; the pixel driving module is used to generate and output second pixel data corresponding to each set of the target pixel data to the display panel according to at least two sets of target pixel data output by at least two row buffer modules; wherein the second pixel data is used to drive pixel rows of a display panel, and the resolution of the display panel is greater than the resolution of the input image.

[0005] In a possible embodiment, the timing control module is also used to: input the at least two first pixel data into the at least two row cache modules in sequence according to the first timing signal; and determine a pixel row to be driven corresponding to the current moment according to the second timing signal; determine the correspondence between the first pixel data and each pixel row in the display panel according to the preset algorithm; determine at least one of the first pixel data corresponding to the current moment according to the correspondence and the pixel row to be driven corresponding to the current moment; use the at least one first pixel data corresponding to the current moment as the set of target pixel data; and determine at least one of the row cache modules used to store the set of target pixel data as the at least one row cache module corresponding to the current moment.

[0006] In a possible embodiment, the timing control module is also used to: when there is at least one row cache module in the row cache module corresponding to the current moment that does not store the target pixel data, extend the period of the current timing pulse in the second timing signal until the target pixel data is stored in all the row cache modules corresponding to the current moment.

[0007] In a possible embodiment, the pixel driving module is also used to receive at least two groups of target pixel data output by the at least two row cache modules; generate second pixel data corresponding to each group of the target pixel data based on the at least two groups of target pixel data; and output the second pixel data corresponding to each group of the target pixel data in sequence to the corresponding pixel rows in the display panel based on the input timing of each group of the target pixel data.

[0008] In a possible embodiment, the pixel driving module includes: a data cache unit, whose input end is electrically connected to the output end of each of the row cache modules, and is used to store the target pixel data output by the at least two row cache modules; and uses the input order of the target pixel data as the output order of the at least two groups of target pixel data; according to the output order, outputs the at least two groups of target pixel data in sequence to the data generation unit; and a data generation unit, whose input end is electrically connected to the data cache unit, and whose output end is electrically connected to the display panel, and is used to generate second pixel data corresponding to each group of the target pixel data according to a preset data calculation method and the at least two groups of target pixel data output by the data cache unit; and outputs each of the second pixel data in sequence to the display panel according to the input timing of each group of the target pixel data.

[0009] In a possible implementation, the first pixel data includes a plurality of first pixel sub-data; wherein the first pixel sub-data corresponds to a pixel point in the input image; the timing control module includes: a first timing generation unit, a second timing generation unit, and a control unit; the first timing generation unit and the second timing generation unit are both electrically connected to the control unit; the first timing generation unit is used to generate and output a first timing signal to the control unit; the second timing generation unit is used to generate and output a second timing signal to the control unit; the control unit is used to sequentially input the at least two first pixel data into the at least two row buffer modules according to the first timing signal; and determine at least one row buffer module corresponding to the current moment according to the second timing signal and a preset algorithm; and generate and sequentially output at least one output control signal to at least one row buffer module corresponding to the current moment according to the second timing signal, drive the at least one row buffer module corresponding to the current moment, and output a set of target pixel data to the pixel driving module; wherein each of the output control signals is used to control at least one row buffer module corresponding to the current moment to output a first preset number of the first pixel sub-data corresponding to the target pixel data to the pixel driving module.

[0010] In a possible implementation, the data cache unit includes at least one cache, each cache is used to receive the first pixel sub-data output by different row cache modules, and determine and output the first pixel sub-data corresponding to the current moment to the data generation unit according to a preset algorithm.

[0011] In a possible implementation, the control unit is also used to shorten the time interval between the output control signal output at the current moment and the output control signal corresponding to the next moment when the number of the first pixel sub-data stored in any of the buffers is less than or equal to a second preset number.

[0012] In a possible implementation, the second preset number is positively correlated with the number of pixels in each row of the input image and the number of pixel units driven within the minimum operation time of the display panel, and is negatively correlated with the number of pixels in each row of the display panel.

[0013] In a possible implementation, the data cache unit is further used to: when storing a first preset number of first pixel sub-data corresponding to the target pixel data output by the at least two row cache modules, output at least one of the first pixel sub-data to the data generation unit.

[0014] In a possible implementation, the timing control module is further used to: when the at least two row cache modules store at least two of the first pixel data, determine and drive at least one of the row cache modules corresponding to the current moment according to a preset algorithm, and output a set of target pixel data to the pixel driving module.

[0015] According to another aspect of the present disclosure, a display device is further provided, comprising a plurality of display units and at least one driving circuit as described in any one of the foregoing descriptions.

[0016] In a possible embodiment, the display unit includes a display panel, and the display panel includes at least one of a liquid crystal display panel, a micro light emitting diode display panel, a light emitting diode display panel, a mini light emitting diode display panel, a quantum dot light emitting diode display panel, an organic light emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel and a small pitch display panel.

[0017] According to another aspect of the present disclosure, an electronic device is further provided, and the electronic device includes the display device mentioned above.

[0018] The driving circuit of the display panel provided by the present disclosure can drive the display panel to display a corresponding image according to an input image with a resolution of 1 to 0.5 times the resolution of the display panel through at least two row cache modules and a preset algorithm, thereby enabling the display panel to support the display of input images with multiple resolutions.

[0019] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0021] Figure 1 A schematic diagram of the structure of a driving circuit provided in an embodiment of the present disclosure.

[0022] Figure 2 A schematic diagram of the structure of a driving circuit provided in an embodiment of the present disclosure.

[0023] Figure 3 A schematic diagram of the structure of a driving circuit provided in an embodiment of the present disclosure.

[0024] Figure 4 A schematic diagram of the structure of a driving circuit provided in an embodiment of the present disclosure.

[0025] Figure 5 A schematic diagram of the structure of a driving circuit provided in an embodiment of the present disclosure.

[0026] Figure 6 A waveform diagram of a second timing signal provided in an embodiment of the present disclosure.

[0027] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0029] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0030] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0031] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0032] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0033] See also Figure 1 As shown, Figure 1 The present disclosure provides a driving circuit 1 for a display panel, which comprises: a timing control module 11, a pixel driving module 13, and at least two row buffer modules 12. The input end of each row buffer module 12 is electrically connected to the timing control module 11, and the output end of each row buffer module 12 is electrically connected to the pixel driving module 13.

[0034] Exemplarily, the timing control module 11 is used to sequentially control at least two row buffer modules 12, and update the pixel data stored in the row buffer module 12 according to the plurality of first pixel data. According to the preset algorithm, a row buffer module 12 corresponding to the current moment is determined and driven, and a set of target pixel data is output to the pixel driving module 13. Among them, the first pixel data corresponds to a row of pixels in the input image.

[0035] For example, see Figure 2 As shown, the resolution of the input image A is 6 6 (i.e., the input image includes 6 pixel rows and 6 pixel columns), and the driving circuit 1 includes four row buffer modules 12 (i.e., row buffer module A, row buffer module B, row buffer module C, and row buffer module D) as an example, when the driving circuit 1 receives the input image A, the timing control module 11 controls the row buffer module A to receive the first row of pixel data of the input image A. The row buffer module B is controlled to receive the second row of pixel data of the input image A. The row buffer module C is controlled to receive the third row of pixel data of the input image A. The row buffer module D is controlled to receive the fourth row of pixel data of the input image A. When the timing control module 11 needs to store the fifth row of pixel data of the input image A in the row buffer module 12, the timing control module 11 controls the row buffer module A to update the first pixel data stored therein to the fifth row of pixel data of the input image A. When the timing control module 11 needs to store the sixth row of pixel data of the input image A in the row buffer module 12, the timing control module 11 controls the row buffer module B to update the first pixel data stored therein to the sixth row of pixel data of the input image A.

[0036] For example, see Figure 1 as well as Figure 2 As shown, when the timing control module 11 starts to instruct the row buffer module 12 to output the first pixel data to the pixel driving module 13, the timing control module 11 can determine that the current moment t1 corresponds to the pixel row X1 (i.e., the first row of pixel units in the display panel 2) according to a preset algorithm, and determine that the pixel row X1 corresponds to the first row of pixel data and the second row of pixel data of the input image A. At this time, the timing control module 11 drives the row buffer module A and the row buffer module B to output the first row of pixel data and the second row of pixel data of the input image A (i.e., a set of target pixel data).

[0037] For example, the preset algorithm is used to represent the correspondence between each pixel row in the display panel 2 and each row of pixel data in the input image. The specific correspondence method can be determined as needed. 4. The resolution of input image A is 3 3 as an example, the timing control module 11 can determine, according to a preset algorithm, that the pixel data of the first pixel row of the display panel 2 corresponds to the first pixel data of the input image A and the second pixel data. Determine that the pixel data of the second pixel row of the display panel 2 corresponds to the first pixel data of the input image A and the second pixel data. Determine that the pixel data of the third pixel row of the display panel 2 corresponds to the second pixel data of the input image A and the third pixel data. Determine that the pixel data of the fourth pixel row of the display panel 2 corresponds to the third pixel data of the input image A.

[0038] Exemplarily, the pixel driving module 13 is used to generate and output second pixel data corresponding to each set of target pixel data to the display panel 2 according to at least two sets of target pixel data output by at least two row buffer modules 12. The second pixel data is used to drive the pixel rows of the display panel 2, and the resolution of the display panel 2 is greater than or equal to the resolution of the input image.

[0039] For example, the resolution of the display panel 2 is 4 4. The resolution of input image A is 3 3 as an example, at time t1, the timing control module 11 determines that at least one row buffer module 12 corresponding to the current time is a row buffer module A and a row buffer module B, and controls the row buffer module A and the row buffer module B to output the first row pixel data and the second row pixel data (i.e., a set of target pixel data) of the input image A to the pixel driving module 13. The pixel driving module 13 generates the pixel data corresponding to the first pixel row in the display panel 2 according to the set of target display data corresponding to time t1, and outputs the pixel data corresponding to the first pixel row in the display panel 2 to the display panel 2 to drive each pixel unit in the first pixel row of the display panel 2. At time t2, the timing control module 11 determines that at least one row buffer module 12 corresponding to the current time is also a row buffer module A and a row buffer module B, and controls the row buffer module A and the row buffer module B to output the first row pixel data and the second row pixel data (i.e., a set of target pixel data) of the input image A to the pixel driving module 13. The pixel driving module 13 generates pixel data corresponding to the second pixel row in the display panel 2 according to a set of target display data corresponding to the time t2, and outputs the pixel data corresponding to the second pixel row in the display panel 2 to the display panel 2, so as to drive each pixel unit in the second pixel row of the display panel 2. At the time t3, the timing control module 11 determines that at least one row buffer module 12 corresponding to the current time is the row buffer module B and the row buffer module C, and controls the row buffer module B and the row buffer module C to output the second row pixel data and the third row pixel data (i.e., a set of target pixel data) of the input image A to the pixel driving module 13. The pixel driving module 13 generates pixel data corresponding to the third pixel row in the display panel 2 according to a set of target display data corresponding to the time t3, and outputs the pixel data corresponding to the third pixel row in the display panel 2 to the display panel 2, so as to drive each pixel unit in the third pixel row of the display panel 2. At the time t4, the timing control module 11 determines that at least one row buffer module 12 corresponding to the current time is the row buffer module C, and controls the row buffer module C to output the third row pixel data (i.e., a set of target pixel data) of the input image A to the pixel driving module 13. The pixel driving module 13 generates pixel data corresponding to the fourth pixel row in the display panel 2 according to a set of target display data corresponding to time t4, and outputs the pixel data corresponding to the fourth pixel row in the display panel 2 to the display panel 2 to drive each pixel unit in the fourth pixel row of the display panel 2.

[0040] The driving circuit of the display panel provided by the present disclosure can drive the display panel to display a corresponding image according to an input image with a resolution of 1 to 0.5 times the resolution of the display panel through at least two row cache modules and a preset algorithm, thereby enabling the display panel to support the display of input images with multiple resolutions.

[0041] In one possible implementation, see Figure 1 as well as Figure 2 As shown, the timing control module 11 is also used to input multiple first pixel data into at least two row buffer modules 12 in sequence according to the first timing signal. And according to the second timing signal, determine a pixel row to be driven corresponding to the current moment. According to a preset algorithm, determine the correspondence between the first pixel data and each pixel row in the display panel. According to the correspondence and a pixel row to be driven corresponding to the current moment, determine at least one first pixel data corresponding to the current moment. Take the at least one first pixel data corresponding to the current moment as a group of target pixel data. Determine at least one row buffer module 12 for storing a group of target pixel data as the at least one row buffer module 12 corresponding to the current moment.

[0042] For example, the resolution of the input image A is 3 3. The resolution of display panel 2 is 4 4 as an example, the timing control module 11 determines the pixel row to be driven in the display panel 2 at the current moment according to the timing pulse in the second timing signal corresponding to the current moment. For example: if the current moment corresponds to the first timing pulse of the second timing signal, the pixel row to be driven in the display panel 2 at the current moment is determined to be the first pixel row, and if the current moment corresponds to the second timing pulse of the second timing signal, the pixel row to be driven in the display panel 2 at the current moment is determined to be the second pixel row. Taking the case where the pixel row to be driven in the display panel 2 at the current moment is the second pixel row, the timing control module 11 can determine the correspondence between the first pixel data and each pixel row in the display panel 2 according to a preset algorithm, and the correspondence can be found in the exemplary content above. Based on the correspondence and the pixel row to be driven in the display panel 2 at the current moment, it can be determined that at least one first pixel data corresponding to the current moment is the first row of pixel data and the second row of pixel data of the input image A. At this time, the first row of pixel data and the second row of pixel data of the input image A are taken as a group of target pixel data, and the row buffer module A storing the first row of pixel data of the input image A and the row buffer module B storing the second row of pixel data of the input image A are determined to be at least one row buffer module 12 corresponding to the current moment. When the timing control module 11 receives the second timing pulse of the second timing signal, it starts to drive the row buffer module A and the row buffer module B to output a group of target pixel data (i.e., the first row of pixel data and the second row of pixel data of the input image A) to the pixel driving module 13.

[0043] In one possible implementation, see Figure 1 to Figure 2As shown, the timing control module 11 is also used to extend the period of the current timing pulse in the second timing signal when there is at least one row cache module 12 in the row cache module 12 corresponding to the current moment that does not store the target pixel data, until the target pixel data is stored in all the row cache modules 12 corresponding to the current moment.

[0044] For example, if the row buffer modules 12 corresponding to the current moment are row buffer modules B and row buffer modules C, and the target pixel data are the sixth row pixel data and the seventh row pixel data of the input image A, if the row buffer module B does not store the sixth row pixel data of the input image A, and / or the row buffer module C does not store the seventh row pixel data of the input image A, then the timing control module 11 extends the period of the current timing pulse Tn in the second timing signal (see Figure 6 As shown), until the sixth line of pixel data of the input image A is stored in the row buffer module B, and the seventh line of pixel data of the input image A is stored in the row buffer module C.

[0045] For example, taking the fifth row of pixel data and the sixth row of pixel data of the input image A corresponding to the fifth row of pixels of the display panel 2, and the pixel behavior that needs to be driven in the display panel at the current moment as an example, if the timing control module 11 updates the fifth row of pixel data and the sixth row of pixel data to the row cache module A and the row cache module B respectively before the current timing pulse T5 of the second timing signal, the timing control module 11 can control the row cache module A and the row cache module B to output a set of target pixel data E (including the fifth row of pixel data and the sixth row of pixel data of the input image A) to the pixel driving module 13 according to the current timing pulse T5 of the second timing signal, and the pixel driving module 13 generates a second pixel data (corresponding to the fifth row of pixels of the display panel 2) according to the set of target pixel data E. If the fifth row of pixel data of the input image A is not stored in the row cache module A, and / or the sixth row of pixel data of the input image A is not stored in the row cache module B, the timing control module 11 extends the period of the current timing pulse T5 in the second timing signal until the fifth row of pixel data of the input image A is stored in the row cache module A, and / or the sixth row of pixel data of the input image A is stored in the row cache module B.

[0046] The driving circuit provided by the present disclosure can determine whether the target pixel data is stored in the row cache module corresponding to the current moment, and if the target pixel data is not stored, extend the period of the current timing pulse of the second timing signal until the row cache modules corresponding to the current moment store the corresponding target pixel data, thereby ensuring that the driving circuit can drive the pixel row to be driven according to the corresponding first pixel data, and prevent the row cache module from outputting the first pixel data that does not correspond to the current pixel row to be driven when the row cache module has not yet stored the target pixel data, causing the display error of the display panel.

[0047] In one possible implementation, see Figure 3 As shown, the timing control module 11 includes: a first timing generation unit 111, a second timing generation unit 112 and a control unit 113. The first timing generation unit 111 and the second timing generation unit 112 are both electrically connected to the control unit 113.

[0048] Exemplarily, the first timing generation unit 111 is used to generate and output a first timing signal to the control unit. The second timing generation unit 112 is used to generate and output a second timing signal to the control unit 113. The control unit 113 is used to sequentially input a plurality of first pixel data into at least two row buffer modules 12 according to the first timing signal. And according to the second timing signal and the preset algorithm, determine at least one row buffer module 12 corresponding to the current moment. According to the second timing signal, generate and sequentially output at least one output control signal to at least one row buffer module 12 corresponding to the current moment, drive at least one row buffer module 12 corresponding to the current moment, and output a set of target pixel data to the pixel driving module. Wherein, each output control signal is used to control at least one row buffer module 12 corresponding to the current moment, and output a first preset number of first pixel sub-data corresponding to the target pixel data to the pixel driving module 13.

[0049] For example, see Figure 2 as well as Figure 3 As shown, the resolution of the input image A is 6 6 as an example, the first timing generation unit 111 generates a first timing signal and outputs it to the control unit 113. The control unit 113 writes the first row of pixel data of the input image A into the row buffer module A according to the first timing pulse in the first timing signal. The control unit 113 writes the second row of pixel data of the input image A into the row buffer module B according to the second timing pulse in the first timing signal. The control unit 113 writes the third row of pixel data of the input image A into the row buffer module C according to the third timing pulse in the first timing signal. The control unit 113 writes the fourth row of pixel data of the input image A into the row buffer module D according to the fourth timing pulse in the first timing signal. The control unit 113 writes the fifth row of pixel data of the input image A into the row buffer module A according to the fifth timing pulse in the first timing signal (the row buffer module A updates the first pixel data stored internally to the fifth row of pixel data of the input image A). The control unit 113 writes the sixth row of pixel data of the input image A into the row buffer module B according to the sixth timing pulse in the first timing signal (the row buffer module B updates the first pixel data stored internally to the sixth row of pixel data of the input image A).

[0050] Exemplarily, the first timing signal may be a row synchronization signal of the display panel 2 .

[0051] Exemplarily, the timing pulse of the second timing signal is equivalent to a trigger signal of the row buffer module.

[0052] Exemplarily, the control unit 113 generates at least one output control signal to the row buffer module A and the row buffer module B according to the current timing pulse T1 of the second timing signal, and controls the row buffer module A and the row buffer module B to output a set of target pixel data A (including the first row of pixel data and the second row of pixel data of the input image A) to the pixel driving module 13. The control unit 113 starts to generate at least one output control signal to the row buffer module A and the row buffer module B according to the current timing pulse T2 of the second timing signal, and controls the row buffer module A and the row buffer module B to output a set of target pixel data B (including the first row of pixel data and the second row of pixel data of the input image A) to the pixel driving module 13. The control unit 113 generates at least one output control signal to the row buffer module B and the row buffer module C according to the current timing pulse T3 of the second timing signal, and controls the row buffer module B and the row buffer module C to output a set of target pixel data C (including the second row of pixel data and the third row of pixel data of the input image A) to the pixel driving module 13.

[0053] Exemplarily, the control unit 113 generates at least one output control signal to the row buffer module C according to the current timing pulse T4 of the second timing signal, and controls the row buffer module C to output a set of target pixel data D (including the third row of pixel data of the input image A) to the pixel driving module 13.

[0054] Exemplarily, the first pixel data includes a plurality of first pixel sub-data. The first pixel sub-data corresponds to a pixel point in the input image. Assuming that the resolution of the input image A is 100 100, the resolution of display panel 2 is 150 Taking 120 as an example, the first row of pixel data of the input image A includes 100 first pixel sub-data, and each first pixel sub-data corresponds to a pixel point of the input image A.

[0055] For example, the resolution of the input image A is 100 100, the resolution of display panel 2 is 150 120 as an example, the control unit 113 determines at least one row cache module corresponding to the current moment according to the second timing signal and the preset algorithm. The details of this process can be found in the following content. When the control unit 113 determines that at least one row cache module corresponding to the current moment is row cache module A and row cache module B, after receiving the second timing signal, the control unit 113 can generate and sequentially output at least one output control signal to row cache module A and row cache module B according to a preset frequency. If each output control signal can drive row cache module A to output four (i.e., the first preset number) first pixel sub-data to the pixel driving module 13, and drive row cache module B to output four first pixel sub-data to the pixel driving module 13, then the row cache module A and row cache module B are controlled to output image A (i.e., the resolution is 100 100) to the data buffer unit 131, 25 output control signals are required.

[0056] Exemplarily, the specific value of the first preset number can be determined according to actual conditions, and the present disclosure does not limit this.

[0057] In one possible implementation, see Figures 1 to 4 As shown, the pixel driving module 13 is also used to receive at least two groups of target pixel data outputted by at least two row buffer modules 12 at different times. According to the at least two groups of target pixel data, second pixel data corresponding to each group of target pixel data is generated. According to the input timing of each group of target pixel data, the second pixel data corresponding to each group of target pixel data is sequentially outputted to the corresponding pixel row in the display panel 2.

[0058] Exemplarily, taking the above-mentioned row buffer module A to row buffer module D sequentially outputting a group of target pixel data A to a group of target pixel data D as an example, the pixel driving module 13 generates the second pixel data A according to the group of target pixel data A, generates the second pixel data B according to the group of target pixel data B, generates the second pixel data C according to the group of target pixel data C, and generates the second pixel data D according to the group of target pixel data D. Since the above four groups of target pixel data are input into the pixel driving module 13 in the order of A, B, C, and D, the pixel driving module 13 first outputs the second pixel data A, then the second pixel data B, then the second pixel data C, and finally the second pixel data D.

[0059] In one possible implementation, see Figures 1 to 5 As shown, the pixel driving module 13 includes: a data buffer unit 131 and a data generating unit 132 .

[0060] Exemplarily, the input end of the data cache unit 131 is electrically connected to the output end of each row buffer module 12. The data cache unit 131 is used to store at least two groups of target pixel data output by at least two row buffer modules 12. The input order of the at least two groups of target pixel data is used as the output order of the at least two groups of target pixel data. According to the output order, the at least two groups of target pixel data are sequentially output to the data generation unit 132.

[0061] For example, the resolution of the input image A in the above text is 3 3 as an example, the data buffer unit 131 is used to store the above-mentioned group of target pixel data A, group of target pixel data B, group of target pixel data C, and group of target pixel data D. The input order of each group of target pixel data is used as the output order of each group of target pixel data, that is, a group of target pixel data A is output to the data generating unit 132 first, then a group of target pixel data B is output to the data generating unit 132, then a group of target pixel data C is output to the data generating unit 132, and finally a group of target pixel data D is output to the data generating unit 132.

[0062] Exemplarily, the input end of the data generating unit 132 is electrically connected to the output end of the data buffer unit 131, and the output end thereof is electrically connected to the display panel 2. The data generating unit 132 is used to generate second pixel data corresponding to each set of target pixel data according to a preset data calculation method and at least two sets of target pixel data output by the data buffer unit 131. Each second pixel data is sequentially output to the display panel 2 according to the input timing of each set of target pixel data.

[0063] Exemplarily, the data generating unit 132 may calculate the first row of pixel data and the second row of pixel data of the input image A in a set of target pixel data A according to a preset data calculation method to generate pixel data A (i.e., pixel data corresponding to the first pixel row of the display panel 2). The first row of pixel data and the second row of pixel data of the input image A in a set of target pixel data B are calculated to generate second pixel data B (i.e., pixel data corresponding to the second pixel row of the display panel 2). The second row of pixel data and the third row of pixel data of the input image A in a set of target pixel data C are calculated to generate second pixel data C (i.e., pixel data corresponding to the third pixel row of the display panel 2). The third row of pixel data of the input image A in a set of target pixel data D is calculated to generate second pixel data D (i.e., pixel data corresponding to the fourth pixel row of the display panel 2). The data generating unit 132 may output the second pixel data A, the second pixel data B, the second pixel data C, and the second pixel data D to the display panel 2 in sequence according to the input timing of the above-mentioned sets of target pixel data.

[0064] Exemplarily, the above-mentioned preset data calculation method can be determined according to the ratio of the resolution of the display panel 2 to the resolution of the input image, or according to the position of the pixel row to be driven by the current display panel 2, which is not limited in the present disclosure.

[0065] In a possible implementation, the data cache unit 131 includes at least one cache, each cache is used to receive the first pixel sub-data output by different row cache modules, and determine and output the first pixel sub-data corresponding to the current moment to the data generation unit 132 according to a preset algorithm.

[0066] For example, see Figure 4 as well as Figure 5 As shown, the data cache unit 131 includes: a first cache 1311 and a second cache 1312 .

[0067] The input end of the first buffer 1311 is electrically connected to the output end of at least one line buffer module 12, and the output end thereof is electrically connected to the input end of the data generation unit 132. The first buffer 1311 is used to receive the first pixel sub-data outputted by one of the at least one line buffer modules 12 corresponding to the current moment. And according to the preset algorithm, the first pixel sub-data corresponding to the current moment is determined and outputted to the data generation unit 132. The input end of the second buffer 1312 is electrically connected to the output end of at least one line buffer module 12, and the output end thereof is electrically connected to the input end of the data generation unit 132. The second buffer 1312 is used to receive the first pixel sub-data outputted by one of the at least one line buffer modules 12 corresponding to the current moment. And according to the preset algorithm, the first pixel sub-data corresponding to the current moment in the target pixel data is determined and outputted to the data generation unit 132. Among them, the first buffer 1311 and the second buffer 1312 are used to receive the first pixel sub-data outputted by different line buffer modules 12.

[0068] Exemplarily, the first buffer 1311 and the second buffer 1312 may be FIFO buffers (first in first out). Taking the example that the driving circuit 1 includes a row buffer module A, a row buffer module B, a row buffer module C, and a row buffer module D, the input end of the first buffer 1311 is electrically connected to the output end of the row buffer module A and the row buffer module C, and the first buffer 1311 is used to receive the target pixel data output by the row buffer module A and the row buffer module C. The input end of the second buffer 1312 is electrically connected to the output end of the row buffer module B and the row buffer module D, and the second buffer 1312 is used to receive the target pixel data output by the row buffer module B and the row buffer module D.

[0069] For example, the resolution of the input image is 100 100, the display panel resolution is 150 120 as an example, when the current moment corresponds to the first timing pulse of the second timing signal, the timing control module 11 determines that the row buffer modules 12 corresponding to the current moment are row buffer modules A and row buffer modules B. The timing control module 11 generates and outputs the first output control signal to the row buffer module A and the row buffer module B. The row buffer module A outputs the first pixel sub-data M1 (data corresponding to the first pixel point of the first row in the input image), the first pixel sub-data M2 (data corresponding to the second pixel point of the first row in the input image), the first pixel sub-data M3 (data corresponding to the third pixel point of the first row in the input image), and the first pixel sub-data M4 (data corresponding to the fourth pixel point of the first row in the input image) to the first buffer 1311. The row buffer module B outputs the first pixel sub-data N1 (data corresponding to the first pixel point of the second row in the input image), the first pixel sub-data N2 (data corresponding to the second pixel point of the second row in the input image), the first pixel sub-data N3 (data corresponding to the third pixel point of the second row in the input image), and the first pixel sub-data N4 (data corresponding to the fourth pixel point of the second row in the input image) to the second buffer 1312. At the current moment, the pixel point to be driven in the display panel 2 is the pixel point in the first column of the first pixel row. If it is determined according to the preset algorithm that the pixel point corresponds to the first pixel point and the second pixel point in the first row, and the first pixel point and the second pixel point in the second row of the input image, then the first buffer 1311 outputs the first pixel sub-data M1 and the first pixel sub-data M2 to the data generation unit 132, and the second buffer 1312 outputs the first pixel sub-data N1 and the first pixel sub-data N2 to the data generation unit 132.

[0070] In one possible implementation, see Figures 2 to 5 As shown, the control unit 113 is also used to shorten the time interval between the output control signal output at the current moment and the output control signal corresponding to the next moment when the number of first pixel sub-data stored in any buffer is less than or equal to the second preset number.

[0071] Exemplarily, the control unit 113 is used to shorten the time interval between the output control signal output at the current moment and the output control signal corresponding to the next moment when the number of first pixel sub-data stored in the first buffer 1311 and / or the second buffer 1312 is less than or equal to a second preset number.

[0072] Exemplarily, taking the first buffer 1311 and the exemplary contents in the foregoing as examples, when the control unit 113 receives the first timing pulse of the second timing signal, it generates and outputs a first output control signal to drive the row buffer module A to output the first pixel sub-data M1, the first pixel sub-data M2, the first pixel sub-data M3 and the first pixel sub-data M4 to the first buffer. If the pixel data to be driven in the current display panel requires the first pixel sub-data M1 to the first pixel sub-data M4, the first buffer outputs the first pixel sub-data M1 to the first pixel sub-data M4 to the data generation unit 132. At this time, the number of the first pixel sub-data in the first buffer 1311 is determined to be 0, that is, the number of the first pixel sub-data in the first buffer 1311 is less than the second preset number (for example: 3). In order to ensure that the driving display of a row of pixel units in the display panel will not be interrupted, the control unit 113 can shorten the time interval between the output control signal output at the current moment and the output control signal corresponding to the next moment, that is, when the number of first pixel sub-data stored in the first buffer 1311 is less than or equal to the second preset number, the output control signal is immediately output to the corresponding row buffer module 12 (that is, row buffer module A), driving the row buffer module A to output the first pixel sub-data M5, the first pixel sub-data M6, the first pixel sub-data M7 and the first pixel sub-data M8 to the first buffer 1311.

[0073] Exemplarily, when the number of first pixel sub-data in the first buffer 1311 and / or the second buffer 1312 is not less than the second preset number, the control unit 113 can maintain the time interval between the output control signal output at the current moment and the output control signal corresponding to the next moment. The time interval between the output control signal output at the current moment and the output control signal corresponding to the next moment can also be extended. It can be set according to actual conditions, and the present disclosure does not limit this.

[0074] Exemplarily, the second preset number is positively correlated with the number of pixels in each row of the input image and the number of pixel units driven within the minimum operation time of the display panel 2 , and is negatively correlated with the number of pixels in each row of the display panel 2 .

[0075] Exemplarily, the second preset number is equal to the product of the ratio of the number of pixels per row of the input image to the number of pixels per row of the display panel 2 and the number of pixel units driven within the minimum operation time of the display panel 2 .

[0076] The driving circuit provided by the present disclosure can predict the number of first pixel sub-data in the data storage unit, and when the number of first pixel sub-data in the data storage unit is insufficient, control the row cache module to output at least one pixel sub-data in the target pixel data, thereby preventing the driving circuit from being able to continuously output pixel data required by each pixel unit in the display panel due to insufficient data in the data cache unit when driving a row of pixel units in the display panel, thereby preventing the occurrence of display interruption and the like.

[0077] In one possible implementation, see Figures 2 to 5 As shown, the data cache unit 131 is also used to: when storing a first preset number of first pixel sub-data corresponding to the target pixel data output by at least two row cache modules 12, output at least one first pixel sub-data to the data generation unit 132.

[0078] For example, see the above exemplary content (i.e., the resolution of the input image is 100 100, the resolution of display panel 2 is 150 120), after the driving circuit 1 is powered on, within the time corresponding to the first timing pulse of the second timing signal, the first buffer 1311 in the data buffer unit 131 stores the first pixel sub-data M1 to the first pixel sub-data M16 output by the row buffer module A, and the second buffer 1312 stores the first pixel sub-data N1 to the first pixel sub-data N16 output by the row buffer module B. At this time, the first buffer 1311 outputs the first pixel sub-data M1 and the first pixel sub-data M2 to the data generating unit 132, and the second buffer 1312 outputs the first pixel sub-data N1 and the first pixel sub-data N2 to the data generating unit 132, and the data generating unit 132 starts to generate the pixel data corresponding to each pixel point in the display panel according to the first pixel sub-data output by the data buffer unit 131.

[0079] Exemplarily, if the data cache unit 131 does not store the first preset number of first pixel sub-data corresponding to the target pixel data output by at least two row cache modules 12 , the first pixel sub-data is not output to the data generation unit 132 .

[0080] In one possible implementation, see Figure 4 As shown, the timing control module 11 is also used to: when at least two row buffer modules 12 store at least two first pixel data, determine and drive at least one row buffer module 12 corresponding to the current moment according to a preset algorithm, and output a set of target pixel data to the pixel driving module 13.

[0081] Exemplarily, after the driving circuit 1 is powered on, the timing control module 11 can control the row cache module A to store the first row of pixel data of the input image A and control the row cache module B to store the second row of pixel data of the input image. Then, according to a preset algorithm, the row cache modules corresponding to the current moment are determined to be row cache module A and row cache module B, and the row cache module A and row cache module B are controlled to output a set of target pixel data to the pixel driving module 13.

[0082] According to another aspect of the present disclosure, the present disclosure further provides a display device, which includes a plurality of display units and the driving circuit 1 described above.

[0083] In a possible embodiment, the display unit includes a display panel, and the display panel includes at least one of a liquid crystal display panel, a micro light emitting diode display panel, a light emitting diode display panel, a mini light emitting diode display panel, a quantum dot light emitting diode display panel, an organic light emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel and a small pitch display panel.

[0084] According to another aspect of the present disclosure, the present disclosure also provides an electronic device, which includes the display device described above.

[0085] Exemplarily, the electronic devices in this embodiment include but are not limited to desktop computers, televisions, mobile devices with large screens such as mobile phones, tablet computers, and other common electronic devices that require multiple chips to be cascaded to achieve driving.

[0086] Exemplarily, the electronic device may also be a user equipment (UE), a mobile device, a user terminal, a terminal, a handheld device, a computing device or a vehicle-mounted device, etc. Exemplarily, some examples of terminals are: a display, a smart phone or a portable device, a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile Internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control (Industrial Control), a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid (Smart Grid), a wireless terminal in transportation safety (Transportation Safety), a wireless terminal in smart city (Smart City), a wireless terminal in smart home (Smart Home), a wireless terminal in Internet of Vehicles, etc. For example, the server may be a local server or a cloud server.

[0087] Figure 7 1 is a block diagram of an electronic device 1900 according to an embodiment of the present disclosure. For example, the electronic device 1900 may be provided as a server or a terminal device. Figure 7 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0088] The electronic device 1900 may also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output (I / O) interface 1958. The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™ or the like.

[0089] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0090] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the protection scope of the present invention. The protection scope of the present invention is determined by the appended claims.

[0091] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0092] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0093] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0094] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A driving circuit for a display panel, characterized in that: The driving circuit includes: a timing control module, a pixel driving module, and at least two row buffer modules; The input end of each of the row buffer modules is electrically connected to the timing control module, and the output end of each of the row buffer modules is electrically connected to the pixel driving module; The timing control module is used to control the at least two row buffer modules in sequence, and update the pixel data stored in the row buffer modules according to the at least two first pixel data; determine and drive at least one row buffer module corresponding to the current moment according to a preset algorithm, and output a set of target pixel data to the pixel driving module; wherein the first pixel data corresponds to a row of pixels in the input image; and the preset algorithm is used to represent the corresponding relationship between each pixel row in the display panel and each row of pixel data in the input image; The pixel driving module is used to generate and output second pixel data corresponding to each group of target pixel data to the display panel according to at least two groups of target pixel data output by at least two row buffer modules; wherein the second pixel data is used to drive a pixel row of the display panel, and the resolution of the display panel is greater than the resolution of the input image; The pixel driving module is further used to receive at least two groups of the target pixel data output by the at least two row buffer modules; generate second pixel data corresponding to each group of the target pixel data according to the at least two groups of the target pixel data; and sequentially output the second pixel data corresponding to each group of the target pixel data to the corresponding pixel row in the display panel according to the input timing of each group of the target pixel data; The pixel driving module comprises: a data cache unit, whose input end is electrically connected to the output end of each of the row cache modules, and is used to store the target pixel data output by the at least two row cache modules; and use the input order of the target pixel data as the output order of the at least two groups of target pixel data; and output the at least two groups of target pixel data to the data generation unit in sequence according to the output order; and A data generating unit, whose input end is electrically connected to the data cache unit, and whose output end is electrically connected to the display panel, is used to generate second pixel data corresponding to each group of target pixel data according to a preset data calculation method and the at least two groups of target pixel data output by the data cache unit; and output each second pixel data to the display panel in sequence according to the input timing of each group of target pixel data.

2. The driving circuit according to claim 1, characterized in that: The timing control module is further used to: input the at least two first pixel data into the at least two row buffer modules in sequence according to the first timing signal; and determine a pixel row to be driven corresponding to the current moment according to the second timing signal; and determine the corresponding relationship between the first pixel data and each pixel row in the display panel according to the preset algorithm; Determine at least one of the first pixel data corresponding to the current moment according to the corresponding relationship and a to-be-driven pixel row corresponding to the current moment; Using at least one first pixel data corresponding to the current moment as the set of target pixel data; The at least one row cache module for storing the set of target pixel data is determined to be the at least one row cache module corresponding to the current moment.

3. The driving circuit according to claim 2, characterized in that: The timing control module is also used to: when at least one of the row cache modules corresponding to the current moment does not store the target pixel data, extend the period of the current timing pulse in the second timing signal until all the row cache modules corresponding to the current moment store the target pixel data.

4. The driving circuit according to claim 1, characterized in that: The first pixel data includes a plurality of first pixel sub-data; wherein the first pixel sub-data corresponds to a pixel point in the input image; the timing control module includes: a first timing generation unit, a second timing generation unit, and a control unit; The first timing generation unit and the second timing generation unit are both electrically connected to the control unit; The first timing generation unit is used to generate and output a first timing signal to the control unit; the second timing generation unit is used to generate and output a second timing signal to the control unit; The control unit is used to input the at least two first pixel data into the at least two row buffer modules in sequence according to the first timing signal; and determine the at least one row buffer module corresponding to the current moment according to the second timing signal and a preset algorithm; generate and sequentially output at least one output control signal to the at least one row buffer module corresponding to the current moment according to the second timing signal, drive the at least one row buffer module corresponding to the current moment, and output a set of target pixel data to the pixel driving module; Each of the output control signals is used to control at least one row buffer module corresponding to the current moment to output a first preset number of the first pixel sub-data corresponding to the target pixel data to the pixel driving module.

5. The driving circuit according to claim 4, characterized in that: The data cache unit includes at least one cache, each cache is used to receive the first pixel sub-data output by different row cache modules, and determine and output the first pixel sub-data corresponding to the current moment to the data generation unit according to a preset algorithm.

6. The driving circuit according to claim 5, characterized in that: The control unit is also used to shorten the time interval between the output control signal output at the current moment and the output control signal corresponding to the next moment when the number of the first pixel sub-data stored in any of the buffers is less than or equal to a second preset number.

7. The driving circuit according to claim 6, characterized in that: The second preset number is positively correlated with the number of pixels in each row of the input image and the number of pixel units driven within the minimum operation time of the display panel, and is negatively correlated with the number of pixels in each row of the display panel.

8. The driving circuit according to claim 4, characterized in that: The data cache unit is further configured to: when storing a first preset number of first pixel sub-data corresponding to the target pixel data output by the at least two row cache modules, output at least one of the first pixel sub-data to the data generation unit.

9. The driving circuit according to claim 1, characterized in that: The timing control module is further used to: when the at least two row buffer modules store at least two of the first pixel data, determine and drive at least one row buffer module corresponding to the current moment according to a preset algorithm, and output a set of target pixel data to the pixel driving module.

10. A display device, characterized in that: The display device comprises a plurality of display units and at least one driving circuit according to any one of claims 1-9.

11. The display device according to claim 10, characterized in that The display unit includes a display panel, and the display panel includes at least one of a liquid crystal display panel, a micro light emitting diode display panel, a light emitting diode display panel, a mini light emitting diode display panel, a quantum dot light emitting diode display panel, an organic light emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel and a small pitch display panel.

12. An electronic device, characterized in that: The electronic device comprises the display device according to claim 10 or 11.

Images