QED Shifter for Memory Device

Abstract

The present disclosure relates to a QED shifter for a memory device. The memory device includes a command interface configured to receive commands from a host device. The memory device also includes a command shifter configured to receive the commands. The command shifter includes a plurality of stages coupled in series and configured to delay the commands. The command shifter includes selection circuitry configured to receive the commands and select an insertion stage for the plurality of stages of the commands. The selection circuitry is configured to select the insertion stage as a location for inserting the commands. The selected insertion stage is selected to control a duration of a delay in the command shifter. The selection of the insertion stage is at least partially based on a path delay between a clock and a data pin of the memory device.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of semiconductor devices. More specifically, embodiments of the present disclosure relate to a QED shifter topology for a memory device. Background Art

[0002] Semiconductor devices (e.g., memory devices) utilize the shifting of timing and data signals, data strobes, commands, and / or other signals to perform operations. A DQ enabled delay (QED) shifter includes multiple stages (e.g., flip-flops) that shift a command having an output element (e.g., a read or on-die termination (RTT)) through the QED shifter to match the latency of the memory device. The duration of the shift can be set according to a latency (e.g., a column address strobe (CAS) latency (CL)) that can be calculated using a delay locked loop (DLL) circuitry in the memory device. This latency can be recalculated after a clock frequency or a cycle duration (tck) of a clock change. Other factors can also be used to set the duration in the QED shifter, such as the duration of a path delay from an input pin of the memory device to an input of the QED shifter and / or a data strobe (DQS). Since the path delay and / or the CL can vary based on the frequency / tck, as the frequency range for the memory device increases, the range of different possible durations in the QED shifter changes. In addition, as the frequency range of the memory device grows, circuitry for adjusting the QED duration based on the CL and / or the path delay can be relatively large and / or can grow quickly as the possible frequency range of the memory device grows.

[0003] Embodiments of the present disclosure may relate to one or more of the problems set forth above. Summary of the Invention

[0004] One aspect of the present disclosure relates to a memory device, comprising: a command interface configured to receive a command from a host device; a command shifter configured to receive the command, wherein the command shifter includes: multiple stages coupled in series and configured to delay the command; and a selection circuitry configured to receive the command and select an insertion stage for the multiple stages of the command, wherein the selection circuitry is configured to select the insertion stage as a position for inserting the command to control a duration of a delay in the command shifter based at least in part on a path delay between a clock and a data pin of the memory device.

[0005] Another aspect of the present disclosure relates to a method, which includes: receiving an indication of latency at a memory device from a host device; determining a path delay from a clock to DQ pins in the memory device; receiving a command at the memory device from the host device; using a selection circuitry of the memory device to determine an insertion point in a command shifter having a plurality of flip-flops, wherein the insertion point is the flip-flop among the plurality of flip-flops determined at least in part based on subtracting the path delay from the latency; inserting the command into the insertion point via the selection circuitry; and shifting the command from the insertion point through a subset of the plurality of flip-flops to an exit point of the plurality of flip-flops.

[0006] Yet another aspect of the present disclosure relates to a method, which includes: receiving an indication of latency at a memory device from a host device; determining a path delay from a clock to DQ pins in the memory device; receiving a command at the memory device from the host device; using a selection circuitry to determine an insertion point in a command shifter having a plurality of shifters, wherein the insertion point is at least in part based on subtracting the path delay from the latency; dynamically inserting the command via the selection circuitry into an entry point of a first pipeline of the plurality of shifters, wherein a position of the entry point among the plurality of shifters is at least in part based on subtracting the path delay from the latency; and outputting the command from the plurality of shifters. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A simplified block diagram showing certain features of a memory device having a QED shifter circuitry according to an embodiment of the present disclosure;

[0008] Figure 2 According to an embodiment Figure 1 A circuit diagram of a QED shifter of a QED shifter circuitry for, wherein the QED shifter includes an input demultiplexer and an output multiplexer;

[0009] Figure 3 According to an embodiment Figure 1 A circuit diagram of a QED shifter of a QED shifter circuitry for, wherein the QED shifter includes an input demultiplexer and the command exits the last stage;

[0010] Figure 4 A timing diagram for a half-frequency mode of a memory device according to an embodiment, the memory device including an even clock driving an even pipeline and having pulses corresponding to even pulses of a system clock of the memory device and an odd clock driving an odd pipeline and having pulses corresponding to odd pulses of the system clock;

[0011] Figure 5A flow chart of a process for driving commands through the even and odd pipelines of Figure 4 , which has a single shift added to the command; and Figure 4 a circuit diagram of a QED shifter of a QED shifter circuit system of ,

[0012] , Figure 6 according to an embodiment, wherein the QED shifter can be implemented for a half-frequency mode of the memory device.

[0012] Figure 6 According to an embodiment Figure 1 a circuit diagram of a QED shifter of a QED shifter circuit system of Figure 1 , wherein the QED shifter can be implemented for a half-frequency mode of the memory device. DETAILED DESCRIPTION

[0013] One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in this specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Additionally, it should be understood that such development work can be complex and time-consuming, but for those of ordinary skill in the art who benefit from this disclosure, these are routine tasks in design, construction, and manufacturing.

[0014] A DQ Enable Delay (QED) shifter can be a plurality of stages / shifters / triggers that shift a command through the QED shifter. The location for exiting the QED shifter can be based on the path delay between the clock and the data (DQ) pins of the memory device. As the duration range through the QED shifter of the memory device grows, the complexity of the multiplexer for selecting when to exit the QED shifter becomes more costly, space-consuming, and latency-increasing. To avoid this latency at the time-critical end of the QED shifter, the selection circuit system for injecting the command into the memory device can be adjusted to compensate for the path delay rather than at the end of the QED shifter. Thus, the command can be injected into the QED shifter at a location based on the set column address strobe (CAS) latency minus the path delay. This shifts the latency for selection (e.g., via a demultiplexer) to a less time-critical part of the memory device.

[0015] In addition, the memory device may operate at half the frequency of the clock from the host device in a half-frequency mode. This half-frequency clock inside the memory device may not affect the overall operating frequency. For example, to accommodate this lower speed, the memory device may include two pipelines in the QED shifter, one for even clock assertions and one for odd clock assertions. Thus, the commands are shifted through the respective pipelines at every other clock cycle. However, some commands may require a shift and / or stretch of a single clock cycle. To address these cases, the QED shifter may shift these commands from the even pipeline to the odd pipeline, or vice versa. In addition, since the shifting of these commands between the pipelines may affect the subsequent stage, swapping the pipelines will require swapping back in the pipelines or the swapping may be performed at the end of the pipelines.

[0016] Turning now to the figures, Figure 1 is a simplified block diagram showing certain features of the memory device 10. Specifically, Figure 1 The block diagram of is a functional block diagram showing certain functionality of the memory device 10. According to one embodiment, the memory device 10 may be a DDR5 SDRAM device. The various features of DDR5 SDRAM allow for reduced power consumption, more bandwidth, and more storage capacity compared to previous generations of DDR SDRAM.

[0017] The memory device 10 may include several memory banks 12. For example, the memory banks 12 may be DDR5 SDRAM memory banks. The memory banks 12 may be disposed on one or more chips (e.g., SDRAM chips) arranged on dual in-line memory modules (DIMMs). It should be understood that each DIMM may include several SDRAM memory chips (e.g., x8 or x16 memory chips). Each SDRAM memory chip may include one or more memory banks 12. The memory device 10 represents a part of a single memory chip (e.g., SDRAM chip) having several memory banks 12. For DDR5, the memory banks 12 may be further arranged to form groups. For example, for an 8 gigabyte (Gb) DDR5 SDRAM, the memory chip may include 16 memory banks 12 arranged in 8 groups, each group including 2 memory banks. For example, for a 16Gb DDR5 SDRAM, the memory chip may include 32 memory banks 12 arranged in 8 groups, each group including 4 memory banks. Depending on the application and design of the entire system, various other configurations, organizations, and sizes of the memory banks 12 on the memory device 10 may be utilized.

[0018] Memory device 10 may include a command interface 14 and an input / output (I / O) interface 16. The command interface 14 is configured to receive a plurality of signals (e.g., signal 15) from an external host device, such as a controller 17 that may be embodied as a processor and / or other host device. The processor or controller may provide various signals 15 to the memory device 10 to facilitate the transfer and reception of data to be written to or read from the memory device 10.

[0019] As will be appreciated, the command interface 14 may include several circuits, such as a clock input circuit 18 and a command address input circuit 20, for example, to ensure proper handling of the signal 15. The command interface 14 may receive one or more clock signals from an external device. Generally, double data rate (DDR) memories utilize a differential pair of system clock signals, which are referred to herein as a true clock signal (Clk_t) and a complementary or inverted clock signal (Clk_c). The positive clock edge of DDR refers to the point at which the rising true clock signal Clk_t crosses the falling inverted clock signal Clk_c, while the negative clock edge indicates the transition of the falling true clock signal Clk_t and the rising of the inverted clock signal Clk_c. Commands (e.g., read commands, write commands, etc.) typically enter on the positive edge of the clock signal and data is transferred or received on both the positive and negative clock edges.

[0020] The clock input circuit 18 receives the true clock signal (Clk_t) and the inverted clock signal (Clk_c) and generates an internal clock signal CLK. The internal clock signal CLK is supplied to an internal clock generator, such as a delay locked loop (DLL) 30. The DLL 30 generates a phase-controlled internal clock signal LCLK based on the received internal clock signal CLK. The phase-controlled internal clock signal LCLK is supplied to, for example, the I / O interface 16 and is used as a timing signal for determining the output timing of the read data.

[0021] The internal clock signal / phase CLK may also be provided to various other components within the memory device 10 and may be used to generate various additional internal clock signals. For example, the internal clock signal CLK may be provided to a command decoder 32. The command decoder 32 may receive command signals from a command bus 34 and may decode the command signals to provide various internal commands. For example, the command decoder 32 may provide the command signals to the DLL 30 via a bus 36 to coordinate the generation of the phase-controlled internal clock signal LCLK. The phase-controlled internal clock signal LCLK may be used, for example, to time data through the IO interface 16.

[0022] In addition, the command decoder 32 can decode commands such as read commands, write commands, mode register set commands, activation commands, etc., and provide access to a specific memory bank 12 corresponding to the command via the bus path 40. Additionally or alternatively, the command decoder can send an internal write signal 41 to the IO interface 16. As will be appreciated, the memory device 10 can include various other decoders, such as row decoders and column decoders, to facilitate access to the memory bank 12. In one embodiment, each memory bank 12 includes a bank control block 22 that provides the necessary decoding (e.g., row decoders and column decoders) and other features, such as timing control and data control, to facilitate the execution of commands to and from the memory bank 12.

[0023] The memory device 10 performs operations such as read commands and write commands based on command / address signals received from an external device such as a processor. In one embodiment, the command / address bus can be a 14-bit bus (CA<13:0>) for accommodating the command / address signals. The command / address signals are timed into the command interface 14 using clock signals (Clk_t and Clk_c). The command interface can include a command address input circuit 20 configured to receive and transmit commands to provide access to the memory bank 12 through, for example, the command decoder 32. Additionally, the command interface 14 can receive a chip select signal (CS_n). The CS_n signal enables the memory device 10 to process commands on the incoming CA<13:0> bus. Access to a specific bank 12 within the memory device 10 is encoded in the CA<13:0> bus by the command.

[0024] Additionally, the command interface 14 can be configured to receive several other command signals. For example, a command / address on-die termination (CA_ODT) signal can be provided to facilitate proper impedance matching within the memory device 10. For example, a reset command (RESET_n) can be used to reset the command interface 14, status register, state machine, etc. during power-on. The command interface 14 can also receive a command / address inversion (CAI) signal, which can be provided to invert the state of the command / address signals CA<13:0> on the command / address bus, for example, depending on the command / address routing of the specific memory device 10. A mirror (MIR) signal can also be provided to facilitate the mirroring function. Based on the configuration of multiple memory devices in a specific application, the MIR signal can be used to multiplex signals so that they can be swapped for use in implementing a certain routing of the signals to the memory device 10. Various signals can also be provided to facilitate testing of the memory device 10, such as a test enable (TEN) signal. For example, the TEN signal can be used to place the memory device 10 in a test mode for connectivity testing.

[0025] The command interface 14 can also be used to provide a warning signal (ALERT_n) to the system processor or controller for certain detectable errors. For example, a warning signal (ALERT_n) can be transmitted from the memory device 10 when a cyclic redundancy check (CRC) error is detected. Other warning signals can also be generated. In addition, the bus and pins used to transmit the warning signal (ALERT_n) from the memory device 10 can be used as input pins during certain operations, such as the connectivity test mode performed using the TEN signal as described above.

[0026] Data can be sent to and from the memory device 10 by transmitting and receiving signals 44 (e.g., data and / or strobes to capture data) via the IO interface 16 using the commands and timing signals discussed above. More specifically, data can be sent to or retrieved from the memory bank 12 through a data path 46 that includes a plurality of bidirectional data buses. Data IO signals, generally referred to as DQ signals, are typically transmitted and received in one or more bidirectional data buses. For some memory devices, such as DDR5 SDRAM memory devices, the IO signals can be divided into high and low bytes. For example, for a x16 memory device, the IO signals can be divided into high and low IO signals (e.g., DQ<15:8> and DQ<7:0>) corresponding to the high and low bytes of the data signal, respectively.

[0027] To allow for higher data rates within the memory device 10, some memory devices, such as DDR memory devices, can utilize a data strobe signal, commonly referred to as DQS. DQS is driven by an external processor or controller that transmits data (e.g., for a write command) or by the memory device 10 (e.g., for a read command). For a read command, DQS is actually an additional data output (DQ) signal with a predefined pattern. For a write command, DQS is used as a clock signal to capture the corresponding input data. Similar to the clock signals (Clk_t and Clk_c), the DQS signal can be provided as a differential pair of data strobe signals (DQS_t and DQS_c) to provide differential pair signaling during reads and writes. For some memory devices, such as DDR5 SDRAM memory devices, the differential pair DQS can be divided into high and low data strobe signals (e.g., UDQS_t and UDQS_c; LDQS_t and LDQS_c) corresponding to the high and low bytes of the data transmitted to and from the memory device 10, respectively.

[0028] An impedance (ZQ) calibration signal may also be provided to the memory device 10 through the IO interface 16. The ZQ calibration signal may be provided to a reference pin and is used to tune the output driver and ODT values by adjusting the pull-up and pull-down resistors of the memory device 10 over changes in process, voltage, and temperature (PVT) values. Since PVT characteristics may affect the ZQ resistor value, the ZQ calibration signal may be provided to the ZQ reference pin to adjust the resistance to calibrate the input impedance to a known value. As will be appreciated, a precision resistor is typically coupled between the ZQ pin on the memory device 10 and GND / VSS external to the memory device 10. This resistor serves as a reference for adjusting the drive strength of the internal ODT and IO pins.

[0029] Additionally, a loopback signal (LOOPBACK) may be provided to the memory device 10 through the IO interface 16. The loopback signal may be used during a test or debug phase to set the memory device 10 into a mode in which signals loop back through the memory device 10 through the same pins. For example, the loopback signal may be used to set the memory device 10 to test the data output (DQ) of the memory device 10. The loopback may include both data and strobe, or may include only the data pins. This is generally intended for monitoring data captured by the memory device 10 at the I / O interface 16.

[0030] The I / O interface 16, command decoder 32, and / or data path 46 may include a shifter circuit system 50 for shifting commands in the memory device 10. Additionally or alternatively, the shifter circuit system 50 may be included in any other location in the memory device 10. For example, the shifter circuit system 50 may be included in the memory bank 12, command interface 14, and / or any other suitable location. The shifter circuit system 50 may include multiple stages (e.g., flip-flops) for shifting through commands. For example, the shifter circuit system 50 may include a QED shifter as a command shifter, which includes multiple stages for shifting a command having an output component (e.g., a read and / or on-die termination (RTT) command) with a specified delay for the memory device 10. For example, the specified delay may be a column address strobe (CAS) latency (CL). The CL may be specified for the memory device 10 from an external host device / controller 17 via a mode register. As discussed below, the memory device 10 may vary various factors according to a specified amount to compensate for deviations, such as the data path delay from the input pins of the memory device 10 to the QED shifter of the shifter circuit system 50.

[0031] As will be appreciated, various other components such as a power supply circuit (for receiving external VDD and VSS signals), a mode register (for defining various modes of programmable operations and configurations), a read / write amplifier (for amplifying signals during read / write operations), a temperature sensor (for sensing the temperature of the memory device 10), etc. may also be incorporated into the memory device 10. Thus, it should be understood that only the Figure 1 block diagram is provided to highlight certain functional features of the memory device 10 to facilitate the subsequent detailed description.

[0032] Figure 2 For an embodiment of the memory device in Figure 1 a circuit diagram of the QED shifter 100 that may be included in the shifter circuitry 50 at any suitable location. As shown, the QED shifter 100 includes a string 102 of shifters 104, 106, 108, 110, 112, and 114 collectively referred to as shifters or "stages" 104 to 114. The shifters 104 to 114 may include a string of flip-flops that are sequentially tied together, and the input of a subsequent flip-flop is tied to the output of a previous flip-flop. Additionally, the shifters 104 to 114 may utilize a common clock. The string 102 of shifters 104 to 114 includes six shifters, but the length of the string 102 may include a number of flip-flop lengths equal to the maximum number of clocks of the CL of the memory device 10. In some embodiments, the string 102 may include some additional flip-flops for additional buffering and / or for future use in the memory device 10. An input selection circuitry 116 (e.g., an input stage demultiplexer) may be used to select where to insert the command 118 into the string 102 of shifters 104 to 114. For example, when selecting the maximum CL for the memory device 10, the input selection circuitry 116 may transmit / inject the command 118 to the leftmost stage (i.e., the input of the shifter 104), and when selecting the minimum CL for the memory device 10, the input selection circuitry 116 may transmit / inject the command 118 to the rightmost stage (i.e., the input of the shifter 108). Similarly, the input selection circuitry 116 may use any intermediate CL duration to transmit / inject the command 118 to any stage between the leftmost and rightmost stages. In other words, as the latency increases, the input stage shifts more to the left. Thus, the input selection circuitry 116 may receive a signal indicating the latency 120, which indicates the duration of the CL. For example, this latency 120 may be received from an external host device / controller 17.

[0033] Although the input selection circuit system 116 can inject a command into the QED shifter 100 to delay the command 118 by a number (e.g., 50) of clock cycles equal to the entire CL, there can be a certain path delay between the clk and DQ pins of the memory device 10. The amount of cycles delayed in the path delay depends on the frequency and on the process corner. Higher frequencies generally result in more cycles of path delay. To compensate for this path delay and output an output command 124 aligned with the clock, the QED shifter 100 can utilize the output selection circuit system 122 based on the amount of the path delay. The DLL 30 ( Figure 1 ) measures and matches the delay based on this path delay. The DLL 30 calculates this path delay as a value called LOOPN 126 that indicates the path delay for the current frequency. Whenever the frequency / tck is changed for the memory device 10, the DLL 30 can recalculate LOOPN 126. When LOOPN 126 increases, the output selection circuit system 122 can select an earlier stage in the QED shifter 100. Additionally, the output selection circuit system 122 is in the time-critical path of the command 118. Further, LOOPN 126 is a DC signal determined by the DLL 30, and the DLL 30 is available well before the command 118 has reached the end of the string 102 of shifters 102 to 114. As the frequency range increases, the range of LOOPN 126 increases. Thus, as more frequencies become available, the size of the output selection circuit system 122 increases. However, the combinational logic in the output selection circuit system 122 also increases in terms of physical size and cost, which may make the output selection circuit system 122 too large or too expensive for the memory device 10. Additionally, the output selection circuit system 122 for a large range can have deep combinational logic, which can slow down the command 118 because the output selection circuit system 122 is in the speed path.

[0034] To address the speed, size, and cost issues of the output selection circuit system 122, the output selection circuit system 122 can be omitted. Figure 3 Shows a circuit diagram of the QED shifter 130 that can be present in any of the Figure 1 shifter circuit systems 50. As shown, the QED shifter 130 does not include the output selection circuit system 122. Instead, the QED shifter 130 includes a selection circuit system 132 that receives the command 134. The function of the input selection circuit system 132 is similar to Figure 2The entry selection circuit system 116, except that the entry selection circuit system 132 selects the entry stage based on the control signal 136 rather than directly using the time delay 120. The control signal 136 is at least partially based on the LOOPN 126 subtracted from the time delay 120. In some embodiments, the control signal 136 can be a function of other signals. For example, the control signal 136 can be the value of the time delay 120 minus the value of the LOOPN 126 and an additional value. For example, the additional value can include a walkback value, a maximum preamble length, a maximum DQS offset, a data rate output shift, and / or other parameters. The walkback value indicates the number of cycles for walking back to a faster clock. The number of cycles for walkback depends on the frequency that can be set using the mode register that specifies the frequency for the memory device 10. The preamble maximum and the maximum DQS offset can be fixed according to the specification for the memory device 10. The data rate output shift can indicate the number of fixed cycles at the output depending on the type of mode for the memory device 10. For example, for full frequency operation, the data rate output cycle can be a first number (e.g., 2) of cycles, and for half frequency operation, the data rate output cycle can be a second number (e.g., 4) of cycles. In other words, the LOOPN 126 and the walkback can depend on the operating frequency, while the other parameters can be fixed but vary between different implementations of the memory device 10.

[0035] By removing the exit selection circuit system 122, the output command 138 can be output from the string 102 of shifters 104 to 114 through a speed path that is no longer affected by the multiplexer, where the selector (e.g., LOOPN 126) is static. Alternatively, in the QED shifter 130, the speed path is a pure timing path.

[0036] As previously noted, the memory device 10 can utilize half frequency operation, where one or more shifters and / or other circuit systems are divided into two separate pipelines that operate at half the clock frequency. For example, Figure 4A timing diagram showing half-frequency operation is presented. As shown, an even clock (CLKE) 152 and an odd clock (CLKO) 154 can each be generated from CLK at half the frequency of CLK. CLKE 152 and CLKO 154 are 180 degrees out of phase with each other. Specifically, CLKE 152 has an assertion 156 corresponding to the assertion of CLK, while CLKO 154 has an assertion 158 of the next assertion of CLK. CLKE 152 is used to drive an even pipeline 160 containing a first set of shifters and / or other circuitry, and CLKO 154 is used to drive an odd pipeline 162 containing a second set of shifters and / or other circuitry. Although CL and burst length (BL) can correspond to an even number of shifts to keep the shifts within the corresponding pipeline, a particular mode register setting can result in an odd number of shifts that shift commands between the even pipeline 160 and the odd pipeline 162. For example, these mode register settings can include shifting the rise / fall edges of on-die termination (RTT) independently in steps of 1tCK. This shift of an odd number of tCKs (e.g., 1tCK shift 164) will result in an odd delay, burst length, or both. To be able to resolve these shifts by an odd number of tCKs, the QED shifter can utilize a mechanism in which commands transition from the even pipeline 160 to the odd pipeline 162 or vice versa.

[0037] Figure 5 A flowchart showing a circuitry 170 that can be utilized in a QED shifter to swap pipelines when shifting an odd number (e.g., 1) of tCKs is presented. As shown, the circuitry 170 includes an even pipeline 172 and an odd pipeline 174, where commands reach a shift circuitry 176 through the even pipeline 172 and / or the odd pipeline 174. The even pipeline 172 can be equivalent to the even pipeline 160, and the odd pipeline 174 can be equivalent to the odd pipeline 162. When a command from either pipeline reaches the shift circuitry 176, the shift circuitry 176 can shift the command. For example, a flip-flop can be used to shift the command to shift the command by a single cycle. The shift circuitry 176 can utilize a selection circuitry (e.g., a multiplexer and / or other combinational logic) to select whether to output a shifted version or an unshifted version of the command. This selection can be based on an added shift signal 177 indicating whether the command is to be shifted.

[0038] For example, when the decoded command corresponds to a 1tCK shift, the add shift signal 177 may be asserted. A copy of the shift and select circuitry may be in the shift circuitry 176 and used for the even pipeline 172, and a second copy of the shift and select circuitry may be included in the shift circuitry 176 and used for the odd pipeline 174. Additionally, since a single shift may correspond to a command switching from one pipeline to another, the select circuitry for each pipeline may select between an unshifted version of its own command or a shifted version of a command from another pipeline. For example, when a shift occurs, the output command 180 is the command received in the even pipeline 172 before the shift, and / or the output command 178 is the command received in the odd pipeline 174 before the shift. Thus, the commands are shifted and the pipelines are shifted. However, for the subsequent stage, a feedback circuitry 182 is used to shift these commands back. The feedback circuitry 182 may use a first select circuitry to determine whether to output the even command 184 from the even pipeline 172 or from the odd pipeline 174. Similarly, the feedback circuitry may use a second select circuitry to determine whether to output the odd command 186 from the even pipeline 172 or from the odd pipeline 174. The selection may be based on a shifted signal 187 indicating whether the command has been shifted and / or swapped between the pipelines. For example, the shifted signal 187 may be a delayed version of the add shift signal 177.

[0039] The shift circuitry 176 that processes shifts for an odd number of cycles may also be used to process commands stretched by 1tCK. To stretch the command, the shift circuitry 176 may shift the command and OR the shifted command with the unshifted command to stretch the command.

[0040] The shift circuitry 176 may be located at the end of the QED shifter. For example, Figure 6 FIG. 200 shows a QED shifter 200 that may be utilized in a memory device 10 using half-frequency operation. The QED shifter 200 includes an even pipeline 202 and an odd pipeline 204. The even pipeline 202 includes shifters 206, 208, 210, 212, 214, and 216 collectively referred to as shifters or stages 206 to 216. The odd pipeline 204 includes shifters 220, 222, 224, 226, 228, and 230 collectively referred to as shifters or stages 220 to 230. The shift circuitry 232 may pull from any of the shifters 214, 216, 228, and 230 in a switch region 218 at the ends of the even pipeline 202 and the odd pipeline 204.

[0041] The QED shifter 200 also includes an entry selection circuit system 234 similar to the entry selection circuit system 132 discussed previously. The entry selection circuit system 234 uses a control signal 238 to control the entry point of the command 236. The control signal 238 can be calculated similarly to how the control signal 136 is calculated.

[0042] A shift circuit system 232 similar to the shift circuit system 176 can receive commands from a switch region 218 that includes levels 2n and 2n + 1 of each pipeline. However, unlike the shift circuit system 176, the commands can be received as shifted from levels 2n and 2n + 1 rather than being shifted within the shift circuit system 232 (e.g., using additional flip - flops). In other words, the shift circuit system 232 receives shifted (e.g., level 2n + 1 output) and unshifted (e.g., level 2n) commands from each pipeline. As discussed above with respect to the shift circuit system 176, the shift circuit system 232 selects the level 2n + 1 (shifted command) of other pipelines (e.g., even - numbered pipelines) when the commands in the corresponding pipeline have a 1tCK shift or stretch. Otherwise, the shift circuit system 232 outputs the corresponding command from the corresponding pipeline without shifting (e.g., from level 2n). When the add shift signal 240 is asserted, the shift circuit system 232 selectively applies a shift. The add shift signal 240 can be asserted when applying 1tCK as discussed previously. The shift circuit system 232 can apply a stretch of the command based on a BLPlus1 signal 242 that is asserted when the burst length is to be stretched by one cycle. Situations in which the blplus1 signal 242 can be asserted to stretch a command by one cycle can include read commands (including non - target reads) when read cyclic redundancy check (CRC) is enabled, offsets at the rising or falling edges of on - die termination (RTT), RTT for various combinations of CRC enabled, write commands (including non - target writes) when CRC is enabled, and / or other command types and parameters. In cases of applying or forgoing selective shifting, the shift circuit system 232 outputs commands based at least in part on the add shift signal 240 and / or the BLPlus1 signal 242.

[0043] While the present disclosure may readily admit of various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the particular forms disclosed. Indeed, the present disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.

[0044] The technology presented and claimed herein is referenced and applied to substantial objects and specific instances with a practical nature, which substantially improve the technical field in an arguable manner and are thus not abstract, intangible, or purely theoretical. Additionally, if any claim appended to the end of this specification contains one or more elements expressed as "means for [performing] [function]..." or "step for [performing] [function]...", such elements are expected to be construed in accordance with 35 U.S.C. 112(f). However, for any claim containing elements specified in any other way, such elements are not expected to be construed under 35 U.S.C. 112(f).

Claims

1. A memory device, comprising: A command interface configured to receive commands from a host device; A command shifter configured to receive the commands, wherein the command shifter includes: A plurality of stages coupled in series and configured to delay the commands, wherein the plurality of stages includes two pipelines, each pipeline being configured to flow at a half frequency of a clock provided by the host device; A switching region configured to add a single cycle shift to the commands by shifting from a first pipeline of the two pipelines to a second pipeline of the two pipelines; and A selection circuitry configured to receive the commands and select an insertion stage of the plurality of stages for the commands, wherein the selection circuitry is configured to select the insertion stage as a position for inserting the commands to control a duration of the delay in the command shifter based at least in part on a path delay between the clock and a data pin of the memory device.

2. The memory device according to claim 1, wherein the plurality of stages includes a plurality of flip-flops.

3. The memory device according to claim 2, wherein the plurality of flip-flops are connected to a common clock.

4. The memory device according to claim 1, wherein the selection circuitry includes a demultiplexer configured to select a stage of the plurality of stages based at least in part on the path delay between the clock and the data pin of the memory device.

5. The memory device according to claim 1, wherein the duration of the delay in the command shifter is based at least in part on a set time delay for the memory device.

6. The memory device according to claim 5, wherein the duration of the delay is based at least in part on the path delay subtracted from the set time delay.

7. The memory device according to claim 6, wherein the duration of the delay is based at least in part on the path delay subtracted from the set time delay and a maximum preamble length for the memory device.

8. The memory device according to claim 6, wherein the duration of the delay is based at least in part on the path delay subtracted from the set time delay and a maximum data strobe offset for the memory device.

9. The memory device according to claim 6, wherein the duration of the delay is based at least in part on the path delay subtracted from the set time delay and a back-off value for the memory device, wherein the back-off value indicates how much to walk the commands back to a faster clock using a gradually faster clock.

10. The memory device according to claim 1, wherein the switching region is located at an output end of the plurality of stages.

11. The memory device according to claim 1, wherein the switching region is located at an output end of the plurality of stages, the switching region being configured to stretch the commands in a single cycle by shifting from the first pipeline of the two pipelines to the second pipeline of the two pipelines.

12. A method of operating a memory device, comprising: Receiving an indication of a latency at the memory device from a host device, wherein receiving the indication of the latency from the host device includes receiving the indication of the latency from the host device via a mode register; Determining a path delay from a clock to DQ pins in the memory device; Receiving a command at the memory device from the host device, wherein receiving the command includes receiving the command in a first pipeline of a plurality of flip - flops, wherein the first pipeline and a second pipeline of the plurality of flip - flops are configured to operate at a frequency that is half the speed of a clock received from the host device; Using a selection circuitry of the memory device to determine an insertion point in a command shifter having the plurality of flip - flops, wherein the insertion point is a flip - flop among the plurality of flip - flops determined at least in part based on subtracting the path delay from the latency; Inserting the command into the insertion point via the selection circuitry; And Shifting the command from the insertion point to an exit point of the plurality of flip - flops through a subset of the plurality of flip - flops, wherein shifting the command includes shifting the command an odd number of clock cycles by shifting the command from the first pipeline to the second pipeline.

13. The method according to claim 12, wherein the latency includes a column address strobe latency for the memory device.

14. The method according to claim 12, wherein the command includes a read command when cyclic redundancy check is enabled, having an offset applied to a rising or falling edge of a die - on termination assertion, or includes a write command when cyclic redundancy check is enabled.

15. The method according to claim 12, wherein determining the insertion point is at least in part based on the path delay subtracted from the latency and a maximum preamble length for the memory device.

16. The method according to claim 12, wherein determining the insertion point is at least in part based on the path delay subtracted from the latency and a maximum data strobe signal offset for the memory device.

17. The method according to claim 12, wherein determining the insertion point is at least in part based on the path delay subtracted from the latency and a back - off value for the memory device, wherein the back - off value indicates how much to walk the command back to a faster clock using a progressively faster clock.

18. A method of operating a memory device, comprising: Receiving an indication of a latency at the memory device from a host device; Determining a path delay from a clock to DQ pins in the memory device; Receiving a command at the memory device from the host device; Using a selection circuitry to determine an insertion point in a command shifter having a plurality of shifters, wherein the insertion point is at least in part based on subtracting the path delay from the latency, wherein determining the insertion point includes determining that the command is to be shifted or stretched an odd number of clock cycles; Dynamically insert the command into an entry point of a first pipeline of the plurality of shifters via the selection circuitry, wherein a position of the entry point among the plurality of shifters is at least partially based on the latency minus the path delay; and Output the command from the plurality of shifters, wherein outputting the command includes outputting the command from a second pipeline of the plurality of shifters.

19. The method of claim 18, wherein outputting the command from the second pipeline of the plurality of shifters is at least partially based on a burst length stretch signal or an add shift signal.

20. The method of claim 19, wherein the burst length stretch signal or the add shift signal is at least partially based on decoding of the command.

21. The method of claim 18, wherein determining the insertion point includes using a demultiplexer to select a stage of a plurality of stages.

22. The method of claim 18, wherein determining the insertion point is at least partially based on the path delay subtracted from the latency and a maximum preamble length for the memory device.

23. The method of claim 18, wherein determining the insertion point is at least partially based on the path delay subtracted from the latency and a maximum data strobe signal offset for the memory device.

24. The method of claim 18, wherein determining the insertion point is at least partially based on the path delay subtracted from the latency and a back-off value for the memory device, wherein the back-off value indicates how much to walk the command back to a faster clock using a progressively faster clock.

Images