Methods for preparing polycrystalline thin films

Abstract

This invention provides a method for preparing polycrystalline thin films. The method includes: providing a substrate; etching grooves on the surface of the substrate; depositing amorphous semiconductor material on the sidewalls of the grooves to form sidewall structures; filling the grooves with a dielectric material and performing planarization to form a filled structure, the surface of the filled structure being flush with the surface of the substrate; growing a thin film layer on the surface of the substrate, the thin film layer covering the sidewall structures and the filled structure; and laser thermally treating the surface of the thin film layer to form a polycrystalline thin film on the substrate. This invention can reduce the manufacturing cost of polycrystalline thin films.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing polycrystalline thin films. Background Technology

[0002] Three-dimensional monolithic integration technology changes the layout of traditional two-dimensional transistors from flat to vertical stacking by stacking, which can significantly improve the integration density of devices.

[0003] Taking CMOS (Complementary Metal-Oxide-Semiconductor) device fabrication as an example, the traditional method for fabricating two-dimensional transistors involves fabricating both NMOS (N-type metal-oxide-semiconductor) and PMOS (P-type metal-oxide-semiconductor) in the CMOS on the same layer of the substrate material. However, for three-dimensional integration technology, the NMOS (or PMOS) is fabricated first, and then the PMOS (or NMOS) is fabricated on top of it. The bottom layer of devices can be fabricated directly on the silicon substrate, while the top layer requires the fabrication of an active region material layer, i.e., a thin film, on top of the bottom layer before the top layer device can be fabricated. Therefore, the quality of this active region material layer has a significant impact on device performance. The higher the quality of the active region material layer, the closer it is to the single-crystal material of the substrate, resulting in a higher quality CMOS device.

[0004] While existing methods can fabricate relatively ideal thin films of single-crystal silicon at the top of the substrate, they are costly and have low yields. Currently, existing methods still employ laser crystallization to fabricate polycrystalline silicon thin films as the active material layer on the underlying device. The main method involves etching deep holes on the upper surface of the substrate, then placing a dielectric layer on the upper surface and within the deep holes. A laser is then used to melt most of the upper surface of the dielectric layer, resulting in recrystallization and the formation of regularly shaped polycrystalline material particles on the substrate surface. The unmelted dielectric layer at the bottom of the deep holes is retained as a seed layer, which recrystallizes after the laser is removed to form the polycrystalline thin film. "Regular shape" refers to the polycrystalline silicon grains being individually square-shaped. The characteristics of a single polycrystalline silicon grain are close to the quality of a single crystal; therefore, if the device can be fabricated within this grain, device performance comparable to that of single-crystal silicon can be achieved.

[0005] However, the key to laser crystallization is ensuring the size and morphology of the deep holes. If the aperture of the laser hole is too large, it is difficult to form grains with few defects, i.e., few grain boundaries and a single crystal orientation. Therefore, the aperture of the deep hole must be controlled to below 150 nm, which requires the use of LPCVD (low-pressure chemical vapor deposition) process. However, this process has a slow growth rate and high thermal budget, which will increase the cost of polycrystalline thin film preparation. Moreover, it is difficult to guarantee the morphology of the laser holes etched by this process, which will reduce the yield of polycrystalline thin films.

[0006] In addition, in the fabrication of SOI (silicon insulated substrate) devices, polycrystalline silicon materials can also be used, and their performance can be close to that of monocrystalline silicon materials.

[0007] Therefore, how to reduce the difficulty and cost of preparing polycrystalline thin films and improve the yield of polycrystalline thin films has become an urgent problem to be solved. Summary of the Invention

[0008] To solve the above problems, the present invention provides a method for preparing polycrystalline thin films by forming a sidewall structure on the sidewall of a groove and using the sidewall structure as a seed crystal filter, so that the thin film layer after laser heat treatment recrystallizes, thereby obtaining a polycrystalline thin film with regularly shaped polycrystalline material particles. The method is simple to operate, low in cost, and has a high yield.

[0009] This invention provides a method for preparing polycrystalline thin films, comprising:

[0010] Provide substrate;

[0011] Grooves are etched into the surface of the substrate;

[0012] Amorphous semiconductor material is deposited on the sidewalls of the groove to form a sidewall structure;

[0013] A dielectric material is filled into the groove and planarized to form a filled structure, the surface of which is flush with the surface of the substrate.

[0014] A thin film layer is grown on the surface of the substrate, which covers the sidewall structure and the filling structure.

[0015] Laser heat treatment is applied to the surface of the thin film layer to recrystallize the thin film layer and form a polycrystalline thin film.

[0016] Optionally, prior to the step of growing a thin film layer on the surface of the substrate, the preparation method further includes:

[0017] The surface of the sidewall structure exposed by reduction annealing is revealed on the substrate surface.

[0018] Optionally, the width of the groove is greater than 100 nm.

[0019] Optionally, the thickness of the sidewall structure is less than 150 nm.

[0020] Optionally, a metal oxide semiconductor is disposed on the surface of the substrate opposite to the groove.

[0021] Alternatively, the substrate material may include silicon or germanium.

[0022] Optionally, the dielectric material is an insulating material.

[0023] Optionally, the dielectric material includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0024] Optionally, the step of growing a thin film layer on the surface of the substrate includes:

[0025] Thin film layers are grown at temperatures below 600 degrees Celsius.

[0026] Optionally, the laser source used in the laser heat treatment of the thin film layer has a penetration depth less than the depth of the groove.

[0027] Optionally, the energy density of the laser source used in the laser heat treatment of the thin film layer is in the range of 1.5 J / cm². 2 Up to 3J / cm 2 .

[0028] Optionally, the step of reducing and annealing the surface of the sidewall structure exposed on the substrate surface includes:

[0029] The surface of the sidewall structure exposed on the substrate is annealed in a nitrogen or inert gas environment at a temperature between 200°C and 600°C.

[0030] An acidic solution is used to etch the surface of the sidewall structure exposed on the substrate surface in order to remove the oxide layer on the surface of the sidewall structure exposed on the substrate surface.

[0031] The polycrystalline thin film fabrication method provided in this invention forms a sidewall structure on the sidewall of a groove, using the sidewall structure, which is wrapped in an insulating medium, as a seed crystal filter. The thickness of the sidewall structure limits the recrystallization process, allowing only a single crystal to pass through and enter the thin film layer, thus restricting the crystal orientation of the crystals in the thin film layer. Compared to laser crystallization methods, the thickness of the sidewall structure in the polycrystalline thin film fabrication method provided by this invention is easier to control than that of holes with a specified diameter formed by photolithography. Furthermore, a sidewall structure of a specified thickness can be formed directly through growth, even achieving nanoscale structures. This simplifies the operation and increases yield. Simultaneously, since deep holes do not need to be etched, the frequency of using high-precision photolithography is reduced, and the hard mask etching technology required for forming deep holes is eliminated, improving the fabrication efficiency of polycrystalline thin films. Furthermore, the preparation method in this invention does not require the use of LPCVD due to the issue of amorphous silicon filling. Instead, the sidewall structure is formed using PECVD (plasma-enhanced chemical vapor deposition), which requires a lower temperature and can fully meet the requirements for seed filters. This reduces the thermal budget of the process and lowers the manufacturing cost of polycrystalline thin films. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic flowchart illustrating a method for preparing a polycrystalline thin film according to an embodiment of this application;

[0034] Figures 2a to 2d This is a schematic structural diagram showing the relevant steps in the preparation method of a fan-shaped polycrystalline thin film according to an embodiment of this application;

[0035] Figure 3 This is a schematic flowchart illustrating a method for preparing a polycrystalline thin film according to an embodiment of this application;

[0036] Figures 4a to 4e This is a schematic structural diagram showing the relevant steps in the preparation method of a polycrystalline thin film according to an embodiment of this application.

[0037] Figure Labels

[0038] 1. Substrate; 11. Groove; 2. First preparatory layer; 21. Preset structure; 211. Sidewall structure; 212. Bottom surface structure; 3. Second preparatory layer; 31. Filling structure; 4. Thin film layer. Detailed Implementation

[0039] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0041] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0042] It should be noted that when an element is referred to as "fixedly connected" to another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intervening element. Conversely, when an element is referred to as being "directly on" another element, there is no intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0043] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0044] Firstly, this embodiment provides a method for preparing a polycrystalline thin film, see [link to previous section]. Figure 1 and combined Figures 2a to 2d The preparation method includes steps S101 to S106:

[0045] Step S101: Provide substrate 1.

[0046] The substrate 1 can be the substrate in the top layer of a CMOS device or an SOI substrate.

[0047] When substrate 1 is the substrate of the top layer device in a CMOS device, a metal-oxide-semiconductor (MODS) is disposed on the lower surface of substrate 1; the material of substrate 1 can be silicon or germanium, but is not limited to these. The MODS beneath substrate 1 can be NMOS or PMOS. In this embodiment, the material of substrate 1 is silicon, and the MODS beneath substrate 1 is NMOS.

[0048] Step S102: Etch groove 11 on the surface of substrate 1.

[0049] The width of the groove 11 is greater than 100 nm, such as 110 nm, 120 nm, 150 nm, or 200 nm. In this embodiment, the groove 11 is located on the upper surface of the substrate 1, and the width of the groove 11 is 120 nm. It should be noted that the depth of the groove 11 is determined by the wavelength of the laser used in step S107. For example, if the laser wavelength is 532 nm, the depth of the groove 11 will not be less than 300 nm.

[0050] Step S103: Deposit amorphous semiconductor material on the sidewall of the groove 11 to form a sidewall structure 211.

[0051] The thickness of the sidewall structure 211 is less than 150nm, preferably less than 100nm.

[0052] In an optional embodiment, step S103 includes step S1031, which involves depositing an amorphous semiconductor material on the upper surface of the substrate 1, the bottom surface of the groove 11, and the sidewalls of the groove 11. The amorphous semiconductor material can be amorphous silicon, amorphous Ge, SiGe, SiC, GaN, or other semiconductor materials, but is not limited to these.

[0053] In this embodiment, the sidewall structure 211 is made of amorphous silicon.

[0054] In an optional embodiment, step S103 includes step S1032, which involves depositing amorphous semiconductor material on the upper surface of the substrate 1, the bottom surface of the groove 11, and the sidewalls of the groove 11, and removing the amorphous semiconductor material deposited on the bottom surface of the groove 11.

[0055] Step S104: Fill the groove 11 with dielectric material and perform planarization to form a filling structure 31. The surface of the filling structure 31 is flush with the surface of the substrate 1.

[0056] The dielectric material is an insulating material. Specifically, the dielectric material includes at least one of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the dielectric material is silicon oxide.

[0057] It should be noted that during the filling of the dielectric material, the dielectric material can cover the amorphous semiconductor material on the substrate 1 obtained in step S1031; then, a chemical mechanical planarization process is performed to remove the dielectric material and amorphous semiconductor material above the substrate 1, thereby forming a preset structure 21 on the bottom and side surfaces of the groove 11 from the amorphous semiconductor material, and a filling structure 31 filling the remaining space in the groove 11. The preset structure 21 includes a sidewall structure 211, and the upper surface of the filling structure 31 obtained in step S104 and the upper surface of the sidewall are flush with the surface of the substrate 1. The dielectric material includes at least one of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the dielectric material is silicon oxide.

[0058] Step S105: Grow a thin film layer 4 on the surface of substrate 1.

[0059] Thin film layer 4 covers sidewall structure 211 and filling structure 31. The material of thin film layer 4 is the same as that of sidewall structure 21, and can be amorphous silicon, amorphous Ge, SiGe, SiC, GaN, or other semiconductor materials, but is not limited to these. In this embodiment, amorphous silicon is used as the material of thin film layer 4.

[0060] Furthermore, the step of growing the thin film layer 4 on the surface of the substrate 1 includes growing the thin film layer 4 at a temperature below 600 degrees Celsius. When the substrate 1 is the substrate of the top layer device in a CMOS device, by limiting the temperature for growing the thin film layer 4, it is possible to ensure that the metal oxide semiconductor beneath the substrate 1 is not damaged by heat treatment.

[0061] In an optional embodiment, prior to step S105, the preparation method further includes: reducing annealing the surface of the sidewall structure 211 exposed on the surface of the substrate 1.

[0062] By reducing and annealing the upper surface of the sidewall structure 211, the upper surface of the sidewall structure 211 can be directly contacted with the subsequent thin film layer 4, and hydrogen in the sidewall structure 211 can be released from the sidewall structure 211, thereby ensuring the quality of the thin film layer 4 recrystallizing into a polycrystalline thin film.

[0063] In an optional embodiment, the step of reducing annealing the surface of the sidewall structure 211 exposed on the surface of the substrate 1 includes:

[0064] In a nitrogen or inert gas environment, the surface of the sidewall structure 211 exposed on the substrate 1 is annealed at a temperature between 200°C and 600°C; the surface of the sidewall structure 211 exposed on the substrate 1 is etched with an acidic solution to remove the natural oxide layer on the upper surface of the sidewall structure 211. The inert gas can be argon or helium, etc.

[0065] Preferably, the surface of the sidewall structure 211 exposed on the surface of the substrate 1 is annealed at a temperature of 400 degrees Celsius.

[0066] The step of etching the surface of the sidewall structure 211 exposed on the surface of the substrate 1 with an acidic solution further includes, but is not limited to, etching the upper surface of the sidewall structure 211 for 30 seconds with a hydrofluoric acid solution of water and solute ratio of 100:1 at a temperature of 18 to 23 degrees Celsius.

[0067] It should be noted that during the reduction annealing process on the upper surface of the sidewall structure 211, the upper surfaces of the substrate 1 and the filling structure 31 are also subjected to reduction annealing. In this embodiment, the reduction annealing is only performed to remove the natural oxide layer formed by air oxidation on the upper surface of the sidewall structure 211, allowing the sidewall structure 211 to directly contact the subsequent thin film layer 4. This facilitates the formation of a polycrystalline silicon thin film after laser heat treatment, improving the quality of the polycrystalline thin film. In addition to using an acidic solution to remove the natural oxide layer on the upper surface of the sidewall structure 211, it can also be removed by grinding.

[0068] In this method, etching the upper surface of substrate 1 with an acidic solution can remove the natural oxide layer on the upper surface of substrate 1.

[0069] Step S106: Laser heat treatment of the surface of thin film layer 4 to recrystallize thin film layer 4 and form polycrystalline thin film.

[0070] The penetration depth of the laser source used in the surface of the laser heat treatment thin film layer 4 is less than the depth of the groove 11; the energy density of the laser source used in the surface of the laser heat treatment thin film layer 4 ranges from 1.5 J / cm2 to 3 J / cm2, and this embodiment does not further limit it.

[0071] Secondly, this embodiment provides a method for preparing polycrystalline thin films, see [link to relevant documentation]. Figure 3 and combined Figures 4a to 4e The preparation method includes steps S201 to S208:

[0072] Step S201: Provide substrate 1.

[0073] Step S202: Etch groove 11 on the surface of substrate 1.

[0074] Step S203: Deposit amorphous silicon on the upper surface of substrate 1, the bottom surface of groove 11 and the sidewall of groove 11 to form a first preparatory layer 2.

[0075] In this process, amorphous semiconductor material is deposited on the sidewall of the groove 11 to form a sidewall structure.

[0076] Step S204: Deposit a medium material on the first preparatory layer 2 to form the second preparatory layer 3.

[0077] The dielectric material covers the amorphous silicon on the upper surface of the substrate 1 and fills the remaining space in the groove 11.

[0078] Step S205: Perform chemical mechanical planarization on the first preparatory layer 2 and the second preparatory layer 3 so that the upper surface of the sidewall structure 211 and the upper surface of the structure formed by the dielectric material are flush with the upper surface of the substrate 1.

[0079] The first preparatory layer 2 after chemical mechanical planarization treatment constitutes a sidewall structure 211 and a bottom structure 212 parallel to the upper surface of the substrate 1. That is, the aforementioned pre-designed structure 21 is composed of the sidewall structure 211 and the bottom structure 212; the dielectric material after chemical mechanical planarization treatment constitutes the filling structure 31.

[0080] Step S206: Restore the upper surface of the sidewall structure 211 to annealing.

[0081] Step S207: Grow a thin film layer 4 on the upper surface of substrate 1.

[0082] The thin film layer 4 covers the sidewall structure 211 and the filling structure 31.

[0083] Step S208: Laser heat treatment of the surface of thin film layer 4 to recrystallize thin film layer 4 and form polycrystalline thin film.

[0084] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0085] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for preparing a polycrystalline thin film, characterized in that, include: Provide substrate; Grooves are etched into the surface of the substrate; Amorphous semiconductor material is deposited on the sidewalls of the groove to form a sidewall structure; A dielectric material is filled into the groove and planarized to form a filling structure, the surface of which is flush with the surface of the substrate. A thin film layer is grown on the surface of the substrate, the thin film layer covering the sidewall structure and the filler structure, the material of the thin film layer being the same as the material of the sidewall structure; Prior to the step of growing a thin film layer on the surface of the substrate, the preparation method further includes: reducing annealing the surface of the sidewall structure that exposes the surface of the substrate; The surface of the thin film layer is subjected to laser heat treatment to recrystallize the thin film layer and form a polycrystalline thin film.

2. The preparation method according to claim 1, characterized in that, The width of the groove is greater than 100 nm.

3. The preparation method according to claim 1, characterized in that, The thickness of the sidewall structure is less than 150 nm.

4. The preparation method according to claim 1, characterized in that, The surface of the substrate opposite to the groove is provided with a metal oxide semiconductor.

5. The preparation method according to claim 1, characterized in that, The medium material is an insulating material.

6. The preparation method according to claim 1, characterized in that, The substrate material includes: silicon or germanium; The dielectric material includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

7. The preparation method according to claim 1, characterized in that, The step of growing a thin film layer on the surface of the substrate includes: The thin film layer is grown at a temperature below 600 degrees Celsius.

8. The preparation method according to claim 1, characterized in that, The laser source used in the laser heat treatment of the surface of the thin film layer has a penetration depth that is less than the depth of the groove.

9. The preparation method according to any one of claims 1 to 8, characterized in that, The step of reducing and annealing to expose the surface of the sidewall structure on the substrate surface includes: The surface of the sidewall structure exposed on the substrate surface is annealed in a nitrogen or inert gas environment at a temperature between 200°C and 600°C. An acidic solution is used to etch the surface of the sidewall structure that exposes the substrate surface in order to remove the oxide layer on the surface of the sidewall structure that exposes the substrate surface.

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