Semiconductor device and method of manufacturing the same

Abstract

Some embodiments of the invention include a method of fabricating a semiconductor device including forming a first recess in a first wafer, wherein the first recess is at a first front side surface of the first wafer and exposes a first interconnect structure of the first wafer. Forming a second recess in a second wafer, wherein the second recess is at a second front side surface of the second wafer. Filling the first recess with a first polymer. Filling the second recess with a second polymer. Bonding the first front side surface of the first wafer to the second front side surface of the second wafer such that the first polymer is bonded to the second polymer. Removing the first polymer in the first recess and the second polymer in the second recess. And, depositing a metal in the first recess and the second recess.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices and methods of manufacturing the same, and particularly to hybrid bonding processes of semiconductor devices. BACKGROUND

[0002] Three-dimensional (3D) integrated circuits are structures formed by vertically stacking wafers. The stacked wafers are connected by through silicon vias (TSVs) or copper-copper bonding. The resulting structures can achieve a variety of advantages. For example, 3D integrated circuits have smaller footprints to increase the density of integration, and shorter lines in 3D integrated circuits can reduce the power consumption of the 3D integrated circuits. However, the technology of 3D integrated circuits still suffers from a number of problems to be solved. SUMMARY

[0003] Some embodiments of the present disclosure include a method of manufacturing a semiconductor device, including forming a first recess in a first wafer, wherein the first recess is at a first front side surface of the first wafer and exposes a first interconnect structure of the first wafer. Forming a second recess in a second wafer, wherein the second recess is at a second front side surface of the second wafer. Filling the first recess with a first polymer. Filling the second recess with a second polymer. Bonding the first front side surface of the first wafer to the second front side surface of the second wafer such that the first polymer is bonded to the second polymer. Removing the first polymer in the first recess and the second polymer in the second recess. And, depositing a metal in the first recess and the second recess.

[0004] In some embodiments, the first recess has a different size than the second recess.

[0005] In some embodiments, filling the first recess with the first polymer includes coating a polymer material on the first front side surface of the first wafer. And, planarizing the first front side surface of the first wafer to remove excess portions of the polymer material to form the first polymer in the first recess.

[0006] In some embodiments, during the bonding of the first front side surface of the first wafer to the second front side surface of the second wafer such that the first polymer is bonded to the second polymer, the first dielectric layer of the first wafer is bonded to the second dielectric layer of the second wafer.

[0007] In some embodiments, the depositing of the metal in the first recess and the second recess is such that the metal deposited in the first recess and the second recess is monolithic.

[0008] In some embodiments, the method further includes, before filling the second recess with the second polymer, conformally depositing an insulating layer in the second recess.

[0009] In some implementations, forming the second recess in the second wafer includes forming a pad recess of the second recess on a second front side surface of the second wafer. Also, forming a substrate via hole of the second recess in the pad recess, and the substrate via hole extends to a substrate of the second wafer.

[0010] In some implementations, the method further includes, after bonding the first front side surface of the first wafer to the second front side surface of the second wafer, grinding the second wafer from a back side surface of the second wafer to expose the second polymer in the substrate via hole. Also, forming a third dielectric layer on the back side surface of the second wafer before removing the first polymer in the first recess and the second polymer in the second recess.

[0011] In some implementations, the method further includes, after depositing the metal in the first recess and the second recess, forming a bump on the metal in the substrate via hole.

[0012] In some implementations, the method further includes, after removing the first polymer in the first recess and the second polymer in the second recess, depositing a barrier layer in the first recess and the second recess.

[0013] In some implementations, the first polymer in the first recess is removed using a chemical solvent.

[0014] In some implementations, the metal includes copper.

[0015] In some implementations, a width of the first recess is between 0.2 microns and 20 microns.

[0016] Some implementations of the disclosure include a semiconductor device including a first wafer, a second wafer, a substrate via structure, a conductive pad, and a barrier layer. The first wafer includes a first interconnect structure. The second wafer includes a second interconnect structure bonded to the first interconnect structure of the first wafer. The substrate via structure extends through the second wafer. The conductive pad contacts the substrate via structure and the first interconnect structure of the first wafer, where a portion of the conductive pad is embedded in the second wafer. The barrier layer extends from a sidewall of the substrate via structure to a bottom surface of the conductive pad.

[0017] In some implementations, the barrier layer is a monolithic material.

[0018] In some implementations, the barrier layer contacts a front side surface of the first wafer.

[0019] In some implementations, the conductive pad and the substrate via structure are a monolithic material.

[0020] In some implementations, the semiconductor device further includes a dielectric layer covering the second wafer such that the second wafer is directly between the first wafer and the dielectric layer.

[0021] In some embodiments, the barrier layer contacts the dielectric layer with the first interconnect structure of the first wafer.

[0022] The present disclosure improves the hybrid bonding process of semiconductor devices. More particularly, a polymer material is used to form pads in different sized recesses. Wafers with different sized pads formed from the polymer material can be well planarized and can reduce the dishing issue of the planarization process. Thus, the subsequently formed conductive pads can be formed with different sizes. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figures 1A to 9 Cross-sectional views of intermediate stages of a process of a semiconductor device according to some embodiments of the present disclosure are illustrated. DETAILED DESCRIPTION

[0024] Several embodiments of the present disclosure will be described with respect to the following figures, in which the figures will serve to illustrate one or more implementations of embodiments of the disclosure. However, the present disclosure should not be limited to the embodiments described and shown in the figures. Rather, the figures are used for explanation only and serve only as a representative of possible implementations. It should be understood that the figures are not intended to limit the spirit or scope of the present disclosure in any way.

[0025] Some embodiments of the present disclosure are directed to a way of manufacturing semiconductor devices that improves the hybrid bonding process of semiconductor devices by bonding together polymer pads of two wafers. After the hybrid bonding process, the semiconductor pads are replaced by conductive pads. Thus, the subsequently formed conductive pads can be formed with different sizes.

[0026] Figures 1A to 9 Cross-sectional views of intermediate stages of a process of a semiconductor device according to some embodiments of the present disclosure are illustrated. Reference is made to Figure 1AA first wafer 100 is provided. The first wafer 100 can include a first substrate 102, first device elements 104, first interconnect structures 106, and first dielectric layers 108. The first substrate 102 can include any suitable material, such as a semiconductor material (e.g., silicon). The first device elements 104 are disposed on the first substrate 102 and can be any suitable elements, such as active regions of semiconductor devices or the like. For example, the first device elements 104 can be active elements, such as transistors or diodes. The first device elements 104 can also be passive elements, such as resistors, inductors, or capacitors, arranged on the first substrate 102. The first interconnect structures 106 are used to provide electrical interconnections between the first device elements 104 and are made of conductive materials. In some embodiments, the first interconnect structures 106 include conductive via elements 105 and conductive lines 107. The conductive via elements 105 are connected to the conductive lines 107 in different layers to form the first interconnect structures 106. The first dielectric layers 108 cover the first substrate 102, the first device elements 104, and the first interconnect structures 106 to electrically isolate adjacent first interconnect structures 106. The first dielectric layers 108 can be made of any suitable material. In some embodiments, the first dielectric layers 108 are made of silicon dioxide, silicon carbide, low-k materials, or the like.

[0027] A plurality of first recesses 110 are formed in a first front side surface 101 of the first wafer 100 and expose the first interconnect structures 106. The first front side surface 101 is also a surface of the first dielectric layers 108. The first recesses 110 are formed by a patterning process and have different sizes. In other words, the sizes of the first recesses 110 are not strictly controlled. In some embodiments, the width of each first recess 110 is between 0.2 micrometers and 20 micrometers.

[0028] Referring to Figure 1B A second wafer 200 is provided. The second wafer 200 can include a second substrate 202, second device elements 204, second interconnect structures 206, and second dielectric layers 208. The second substrate 202, the second device elements 204, the second interconnect structures 206, and the second dielectric layers 208 are similar or identical to the first substrate 102, the first device elements 104, the first interconnect structures 106, and the first dielectric layers 108, respectively. Therefore, related details are not repeated here.

[0029] A plurality of second recesses 210 are formed in a second front side surface 201 of the second wafer 200. Forming the second recesses 210 includes first forming pad recesses 212 in the second front side surface 201 of the second wafer 200. Then, substrate through-holes 214 of the second recesses 210 are formed in the pad recesses 212 and extend to the second substrate 202 of the second wafer 200. The pad recesses 212 and the first recesses 110 will be used to deposit conductive pads (e.g., solder pads) on the second wafer 200. Figure 8the conductive pads 304 in the first wafer 100, and the substrate via holes 214 will be used to deposit via members (e.g. Figure 8 The second front side surface 201 is a surface of the second dielectric layer 208. The substrate via holes 214 do not expose the second interconnect structures 206, so materials formed in the substrate via holes 214 in subsequent processes will not contact the second interconnect structures 206, to ensure that the substrate via structures (e.g. Figure 8 The second front side surface 201 is a surface of the second dielectric layer 208. The substrate via holes 214 do not expose the second interconnect structures 206, so materials formed in the substrate via holes 214 in subsequent processes will not contact the second interconnect structures 206, to ensure that the substrate via structures (e.g.

[0030] Referring to Figure 2 In some embodiments, an insulating layer 215 is conformally deposited in the second recesses 210. The insulating layer 215 is used for isolation between metals subsequently formed in the second recesses 210. In some embodiments, the insulating layer 215 can not be formed in the second recesses 210.

[0031] Referring to Figure 3A The first recesses 110 are filled with the first polymers 120, respectively. More specifically, a polymer material is coated on the first front side surface 101 of the first wafer 100, by, for example, spin coating. During the coating of the polymer material, portions of the polymer material fill in the first recesses 110, while excess portions of the polymer material are on the first front side surface 101 of the first wafer 100 and not in the first recesses 110. Then, the first front side surface 101 of the first wafer 100 is planarized to remove the excess portions of the polymer material, to form the first polymers 120 in the first recesses 110. The first wafer 100 can be planarized by any suitable means, such as chemical mechanical polishing (CMP). Each of the first polymers 120 acts as a sacrificial pad, and will be removed in subsequent processes (see Figure 7) are replaced. The polymer material is a flowable and low thermal expansion material. In some embodiments, the polymer material used to form the first polymer 120 is an organic material, such as low density polyethylene (LDPE), high density polyethylene (HDPE), polypropylene (PP), polyvinyl chloride (PVC), polystyrene (PS), nylon, Teflon, thermoplastic polyurethane (TPU), or the like. In the planarization process, the polymer material can shrink like other materials (e.g., metal). Thus, after the polymer material is planarized to form the first polymer 120 in the different sized first recesses 110, the first front side surface 101 is still planar (or smooth). Because of the good stretchability of the polymer material, the different sized first polymers 120 at the first front side surface 101 are planarized at substantially the same height, thereby reducing the dishing issue in the planarization process. Referring to Figure 3B The second recesses 210 are filled with the second polymer 220, respectively. The process of filling the second recesses 210 with the second polymer 220 is similar or the same as the process of filling the first recesses 110 with the first polymer 120, the material of the second polymer 220, and the material of the first polymer 120 are similar or the same as described above. Thus, the related details are not repeated here. Figure 3A

[0032] Referring to Figure 4 ​The hybrid bonding process is performed. In the hybrid bonding process, the second wafer 200 is flipped upside down and placed on the first wafer 100 to form the semiconductor device 300. The first front side surface 101 of the first wafer 100 is bonded to the second front side surface 201 of the second wafer 200 such that the first polymer 120 is bonded to the second polymer 220. In addition, the first dielectric layer 108 of the first wafer 100 is also bonded to the second dielectric layer 208 of the second wafer 200. The first front side surface 101 of the first wafer 100 and the second front side surface 201 of the second wafer 200 are substantially planar and do not suffer from the recess problem. Therefore, the first wafer 100 and the second wafer 200 can be closely bonded to each other so that the first polymer 120 and the second polymer 220 can contact each other. The first polymer 120 in the first recess 110 and the second polymer 220 in the second recess 210 are formed in different sizes so that the size of each first polymer 120 does not need to be the same as the corresponding second polymer 220. That is, the sidewall of the first polymer 120 does not need to align with the sidewall of the corresponding second polymer 220. The term "corresponding second polymer 220" as used herein refers to the second polymer 220 that is in contact with the first polymer 120.

[0033] Referring to Figure 5 After the first front side surface 101 of the first wafer 100 is bonded to the second front side surface 201 of the second wafer 200, the second wafer 200 is thinned from the back side surface 209 of the second wafer 200 to expose the second polymer 220 in the substrate via hole 214 of the second recess 210. The back side surface 209 is a surface of the second substrate 202 and is opposite to the second front side surface 201. The second substrate 202 and the second polymer 220 in the substrate via hole 214 are made of different materials. Only a portion of the second substrate 202 can be removed in the process of thinning the second substrate 202, and the portion of the second polymer 220 initially embedded in the second substrate 202 is hardly removed. Therefore, the second polymer 220 protrudes from the second recess 210 and penetrates through the second substrate 202. In some embodiments, the insulating layer 215 exposed from the second substrate 202 of the second wafer 200 is removed in the grinding process, as shown in FIG. 2C. In some other embodiments, the insulating layer 215 exposed from the second substrate 202 of the second wafer 200 can be retained. Figure 5

[0034] Referring to Figure 6 ​A third dielectric layer 230 is formed on the backside surface 209 of the second wafer 200. In some embodiments, the third dielectric layer 230 is first formed to completely cover the backside surface 209 of the second wafer 200 and the protruding second polymer 220. Then, the third dielectric layer 230 is etched back to expose the second polymer 220. In this way, the third dielectric layer 230 is formed in between adjacent second polymers 220 to provide electrical isolation between subsequently formed contacts. Any suitable material can be used to form the third dielectric layer 230. In some embodiments, the third dielectric layer 230 can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like, and the third dielectric layer 230 can be made of silicon dioxide, silicon carbide, low-k material, or the like.

[0035] Referring to Figure 7 The first polymer 120 in the first recess 110 and the second polymer 220 in the second recess 210 are removed. After the first polymer 120 and the second polymer 220 are removed, the first recess 110 and the second recess 210 collectively form a space S in the semiconductor device 300. The space S extends from the backside surface 209 of the second wafer 200 to the first wafer 100 to expose the first interconnect structure 106. The space S is between and does not contact the adjacent second interconnect structures 206. The first polymer 120 and the second polymer 220 can be removed by any suitable means. In some embodiments, the first polymer 120 and the second polymer 220 are removed by a selective etching process that includes the use of a chemical solvent. The etching rate of this chemical solvent to remove polymer materials (e.g., the first polymer 120 and the second polymer 220) is faster than to remove dielectric materials (e.g., the first dielectric layer 108, the second dielectric layer 208, the insulating layer 215, and the third dielectric layer 230).

[0036] Referring to Figure 8A barrier layer 302 is conformally formed in the first recess 110 and the second recess 210. Then, a metal material is deposited in the first recess 110 and the second recess 210 to form the conductive pads 304 and the substrate via structures 306. The barrier layer 302 is used to prevent the metal material of the conductive pads 304 and the substrate via structures 306 from diffusing to the first dielectric layer 108 and the second dielectric layer 208, which can cause damage to the semiconductor device 300. The conductive pads 304 and the substrate via structures 306 can be formed in a single process. Thus, each conductive pad 304 and the corresponding substrate via structure 306 is a single continuous material and is a monolithic material. Similarly, each barrier layer 302 is conformally deposited in the first recess 110 and the corresponding second recess 210 in a single process. Thus, the barrier layer 302 is a single continuous material extending from the sidewalls of the substrate via structures 306, the sidewalls of the conductive pads 304 to the bottom surface of the conductive pads 304 and the barrier layer 302 is a monolithic material. The barrier layer 302, the conductive pads 304 and the substrate via structures 306 comprise suitable materials. In some embodiments, the barrier layer 302 can comprise tantalum and the conductive pads 304 and the substrate via structures 306 can comprise copper.

[0037] Although Figure 8 Although the conductive pads 304 and the substrate via structures 306 are illustrated as a single continuous material fabricated in a single process, the conductive pads 304 and the substrate via structures 306 can be made of different materials. For example, the conductive pads 304 can be first formed in the pad recesses 212 of the first recess 110 and the second recess 210. The barrier layer 302 can be conformally formed on the sidewalls of the conductive pads 304 and the substrate via holes 214. Then, the material of the substrate via structures 306 can be subsequently formed in the substrate via holes 214.

[0038] Referring Figure 9 After the metal is deposited in the first recess 110 and the second recess 210 to form the conductive pads 304 and the substrate via structures 306, bumps 308 are formed on the substrate via structures 306. The bumps 308 can be further connected to other application elements, such as a circuit board. The bumps 308 are made of a conductive material. In some embodiments, the bumps 308 are made of tin.

[0039] In Figure 9In the semiconductor device 300, a first wafer 100, a second wafer 200, a substrate through-hole structure 306, a conductive pad 304, and a barrier layer 302 are included. The first wafer 100 includes a first interconnect structure 106. The second wafer 200 includes a second interconnect structure 206, which is bonded to the first interconnect structure 106 of the first wafer 100. The substrate through-hole structure 306 extends through the second wafer 200. The conductive pad 304 contacts the substrate through-hole structure 306 and the first interconnect structure 106 of the first wafer 100, wherein a portion of the conductive pad 304 is embedded in the second wafer 200. The barrier layer 302 extends from the sidewall 306S of the substrate through-hole structure 306 to the bottom surface 304B of the conductive pad 304.

[0040] Specifically, the barrier layer 302 laterally surrounds the substrate through-hole structure 306 and the conductive pad 304. Because the barrier layer 302 is formed after a hybrid bonding process, no interface (e.g., bonding interface) will be formed in the barrier layer 302 near the bonding interface between the first wafer 100 and the second wafer 200 (e.g., the first front surface 101 and the second front surface 201). Furthermore, because the first polymer 120 and the second polymer 220 (see...) are removed... Figure 6 and Figure 7 Afterwards, a portion of the first front surface 101 is exposed, and the barrier layer 302 also covers and contacts a portion of the first front surface 101. In other words, because the sidewalls of the first polymer 120 may not align with the corresponding sidewalls of the second polymer 220 (see...). Figure 4 The barrier layer 302 may be horizontally formed on the first front surface 101 of the first wafer 100 (or the second front surface 201 of the second wafer 200).

[0041] like Figure 9 As shown, each conductive pad 304 has a first portion embedded in the first wafer 100 and a second portion embedded in the second wafer 200. Because the conductive pad 304 is formed after a hybrid bonding process, no interface (e.g., bonding interface) is formed in the conductive pad 304 near the bonding interface between the first wafer 100 and the second wafer 200 (e.g., the first front surface 101 and the second front surface 201).

[0042] The semiconductor device 300 further includes a third dielectric layer 230 covering a second wafer 200, such that the second wafer 200 is directly located between the first wafer 100 and the third dielectric layer 230. A barrier layer 302 contacts the third dielectric layer 230 and the first interconnect structure 106 of the first wafer 100. In other words, the barrier layer 302 extends from the third dielectric layer 230 to the conductive via 105 of the first interconnect structure 106 (see FIG. 1).

[0043] Some embodiments of the present application provide some advantages. For example, the conductive pads can be formed to have different sizes, and in a hybrid bonding process, the conductive pads in one wafer do not need to be aligned with the conductive pads in another wafer. The sacrificial pads made of polymer material have good stretchability, and when planarizing the surface of the wafer, the good stretchability of the polymer material makes the surface of the wafer more planar. In addition, the polymer material is not so easy to thermally expand and contract during the wafer planarization process. Although the sacrificial pads are formed to have different sizes, the surface of the wafer does not suffer from the problem of dishing. When having such advantages, the problems caused when planarizing the wafer to form a semiconductor device can be reduced or solved.

[0044] While the application has been disclosed in an implementation with reference to a few embodiments, it will be apparent to those skilled in the art that various modifications and variations can be made therein without departing from the spirit and scope of the application. Thus, it is intended that the present application cover the modifications and variations of this implementation provided they come within the scope of the appended claims and their equivalents.

[0045] [SYMBOL DESCRIPTION]

[0046] 100: first wafer

[0047] 101: first front side surface

[0048] 102: first substrate

[0049] 104: first device element

[0050] 105: conductive via

[0051] 106: first interconnect structure

[0052] 107: conductive line

[0053] 108: first dielectric layer

[0054] 110: first recess

[0055] 120: first polymer

[0056] 200: second wafer

[0057] 201: second front side surface

[0058] 202: second substrate

[0059] 204: second device element

[0060] 206: second interconnect structure

[0061] 208: second dielectric layer

[0062] 209: back side surface

[0063] 210: second recess

[0064] 212: pad recess

[0065] 214: substrate via hole

[0066] 215: insulating layer

[0067] 220: second polymer

[0068] 230: third dielectric layer

[0069] 300: semiconductor device

[0070] 302: barrier layer

[0071] 304: conductive pad

[0072] 304B: bottom surface

[0073] 306: substrate via structure

[0074] 306S: sidewall

[0075] 308: bump

[0076] S: space.

Claims

1. A method of manufacturing a semiconductor device, characterized by, comprising: forming a first recess in a first wafer, wherein the first recess is on a first front side surface of the first wafer and exposes a first interconnect structure of the first wafer; forming a second recess in a second wafer, wherein the second recess is on a second front side surface of the second wafer; filling the first recess with a first polymer; filling the second recess with a second polymer; bonding the first front side surface of the first wafer to the second front side surface of the second wafer such that the first polymer is bonded to the second polymer; removing the first polymer in the first recess and the second polymer in the second recess; and depositing a metal in the first recess and the second recess.

2. The method of claim 1, wherein a size of the first recess is different from a size of the second recess.

3. The method of claim 1, wherein filling the first recess with the first polymer comprises: coating a polymer material on the first front side surface of the first wafer; and planarizing the first front side surface of the first wafer to remove excess portions of the polymer material to form the first polymer in the first recess.

4. The method of claim 1, wherein during bonding the first front side surface of the first wafer to the second front side surface of the second wafer such that the first polymer is bonded to the second polymer, a first dielectric layer of the first wafer is bonded to a second dielectric layer of the second wafer.

5. The method of claim 4, wherein depositing the metal in the first recess and the second recess such that the metal deposited in the first recess and the second recess is monolithic. further comprising, prior to filling the second recess with the second polymer, conformally depositing an insulating layer in the second recess.

6. The method of claim 1, wherein, 7. The method of claim 1, wherein forming the second recess in the second wafer comprises: forming a pad recess of the second recess on the second front side surface of the second wafer; and forming a substrate via in the pad recess, and the substrate via extends to a substrate of the second wafer. further comprising:

8. The method of claim 7, wherein, after bonding the first front side surface of the first wafer to the second front side surface of the second wafer, grinding the second wafer from a backside surface of the second wafer to expose the second polymer in the substrate via; and prior to removing the first polymer in the first recess and the second polymer in the second recess, forming a third dielectric layer on the backside surface of the second wafer. further comprising, after depositing the metal in the first recess and the second recess, forming a bump on the metal in the substrate via. further comprising, after removing the first polymer in the first recess and the second polymer in the second recess, depositing a barrier layer in the first recess and the second recess.

9. The method of claim 7, wherein, 11. The method of claim 1, wherein the first polymer in the first recess is removed using a chemical solvent.

10. The method of claim 1, wherein, 12. The method of claim 1, wherein the metal comprises copper.

13. The method of claim 1, wherein a width of the first recess is between 0.2 microns and 20 microns. comprising: ​ 14. A semiconductor device, characterized by comprising: ​ a first wafer comprising a first interconnect structure; a second wafer comprising a second interconnect structure bonded to the first interconnect structure of the first wafer; a substrate via structure extending through the second wafer; a conductive pad contacting the substrate via structure and the first interconnect structure of the first wafer, wherein the conductive pad has a first portion embedded in the first wafer and a second portion embedded in the second wafer, sidewalls of the first portion and the second portion are misaligned, such that the first portion of the conductive pad has a horizontal surface facing the second wafer; and a barrier layer extending from sidewalls of the substrate via structure to the sidewalls of the second portion of the conductive pad, the horizontal surface of the first portion of the conductive pad, the sidewalls of the first portion of the conductive pad, and to a bottom surface of the conductive pad, and the barrier layer is a monolithic material.

15. The semiconductor device of claim 14, wherein the barrier layer contacts a front side surface of the first wafer.

16. The semiconductor device of claim 14, wherein the conductive pad and the substrate via structure are a monolithic material. further comprising a dielectric layer covering the second wafer, such that the second wafer is directly between the first wafer and the dielectric layer.

17. The semiconductor device according to claim 14, wherein 18. The semiconductor device of claim 17, wherein the barrier layer contacts the dielectric layer and the first interconnect structure of the first wafer. ​

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