Thin film transistor, substrate and method for manufacturing the same, display device

Abstract

The embodiment of the present disclosure provides a thin film transistor, a substrate and a preparation method thereof, and a display device. The thin film transistor comprises: a first electrode located on the upper side of a substrate; a first insulating layer located on the upper side of the first electrode; a protruding structure located on the upper side of the first insulating layer and extending along a first direction; an active layer located on the upper side of the protruding structure and comprising a first conductive region, a second conductive region and a channel, the channel crossing the protruding structure along a second direction, and the first conductive region being connected with the first electrode; a second insulating layer located on the upper side of the active layer; a gate electrode located on the upper side of the second insulating layer, and the orthographic projection of the channel on the substrate being located within the orthographic projection of the gate electrode on the substrate; a third insulating layer located on the upper side of the gate electrode; and a second electrode located on the upper side of the third insulating layer and connected with the second conductive region. The technical scheme of the present disclosure can increase the length of the channel and reduce the short channel effect.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a thin-film transistor, a substrate, a method for fabricating the same, and a display device. Background Technology

[0002] Virtual Reality / Augmented Reality (VR / AR) technology is currently a popular display technology. In VR displays, the core component is the head-mounted display (HMD). Because the screen is very close to the eyes, VR devices are near-eye display devices. Near-eye display devices have extremely high resolution requirements. VR displays need a 6K pixel resolution within a 100-degree field of view to completely eliminate the screen-door effect. Currently, most VR products have a display resolution in the range of 2K to 4K; higher resolution screens are an inevitable requirement for future product development.

[0003] LCD (Liquid Crystal Display) technology is easier to achieve high resolution compared to Organic Light-Emitting Diode (OLED) display technology, making it the mainstream display technology in VR / AR products. However, LCD technology requires backlighting as its light source, resulting in higher energy consumption and limiting its application in products. The power consumption of an LCD display is directly related to its aperture ratio, which determines the brightness of the display screen. Figure 1 This is a planar schematic diagram of an LCD product. Figure 1 The circuit uses a conventional 1T1C structure, such as... Figure 1 As shown, the data line 11 extends along the second direction Y, the gate line 17 extends along the first direction X, the channel 153 of the active layer is inclined, and a light-shielding layer 50 is provided below the active layer. Figure 1 The opening region 40 is shown in the figure. Figure 1 The aperture ratio of the array substrate shown is approximately 39%. From Figure 1 It can be seen from this that Figure 1 The light-shielding layer 50 occupies a large space, limiting the opening ratio.

[0004] In related technologies, increasing the aperture ratio leads to a reduction in the channel length of the active layer, resulting in a short-channel effect. Summary of the Invention

[0005] This disclosure provides a thin-film transistor, a substrate, a method for fabricating the same, and a display device to solve or alleviate one or more technical problems in the prior art.

[0006] As a first aspect of the present disclosure, the present disclosure provides a thin-film transistor, comprising:

[0007] Base;

[0008] The first pole is located on one side of the substrate;

[0009] The first insulating layer is located on the side of the first electrode facing away from the substrate;

[0010] A raised structure is located on the side of the first insulating layer away from the substrate, and the raised structure extends along a first direction;

[0011] An active layer is located on the side of the protrusion structure away from the substrate. The active layer includes a first conductive region, a second conductive region, and a channel located between the first conductive region and the second conductive region. The channel crosses the protrusion structure along a second direction. The first conductive region is connected to the first electrode through a first via penetrating the first insulating layer. The second direction intersects with the first direction.

[0012] The second insulating layer is located on the side of the active layer away from the substrate;

[0013] The gate is located on the side of the second insulating layer away from the substrate, and the orthogonal projection of the channel on the substrate is within the range of the orthogonal projection of the gate on the substrate.

[0014] The third insulating layer is located on the side of the gate that is away from the substrate;

[0015] The second electrode is located on the side of the third insulating layer away from the substrate. The second electrode is connected to the second conductive region through a second via penetrating the third and second insulating layers.

[0016] In one embodiment, a fourth insulating layer is further included, which is located between the raised structure and the active layer, and the first conductive region is connected to the first electrode through a first via penetrating the fourth insulating layer and the first insulating layer.

[0017] In one embodiment, the thickness of the protrusion is greater than 1 μm; and / or, the size of the orthogonal projection of the protrusion onto the substrate in the second direction is 1.5 μm to 2 μm.

[0018] In one embodiment, the protruding structure is made of SOG or a black organic material.

[0019] In one embodiment, the active layer is made of indium gallium zinc oxide.

[0020] As a second aspect of the present disclosure, the present disclosure provides a substrate including a thin-film transistor as described in any embodiment of the present disclosure.

[0021] In one embodiment, the substrate further includes a data line disposed on the same layer as the first electrode, the data line extending along a second direction, and a portion of the data line being the first electrode;

[0022] The substrate also includes a gate line disposed in the same layer as the gate, the gate line extending along a first direction, and a portion of the gate line being the gate.

[0023] In one embodiment, the orthographic projection of the protrusion on the substrate is within the range of the orthographic projection of the grid line on the substrate.

[0024] In one embodiment, the orthographic projection of the protrusion on the substrate and the orthographic projection of the data line on the substrate have a first overlapping region, which is located within the range of the orthographic projection of the channel on the substrate.

[0025] In one embodiment, the dielectric constant of the material of the protrusion structure is less than the dielectric constant of the active layer material.

[0026] In one embodiment, the data cable is made of a transparent conductive material, and the second electrode is also made of a transparent conductive material.

[0027] As a third aspect of this disclosure, this disclosure provides a method for preparing a substrate, comprising:

[0028] A data line is formed on one side of the substrate, the data line extends along a second direction, and a portion of the data line is the first electrode of the thin-film transistor;

[0029] A first insulating layer is formed on the side of the data cable that is away from the base;

[0030] A raised structure is formed on the side of the first insulating layer away from the substrate, and the raised structure extends along the first direction;

[0031] An active layer of a thin-film transistor is formed on the side of the protrusion structure away from the substrate. The active layer includes a first conductive region, a second conductive region, and a channel located between the first conductive region and the second conductive region. The channel crosses the protrusion structure along a second direction. The first conductive region is connected to the first electrode through a first via penetrating the first insulating layer.

[0032] A second insulating layer is formed on the side of the active layer away from the substrate;

[0033] A gate line is formed on the side of the second insulating layer away from the substrate. The gate line extends along the first direction. A portion of the gate line is the gate of the thin-film transistor. The orthogonal projection of the channel on the substrate is within the range of the orthogonal projection of the gate line on the substrate. The second direction is not parallel to the first direction.

[0034] A third insulating layer is formed on the side of the grid line away from the substrate, and a second via is formed in the third insulating layer, penetrating the third insulating layer and the second insulating layer;

[0035] A second electrode of a thin-film transistor is formed on the side of the third insulating layer away from the substrate, and the second electrode is connected to the second conductive region through a second via.

[0036] As a fourth aspect of the present disclosure, the present disclosure provides a display device that includes a thin-film transistor as described in any embodiment of the present disclosure, or includes a substrate as described in any embodiment of the present disclosure.

[0037] The technical solution of this disclosure improves the performance of thin-film transistors by setting a protruding structure and having the channel cross the protruding structure in a second direction, thereby increasing the length of the channel and avoiding the short-channel effect caused by the channel being too short.

[0038] The above overview is for illustrative purposes only and is not intended to be limiting in any way. Further aspects, embodiments, and features of this disclosure will become readily apparent from the accompanying drawings and the following detailed description, in addition to the illustrative aspects, embodiments, and features described above. Attached Figure Description

[0039] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments according to this disclosure and should not be construed as limiting the scope of this disclosure.

[0040] Figure 1 A plan view of an LCD product;

[0041] Figure 2 A plan view of an LCD product;

[0042] Figure 3 This is a planar schematic diagram of a substrate according to an embodiment of the present disclosure;

[0043] Figure 4 for Figure 3 A schematic diagram of cross-section AA of the substrate shown in one embodiment;

[0044] Figure 5 This is a schematic diagram of a substrate preparation method according to an embodiment of the present disclosure;

[0045] Figure 6A This is a planar schematic diagram of a substrate after data lines have been formed in an embodiment of this disclosure;

[0046] Figure 6B for Figure 6A Schematic diagram of section AA in the diagram;

[0047] Figure 7A This is a planar schematic diagram of a substrate after a protrusion structure has been formed in an embodiment of the present disclosure;

[0048] Figure 7B for Figure 7A Schematic diagram of section AA in the diagram;

[0049] Figure 8A This is a planar schematic diagram of a substrate after a fourth insulating layer has been formed in an embodiment of the present disclosure;

[0050] Figure 8B for Figure 8A Schematic diagram of section AA in the diagram;

[0051] Figure 9A This is a planar schematic diagram of a substrate after an active layer has been formed in an embodiment of the present disclosure;

[0052] Figure 9B for Figure 9A Schematic diagram of section AA in the diagram;

[0053] Figure 10A This is a planar schematic diagram of a substrate after gate lines have been formed in an embodiment of the present disclosure;

[0054] Figure 10B for Figure 10A Schematic diagram of section AA in the diagram;

[0055] Figure 11 This is a schematic diagram of the ion implantation process for the active layer;

[0056] Figure 12A This is a planar schematic diagram of a substrate after a third insulating layer has been formed in an embodiment of this disclosure;

[0057] Figure 12B for Figure 12A Schematic diagram of section AA in the diagram;

[0058] Figure 13 for Figure 3 A schematic diagram of cross-section AA of the substrate shown in another embodiment;

[0059] Figure 14A These are characteristic curves of thin-film transistors in the substrate of this embodiment;

[0060] Figure 14B Characteristic curves of thin-film transistors in substrates using conventional techniques;

[0061] Figure 15 This is a microscope diagram of the substrate at the protrusion structure location in an embodiment of this disclosure.

[0062] Explanation of reference numerals in the attached figures:

[0063] 10. Substrate; 11. Data line; 111. First electrode; 12. First insulating layer; 13. Protrusion structure; 14. Fourth insulating layer; 15. Active layer; 151. First conductive region; 152. Second conductive region; 153. Channel; 16. Second insulating layer; 17. Gate line; 171. Gate; 18. Third insulating layer; 191. Second electrode; 21. Planarization layer; 22. Pixel electrode; 31. First via; 32. Second via; 33. Third via. Detailed Implementation

[0064] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this disclosure, and different embodiments can be combined arbitrarily without conflict. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0065] Figure 2 This is a planar schematic diagram of an LCD product. (Example) Figure 2 As shown, the data line 11 extends along the second direction Y, the gate line 17 extends along the first direction X, and the channel 153 of the active layer is located in the area where the data line 11 is located, using the data line 11 as a light-shielding layer. Figure 2 The structure shown is compared to Figure 1 The structure shown can increase the aperture region 40, raising the aperture ratio to 56%. However, due to the reduction in the size of the data line 11 and the gate line 17, the channel length is also reduced, leading to short-channel effects such as device discreteness and negative bias of the threshold voltage Vth. Furthermore, the channel is located above the data line 11, making it susceptible to electrical crosstalk caused by the signal on the data line 11.

[0066] Figure 3 This is a planar schematic diagram of the substrate according to one embodiment of the present disclosure. Figure 4 for Figure 3 The diagram shows a schematic cross-sectional view (AA section) of the substrate in one embodiment. This disclosure provides a substrate, such as... Figure 3 and Figure 4 As shown, the substrate includes a substrate 10 and a thin-film transistor disposed on one side of the substrate 10. The thin-film transistor includes a first electrode 111, a protrusion structure 13, an active layer 15, a gate 171, and a second electrode 191. One of the first electrode 111 and the second electrode 191 can be a source electrode and the other can be a drain electrode. For example, the first electrode 111 can be a source electrode and the second electrode 191 can be a drain electrode. The first electrode 111 is located on one side of the substrate 10. A first insulating layer 12 is located on the side of the first electrode 111 opposite to the substrate 10. The protrusion structure 13 is located on the side of the first insulating layer 12 opposite to the substrate 10, and the protrusion structure 13 extends along a first direction X.

[0067] The active layer 15 is located on the side of the protrusion structure 13 facing away from the substrate 10. The active layer 15 includes a first conductive region 151, a second conductive region 152, and a channel 153 located between the first conductive region 151 and the second conductive region 152. The channel 153 crosses the protrusion structure 13 along a second direction Y, that is, the channel 153 covers the protrusion structure 13 in the second direction Y. The first conductive region 151 is connected to the first electrode 111 through a first via 31 penetrating the first insulating layer 12. The second direction Y intersects the first direction X, and exemplarily, the second direction Y is perpendicular to the first direction X. Exemplarily, the second direction Y can be the length direction of the channel 153, and the first conductive region 151 and the second conductive region 152 can be respectively disposed on both sides of the channel 153 along the second direction Y. The second insulating layer 16 is located on the side of the active layer 15 facing away from the substrate 10.

[0068] The gate 171 is located on the side of the second insulating layer 16 away from the substrate 10, and the orthogonal projection of the channel 153 on the substrate 10 is within the range of the orthogonal projection of the gate 171 on the substrate 10.

[0069] The third insulating layer 18 is located on the side of the gate 171 facing away from the substrate 10. The second electrode 191 is located on the side of the third insulating layer 18 facing away from the substrate 10, and the second electrode 191 is connected to the second conductive region 152 through a second via 32 penetrating the third insulating layer 18 and the second insulating layer 16.

[0070] In related technologies, thin-film transistors suffer from short-channel effects due to their short channel length. The thin-film transistor of this embodiment addresses this issue by providing a raised structure 13, with the channel 153 extending across the raised structure 13 along the second direction Y. This transforms the channel 153 from a straight line in the second direction Y (i.e., the length direction of the channel) into a zigzag shape. This increases the length of the channel 153, preventing the short-channel effect caused by its excessive length and improving the performance of the thin-film transistor. Furthermore, while maintaining the length of the channel 153, the projected area of ​​the active layer on the substrate can be further reduced, thus decreasing the size of the thin-film transistor.

[0071] For example, such as Figure 4 As shown, the cross-sectional shape of the protrusion structure 13 is quadrilateral. In other embodiments, the cross-sectional shape of the protrusion structure 13 can also be other shapes, such as triangles, semicircles, etc., as long as the protrusion structure 13 protrudes in a direction away from the base 10. For example, as... Figure 3 and Figure 4 As shown, the protrusion structure 13 includes a protrusion in the second direction Y. In other embodiments, the protrusion structure 13 may include multiple protrusions in the second direction Y.

[0072] In one embodiment, the protrusion structure 13 is made of an insulating material. For example, the material of the protrusion structure 13 may include organic materials, such as SOG (spin-on-glass), polymer materials, or other similar materials. Exemplarily, the material of the protrusion structure 13 may include a black organic material, such as a black resin material. By setting the material of the protrusion structure 13 to a black organic material, the protrusion structure 13 can shield the channel 153 from light, ensuring that light does not affect the characteristics of the thin-film transistor.

[0073] In one embodiment, such as Figure 4 As shown, the thin-film transistor may further include a fourth insulating layer 14, which is located between the bump structure 13 and the active layer 15. A first conductive region 151 is connected to a first electrode 111 through a first via 31 penetrating the fourth insulating layer 14 and the first insulating layer 12. The fourth insulating layer 14 isolates the bump structure 13 from the active layer 15, preventing the active layer 15 from being affected by the material of the bump structure 13. Exemplarily, the material of the fourth insulating layer 14 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. Exemplarily, the thickness of the fourth insulating layer 14 may range from 3000 angstroms to 4000 angstroms. For example, the thickness of the fourth insulating layer 14 may be 3500 angstroms.

[0074] In one implementation, such as Figure 4 As shown, the thickness of the protrusion structure 13 can be greater than 1 μm, thereby increasing the length of the channel 153 by at least 2 μm and avoiding the short-channel effect.

[0075] In one implementation, such as Figure 4 As shown, the orthogonal projection of the protrusion structure 13 onto the substrate 10 in the second direction Y has a size L1 of 1.5 μm to 2 μm (including the endpoint value). Exemplarily, the size L1 can be any value between 1.5 μm and 2 μm; for example, L1 can be 1.5 μm, 1.8 μm, or 2 μm. Setting L1 to 1.5 μm to 2 μm can avoid short-channel effects and improve the performance of the thin-film transistor while maintaining a small size.

[0076] This disclosure also provides a substrate, such as... Figure 3 and Figure 4 As shown, the substrate may include the thin-film transistors in any embodiment of this disclosure.

[0077] like Figure 3 and Figure 4As shown, the substrate may include data lines 11, and the number of data lines 11 may be multiple. The data lines 11 are disposed on the same layer as the first electrode 111. The data lines 11 extend along the second direction Y, and the multiple data lines 11 are arranged along the first direction X. Exemplarily, the first electrode 111 of the thin-film transistor may be a part of the data lines 11, that is, a part of the data lines 11 is the first electrode 111.

[0078] like Figure 3 and Figure 4 As shown, the substrate may further include gate lines 17, which may be disposed on the same layer as the gate 171. There may be multiple gate lines 17, extending along a first direction X, and the multiple gate lines 17 are arranged along a second direction Y. Exemplarily, the gate 171 of the thin-film transistor may be a portion of the gate line 17; that is, a portion of the gate line 17 may be the gate 171. Exemplarily, the orthogonal projection of the channel 153 onto the substrate 10 is within the range of the orthogonal projection of the gate 171 onto the substrate 10. Therefore, the orthogonal projection of the channel 153 onto the substrate 10 is within the range of the orthogonal projection of the gate line 17 onto the substrate 10, thus avoiding the influence of the channel 153 on the aperture ratio.

[0079] In one embodiment, multiple data lines 11 and multiple gate lines 17 can intersect to define multiple pixel regions, and each pixel region can be correspondingly provided with a thin-film transistor as described in this embodiment, such as... Figure 3 As shown.

[0080] For example, such as Figure 3 As shown, the orthographic projection of the first via 31 on the substrate 10 can be located within the orthographic projection range of the data line 11 on the substrate 10, and the part of the data line 11 corresponding to the first via 31 can be the first pole 11.

[0081] In one implementation, such as Figure 3 As shown, the orthographic projection of the protrusion structure 13 onto the substrate 10 can be located within the range of the orthographic projection of the gate line 17 onto the substrate 10. Therefore, the protrusion structure 13 does not affect the aperture ratio of the substrate.

[0082] For example, Figure 3 In this configuration, the active layer located in region B1 is the first conductive region 151, the active layer located in region B2 is the second conductive region 152, and the active layer located in region B3 is the channel 152. In one embodiment, as... Figure 3As shown, the orthographic projection of the protrusion 13 on the substrate 10 and the orthographic projection of the data line 11 on the substrate 10 have a first overlapping region, which is located within the range of the orthographic projection of the channel 153 on the substrate 10. With this structure, a portion of the orthographic projection of the active layer 15 on the substrate 10 overlaps with the orthographic projection of the data line 11 on the substrate 10, which can further reduce the size of the additional area occupied by the active layer and reduce the impact of the active layer on the aperture ratio.

[0083] In related technologies, refer to Figure 3 and Figure 4 The channel 153 is located between the data line 11 and the gate line 17. Signals on the data line 11 can cause crosstalk to the channel 153. In this embodiment, the protrusion structure 13 is located between the data line 11 and the gate line 17. Exemplarily, the dielectric constant of the material of the protrusion structure 13 is less than that of the active layer material. Therefore, by placing the protrusion structure 13 between the data line 11 and the gate line 17, the parasitic capacitance between the data line 11 and the gate line 17 can be reduced, thereby reducing the crosstalk of signals on the data line 11 to the channel 153.

[0084] For example, the dielectric constant of the material of the protrusion structure can be less than 3.5.

[0085] In one embodiment, the active layer 15 may be made of an oxide. Exemplarily, the active layer may be made of indium gallium zinc oxide (IGZO), such as amorphous indium gallium zinc oxide (a-IGZO). Exemplarily, the active layer may be made of low-temperature polycrystalline oxide (LTPO). This type of active layer is transparent, and when thin-film transistors are applied to a display device, the active layer does not affect the aperture ratio of the display device.

[0086] In one embodiment, the second electrode 191 of the thin-film transistor is made of a transparent conductive material. For example, the data line 11 may be made of at least one of indium tin oxide and indium zinc oxide.

[0087] When the active layer is made of oxide and the second electrode 191 of the thin-film transistor is made of a transparent conductive material, neither the active layer nor the second electrode 191 will affect the opening region of the substrate. For example... Figure 3 In the diagram, a black square 40 is used to indicate the opening area of ​​the pixel area. Since the active layer and the second electrode 191 are both made of transparent materials, the active layer and the second electrode 191 will not affect the opening area, thus further improving the aperture ratio of the display device.

[0088] In one embodiment, the data line 11 may be made of a transparent conductive material. For example, the data line 11 may be made of at least one of indium tin oxide and indium zinc oxide. In this way, the area where the data line 11 is located can also transmit light, further increasing the light-transmitting area of ​​the substrate and improving the brightness of the display device.

[0089] Figure 5 This is a schematic diagram illustrating a method for fabricating a substrate according to an embodiment of this disclosure. This disclosure also provides a method for fabricating a substrate, such as... Figure 5 As shown, the substrate fabrication method includes: forming a data line on one side of the substrate, the data line extending along a second direction, a portion of the data line being a first electrode of a thin-film transistor; forming a first insulating layer on the side of the data line away from the substrate; forming a protrusion structure on the side of the first insulating layer away from the substrate, the protrusion structure extending along a first direction; forming an active layer of the thin-film transistor on the side of the protrusion structure away from the substrate, the active layer including a first conductive region, a second conductive region, and a channel located between the first conductive region and the second conductive region, the channel crossing the protrusion structure along the second direction, and the first conductive region passing through a first electrode of the first insulating layer. A via is connected to the first electrode; a second insulating layer is formed on the side of the active layer away from the substrate; a gate line is formed on the side of the second insulating layer away from the substrate, the gate line extends along a first direction, a portion of the gate line is the gate of the thin-film transistor, the orthogonal projection of the channel on the substrate is within the range of the orthogonal projection of the gate line on the substrate, wherein the second direction is not parallel to the first direction; a third insulating layer is formed on the side of the gate line away from the substrate, the third insulating layer has a second via penetrating the third insulating layer and the second insulating layer; a second electrode of the thin-film transistor is formed on the side of the third insulating layer away from the substrate, the second electrode is connected to the second conductive region through the second via.

[0090] The following is an embodiment of the present disclosure. Figure 3 and Figure 4 The substrate fabrication process shown further illustrates the technical solutions of the embodiments of this disclosure. It is understood that the term "patterning" as used herein includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping when the patterning material is inorganic or metallic; and processes such as mask exposure and development when the patterning material is organic. Evaporation, deposition, coating, and plating as mentioned herein are all mature fabrication processes in related technologies.

[0091] Data line 11 is formed on one side of the base, such as Figure 6A and Figure 6B As shown, Figure 6A This is a planar schematic diagram of a substrate after data lines have been formed in an embodiment of this disclosure; Figure 6B for Figure 6AThe diagram shows a cross-sectional view of section AA. Data line 11 extends along the second direction Y, and a portion of data line 11 forms the first electrode of a thin-film transistor. Exemplarily, data line 11 can be made of a transparent conductive material, such as indium tin oxide or indium zinc oxide.

[0092] A first insulating layer 12 is formed on the side of the data line 11 facing away from the substrate 10. Exemplarily, the first insulating layer 12 can be formed by deposition, such as... Figure 7A and Figure 7B As shown, Figure 7A This is a planar schematic diagram of a substrate after a protrusion structure has been formed in an embodiment of the present disclosure; Figure 7B for Figure 7A The diagram shows a cross-section AA. For example, the first insulating layer 12 can also be called a buffer layer, and the material of the first insulating layer 12 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The thickness of the first insulating layer 12 can be 2500 angstroms to 3500 angstroms; for example, the material of the first insulating layer 12 is silicon oxide, and the thickness can be 3000 angstroms.

[0093] A protrusion structure 13 is formed on the side of the first insulating layer 12 facing away from the substrate 10. The protrusion structure 13 extends along the first direction X, such as... Figure 7A and Figure 7B As shown. Exemplarily, the material of the protrusion structure 13 may include a resin material. The resin material can be coated on the side of the first insulating layer 12 facing away from the substrate 10, and the resin material can be exposed and developed to form the protrusion structure 13. The thickness of the protrusion structure 13 can be greater than 1 μm, and the dimension L1 of the orthographic projection of the protrusion structure 13 onto the substrate 10 in the second direction Y is 1.5 μm to 2 μm. Exemplarily, the cross-section of the protrusion structure 13 can be a trapezoid, and the slope of the side surface of the protrusion structure 13 is relatively gentle, which is beneficial to the uniformity of the subsequent film thickness.

[0094] A fourth insulating layer 14 is formed on the side of the protrusion structure 13 facing away from the substrate 10. The fourth insulating layer 14 has a first via 31 penetrating both the fourth insulating layer 14 and the first insulating layer 12. The first via 31 exposes a portion of the surface of the data line 11. The portion of the data line 11 exposed through the first via 31 can be the first electrode 111 of a thin-film transistor, such as... Figure 8A and 8B As shown, Figure 8A This is a planar schematic diagram of a substrate after a fourth insulating layer has been formed in an embodiment of the present disclosure; Figure 8B for Figure 8AA schematic diagram of section AA is shown in the figure. Exemplarily, a fourth insulating layer can be deposited on the side of the protrusion 13 facing away from the substrate 10; the fourth insulating layer 14 is patterned to form a first via 31 penetrating the fourth insulating layer 14 and the first insulating layer 12. Exemplarily, the material of the fourth insulating layer 14 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride. The fourth insulating layer 14 can be a single-layer structure or a stacked structure of at least two layers. For example, the fourth insulating layer 14 may include a stacked silicon nitride layer and a silicon oxide layer. The thickness of the fourth insulating layer 14 can be 3000 angstroms to 4000 angstroms; for example, the thickness of the fourth insulating layer 14 can be about 3500 angstroms.

[0095] An active layer 15 is formed on the side of the fourth insulating layer 14 facing away from the substrate 10, such as Figure 9A and 9B As shown, Figure 9A This is a planar schematic diagram of a substrate after an active layer has been formed in an embodiment of the present disclosure; Figure 9B for Figure 9A A schematic diagram of the AA cross-section is shown. Exemplarily, an active thin film can be deposited on the side of the fourth insulating layer 14 opposite to 10, and the active thin film can be patterned to form an active layer 15. The active layer 15 spans the protrusion structure 13 in the second direction Y, and the active layer 15 is connected to the data line 11 through the first via 31, as shown. Figure 9A and Figure 9B As shown.

[0096] A second insulating layer 16 is formed on the side of the active layer 15 facing away from the substrate 10, such as Figure 10A and Figure 10B As shown, Figure 10A This is a planar schematic diagram of a substrate after gate lines have been formed in an embodiment of the present disclosure; Figure 10B for Figure 10A A schematic diagram of the AA cross-section is shown. Exemplarily, the second insulating layer 16 can be formed by deposition. Exemplarily, the second insulating layer 16 can also be called a gate insulating layer (GI layer). Exemplarily, the thickness of the second insulating layer 16 can be 1500 angstroms.

[0097] A gate line 17 is formed on the side of the second insulating layer 16 facing away from the substrate 10. The gate line 17 extends along the first direction X, and a portion of the gate line 17 is the gate 171 of a thin-film transistor, such as... Figure 10A and Figure 10B As shown. Exemplarily, a gate metal film can be deposited on the side of the second insulating layer 16 facing away from the substrate 10, and the gate metal film can be patterned to form gate lines 17. Exemplarily, the thickness of the gate lines 17 can be 2500 angstroms to 3500 angstroms; for example, the thickness of the gate lines 17 can be 3000 angstroms. After forming the gate lines 17, the active layer 15 can be conductive using a self-aligned technique. Figure 11 This is a schematic diagram of the ion implantation process for the active layer, as shown below. Figure 11 As shown, the active layer 15 can be conductive using an ion implantation process. The active layer 15 located outside the gate line 17 is conductive, forming a first conductive region 151 and a second conductive region 152. The active layer below the gate line 17 forms a channel 153, so that the orthographic projection of the channel 153 onto the substrate 10 lies within the range of the orthographic projection of the gate line 17 onto the substrate. The first conductive region 151 and the second conductive region 152 are located on opposite sides of the channel 153 along the second direction Y, as shown. Figure 11 As shown. The first conductive region 151 is connected to the data line 11 through the first via 31. In one embodiment, the thickness of the protrusion structure 13 is 1 μm and the dimension of the protrusion structure 13 in the second direction Y is 2 μm. Then, the length of the channel 153 is at least 4 μm. This length of channel 153 will not cause short-channel effect and reduce device discreteness and threshold voltage negative bias.

[0098] A third insulating layer 18 is formed on the side of the gate line 17 facing away from the substrate 10. The third insulating layer 18 has a second via 32 penetrating through the third insulating layer 18 and the second insulating layer 16. Figure 12A and Figure 12B As shown, Figure 12A This is a planar schematic diagram of a substrate after a third insulating layer has been formed in an embodiment of this disclosure; Figure 12B for Figure 12A A schematic diagram of the AA cross-section is shown. Exemplarily, a third insulating layer 18 can be deposited on the side of the gate line 17 facing away from the substrate 10, and the third insulating layer 18 can be patterned to form a second via 32. The third insulating layer 18 can be called a passivation layer (PVX layer), and the material of the third insulating layer 18 can include at least one of silicon nitride, silicon oxide, and silicon oxynitride. Exemplarily, the third insulating layer 18 can include a silicon nitride layer and a silicon oxide layer stacked together. The thickness of the third insulating layer 18 can be 2500 angstroms to 3500 angstroms; exemplaryly, the thickness of the third insulating layer 18 can be 3000 angstroms.

[0099] A second electrode 191 of a thin-film transistor is formed on the side of the third insulating layer 18 facing away from the substrate 10. The second electrode 191 is connected to the second conductive region 152 through the second via 31. Figure 3 and Figure 4 As shown. For example, the material of the second electrode 191 can be a transparent conductive material, such as indium tin oxide or indium zinc oxide.

[0100] Figure 13 for Figure 3The diagram shows a schematic cross-sectional view of the substrate in another embodiment. In one embodiment, the substrate may further include a planarization layer 21 located on the side of the second electrode 191 opposite to the substrate 10. The planarization layer 21 may be provided with a third via 33, such as... Figure 13 As shown, the third via 33 can expose a portion of the surface of the second electrode 191. The substrate may also include a pixel electrode layer 22, which is located on the side of the planarization layer 21 opposite to the substrate 10, and the pixel electrode layer 22 is connected to the first electrode 191 of the thin-film transistor through the third via 33.

[0101] In one embodiment, the aperture size of the first via, the second via, and the third via can be approximately 2 μm. The orthogonal projection of the gate line 17 onto the substrate 10 in the second direction Y can also be approximately 2 μm. For example... Figure 12A As shown, the distance between the first via 31 and the upper edge of the active layer 15 is approximately 1 μm, and the distance between the first via 31 and the gate line 17 is approximately 1 μm. In specific implementations, the size of the vias, the size of each patterned film layer, and the distance between them can be set as needed, and are not specifically limited here.

[0102] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The gate lines may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multilayer composite structure, such as Ti / Al / Ti.

[0103] Figure 14A These are characteristic curves of the thin-film transistors in the substrate of this embodiment. Figure 14B These are the characteristic curves of thin-film transistors in a substrate using conventional technology. It should be noted that... Figure 14A and Figure 14B For the corresponding thin-film transistors, the orthographic projection dimensions of each film layer on the substrate are the same. Figure 14B The corresponding thin-film transistor does not include a bump structure. (By comparison...) Figure 14A and Figure 14B It can be seen that the thin-film transistors in conventional substrates have small channel lengths, resulting in a negative bias of the threshold voltage Vth of -0.04V. In the substrate of this embodiment, the protrusion structure 13 increases the channel length of the thin-film transistor, improving the negative bias of the threshold voltage Vth, which is approximately 0.04V. Further comparison... Figure 14A and Figure 14BIt can be seen that the 13 protrusion structures are for thin-film transistor devices V g -I d The effect of the characteristics is minimal.

[0104] Figure 15 This is a microscope illustration of the substrate at the location of the protruding structure in an embodiment of this disclosure. Figure 15 As can be seen, the fourth insulating layer 14 above the protruding structure 13 in this embodiment of the present disclosure has good coverage of the protruding structure 13, and the fourth insulating layer 14 has no cracks, which can ensure the uniformity and continuity of the subsequent film layers.

[0105] The thin-film transistor and substrate of the present disclosure can increase the channel length of the thin-film transistor while increasing the aperture ratio, thereby reducing the short-channel effect of the thin-film transistor device; while ensuring the channel length of the thin-film transistor, the size of the thin-film transistor can be reduced; and crosstalk between the data line and the gate line can be reduced, thereby reducing the impact of the data line on the characteristics of the thin-film transistor.

[0106] Based on the inventive concept of the foregoing embodiments, this disclosure also provides a display device, which includes a thin-film transistor or a substrate as described in any embodiment of this disclosure. The display device can be a liquid crystal display, an organic light-emitting diode (OLED) display, an LED display, or other similar types. The display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0107] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0108] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0109] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0110] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0111] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this disclosure. To simplify this disclosure, the components and arrangements of specific examples are described above. Of course, these are merely examples and are not intended to limit this disclosure. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0112] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this disclosure, and these should all be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A thin-film transistor, characterized in that, include: Base; The first pole is located on one side of the substrate; A first insulating layer is located on the side of the first electrode facing away from the substrate; A raised structure is located on the side of the first insulating layer opposite to the substrate, and the raised structure extends along a first direction; the material of the raised structure includes SOG or a black organic material; An active layer is located on the side of the protrusion structure opposite to the substrate. The active layer includes a first conductive region, a second conductive region, and a channel located between the first conductive region and the second conductive region. The channel crosses the protrusion structure along a second direction. The first conductive region is connected to the first electrode through a first via penetrating the first insulating layer. The second direction intersects the first direction. The orthogonal projection of the protrusion structure onto the substrate crosses the orthogonal projection of the active layer onto the substrate in the first direction; The second insulating layer is located on the side of the active layer opposite to the substrate; The gate is located on the side of the second insulating layer opposite to the substrate, and the orthogonal projection of the channel on the substrate is within the range of the orthogonal projection of the gate on the substrate; A third insulating layer is located on the side of the gate opposite to the substrate; The second electrode is located on the side of the third insulating layer opposite to the substrate, and the second electrode is connected to the second conductive region through a second via penetrating the third insulating layer and the second insulating layer.

2. The thin-film transistor according to claim 1, characterized in that, It also includes a fourth insulating layer located between the protrusion structure and the active layer, and the first conductive region is connected to the first electrode through a first via penetrating the fourth insulating layer and the first insulating layer.

3. The thin-film transistor according to claim 1, characterized in that, The thickness of the protrusion is greater than 1 μm; and / or, the size of the orthographic projection of the protrusion on the substrate in the second direction is 1.5 μm to 2 μm.

4. The thin-film transistor according to any one of claims 1-3, characterized in that, The active layer is made of indium gallium zinc oxide.

5. A substrate, characterized in that, The thin-film transistor includes any one of claims 1-4.

6. The substrate according to claim 5, characterized in that, The substrate further includes a data line disposed on the same layer as the first electrode, the data line extending along the second direction, and a portion of the data line being the first electrode; The substrate further includes a gate line disposed on the same layer as the gate, the gate line extending along the first direction, and a portion of the gate line being the gate.

7. The substrate according to claim 6, characterized in that, The orthographic projection of the protrusion structure onto the substrate lies within the range of the orthographic projection of the grating line onto the substrate.

8. The substrate according to claim 7, characterized in that, The orthographic projection of the protrusion structure on the substrate and the orthographic projection of the data line on the substrate have a first overlapping area, which is located within the range of the orthographic projection of the channel on the substrate.

9. The substrate according to claim 6, characterized in that, The dielectric constant of the material of the protrusion structure is less than that of the active layer material.

10. The substrate according to any one of claims 6-9, characterized in that, The data cable is made of a transparent conductive material, and the second electrode is also made of a transparent conductive material.

11. A method for preparing a substrate, characterized in that, The method for preparing a substrate as described in any one of claims 5 to 10 comprises: A data line is formed on one side of the substrate, the data line extends along a second direction, and a portion of the data line is the first electrode of a thin-film transistor; A first insulating layer is formed on the side of the data line opposite to the substrate; A protruding structure is formed on the side of the first insulating layer opposite to the substrate, and the protruding structure extends along a first direction; An active layer of a thin-film transistor is formed on the side of the protrusion structure opposite to the substrate. The active layer includes a first conductive region, a second conductive region, and a channel located between the first conductive region and the second conductive region. The channel spans the protrusion structure along the second direction. The first conductive region is connected to the first electrode through a first via penetrating the first insulating layer. A second insulating layer is formed on the side of the active layer opposite to the substrate; A gate line is formed on the side of the second insulating layer away from the substrate, the gate line extends along the first direction, a portion of the gate line is the gate of the thin film transistor, the orthogonal projection of the channel on the substrate is within the range of the orthogonal projection of the gate line on the substrate, wherein the second direction is not parallel to the first direction; A third insulating layer is formed on the side of the gate line opposite to the substrate, and the third insulating layer has a second via penetrating the third insulating layer and the second insulating layer; The second electrode of the thin-film transistor is formed on the side of the third insulating layer opposite to the substrate, and the second electrode is connected to the second conductive region through the second via.

12. A display device, characterized in that, It includes the thin-film transistor according to any one of claims 1-4, or the substrate according to any one of claims 5-10.

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