A high-voltage driving circuit based on a switched-capacitor amplifier
By combining the sampling and maintenance of switching capacitor amplifiers and high-voltage amplification and adding discharge timing, the problems of large area and high power consumption of traditional high-voltage driving circuits are solved, and are suitable for high-voltage driving arrays with adjustable wavelength infrared sensors.
Patent Information
- Application Number
- CN202211598014.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-12
- Publication Date
- 2025-07-04
- Estimated Expiration
- 2042-12-12
AI Technical Summary
Traditional high-voltage driving circuits have large area and high power consumption, making it difficult to meet the needs of larger-scale arrays.
A high-voltage driving circuit based on a switching capacitor amplifier is adopted to combine the sampling and maintenance of the switching capacitor amplifier with high-voltage amplification, and a combination of swing through low-voltage domain amplification and high-voltage domain is provided, and discharge timing is added to avoid breakdown of the negative input end of the gain stage and reduce layout area and power consumption.
It realizes a high-voltage drive array suitable for adjustable wavelength infrared sensors while providing sufficient gain and swing while reducing layout area and power consumption.
Smart Images
Figure CN115733451B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of analog integrated circuits, and particularly relates to a high-voltage driving circuit based on a switched-capacitor amplifier, which can be applied to a tunable wavelength infrared sensor. Background Art
[0002] In many application fields, the demand for portable infrared sensors is increasing, and the production cost is getting lower and lower. Therefore, the miniaturization technology of infrared sensors has gradually emerged. Thanks to the continuous development of silicon-based microelectromechanical system (MEMS) processing technology, the micro-mechanical structure can be compatible with the traditional integrated circuit (IC) process, which greatly reduces the manufacturing cost of portable infrared sensor chips and improves the compactness at the same time.
[0003] In the application of infrared sensors, a high-voltage driving array is often required. The traditional high-voltage driving module adopts a combination of a pre-stage sample-and-hold circuit and a post-stage high-voltage amplification circuit. The pre-stage sample-and-hold circuit samples the output signal from a digital-to-analog converter (DAC) in a unity-gain mode, and the post-stage high-voltage amplification circuit amplifies the sampled signal for driving a filter. In order to ensure that the sample-and-hold stage holds the DAC output signal for a long enough time, an active sample-and-hold circuit is generally used, that is, a sample-and-hold structure composed of an operational amplifier. At the same time, in order to achieve sufficient sample-and-hold accuracy, the gain of the operational amplifier in the active sample-and-hold circuit needs to be high enough, so the power consumption of the sample-and-hold stage is relatively high. Similarly, in order to make the high-voltage output accurate enough, the gain of the high-voltage operational amplifier also needs to be high enough, and the power consumption is relatively large.
[0004] Generally speaking, the traditional high-voltage driving circuit adopts a two-stage structure in circuit implementation, which makes the total layout area and power consumption large. For the high-voltage driving circuit applied to a large-scale array, the above disadvantages are unacceptable. Summary of the Invention
[0005] Aiming at the above existing problems or deficiencies, in order to solve the problems of large area and high power consumption of the traditional high-voltage driving circuit, the present invention provides a high-voltage driving circuit based on a switched-capacitor amplifier, which combines the sample-and-hold and high-voltage amplification of the switched-capacitor amplifier itself, effectively reducing the layout area and circuit power consumption, thereby reducing the area and power consumption of the sensor chip.
[0006] The specific technical solution of the present invention is as follows:
[0007] A high-voltage driving circuit based on a switched-capacitor amplifier, as Figure 1As shown in the figure, it includes the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6, the first zener diode Z1, the first resistor R1, the first capacitor C1, the second capacitor C2, the first load capacitor CL, the first diode D1, the second diode D2, the gain stage amplifier circuit Gain, and control clocks (including four clocks CK0, CK1, CK2, and CK3). Among them, the first MOS transistor M1 and the second MOS transistor M2 are low-voltage N-type MOS transistors with a voltage ≤ 5V, M3, M5, and M6 are high-voltage N-type MOS transistors with a voltage > 5V, and M4 is a high-voltage P-type MOS transistor with a voltage > 5V.
[0008] The source of the first MOS transistor M1 is connected to the input signal VIN, its drain is respectively connected to the drain of the second MOS transistor M2 and the left plate of the first capacitor C1, and the gate of the first MOS transistor M1 is connected to the input clock signal CK1.
[0009] The gate of the second MOS transistor M2 is connected to the input clock signal CK2, and its source is grounded.
[0010] The right plate of the first capacitor C1, the left plate of the second capacitor C2, and the source of the sixth MOS transistor M6 are all connected to the negative input terminal X of the gain stage circuit Gain. The positive input terminal of the gain stage circuit Gain is connected to the low-voltage common-mode signal VCM, and the gate terminal of the sixth MOS transistor M6 is connected to the input clock signal CK0.
[0011] The drains of the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, and the sixth MOS transistor M6 are connected together with the upper plate of the first load capacitor CL as the output terminal VOUT, and the lower plate of the first load capacitor CL is grounded.
[0012] The gate of the third MOS transistor M3 is connected to the output of the gain stage circuit Gain, and its source is grounded. The gate of the fourth MOS transistor M4 is connected to the bias voltage VBP, its source is connected to the high-voltage power supply HVDD, and the first resistor R1 and the first zener diode Z1 are connected in series and connected across the source and gate of the fourth MOS transistor M4.
[0013] The gate of the fifth MOS transistor M5 is connected to the input clock signal CK3, and the first diode D1 and the second diode D2 are connected in parallel and connected across the source of the fifth MOS transistor M5 and the ground.
[0014] The entire high-voltage drive circuit based on the switched-capacitor amplifier includes two voltage domains. The gain stage circuit Gain operates in the low-voltage domain LVDD ≤ 5V, while the output stage third MOS transistor M3 and fourth MOS transistor M4 belong to the high-voltage domain HVDD (5V < HVDD ≤ 35V).
[0015] The above high-voltage drive circuit based on switched-capacitor amplification has the following specific working process:
[0016] When the high-voltage drive circuit operates in the sampling mode: the input clock signals CK0 and CK1 are at high level, and the input clock signals CK2 and CK3 are at low level. At this time, the first MOS transistor M1 and the sixth MOS transistor M6 are turned on, and the second MOS transistor M2 and the fifth MOS transistor M5 are turned off.
[0017] The turned-on sixth MOS transistor M6 shorts the negative input terminal X and the output terminal VOUT of the gain stage circuit Gain. Thus, the gain stage circuit Gain operates in the unity-gain feedback mode, making the voltage at the negative input terminal X of the gain stage circuit Gain and the output voltage VOUT both finally established as VCM. The turned-on first MOS transistor M1 connects the input signal VIN to the left plate of the first capacitor C1, and VIN charges the first capacitor C1. The turned-off second MOS transistor M2 and fifth MOS transistor M5 are equivalent to open circuits in the sampling mode.
[0018] During the process of the high-voltage drive circuit entering the amplification mode (also known as the holding mode) from the sampling mode: the input clock signal CK0 first becomes low level, and the sixth MOS transistor M6 first turns off, causing the gain stage circuit Gain to exit the unity-gain mode; then CK1 becomes low level. At this time, the first MOS transistor M1 turns off, stopping the sampling of the input signal VIN by the first capacitor C1. After CK1 becomes low level, the circuit starts to enter the amplification stage, and CK2 starts to become high level. The second MOS transistor M2 turns on, and the left plate of the first capacitor C1 is shorted to ground by the second MOS transistor M2. After CK2 becomes high level, the circuit operates in the amplification mode. During this process, the input clock signal CK3 is always at low level.
[0019] After the high-voltage drive circuit ends the amplification mode and enters the discharge mode, the input clock signal CK3 first becomes high level, the circuit enters the discharge mode, and the fifth MOS transistor M5 turns on.
[0020] If the output voltage VOUT is a high voltage, then the first diode D1 and the second diode D2 will conduct, and the charge on the first load capacitor CL is conducted to ground through the first diode D1 and the second diode D2, and the high-voltage output VOUT is quickly pulled down. If the output voltage VOUT is a low voltage, then the first diode D1 and the second diode D2 will not conduct.
[0021] Subsequently, CK0 becomes high level, and the sixth MOS transistor M6 turns on. However, due to the effect of the discharge stage, the output voltage VOUT is discharged to a low voltage and will not break down the negative input terminal of the gain stage circuit Gain.
[0022] After the discharge mode ends, CK2 and CK3 become low level, and the second MOS transistor M2 and the fifth MOS transistor M5 are cut off. At the same time, CK1 becomes high level, and the circuit re-enters the sampling mode.
[0023] In summary, the present invention realizes a high-voltage output driving circuit based on switched-capacitor amplification by adopting a method combining low-voltage domain amplification and high-voltage domain swing provision, and ensures that the MOS transistors in the low-voltage input stage will not be broken down by adding a discharge timing sequence. The present invention can be applied to array driving, meet the requirements of gain and swing at the same time, and provide relatively low power consumption. And while providing a sufficiently large gain, it avoids using a large number of high-voltage MOS transistors, greatly reducing the layout area. It effectively solves the problems of large area and high power consumption of traditional high-voltage driving circuits, and is especially suitable for tunable wavelength infrared sensors. Brief Description of the Drawings
[0024] Figure 1 is the circuit diagram of the present invention;
[0025] Figure 2 is the timing diagram of the present invention;
[0026] Figure 3 is the simulation verification result of the embodiment. Detailed Embodiment
[0027] The technical solution of the present invention will be described in detail below with reference to the drawings and embodiments.
[0028] This embodiment provides a high-voltage driving circuit based on a switched-capacitor amplifier (as Figure 1 shown), which is applied to a tunable wavelength infrared sensor. It includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a first zener diode Z1, a first resistor R1, a first capacitor C1, a second capacitor C2, a first load capacitor CL, a first diode D1, a second diode D2, a gain-stage amplifier circuit Gain, and four control clocks (CK0, CK1, CK2, and CK3). Among them, the first MOS transistor M1 and the second MOS transistor M2 are low-voltage N-type MOS transistors, M3, M5, and M6 are high-voltage N-type MOS transistors, and M4 is a high-voltage P-type MOS transistor.
[0029] The source of the first MOS transistor M1 is connected to the input signal VIN, and its drain is respectively connected to the drain of the second MOS transistor M2 and the left plate of the first capacitor C1. The gate of the first MOS transistor M1 is connected to the input clock signal CK1. The gate of the second MOS transistor M2 is connected to the input clock signal CK2, and its source is grounded. The right plate of the first capacitor C1, the left plate of the second capacitor C2, and the source of the sixth MOS transistor M6 are all connected to the negative input terminal X of the gain stage circuit Gain. The positive input terminal of the gain stage circuit Gain is connected to the low-voltage common-mode signal VCM. The gate terminal of the sixth MOS transistor M6 is connected to the input clock signal CK0. The drain terminals of the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, and the sixth MOS transistor M6 are connected together with the upper plate of the load capacitor CL as the output terminal VOUT, and the lower plate of the load capacitor CL is grounded. The gate of the third MOS transistor M3 is connected to the output of the gain stage circuit Gain, and its source is grounded. The gate of the fourth MOS transistor M4 is connected to the bias voltage VBP, and its source is connected to the high-voltage power supply HVDD. The first resistor R1 and the zener diode Z1 are connected in series and connected across the source and gate of the fourth MOS transistor M4. The gate of the fifth MOS transistor M5 is connected to the input clock signal CK3. The first diode D1 and the second diode D2 are connected in parallel and connected across the source of the fifth MOS transistor M5 and the ground.
[0030] The working principle of the present invention will be described below in conjunction with Figure 2 the following.
[0031] 1. Sampling mode: The input clock signals CK0 and CK1 are at high level, and the input clock signals CK2 and CK3 are at low level. At this time, the first MOS transistor M1 and the sixth MOS transistor M6 are turned on, and the second MOS transistor M2 and the fifth MOS transistor M5 are turned off. The turned-on sixth MOS transistor M6 shorts the negative input terminal X of the gain stage circuit Gain and the output terminal VOUT. Therefore, the gain stage circuit Gain operates in the unity-gain feedback mode, so that the voltage at the negative input terminal X of the gain stage circuit Gain and the output voltage VOUT are finally both established as VCM. The turned-on first MOS transistor M1 shorts the input signal VIN and the left plate of the first capacitor C1, and VIN charges the capacitor C1. The turned-off second MOS transistor M2 and fifth MOS transistor M5 are equivalent to open circuits during the sampling mode.
[0032] 2. Sampling mode enters the amplification mode: The input clock signal CK0 first goes low, and the sixth MOS transistor M6 first turns off, causing the gain stage circuit Gain to exit the unity gain mode; then CK1 goes low. At this time, the first MOS transistor M1 turns off, and the sampling capacitor C1 stops sampling the input signal VIN. After CK1 goes low, the circuit starts to enter the amplification mode, and CK2 starts to go high. The second MOS transistor M2 turns on, and the left plate of the sampling capacitor C1 is shorted to ground by the second MOS transistor M2. After CK2 goes high, the circuit operates in the amplification mode. During this process, the input clock signal CK3 is always low.
[0033] 3. The amplification mode enters the discharge mode: The input clock signal CK3 first goes high, and the circuit enters the discharge mode, and the fifth MOS transistor M5 turns on.
[0034] If the output voltage VOUT is a high voltage, then the diodes D1 and D2 will conduct, and the charge on the load capacitor CL is conducted to ground through the diodes D1 and D2, and the high-voltage output VOUT is quickly pulled low; if the output voltage VOUT is a low voltage, then the diodes D1 and D2 will not conduct.
[0035] Subsequently, CK0 goes high, and the sixth MOS transistor M6 turns on. However, due to the effect of the discharge stage, the output voltage VOUT is discharged to a low voltage and will not break down the negative input terminal of the gain stage circuit Gain. After the discharge stage ends, CK2 and CK3 go low, and the second MOS transistor M2 and the fifth MOS transistor M5 turn off. Immediately afterwards, CK1 goes high, and the circuit re-enters the sampling mode.
[0036] The high-voltage drive circuit of the present invention provides a timing sequence to avoid the breakdown of the input terminal of the low-voltage gain stage Gain, including during the working process (such as Figure 2 ). This timing sequence can be simply described as inserting an additional control timing sequence after the amplification mode ends and before the sampling mode starts. The function of this timing sequence is to convert the high voltage established in the amplification mode into a low voltage that the input terminal x of the gain stage circuit Gain can accept, preventing breakdown. The circuit operating mode corresponding to the timing sequence introduced by the input clock signal CK3 is called the discharge mode.
[0037] Specifically, if there is no discharge mode introduced by the CK3 timing, then when the circuit transitions from the amplification mode to the sampling mode, CK2 goes low, the second MOS transistor M2 is turned off, CK0 and CK1 go high, the sixth MOS transistor M6 is turned on, the first MOS transistor M1 is turned on, and the left plate of the first capacitor C1 follows the input signal VIN. Since the final stable output voltage VOUT in the amplification mode may be a high voltage, if this high-voltage signal is directly connected to the low-voltage negative input stage X node of the gain stage circuit Gain through the sixth MOS transistor M6, the input transistor of the gain stage circuit Gain will be damaged by breakdown.
[0038] Specifically, if there is a discharge mode introduced by the CK3 timing, when the circuit transitions from the amplification mode to the discharge mode, the fifth MOS transistor M5 conducts first, thus forming a current path from VOUT to the fifth MOS transistor M5, through the first diode D1 and the second diode D2, and then to ground. Due to the forward conduction characteristics of the first diode D1 and the second diode D2, the high-voltage output voltage VOUT will be quickly pulled down to a smaller value. It should be noted that the pull-down circuit composed of the fifth MOS transistor M5, the first diode D1, and the second diode D2 only needs to ensure that the high-voltage output VOUT is pulled down to a smaller value within a relatively short time, rather than to a specific value, because the next timing is the sampling mode, and the circuit can establish the output VOUT to be close to the input common-mode voltage VCM during the entire sampling mode time. At this time, since the discharge mode has ended, VOUT will not be affected by the pull-down circuit.
[0039] The simulation verification results of this embodiment are as Figure 3 shown, verifying that the output is stabilized at a voltage less than 5V during the discharge phase. Figure 3 Only the simulation waveforms of the clock CK0, CK3, and the output VOUT are shown. From the simulation results, it can be seen that when CK3 is valid, the output voltage is quickly pulled down to a low voltage (about 1.24V). Obviously, this voltage will not cause the input terminal X of the gain stage circuit Gain to be damaged by breakdown.
[0040] As can be seen from the above embodiments, the present invention involves two voltage domains, namely the 5V low-voltage domain LVDD and the 35V high-voltage domain HVDD. The gain stage circuit Gain operates in the 5V voltage domain, so the maximum input voltage that its negative input terminal X can withstand is 5V. However, since the output voltage of the circuit of the present invention is a high voltage greater than 5V, the traditional structure without a discharge mode has a risk that the negative input terminal X of the gain stage circuit will be damaged by breakdown. After adding the discharge mode timing, before the gain stage circuit Gain enters the unity-gain mode, the high-voltage output VOUT will be quickly discharged through the pull-down current path composed of the fifth MOS transistor M5 and the diodes D1 and D2, thus avoiding the risk of the negative input terminal of the gain stage circuit Gain being damaged by breakdown.
[0041] The discharge timing proposed by the present invention is added between the hold mode and the sampling mode. This timing can ensure that the high-voltage output is quickly discharged to a low enough voltage before the high voltage acts on the negative input terminal of the gain stage, so as to address the problem of high-voltage breakdown at the negative input terminal of the gain stage when switching from the amplification mode to the sampling mode. The present invention uses a switched-capacitor amplifier to simultaneously achieve the functions of sampling and holding and high-voltage amplification, reducing the circuit layout area and power consumption of the traditional high-voltage drive circuit, and is particularly suitable for high-voltage drive arrays of tunable-wavelength infrared sensors.
Claims
1. A high-voltage driving circuit based on a switched-capacitor amplifier, characterized in that: It includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a first zener diode Z1, a first resistor R1, a first capacitor C1, a second capacitor C2, a first load capacitor CL, a first diode D1, a second diode D2, a gain stage amplifier circuit Gain, and a control clock; among them, M1 and M2 are low-voltage N-type MOS transistors with ≤5V, M3, M5, and M6 are high-voltage N-type MOS transistors with >5V, and M4 is a high-voltage P-type MOS transistor with >5V; the control clock includes four signals: CK0, CK1, CK2, and CK3. The source of the first MOS transistor M1 is connected to the input signal VIN, its drain is respectively connected to the drain of the second MOS transistor M2 and the left plate of the first capacitor C1, and the gate of the first MOS transistor M1 is connected to the input clock signal CK1. The gate of the second MOS transistor M2 is connected to the input clock signal CK2, and its source is grounded. The right plate of the first capacitor C1, the left plate of the second capacitor C2, and the source of the sixth MOS transistor M6 are all connected to the negative input terminal X of the gain stage circuit Gain. The positive input terminal of the gain stage circuit Gain is connected to the low-voltage common-mode signal VCM, and the gate terminal of the sixth MOS transistor M6 is connected to the input clock signal CK0. The drains of the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, and the sixth MOS transistor M6 are connected together with the upper plate of the first load capacitor CL as the output terminal VOUT, and the lower plate of the first load capacitor CL is grounded. The gate of the third MOS transistor M3 is connected to the output of the gain stage circuit Gain, and its source is grounded; the gate of the fourth MOS transistor M4 is connected to the bias voltage VBP, its source is connected to the high-voltage power supply HVDD, and the first resistor R1 and the first zener diode Z1 are connected in series and connected across the source and gate of the fourth MOS transistor M4. The gate of the fifth MOS transistor M5 is connected to the input clock signal CK3, and the first diode D1 and the second diode D2 are connected in parallel and connected across the source of the fifth MOS transistor M5 and the ground. The entire high-voltage drive circuit based on the switched-capacitor amplifier includes two voltage domains. The gain stage circuit Gain operates in the low-voltage domain LVDD≤5V, and the output stage third MOS transistor M3 and fourth MOS transistor M4 belong to the high-voltage domain HVDD, where 5V<HVDD≤35V.
2. The high-voltage driving circuit based on switched-capacitor amplification according to claim 1, wherein The specific working process is as follows: When the high-voltage drive circuit operates in the sampling mode: the input clock signals CK0 and CK1 are at high level, and the input clock signals CK2 and CK3 are at low level. At this time, the first MOS transistor M1 and the sixth MOS transistor M6 are turned on, and the second MOS transistor M2 and the fifth MOS transistor M5 are turned off. The conducting sixth MOS transistor M6 shorts the negative input terminal X and the output terminal VOUT of the gain stage circuit Gain. Thus, the gain stage circuit Gain operates in the unity-gain feedback mode, causing the voltage at the negative input terminal X of the gain stage circuit Gain and the output voltage VOUT to eventually be established as VCM. The conducting first MOS transistor M1 connects the input signal VIN to the left plate of the first capacitor C1, and VIN charges the first capacitor C1. The non-conducting second MOS transistor M2 and fifth MOS transistor M5 are equivalent to an open circuit during the sampling mode. During the process of the high-voltage driving circuit transitioning from the sampling mode to the amplification mode: The input clock signal CK0 first becomes low level, and the sixth MOS transistor M6 first turns off, causing the gain stage circuit Gain to exit the unity-gain mode. Subsequently, CK1 becomes low level. At this time, the first MOS transistor M1 turns off, stopping the sampling of the input signal VIN by the first capacitor C1. After CK1 becomes low level, the circuit begins to enter the amplification stage, and CK2 begins to become high level. The second MOS transistor M2 turns on, and the left plate of the first capacitor C1 is shorted to ground by the second MOS transistor M2. After CK2 becomes high level ends, the circuit operates in the amplification mode. During this process, the input clock signal CK3 is always at low level. After the amplification mode of the high-voltage driving circuit ends and enters the discharge mode, the input clock signal CK3 first becomes high level, the circuit enters the discharge mode, and the fifth MOS transistor M5 turns on. If the output voltage VOUT is a high voltage, the first diode D1 and the second diode D2 conduct, and the charge on the first load capacitor CL is conducted to ground through the first diode D1 and the second diode D2, and the high-voltage output VOUT is quickly pulled down. If the output voltage VOUT is a low voltage, the first diode D1 and the second diode D2 do not conduct. Subsequently, CK0 becomes high level, and the sixth MOS transistor M6 turns on. However, due to the effect of the discharge stage, the output voltage VOUT is discharged to a low voltage and will not break down the negative input terminal of the gain stage circuit Gain. After the discharge mode ends, CK2 and CK3 become low level, and the second MOS transistor M2 and the fifth MOS transistor M5 turn off. At the same time, CK1 becomes high level, and the circuit re-enters the sampling mode.
3. The high-voltage driving circuit based on switched-capacitor amplification according to claim 2, wherein: The CK3 timing introduces the discharge mode. When the circuit transitions from the amplification mode to the discharge mode, the fifth MOS transistor M5 first turns on. Thus, a current path is formed from VOUT to the fifth MOS transistor M5 to the first diode D1, the second diode D2, and then to ground. Due to the forward conduction characteristics of the first diode D1 and the second diode D2, the high-voltage output voltage VOUT will be quickly pulled down to a smaller value. The pull-down circuit composed of the fifth MOS transistor M5, the first diode D1, and the second diode D2 only needs to ensure that the high-voltage output VOUT is pulled down to a relatively small value within a relatively short time, rather than being pulled down to a specific value, because the next timing is the sampling mode, and the circuit can establish the output VOUT to be close to the input common-mode voltage VCM during the entire sampling mode time. At this time, since the discharge mode has ended, VOUT will not be affected by the pull-down circuit; thus preventing the input terminal X of the gain stage circuit Gain from being broken down.
4. The high-voltage driving circuit based on switched-capacitor amplification according to claim 1, wherein: Applied to tunable wavelength infrared sensors.