Light emitting control circuit, display driving circuit and display device

Abstract

The present invention discloses a light-emitting control circuit, a display driver circuit, and a display device. The light-emitting control circuit includes: an output subcircuit, a first control subcircuit, and a second control subcircuit; the output end of the output subcircuit is connected to an output node; the first control end of the output subcircuit and the output end of the first control subcircuit are both connected to the first control node; the second control end of the output subcircuit and the first control end of the first control subcircuit are both connected to the second control node; and the second control end of the first control subcircuit is connected to the output end of the second control subcircuit. The present invention can reduce the use of transistors, achieve a reduction in circuit area, and facilitate the design of high-resolution display panels.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a light emitting control circuit, a display driving circuit and a display device. Background Art

[0002] In current display technology, each row of pixels in the display panel is controlled by a GOA (Gate Driver On Array, array substrate row drive scanning circuit) driver unit and an EOA (Emission Driver On Array, light-emitting control signal driver circuit) driver unit. When the GOA driver unit is turned on, it outputs a row scanning drive signal, and then stores the data signal on the data line into the pixel circuit; when the EOA driver unit is turned on, it outputs a light-emitting control signal, and the display panel emits light according to the stored data signal. However, the current EOA circuit design uses a large number of thin-film transistors, which is extremely unfavorable for the high-resolution design of the display panel. Therefore, how to further reduce the number of transistors in the EOA circuit and reduce the circuit area has become a problem that needs to be solved urgently. Summary of the Invention

[0003] In view of the above problems, the present invention proposes a light emitting control circuit, a display driving circuit and a display device, which can reduce the use of transistors, achieve a reduction in circuit area, and facilitate high-resolution design of display panels.

[0004] In the first aspect, the present application provides the following technical solutions through an embodiment:

[0005] A light-emitting control circuit, characterized by comprising: an output subcircuit, a first control subcircuit, and a second control subcircuit; the output end of the output subcircuit is connected to an output node; the first control end of the output subcircuit and the output end of the first control subcircuit are both connected to the first control node; the second control end of the output subcircuit and the first control end of the first control subcircuit are both connected to the second control node; the second control end of the first control subcircuit is connected to the output end of the second control subcircuit; the second control end of the first control subcircuit is configured to: write a first level or a second level to the second control end of the first control subcircuit in response to control of a clock signal and a trigger signal; the first control subcircuit is configured to: write a second level to the first control node in response to the second control end of the first control subcircuit being written to the second level and the second control node being written to the first level; and maintain the first control node at the second level in response to the second control end of the first control subcircuit and the second control node being written to the first level; the output subcircuit is configured to: write a first light-emitting drive level to the output node in response to the first control node being written to the second level and the second control node being written to the first level.

[0006] Optionally, the output sub-circuit includes: a first output sub-circuit and a second output sub-circuit; the output end of the first output sub-circuit and the output end of the second output sub-circuit are both connected to the output node; the control end of the first output sub-circuit is connected to the first control node, and the control end of the second output sub-circuit is connected to the second control node; the first output sub-circuit is configured to: in response to the first control node being written to the second level and the second control node being written to the first level, write the first light-emitting drive level to the output node; the second output sub-circuit is configured to: in response to the first control node being written to the first level and the second control node being written to the second level, write the second light-emitting drive level for turning off the light emission to the output node.

[0007] Optionally, the first light-emitting drive level is a first level; the first output sub-circuit includes: a first transistor and a first capacitor; the first end of the first transistor and the first end of the first capacitor are both configured to access the first level, and the control end of the first transistor and the second end of the first capacitor are both connected to the first control node; the second end of the first transistor is connected to the output node; the first transistor is configured to: turn on in response to the first control node being at the second level, and write the first level to the output node.

[0008] Optionally, the second light-emitting drive level is a second level; the second output sub-circuit includes: a second transistor and a second capacitor, the first end of the second transistor and the first end of the second capacitor are connected to the output node, the control end of the second transistor and the second end of the second capacitor are connected to the second control node; the second end of the second transistor is configured to access the second level; the second transistor is configured to: turn on in response to the second control node being at the second level, and write the second level to the output node.

[0009] Optionally, the light emitting control circuit further includes a third control subcircuit, and the control end of the second output subcircuit is connected to the second control node through the third control subcircuit.

[0010] Optionally, the first control subcircuit includes: a third transistor and a fourth transistor; the first end of the third transistor is configured to access the first level, the control end of the third transistor is connected to the second control node, the second end of the third transistor and the first end of the fourth transistor are both connected to the first control node, the control end of the fourth transistor is connected to the output end of the second control subcircuit, and the second end of the fourth transistor is configured to access the second level; wherein the control end of the third transistor is the first control end of the first control subcircuit, and the control end of the fourth transistor is the second control end of the first control subcircuit.

[0011] Optionally, the second control subcircuit includes: a fifth transistor, a sixth transistor and a third capacitor; the first end of the fifth transistor is configured to access the first level, and the second end of the fifth transistor is configured to access the trigger signal; the second end of the fifth transistor, the first end of the third capacitor, the second control end of the first control subcircuit and the first end of the sixth transistor are all connected to the third control node, the second end of the third capacitor is connected to the first control node, the second end of the sixth transistor is configured to access the second level, and the control end of the sixth transistor is configured to access the clock signal; the fifth transistor is configured to: in response to the trigger signal being the second level and the clock signal being the first level, write the first level to the third control node; the sixth transistor is configured to: in response to the trigger signal being the first level and the clock signal being the second level, write the second level to the third control node.

[0012] Optionally, the light-emitting control circuit further includes: a fourth control subcircuit; the output end of the fourth control subcircuit is connected to the second control node, the input end of the fourth control subcircuit is configured to access the trigger signal, and the control end of the fourth control subcircuit is configured to access the clock signal; the fourth control subcircuit is configured to: write the level of the trigger signal to the second control node in response to the control of the clock signal; the trigger signal is the first level or the second level.

[0013] Optionally, the fourth control subcircuit includes a seventh transistor, the first end of the seventh transistor is connected to the second control node, the control end of the seventh transistor is configured to access the clock signal, and the second end of the seventh transistor is configured to access the trigger signal.

[0014] In the second aspect, based on the same inventive concept, this application provides the following technical solution through an embodiment:

[0015] A display drive circuit, comprising: N light-emitting control circuits as described in any one of the first aspects above; N is a positive integer, and the N light-emitting control circuits are cascaded; the light-emitting drive level output by the light-emitting control circuit of the nth stage is the trigger signal of the light-emitting control circuit of the n-1th stage, 2≤n≤N, and n is a positive integer.

[0016] In the third aspect, based on the same inventive concept, this application provides the following technical solution through an embodiment:

[0017] A display device comprises: a sub-pixel, a gate drive circuit, and a light-emitting control circuit as described in any one of the first aspects above; the gate drive circuit is connected to the charge control transistor of the sub-pixel, and the light-emitting control circuit is connected to the light-emitting control transistor of the sub-pixel; the gate drive circuit is configured to control the charge control transistor to be turned on during a charging phase to write a data signal to a storage capacitor of the sub-pixel; the light-emitting control circuit is configured to control the light-emitting control transistor to be turned on during a light-emitting phase to control the sub-pixel to emit light.

[0018] Embodiments of the present invention provide a light-emitting control circuit, a display driver circuit, and a display device, wherein the light-emitting control circuit includes: an output subcircuit, a first control subcircuit, and a second control subcircuit; an output terminal of the output subcircuit is connected to an output node; a first control terminal of the output subcircuit and an output terminal of the first control subcircuit are both connected to the first control node; a second control terminal of the output subcircuit and the first control terminal of the first control subcircuit are both connected to the second control node; and the second control terminal of the first control subcircuit is connected to the output terminal of the second control subcircuit; wherein the second control subcircuit is configured to: write a second level to the second control terminal of the first control subcircuit in response to control of a clock signal and a trigger signal; the first control subcircuit is configured to: write the second level to the first control node in response to the second level being written to the second control terminal of the first control subcircuit and the first level being written to the second control node; and maintain the first control node at the second level in response to the first level being written to the second control terminal and the second control node; and the output subcircuit is configured to: write a first light-emitting drive level for turning on light emission to the output node in response to the second level being written to the first control node and the first level being written to the second control node. Based on the above control structure, the pulse width of the output first light-emitting drive level can be controlled only through the control of the clock signal and the trigger signal; therefore, at least the thin-film transistors corresponding to the anti-clock signal can be reduced, thereby reducing the circuit area, which is beneficial to the high-resolution design of the display panel.

[0019] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present invention. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0021] Figure 1 Schematic diagram of the structure of the first light-emitting control circuit in an embodiment of the present invention;

[0022] Figure 2 2 is a schematic structural diagram of a second light-emitting control circuit according to an embodiment of the present invention;

[0023] Figure 2A 2 is a schematic structural diagram of a third light-emitting control circuit according to an embodiment of the present invention;

[0024] Figure 3 for Figure 2A A structural diagram of a specific example of a light emitting control circuit;

[0025] Figure 4 for Figure 3 Control timing diagram of the light emitting control circuit;

[0026] Figure 5 for Figure 3 Schematic diagram of the ① stage control device of the light emitting control circuit;

[0027] Figure 6 for Figure 3 Schematic diagram of the control device of stage ② of the light emitting control circuit;

[0028] Figure 7 for Figure 3 Schematic diagram of the ③ stage control device of the light emitting control circuit;

[0029] Figure 8 for Figure 3 Schematic diagram of the control device of stage ④ of the light emitting control circuit;

[0030] Figure 9 for Figure 3 Schematic diagram of the ⑤ stage control device of the light emitting control circuit;

[0031] Figure 10 for Figure 3Schematic diagram of the ⑥ stage control device of the light emitting control circuit;

[0032] Figure 11 for Figure 3 7. Schematic diagram of the control device of the light emitting control circuit;

[0033] Figure 12 for Figure 3 ⑧ stage control device schematic diagram of the light emitting control circuit;

[0034] Figure 13 for Figure 3 Schematic diagram of the control device of stage 9 of the light emitting control circuit;

[0035] Figure 14 for Figure 3 Schematic diagram of the control device of stage ⑩ of the light emitting control circuit;

[0036] Figure 15 for Figure 3 Schematic diagram of signals of each node obtained from the simulation test of the light emitting control circuit. DETAILED DESCRIPTION

[0037] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0038] Currently, the number of transistors in the EOA circuit of the display panel is relatively large. For example, in some implementations, the PMOS EOA circuit adopts a 10T3C (10 thin film transistors and 3 capacitors) circuit, such as Figure 1 shown.

[0039] The 10T3C circuit includes first to tenth transistors M1 to M10, and first to third capacitors C1 to C3; wherein, a first end of the first transistor M1, a second end of the second transistor M2, a control end of the third transistor M3, a control end of the sixth transistor M6, a control end of the tenth transistor M10, and a first end of the third capacitor C3 are all connected to a first node node1; a first end of the fifth transistor M5, a first end of the sixth transistor M6, a control end of the seventh transistor M7, a control end of the eighth transistor M8, and a second end of the first capacitor C1 are all connected to a second node node2; a first end of the second transistor M2 and a second end of the seventh transistor M7 are both connected to a third node node3; a first end of the first capacitor C1, a first end of the eighth transistor M8, and a first end of the ninth transistor M9 are all connected to a fourth node node4; a control end of the fourth transistor M4, a second end of the ninth transistor M9, a second end of the tenth transistor M10, and a second end of the second capacitor C2 are all connected to a fifth node node5; and a second end of the fourth transistor M4 and a first end of the third transistor M3 are both connected to an output node. Furthermore, the control end of the first transistor M1, the control end of the fifth transistor M5, and the control end of the sixth transistor M6 are all configured to receive a clock signal; the control end of the second transistor M2, the second end of the eighth transistor M8, the control end of the ninth transistor M9, and the second end of the third capacitor C3 are all configured to receive an inverse clock signal that is opposite to the clock signal; the second end of the first transistor M1 is configured to receive a trigger signal; the second end of the third transistor M3 and the second end of the fifth transistor M5 are both configured to receive a low level; the first end of the fourth transistor M4, the first end of the seventh transistor M7, the first end of the tenth transistor M10, and the first end of the second capacitor C2 are all configured to receive a high level.

[0040] However, this type of EOA circuit requires the use of a clock signal (ECK) and an anti-clock signal (ECB) that is opposite to the clock signal, but it still cannot effectively reduce the number of thin-film transistors. Therefore, this design method will seriously restrict the high-resolution design of the MLED panel in the existing MLED (Mini / Micro LED) type display panel. Of course, it is not limited to MLED type display panels, and can also be OLED panels, etc. Therefore, in an embodiment of the present invention, a light-emitting control circuit is provided. The light-emitting control circuit can realize the width control of the output pulse of the entire circuit through a clock signal and a trigger signal, and does not need to use an anti-clock signal. Compared with the EOA circuit of the prior art, since the control of the anti-clock signal is reduced, the number of thin-film transistors used can be reduced, and the circuit area is effectively reduced, which is conducive to the high-resolution design of the MLED type display panel. The overall concept and implementation details of the light-emitting control circuit of the present invention are elaborated and explained in detail below through specific embodiments.

[0041] See Figure 2 In one embodiment of the present invention, a light emitting control circuit 200 is provided. The light emitting control circuit 200 includes: an output sub-circuit 20 , a first control sub-circuit 230 , and a second control sub-circuit 240 .

[0042] The output end of the output sub-circuit 20 is connected to the output node OUT; the first control end of the output sub-circuit 20 and the output end of the first control sub-circuit 230 are both connected to the first control node PD; the second control end of the output sub-circuit 20 and the first control end of the first control sub-circuit 230 are both connected to the second control node PU; the second control end of the first control sub-circuit 230 is connected to the output end of the second control sub-circuit 240.

[0043] The second control subcircuit 240 is configured to, in response to the control of the clock signal and the trigger signal, write a second level to the second control terminal of the first control subcircuit 230. The first control subcircuit 230 is configured to, in response to the second level being written to the second control terminal of the first control subcircuit 230 and the first level being written to the second control node PU, write a second level to the first control node PD. Furthermore, in response to both the second control terminal and the second control node PU of the first control subcircuit 230 being written to the first level, maintain the first control node PD at the second level. The output subcircuit 20 is configured to, in response to the second level being written to the first control node PD and the first level being written to the second control node PU, write a first light-emitting drive level to the output node OUT to enable light emission. With the above circuit structure, the pulse width of the output first light-emitting drive level can be controlled solely through the control of the clock signal and the trigger signal. Therefore, at least the number of thin-film transistors corresponding to the counter-clock signal can be reduced, thereby reducing the circuit area.

[0044] In some implementations, the output sub-circuit 20 includes: a first output sub-circuit 210 and a second output sub-circuit 220; the output terminal of the first output sub-circuit 210 and the output terminal of the second output sub-circuit 220 are both connected to an output node OUT; the control terminal of the first output sub-circuit 210 is connected to a first control node PD, and the control terminal of the second output sub-circuit 220 is connected to a second control node PU. The control terminal of the first output sub-circuit 210 is the first control terminal of the output sub-circuit 20, and the control terminal of the second output sub-circuit 220 is the second control terminal of the output sub-circuit 20.

[0045] The first output sub-circuit 210 is configured to write a first light-emitting drive level to the output node OUT in response to the second level being written to the first control node PD and the first level being written to the second control node PU. The second output sub-circuit 220 is configured to write a second light-emitting drive level for turning off light emission to the output node OUT in response to the first level being written to the first control node PD and the second level being written to the second control node PU. It will be appreciated that the first light-emitting drive level and the second light-emitting drive level are two different levels. For example, when the first light-emitting drive level is high, the second light-emitting drive level is low. After the first light-emitting drive level is written to the output node OUT, writing the second light-emitting drive level can reset the output node OUT, and vice versa.

[0046] It should be noted that the first level and the second level in this embodiment represent a relatively high level or a relatively low level, respectively. Based on the different types of thin film transistors, the first level can be a high level or a low level; similarly, the second level can be a high level or a low level, without limitation. Moreover, the specific values ​​of the low levels connected to different sub-circuits can be the same or different; similarly, the specific values ​​of the high levels can be the same or different; this can be achieved with reference to the prior art. For example, the second level VGL can be slightly smaller than the second level VL. In the subsequent description of this embodiment, a P-type thin film transistor (PMOS) is used as an example. In this case, the first level is a high level and the second level is a low level.

[0047] See also Figure 2A In some implementations, the light emission control circuit 200 further includes a third control subcircuit 250, and the control terminal of the second output subcircuit 220 is connected to the second control node PU via the third control subcircuit 250. That is, a first terminal of the third control subcircuit 250 is connected to the control terminal of the second output subcircuit 220, and a second terminal of the third control subcircuit 250 is connected to the second control node PU. The control terminal of the third control subcircuit 250 can be configured to be connected to a second electrical level, thereby turning on the third control subcircuit 250. Changes in the electrical level of the second control node PU can control the second output subcircuit 220.

[0048] Please continue reading Figure 2 and Figure 2AIn some implementations, the light emission control circuit 200 may further include a fourth control subcircuit 260. The output of the fourth control subcircuit 260 is connected to the second control node PU, the input of the fourth control subcircuit 260 is configured to receive a trigger signal, and the control terminal of the fourth control subcircuit 260 is configured to receive a clock signal. The fourth control subcircuit 260 is configured to write a trigger signal level to the second control node PU in response to the clock signal. The trigger signal can be a first level or a second level. For example, when the second output subcircuit 220 needs to be turned off, a first level may be written to the second control node PU; otherwise, a second level may be written to the second control node PU.

[0049] See also Figure 3 In some implementations, the first light-emitting drive level is a first level. The first output sub-circuit 210 includes a first transistor M1 and a first capacitor C1. The first terminal of the first transistor M1 and the first terminal of the first capacitor C1 are both configured to receive the first level, and the control terminal of the first transistor M1 and the second terminal of the first capacitor C1 are both connected to a first control node PD. The second terminal of the first transistor M1 is connected to the output node OUT. The first transistor M1 is configured to turn on in response to the first control node PD being at a second level, and write the first level to the output node OUT.

[0050] The second light-emitting drive level is the second level. The second output sub-circuit 220 includes a second transistor M2 and a second capacitor C2. The first end of the second transistor M2 and the first end of the second capacitor C2 are connected to the output node OUT, and the control end of the second transistor M2 and the second end of the second capacitor C2 are connected to the second control node PU. The second end of the second transistor M2 is configured to receive the second level. The second transistor M2 is configured to turn on in response to the second control node PU being at the second level, and write the second level to the output node OUT.

[0051] Therefore, by controlling the levels of the first control node PD and the second control node PU, the first output sub-circuit 210 and the second output sub-circuit 220 can be controlled to write different levels to the output node OUT, thereby achieving pulse width control of the output light emitting drive level.

[0052] Furthermore, the third control subcircuit 250 may include a switching transistor M0. A first terminal of the switching transistor M0 may serve as the first terminal of the third control subcircuit 250 and be connected to the control terminal of the second output subcircuit 220. A second terminal of the switching transistor M0 may serve as the second terminal of the third control subcircuit 250 and be connected to the second control node PU. The control terminal of the switching transistor M0 is configured to be connected to the second voltage level. The switching transistor M0 ensures the control accuracy of the second output subcircuit 220.

[0053] The first control subcircuit 230 may include: a third transistor M3 and a fourth transistor M4; the first terminal of the third transistor M3 is configured to be connected to the first voltage level, the control terminal of the third transistor M3 is connected to the second control node PU, the second terminal of the third transistor M3 and the first terminal of the fourth transistor M4 are both connected to the first control node PD, the control terminal of the fourth transistor M4 is connected to the output terminal of the second control subcircuit 240, and the second terminal of the fourth transistor M4 is configured to be connected to the second voltage level. The control terminal of the third transistor M3 serves as the first control terminal of the first control subcircuit 230, and the control terminal of the fourth transistor M4 serves as the second control terminal of the first control subcircuit 230.

[0054] By controlling the level change of the second control node PU, the conduction or shutoff of the third transistor M3 can be controlled, thereby controlling whether the first level is written to the first control node PD. The output end of the second control sub-circuit 240 can control the conduction and shutoff of the fourth transistor M4, thereby controlling whether the second level is written to the first control node PD. More specifically, when the third transistor M3 is on and the fourth transistor M4 is off, the first control node PD can be written to the first level; when the third transistor M3 is off and the fourth transistor M4 is on, the first control node PD can be written to the second level. When the third transistor M3 and the fourth transistor M4 are turned off at the same time, the level of the first control node PD can remain unchanged at the previous moment, ensuring that the level of the output node OUT remains unchanged. The level change of the first control node PD can control the corresponding first output sub-circuit 210.

[0055] Furthermore, the second control subcircuit 240 may include: a fifth transistor M5, a sixth transistor M6 and a third capacitor C3; the first end of the fifth transistor M5 is configured to access the first level, and the second end of the fifth transistor M5 is configured to access the trigger signal; the second end of the fifth transistor M5, the first end of the third capacitor C3, the second control end of the first control subcircuit 230 and the first end of the sixth transistor M6 are all connected to the third control node PD_C, the second end of the third capacitor C3 is connected to the first control node PD, the second end of the sixth transistor M6 is configured to access the second level, and the control end of the sixth transistor M6 is configured to access the clock signal.

[0056] The fifth transistor M5 is configured to write a first level to the third control node PD_C in response to the trigger signal being at the second level and the clock signal being at the first level. The sixth transistor M6 is configured to write a second level to the third control node PD_C in response to the trigger signal being at the first level and the clock signal being at the second level. At this time, when both the fifth transistor M5 and the sixth transistor M6 in the second control sub-circuit 240 are turned off, the level of the third control node PD_C can be maintained unchanged, ensuring that the second control terminal in the first control sub-circuit 230 is stably turned off. In other words, the on / off state of the fourth transistor M4 can be controlled by the on / off state of the fifth transistor M5 and the sixth transistor M6. Specifically, when the fifth transistor M5 is turned on and the sixth transistor M6 is turned off, the first level can be written to the third control node PD_C, thereby turning off the fourth transistor M4. When the fifth transistor M5 is turned off and the sixth transistor M6 is turned on, the second level can be written to the third control node PD_C, thereby turning on the fourth transistor M4.

[0057] Furthermore, the fourth control subcircuit 260 includes a seventh transistor M7. A first terminal of the seventh transistor M7 is connected to the second control node PU. A control terminal of the seventh transistor M7 is configured to receive a clock signal, and a second terminal of the seventh transistor M7 is configured to receive a trigger signal. The clock signal can be used to control the on and off state of the seventh transistor M7, thereby allowing the level of the trigger signal to be written to the second control node PU.

[0058] The light control circuit 200 in this embodiment is implemented as an 8T3C (eight thin-film transistors and three capacitors) structure to achieve light control without adding an inverse clock signal. The pulse width of the output light drive signal, i.e., the width of the first light drive level, can be controlled by an initial trigger signal. To facilitate understanding of the inventive concept of this embodiment, a specific example is provided below to illustrate.

[0059] See also Figure 3 and Figure 4 , Figure 4 The control timing diagram of the clock signal and the trigger signal is given in FIG, and the level changes of different node positions in different driving stages are also shown. Figure 4 The following describes ten drive nodes, namely ① to ⑩. Eout(n-1) is the trigger signal, EM_STV represents the first trigger signal, EM_OUT is the output light-emitting drive signal, ECK is the clock signal, and ECB is the inverse clock signal (unused).

[0060] In stage ①, Eout(n-1) is low level, ECK is low level, and the transistor state is as follows: Figure 5 As shown, where “×” indicates off.

[0061] Second control node PU: the seventh transistor M7 is turned on, the second control node PU is discharged, and a low level is written;

[0062] Fourth control node PU1: the switch transistor M0 is turned on, a low level is written to the fourth control node PU1, and the second transistor M2 is turned on;

[0063] Third control node PD_C: The fifth transistor M5 is turned on, and a high level is written to the third control node PD_C. The fifth transistor M5 and the sixth transistor M6 are turned on at the same time, but the resistance of the sixth transistor M6 is designed to be greater than the resistance of the fifth transistor M5, so that the third control node PD_C can maintain a high level.

[0064] First control node PD: Since the third control node PD_C is at a high level, the fourth transistor M4 is turned off, and the third transistor M3 is turned on to write a high level to the first control node PD;

[0065] Output node OUT: the first control node PD is at a high level and the fourth control node PU1 is at a low level, so that the first transistor M1 is turned off and the second transistor M2 is turned on, and the output node OUT is written to a low level.

[0066] In stage ②, Eout(n-1) is high level, ECK is high level, and the transistor state is as follows: Figure 6 shown.

[0067] Second control node PU: the seventh transistor M7 is turned off, and the second control node PU maintains a low level;

[0068] Fourth control node PU1: the switch transistor M0 is turned on, the fourth control node PU1 also maintains a low level, and the second transistor M2 is turned on;

[0069] Third control node PD_C: the fifth transistor M5 and the sixth transistor M6 are turned off at the same time, so that the third control node PD_C can continue to maintain a high level;

[0070] First control node PD: Since the third control node PD_C is at a high level, the fourth transistor M4 is turned off, and the third transistor M3 is turned on to write a high level to the first control node PD, and the high level continues to be maintained;

[0071] Output node OUT: the first control node PD is at a high level and the fourth control node PU1 is at a low level, so that the first transistor M1 is turned off and the second transistor M2 is turned on, and the output node OUT is written to a low level.

[0072] In stage ③, Eout(n-1) is high level, ECK is low level, and the transistor state is as follows: Figure 7 shown.

[0073] Second control node PU: the seventh transistor M7 is turned on, and a high level is written to the second control node PU;

[0074] Fourth control node PU1: the switch transistor M0 is turned on, the fourth control node PU1 is also written to a high level, and the second transistor M2 is turned off;

[0075] Third control node PD_C: The fifth transistor M5 is turned off, the sixth transistor M6 is turned on, and the third control node PD_C is written to a low level, so that the fourth transistor M4 is turned on; when the fourth transistor M4 is turned on, the first control node PD becomes a low voltage, and the third control node PD_C can be lowered to a lower voltage by the third capacitor C3. The level of the third control node PD_C and the level of the first control node PD can be expressed as: ΔV PD_C =[C3 / (C gsM4 +C3+C PD_C )]*ΔV PD ; where ΔV PD_C represents the level of the third control node PD_C, ΔV PD represents the level of the first control node PD, C3 represents the capacitance value of the third capacitor C3, and C gsM4 represents the parasitic capacitance formed by the fourth transistor M4, C PD_C Indicates C3 and C gsM4 a capacitance of a third control node PD_C other than PD_C;

[0076] First control node PD: the fourth transistor M4 is turned on, and the third transistor M3 is turned off, so that the first control node PD is written into a low level, and then the first transistor M1 is turned on;

[0077] Output node OUT: the first control node PD is at a low level and the fourth control node PU1 is at a high level, so that the first transistor M1 is turned on and the second transistor M2 is turned off, and a high level is written to the output node OUT.

[0078] In stage ④, Eout(n-1) is high level, ECK is high level, and the transistor state is as follows: Figure 8 shown.

[0079] Second control node PU: the seventh transistor M7 is turned off, and the second control node PU maintains a high level;

[0080] Fourth control node PU1: the switch transistor M0 is turned on, the fourth control node PU1 also maintains a high level, and the second transistor M2 is turned off;

[0081] The third control node PD_C: the fifth transistor M5 is turned off, the sixth transistor M6 is turned off, and the third control node PD_C maintains a low level, so that the fourth transistor M4 remains turned on;

[0082] First control node PD: the fourth transistor M4 is turned on, and the third transistor M3 is turned off, so that the first control node PD is written into a low level, and then the first transistor M1 is turned on;

[0083] Output node OUT: the first control node PD is at a low level and the fourth control node PU1 is at a high level, so that the first transistor M1 is turned on and the second transistor M2 is turned off, and a high level is written to the output node OUT.

[0084] In stage ⑤, Eout(n-1) is high level, ECK is low level, and the transistor state is as follows: Figure 9 shown.

[0085] Second control node PU: the seventh transistor M7 is turned on, and a high level is written to the second control node PU;

[0086] Fourth control node PU1: the switch transistor M0 is turned on, the fourth control node PU1 is also written to a high level, and the second transistor M2 is turned off;

[0087] Third control node PD_C: the fifth transistor M5 is turned off, the sixth transistor M6 is turned on, and the third control node PD_C is written to a low level, so that the fourth transistor M4 remains turned on;

[0088] First control node PD: the fourth transistor M4 is turned on, and the third transistor M3 is turned off, so that the first control node PD is written into a low level, and then the first transistor M1 is turned on;

[0089] Output node OUT: the first control node PD is at a low level and the fourth control node PU1 is at a high level, so that the first transistor M1 is turned on and the second transistor M2 is turned off, and a high level is written to the output node OUT.

[0090] In stage ⑥, Eout(n-1) is high, ECK is high, and the transistor state is as follows: Figure 10 shown.

[0091] Second control node PU: the seventh transistor M7 is turned off, and the second control node PU maintains a high level;

[0092] Fourth control node PU1: the switch transistor M0 is turned on, the fourth control node PU1 also maintains a high level, and the second transistor M2 is turned off;

[0093] The third control node PD_C: the fifth transistor M5 is turned off, the sixth transistor M6 is turned off, and the third control node PD_C maintains a low level, so that the fourth transistor M4 remains turned on;

[0094] First control node PD: the fourth transistor M4 is turned on, and the third transistor M3 is turned off, so that the first control node PD is written into a low level, and then the first transistor M1 is turned on;

[0095] Output node OUT: the first control node PD is at a low level and the fourth control node PU1 is at a high level, so that the first transistor M1 is turned on and the second transistor M2 is turned off, and a high level is written to the output node OUT.

[0096] In stage ⑦, Eout(n-1) is high level, ECK is low level, and the transistor state is as follows: Figure 11 shown.

[0097] Second control node PU: the seventh transistor M7 is turned on, and a high level is written to the second control node PU;

[0098] Fourth control node PU1: the switch transistor M0 is turned on, the fourth control node PU1 is also written to a high level, and the second transistor M2 is turned off;

[0099] Third control node PD_C: the fifth transistor M5 is turned off, the sixth transistor M6 is turned on, and a low level is written to the third control node PD_C, so that the fourth transistor M4 is turned on;

[0100] First control node PD: the fourth transistor M4 is turned on, and the third transistor M3 is turned off, so that the first control node PD is written into a low level, and then the first transistor M1 is turned on;

[0101] Output node OUT: the first control node PD is at a low level and the fourth control node PU1 is at a high level, so that the first transistor M1 is turned on and the second transistor M2 is turned off, and a high level is written to the output node OUT.

[0102] In stage ⑧, Eout(n-1) is low level, ECK is low level, and the transistor state is as follows: Figure 12 shown.

[0103] Second control node PU: the seventh transistor M7 is turned off, and the second control node PU maintains a high level;

[0104] Fourth control node PU1: the switch transistor M0 is turned on, the fourth control node PU1 also maintains a high level, and the second transistor M2 is turned off;

[0105] Third control node PD_C: the fifth transistor M5 is turned on, the sixth transistor M6 is turned off, and a high level is written to the third control node PD_C, so that the fourth transistor M4 is turned off;

[0106] First control node PD: the fourth transistor M4 is turned off, and the third transistor M3 is turned off, so that the first control node PD maintains a low level, and then the first transistor M1 is turned on;

[0107] Output node OUT: the first control node PD is at a low level and the fourth control node PU1 is at a high level, so that the first transistor M1 is turned on and the second transistor M2 is turned off, and a high level is written to the output node OUT.

[0108] In stage ⑨, Eout(n-1) is low level, ECK is low level, and the transistor state is as follows: Figure 13 shown.

[0109] Second control node PU: the seventh transistor M7 is turned on, and the second control node PU is written into a low level;

[0110] Fourth control node PU1: The switch transistor M0 is turned on, and the fourth control node PU1 is also written to a low level, and the second transistor M2 is turned on; when the second transistor M2 is turned on, the level of the fourth control node PU1 is pulled lower by the second capacitor C2; the relationship between the level of the fourth control node PU1 and the level of the output node OUT is: ΔV PU1 =[C2 / (C gsM2 +C1+C PU1 )]*ΔEout; where ΔV PU1 represents the level of the fourth control node PU1, ΔEout represents the level of the output node OUT, C2 represents the capacitance value of the second capacitor C2, C gsM2 represents the parasitic capacitance formed by the second transistor M2, C PU1 Indicates C2 and C gsM2 The capacitance of the fourth control node PU1 outside the control node;

[0111] Third control node PD_C: the fifth transistor M5 is turned on, the sixth transistor M6 is turned on, and a high level is written to the third control node PD_C, so that the fourth transistor M4 is turned off;

[0112] First control node PD: the fourth transistor M4 is turned off, and the third transistor M3 is turned on, so that a high level is written to the first control node PD, and then the first transistor M1 is turned off;

[0113] Output node OUT: the first control node PD is at a high level and the fourth control node PU1 is at a low level, so that the first transistor M1 is turned off and the second transistor M2 is turned on, and the output node OUT is written to a low level.

[0114] In stage ⑩, Eout(n-1) is low level, ECK is high level, and the transistor state is as follows: Figure 14 shown.

[0115] Second control node PU: the seventh transistor M7 is turned off, and the second control node PU maintains a low level;

[0116] Fourth control node PU1: the switch transistor M0 is turned on, the fourth control node PU1 also maintains a low level, and the second transistor M2 is turned on;

[0117] Third control node PD_C: the fifth transistor M5 is turned on, the sixth transistor M6 is turned off, and a high level is written to the third control node PD_C, so that the fourth transistor M4 is turned off;

[0118] First control node PD: the fourth transistor M4 is turned off, and the third transistor M3 is turned on, so that a high level is written to the first control node PD, and then the first transistor M1 is turned off;

[0119] Output node OUT: the first control node PD is at a high level and the fourth control node PU1 is at a low level, so that the first transistor M1 is turned off and the second transistor M2 is turned on, and the output node OUT is written to a low level.

[0120] The corresponding test timing diagram can be obtained through actual testing, such as Figure 15 shown; from Figure 15 It can be seen that the timing of the trigger signal and the output light-emitting control signal meets the requirements of actual light-emitting drive, and the pulse width of the light-emitting control signal is the same as the pulse width of the trigger signal.

[0121] To sum up, the light-emitting control circuit 200 provided in this embodiment can realize the width control of the output pulse of the entire circuit through the clock signal and the trigger signal, without the need to use an anti-clock signal. Compared with the EOA circuit of the prior art, since the control of the anti-clock signal is reduced, the number of thin-film transistors used can be reduced, and the circuit area is effectively reduced, which is conducive to the high-resolution design of MLED type display panels.

[0122] Based on the same inventive concept, in one embodiment of the present invention, a display driving circuit is further provided, comprising: N light-emitting control circuits as described in any one of the aforementioned embodiments; N is a positive integer, and the N light-emitting control circuits are cascaded; the light-emitting driving level output by the light-emitting control circuit of the nth stage is the trigger signal of the light-emitting control circuit of the n-1th stage, 2≤n≤N, and n is a positive integer.

[0123] It should be noted that, in the present invention, a real panel may include one or more sets of such display driver circuits, without limitation. The specific implementation and beneficial effects of the light-emitting control circuit included in the display driver circuit have been described and illustrated in the aforementioned embodiments. The relevant implementation methods and beneficial effects can be referred to in the relevant descriptions of the aforementioned embodiments. Any aspects not mentioned as being achievable by reference to existing technologies will not be further elaborated here.

[0124] Based on the same inventive concept, a display device is also provided in one embodiment of the present invention, including: a sub-pixel, a gate driving circuit and a light-emitting control circuit as described in any of the aforementioned embodiments; the gate driving circuit is connected to the charging control transistor of the sub-pixel, and the light-emitting control circuit is connected to the light-emitting control transistor of the sub-pixel; the gate driving circuit is configured to control the charging control transistor to be turned on during the charging stage to write a data signal to the storage capacitor of the sub-pixel; the light-emitting control circuit is configured to control the light-emitting control transistor to be turned on during the light-emitting stage to control the sub-pixel to emit light.

[0125] It should be noted that the display device can be any product or component with a display function, such as a mobile phone, a liquid crystal panel, an MLED panel, an electronic paper, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame or a navigator.

[0126] Since the light-emitting control circuit included in the display device according to the embodiment of the present invention has been described above, those skilled in the art will be able to understand the specific structure and operating principle of the display device based on the light-emitting control circuit described in the embodiment of the present invention, and therefore will not be described in detail here. Any display device including the light-emitting control circuit according to the embodiment of the present invention falls within the scope of protection of the present invention.

[0127] In the description provided herein, numerous specific details are described. However, it is understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0128] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Accordingly, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the invention.

[0129] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and further may be divided into a plurality of submodules or subunits or subcomponents. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed herein may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0130] Furthermore, those skilled in the art will appreciate that although some embodiments herein include certain features included in other embodiments but not other features, combinations of features from different embodiments are intended to be within the scope of the present invention and to form different embodiments. For example, in the claims below, any of the claimed embodiments may be used in any combination.

[0131] It should be noted that the above embodiments illustrate rather than limit the invention, and that a person skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between brackets should not be construed as limiting the claims. The word "comprising" does not exclude the presence of components or steps not listed in the claims. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The present invention may be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

Claims

1. A light emitting control circuit, characterized in that: include: an output subcircuit, a first control subcircuit, and a second control subcircuit; the output terminal of the output subcircuit is connected to an output node; the first control terminal of the output subcircuit and the output terminal of the first control subcircuit are both connected to a first control node; the second control terminal of the output subcircuit and the first control terminal of the first control subcircuit are both connected to a second control node; the second control terminal of the first control subcircuit is connected to the output terminal of the second control subcircuit; The second control subcircuit is configured to: write a first level or a second level to the second control terminal of the first control subcircuit in response to control of a clock signal and a trigger signal; The first control sub-circuit is configured to: in response to the second control terminal of the first control sub-circuit being written with the second level and the second control node being written with the first level, write the second level to the first control node; and in response to the second control terminal of the first control subcircuit and the second control node both being written with the first level, maintaining the first control node at the second level; The output sub-circuit is configured to write a first light emission driving level to the output node in response to the first control node being written to the second level and the second control node being written to the first level.

2. The light emitting control circuit according to claim 1, characterized in that: The output subcircuit includes: a first output subcircuit and a second output subcircuit; the output end of the first output subcircuit and the output end of the second output subcircuit are both connected to the output node; the control end of the first output subcircuit is connected to the first control node, and the control end of the second output subcircuit is connected to the second control node; The first output sub-circuit is configured to: in response to the first control node being written to the second level and the second control node being written to the first level, write the first light emitting driving level to the output node; The second output sub-circuit is configured to write a second light emission driving level for turning off light emission into the output node in response to a first level being written to the first control node and a second level being written to the second control node.

3. The light emitting control circuit according to claim 2, characterized in that: The first light-emitting drive level is a first level; the first output sub-circuit includes: a first transistor and a first capacitor; a first end of the first transistor and a first end of the first capacitor are both configured to be connected to the first level, a control end of the first transistor and a second end of the first capacitor are both connected to the first control node; and a second end of the first transistor is connected to the output node; The first transistor is configured to be turned on in response to the first control node being at a second level, and to write a first level to the output node.

4. The light emitting control circuit according to claim 2, wherein: The second light-emitting drive level is a second level; the second output sub-circuit includes: a second transistor and a second capacitor, a first end of the second transistor and a first end of the second capacitor are connected to the output node, a control end of the second transistor and a second end of the second capacitor are connected to the second control node; and a second end of the second transistor is configured to receive the second level; The second transistor is configured to be turned on in response to the second control node being at a second level, and to write the second level to the output node.

5. The light emitting control circuit according to claim 4, characterized in that: It also includes a third control sub-circuit, and the control end of the second output sub-circuit is connected to the second control node through the third control sub-circuit.

6. The light emitting control circuit according to claim 1, wherein: The first control subcircuit includes: a third transistor and a fourth transistor; a first terminal of the third transistor is configured to be connected to a first electrical level, a control terminal of the third transistor is connected to the second control node, a second terminal of the third transistor and a first terminal of the fourth transistor are both connected to the first control node, a control terminal of the fourth transistor is connected to the output terminal of the second control subcircuit, and a second terminal of the fourth transistor is configured to be connected to a second electrical level; The control end of the third transistor is the first control end of the first control sub-circuit, and the control end of the fourth transistor is the second control end of the first control sub-circuit.

7. The light emitting control circuit according to claim 1, characterized in that: The second control subcircuit includes: a fifth transistor, a sixth transistor, and a third capacitor; a first terminal of the fifth transistor is configured to be connected to a first electrical level, and a second terminal of the fifth transistor is configured to be connected to the trigger signal; a second terminal of the fifth transistor, a first terminal of the third capacitor, a second control terminal of the first control subcircuit, and a first terminal of the sixth transistor are all connected to a third control node, a second terminal of the third capacitor is connected to the first control node, a second terminal of the sixth transistor is configured to be connected to a second electrical level, and a control terminal of the sixth transistor is configured to be connected to the clock signal; The fifth transistor is configured to: in response to the trigger signal being at the second level and the clock signal being at the first level, write the first level to the third control node; The sixth transistor is configured to write a second level to the third control node in response to the trigger signal being at the first level and the clock signal being at the second level.

8. The light emitting control circuit according to claim 1, wherein: Also includes: a fourth control subcircuit; The output terminal of the fourth control subcircuit is connected to the second control node, the input terminal of the fourth control subcircuit is configured to receive the trigger signal, and the control terminal of the fourth control subcircuit is configured to receive the clock signal; The fourth control sub-circuit is configured to: write the level of the trigger signal to the second control node in response to control of the clock signal; the trigger signal is a first level or a second level.

9. The light emitting control circuit according to claim 8, characterized in that: The fourth control subcircuit includes a seventh transistor, a first terminal of the seventh transistor is connected to the second control node, a control terminal of the seventh transistor is configured to access the clock signal, and a second terminal of the seventh transistor is configured to access the trigger signal.

10. A display driving circuit, characterized in that: include: N light-emitting control circuits according to any one of claims 1 to 9; N is a positive integer, and the N light-emitting control circuits are cascaded; the light-emitting drive level output by the light-emitting control circuit of the nth level is the trigger signal of the light-emitting control circuit of the n-1th level, 2≤n≤N, and n is a positive integer.

11. A display device, characterized in that: include: A sub-pixel, a gate drive circuit, and a light-emitting control circuit according to any one of claims 1 to 9; the gate drive circuit is connected to the charge control transistor of the sub-pixel, and the light-emitting control circuit is connected to the light-emitting control transistor of the sub-pixel; The gate driving circuit is configured to control the charging control transistor to be turned on during a charging phase so as to write a data signal into the storage capacitor of the sub-pixel; The light emitting control circuit is configured to control the light emitting control transistor to be turned on during a light emitting phase, so as to control the sub-pixel to emit light.

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