Performance optimization design method, system, medium and equipment for pass-through I / O virtualization

Abstract

The application provides a design method, system, medium and equipment for performance optimization of pass-through I / O virtualization, comprising: an I / O page table configuration step; a DMA buffer detection step; and a DMA buffer dynamic migration step. The application focuses on performance overhead which is not focused on by the prior art, and the design scheme well solves the overhead. The design scheme of the application is designed around I / O devices, which is more in line with the current hardware development trend compared with the design scheme around the CPU in the past work. The design scheme of the application is not sensed by the guest virtual machine, and the guest virtual machine can enjoy the performance improvement brought by the scheme without modifying the source code.

Description

Technical Field

[0001] This invention relates to the field of virtualization technology, specifically to a performance optimization design method, system, medium, and device for pass-through I / O virtualization, and particularly to the performance optimization of IOMMU and DMA buffers in virtualization device pass-through technology under NUMA scenarios. Background Technology

[0002] The widespread adoption of cloud computing has brought virtualization technology into the spotlight. The development of the national computing power industry has further boosted the growth of the cloud computing industry. Virtualization technology, as the core and cornerstone of cloud computing, plays a crucial role. Based on the types of virtual resources, virtualization technology can be further subdivided into CPU virtualization, memory virtualization, and I / O virtualization. These correspond to the processor, memory, and I / O resources, respectively, providing a unified resource abstraction for upper-layer applications.

[0003] Paravirtualization is a popular I / O virtualization technology, but it still faces challenges such as high virtualization management overhead and the need to modify guest driver code, leading to a trend of being replaced by device pass-through technology. Paravirtualization establishes a new interface between the guest virtual machine and the virtual machine monitor. This interface avoids the numerous trap operations inherent in full emulation, significantly reducing the overhead of interaction between the guest virtual machine and the virtual machine monitor, and greatly improving I / O virtualization performance. However, with the gradual development and increasing speed of I / O devices, the virtualization management performance overhead of paravirtualization has become a pressing issue that needs to be addressed in the development of I / O virtualization technology.

[0004] Device passthrough technology directly assigns a physical device to a virtual machine, allowing the virtual machine to use that physical device exclusively. Meanwhile, the virtualization capabilities of the physical devices themselves are also evolving, leading to various hardware-level I / O virtualization solutions. For example, SRIOV (Single Root I / O Virtualization) can abstract a physical device into multiple VFs (Virtual Functions), each of which can be provided as a device entity for exclusive use by guest virtual machines.

[0005] More specifically, in a device pass-through solution, the IOMMU (I / O Memory Management Unit) is an essential hardware component. The IOMMU functions similarly to the MMU, providing isolation. While the CPU MMU isolates address spaces between processes, the IOMMU isolates I / O devices, configuring an independent address space for each I / O device, and even for each process using an I / O device. This mapping of independent address spaces is accomplished through I / O page tables. The IOMMU hardware topology resides on the PCI main bridge. Memory access requests from I / O devices pass through the IOMMU on the PCI main bridge. The IOMMU translates the virtual address held by the device into the actual physical address before performing the memory access operation. However, the introduction of the IOMMU hardware introduces greater performance overhead for I / O operations, such as the overhead of I / O page table translation and configuration. The I / O page table is a data structure similar to the MMU page table.

[0006] On the other hand, as single-core frequency and performance improvements reached their limits, processor development shifted towards multi-core and NUMA (Non-Uniform Memory Access) architectures to improve overall performance through horizontal scaling. NUMA divides the original single processor into multiple nodes, each with its own processor and memory. When a processor accesses memory outside its own node, memory access latency increases significantly. Most current server processors utilize NUMA architecture, which has become the mainstream design approach for server processors.

[0007] While NUMA architecture offers better scalability, it also introduces performance challenges. Because NUMA distributes CPU and memory across different nodes, it creates a special type of memory access: cross-node memory access. For example, if the CPU of node 0 needs to access data in the memory of node 1, it must traverse the inter-node communication bridge. However, if the CPU of node 0 needs to access memory within the same node, it does not need to traverse this communication bridge. The added process in cross-node memory access incurs performance overhead. This includes increased latency for a single memory access and limitations on the overall bandwidth of multiple memory accesses. Specifically, firstly, the overhead of a single cross-node memory access is greater than that of an intra-node memory access. If a process frequently and extensively performs cross-node memory accesses, its performance will degrade significantly. Furthermore, because the underlying NUMA topology is often hidden from view, it can cause unexpected performance overhead in real-world applications. Secondly, due to the bandwidth limitations of the memory controller, if multiple processors simultaneously initiate memory access operations on a node, the communication bridge between nodes often experiences memory access blockage. In this case, these cross-node memory accesses will cause memory lag, which will also lead to increased memory access overhead in specific processes. This is one of the sources of performance problems in the current NUMA scenario.

[0008] Specifically, the uneven memory distribution characteristic of NUMA architecture has inspired a series of inventions and innovations, all aimed at optimizing the performance overhead of CPU accessing remote node memory. However, what is widely overlooked is that the uneven memory distribution in NUMA architecture also leads to performance issues for I / O devices accessing remote memory. For ease of explanation, we will call the CPU where the current task resides the working CPU, the NUMA node where the working CPU resides the CPU-local node, and all other nodes the CPU-remote nodes. Similarly, from the perspective of I / O devices, we will call the NUMA node where the I / O device resides the device-local node, and the remaining nodes the device-remote nodes.

[0009] Therefore, a new technical solution is needed to improve the above-mentioned technical problems. Summary of the Invention

[0010] To address the shortcomings of existing technologies, the purpose of this invention is to provide a performance optimization design method, system, medium, and device for pass-through I / O virtualization.

[0011] According to the present invention, a performance optimization method for virtualization device passthrough technology IOMMU and DMA buffer is provided, the method comprising the following steps:

[0012] Step S1: Manage the allocation logic of I / O page tables. In the I / O page table allocation process, check the NUMA location of the corresponding device and allocate the I / O page table to the local node of the device.

[0013] Step S2: Add a DMA buffer detection step to the virtual machine monitor to obtain the guest virtual machine DMA buffer information by directly reading the hardware configuration information in the I / O device;

[0014] Step S3: Add a dynamic migration step for the DMA buffer in the virtual machine monitor. Based on step S2, dynamically migrate the DMA buffer located on the remote node of the device in the guest virtual machine to the near node of the device. After the migration is completed, the device DMA memory access operation is a near-end memory access operation.

[0015] Preferably, step S1 fixes the I / O page table allocation location on the NUMA node where the corresponding I / O device is located.

[0016] Preferably, step S2 involves reading the I / O device hardware configuration space to obtain the DMA buffer information in the guest virtual machine.

[0017] Preferably, step S3 migrates the DMA buffer with minimal performance overhead, without the guest virtual machine being aware of it; the guest virtual machine's DMA buffer is dynamically migrated to the device's local node without affecting the guest virtual machine's operation; the DMA operation after the migration is completed is a near-end operation.

[0018] This invention also provides a performance optimization system for virtualization device passthrough technology IOMMU and DMA buffer, the system comprising the following modules:

[0019] Module M1: Manages the allocation logic of I / O page tables. In the I / O page table allocation process, it checks the NUMA location of the corresponding device and allocates the I / O page table to the local node of the device.

[0020] Module M2: Adds a DMA buffer detection module to the virtual machine monitor to obtain the DMA buffer information of the guest virtual machine by directly reading the hardware configuration information in the I / O device;

[0021] Module M3: Adds a dynamic migration module for DMA buffers to the virtual machine monitor. Based on module M2, it dynamically migrates the DMA buffers located on the remote node of the device in the guest virtual machine to the near node of the device. After the migration is completed, the device DMA memory access operation is a near-end memory access operation.

[0022] Preferably, module M1 fixes the I / O page table allocation location on the NUMA node where the corresponding I / O device is located.

[0023] Preferably, the module M2 obtains the DMA buffer information in the client virtual machine by reading the I / O device hardware configuration space.

[0024] Preferably, module M3 migrates the DMA buffer with minimal performance overhead, without the guest virtual machine being aware of it; it dynamically migrates the guest virtual machine's DMA buffer to the device's local node without affecting the guest virtual machine's operation; the DMA operation after the migration is completed is a near-end operation.

[0025] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the performance optimization method for virtualization device pass-through technology IOMMU and DMA buffer described above.

[0026] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the virtualization device pass-through technology IOMMU and DMA buffer performance optimization method described above.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] 1. This invention addresses performance overhead that has not been addressed in existing technologies, and the design effectively solves this overhead problem;

[0029] 2. The design scheme of this invention focuses on I / O devices, which is more in line with the current hardware development trend compared to previous work that focused on CPU design schemes;

[0030] 3. The design scheme of the present invention is imperceptible to the guest virtual machine. The guest virtual machine can enjoy the performance improvement brought by the scheme of the present invention without modifying the source code. Attached Figure Description

[0031] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0032] Figure 1 This is a flowchart of the present invention;

[0033] Figure 2 This is a diagram of the overall architecture of the present invention;

[0034] Figure 3 This is a perspective diagram of the hardware architecture related to this invention;

[0035] Figure 4 A schematic diagram illustrating the steps involved in configuring I / O page tables;

[0036] Figure 5 A schematic diagram of the DMA buffer detection process;

[0037] Figure 6 This is a schematic diagram of the dynamic migration process for the DMA buffer. Detailed Implementation

[0038] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0039] Example 1:

[0040] According to the present invention, a performance optimization method for virtualization device passthrough technology IOMMU and DMA buffer is provided, the method comprising the following steps:

[0041] Step S1: Manage the allocation logic of I / O page tables. In the I / O page table allocation process, check the NUMA location of the corresponding device and allocate the I / O page table to the local node of the device; fix the I / O page table allocation location on the NUMA node where the corresponding I / O device is located.

[0042] Step S2: Add a DMA buffer detection step to the virtual machine monitor. Obtain the DMA buffer information of the guest virtual machine by directly reading the hardware configuration information in the I / O device; obtain the DMA buffer information in the guest virtual machine by reading the hardware configuration space of the I / O device.

[0043] Step S3: Add a dynamic migration step for the DMA buffer in the virtual machine monitor. Based on step S2, dynamically migrate the DMA buffer in the guest virtual machine located on the remote node of the device to the near node of the device. After the migration, the device DMA memory access operation is a near-end memory access operation. The DMA buffer is migrated with minimal performance overhead, and the guest virtual machine is unaware of it. Without affecting the operation of the guest virtual machine, the DMA buffer of the guest virtual machine is dynamically migrated to the local node of the device. The DMA operation after the migration is completed is a near-end operation.

[0044] The present invention also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the above-described performance optimization method for virtualization device pass-through technology IOMMU and DMA buffer.

[0045] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, it implements the steps of the virtualization device pass-through technology IOMMU and DMA buffer performance optimization method described above.

[0046] This invention also provides a performance optimization system for virtualization device passthrough technology IOMMU and DMA buffer. The performance optimization system for virtualization device passthrough technology IOMMU and DMA buffer can be implemented by executing the process steps of the performance optimization method for virtualization device passthrough technology IOMMU and DMA buffer. That is, those skilled in the art can understand the performance optimization method for virtualization device passthrough technology IOMMU and DMA buffer as a preferred embodiment of the performance optimization system for virtualization device passthrough technology IOMMU and DMA buffer.

[0047] Example 2:

[0048] Example 2 is a preferred embodiment of Example 1, and is used to illustrate the present invention in more detail.

[0049] This invention also provides a performance optimization system for virtualization device passthrough technology IOMMU and DMA buffer, the system comprising the following modules:

[0050] Module M1: Manages the allocation logic of I / O page tables. In the I / O page table allocation process, it checks the NUMA location of the corresponding device and allocates the I / O page table to the local node of the device; it also fixes the I / O page table allocation location on the NUMA node where the corresponding I / O device is located.

[0051] Module M2: Adds a DMA buffer detection module to the virtual machine monitor to obtain the DMA buffer information of the guest virtual machine by directly reading the hardware configuration information in the I / O device; and obtains the DMA buffer information in the guest virtual machine by reading the hardware configuration space of the I / O device.

[0052] Module M3: Adds a dynamic DMA buffer migration module to the virtual machine monitor. Based on Module M2, it dynamically migrates the DMA buffers of guest virtual machines located on the remote node of the device to the near node of the device. After migration, the device DMA memory access operation is a near-end memory access operation. The DMA buffer migration is performed with minimal performance overhead, and the guest virtual machine is unaware of it. The DMA buffers of guest virtual machines are dynamically migrated to the local node of the device without affecting the operation of the guest virtual machine. The DMA operation after migration is a near-end operation.

[0053] Example 3:

[0054] Example 3 is a preferred example of Example 1, and is used to illustrate the present invention in more detail.

[0055] This invention will focus on I / O virtualization technology. The development of I / O virtualization technology has gone through three stages: full emulation, semi-virtualization, and device pass-through. Full emulation technology is the most primitive I / O virtualization technology. The operations of the guest virtual machine on the device are captured by the virtual machine monitor, which simulates the operations and returns the simulation results to the guest virtual machine.

[0056] Device passthrough technology theoretically offers the best performance, fully utilizing the physical capabilities of devices. Its virtualization management overhead is the lowest among the three technologies, representing the current trend and future of I / O virtualization technology. However, in practical engineering applications, device passthrough solutions still suffer from certain functional deficiencies and performance issues. For example, commonly used functions in public cloud scenarios, such as hot migration, cannot be implemented. Specifically, in terms of performance, the actual performance of device passthrough solutions still falls short of its theoretical upper limit. This invention focuses on this performance overhead, aiming to bring the performance of device passthrough solutions closer to their theoretical upper limit.

[0057] Based on the above observations, this invention identifies performance issues with pass-through I / O virtualization under NUMA architecture and designs a technical solution that successfully optimizes these issues. This invention demonstrates its technology based on the ARM hardware platform, but the design solutions included in this invention are not limited to the ARM hardware platform and can be applied to any hardware platform with IOMMU functionality and NUMA architecture. Those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the substantive content of this invention.

[0058] To address the shortcomings of existing technologies, the purpose of this invention is to optimize the performance overhead of pass-through I / O virtualization technology in NUMA scenarios.

[0059] This invention aims to solve the performance problems of pass-through I / O virtualization technology in NUMA scenarios. From a complete I / O processing flow perspective, the complete process is as follows: First, when the guest virtual machine starts, the virtual machine monitor configures the IOMMU, including the configuration of I / O device information and I / O page tables. Second, when the guest virtual machine is running, before the application initiates an I / O operation, a DMA buffer is allocated, and after allocation, a DMA operation is initiated. This is mainly divided into startup operations and runtime operations.

[0060] This invention modifies the I / O page table configuration steps during the guest virtual machine startup process. During the guest virtual machine runtime process, it adds DMA buffer detection and DMA buffer dynamic migration steps. The specific steps are as follows.

[0061] The pass-through I / O performance optimization design method for NUMA scenarios provided by the present invention includes an I / O page table configuration step, a DMA buffer detection step, and a DMA buffer dynamic migration step.

[0062] I / O Page Table Configuration Steps: Before a physical device initiates actual read / write operations, the IOMMU needs to be configured, including the configuration of IOMMU-related control registers and the I / O page table. Before IOMMU initialization, the device has the ability to read and write global physical addresses. On platforms without IOMMU, the general process of initiating a DMA operation is as follows: after allocating the DMA buffer, the device's register interface is written directly, and then the device initiates a read / write request to read and write data from main memory. After introducing IOMMU, after allocating the DMA buffer, the I / O page table needs to be configured first to map the I / O virtual address to the physical address. Then, the I / O virtual address is written to the device's register interface, and the device can initiate a DMA read / write request. The purpose of the I / O page table is to change the address written to the device from the real physical address to the I / O virtual address, thereby preventing the device from obtaining real memory information. The I / O page table configuration steps mainly consist of two steps: first, allocating physical pages as I / O page table pages; second, filling the mapping information from I / O virtual address to physical address into the allocated physical pages according to the page table format.

[0063] DMA buffer detection steps: Typically, in a device scenario, the DMA buffer in a guest virtual machine is not visible to the virtual machine monitor, representing one example of the "semantic gap" in virtualization. Without the virtual machine monitor's ability to detect the DMA buffer's location, it cannot perform optimization operations related to the DMA buffer's placement. This invention innovatively proposes a method for DMA buffer detection.

[0064] DMA Buffer Dynamic Migration Steps: Normally, DMA buffers do not undergo a migration step. This invention innovatively proposes a dynamic migration step for DMA buffers. The dynamic migration step refers to moving the DMA buffer from a suboptimal physical location to a more optimal one. Typically, after the operating system marks a memory block as a DMA buffer, its location remains unchanged until the device completes the I / O operation. However, guest virtual machines generally cannot perceive the actual NUMA topology of the physical machine, thus DMA buffer allocation is often suboptimal. A suboptimal case is when the I / O device is on NUMA node 0, but the allocated DMA buffer is on NUMA node 1. The dynamic migration step for DMA buffers proposed in this invention will solve the performance overhead problem caused by such suboptimal allocation.

[0065] Preferably, in the IO page table configuration step, this invention combines the allocation location of the IO page table with the location of its corresponding device. Specifically, it allocates the IO page table to the same NUMA node as the device. The background to this design is that physical page allocation is often overlooked due to its low memory overhead, but the location of the page table itself can cause performance issues in critical scenarios. Specifically, when the device initiates an address translation request, the IOMMU hardware needs to read the IO page table, accessing the IO page table pages level by level according to the IO virtual address, and finally reading the physical address. The device can then perform the actual memory access operation based on this physical address. This involves multiple accesses to the IO page table, as the IO page table is a multi-level table. Therefore, the entire IO virtual address translation process may involve multiple IO page table accesses. If these page tables are scattered across different NUMA nodes, the memory access overhead of multiple accesses to remote nodes will lead to a significant performance degradation in critical applications. In fact, the current mainstream server operating system Linux's I / O page table allocation strategy still doesn't take this issue into account. It uses a First-Touch strategy, which allocates I / O page tables to the NUMA node where the current process resides. Under normal circumstances, this is optimal because allocating to the current NUMA node minimizes the overhead of CPU access to the data. However, this approach doesn't consider the read / write performance issues on the device side, specifically the performance of DMA memory access.

[0066] Preferably, in the DMA buffer detection step, this invention innovatively proposes to obtain the location of the DMA buffer currently used by the I / O peripheral by reading the hardware configuration space of the I / O peripheral at the virtual machine monitor level. Taking PCI devices as an example, the SR-IOV device virtualization scheme is generally adopted, which is divided into physical functions (PF) and virtual functions (VF). The virtual machine monitor generally uses PF to operate the device. One PF often corresponds to multiple VFs, and each VF can be exclusively provided to a guest virtual machine. In typical use cases, the virtual machine monitor generally only operates on the PF, and the guest virtual machine only operates on the VF assigned to it. However, in reality, the virtual machine monitor has the highest global privileges, so it can read the information of all VFs. Since the VF needs to specify the location and size of the DMA buffer for the I / O device, it stores the location and size information of the DMA buffer. Therefore, we add a DMA buffer detection step to the traditional I / O process and innovatively propose a detection method for guest virtual machines from the virtual machine monitor.

[0067] Preferably, in the DMA buffer dynamic migration step, this invention innovatively proposes a DMA buffer dynamic migration method and removes the dynamic migration process from the critical path, minimizing the performance overhead of the migration. Specifically, we start one or more asynchronous threads in the virtual machine monitor and use the DMA buffer detection method proposed in this invention to continuously detect the DMA buffer position of a specific I / O device. When it is found that the DMA buffer position of a specific I / O device is not optimal, the migration process is initiated to migrate the DMA buffer to the optimal position and update the I / O page table mapping and the secondary page table mapping of the guest virtual machine.

[0068] Preferably, in the DMA buffer dynamic migration step, this invention innovatively proposes a prefetch migration technique. That is, after detecting that a certain segment of physical memory is the current device's DMA buffer, adjacent memory regions are checked. If they are still within the memory range of the current guest virtual machine, the adjacent regions are dynamically migrated to the NUMA node where the I / O device resides. Therefore, when performing actual I / O operations in adjacent DMA buffers, the overhead of dynamic migration is entirely outside the critical path. The critical path refers to the sequential combination of key steps essential to completing the current operation.

[0069] Preferably, in the DMA buffer dynamic migration step, this invention innovatively uses DMA buffer memory pool technology. In the dynamic migration step, a certain amount of memory needs to be allocated in the device local node first, and then the contents of the original DMA buffer located on the remote device node are copied to the memory of the device local node. The performance overhead of the memory allocation process in the device local node is considerable. Therefore, to address this performance overhead, this invention innovatively proposes DMA buffer memory pool technology, which pre-allocates a certain amount of memory in the device local node for DMA buffer migration. DMA buffer memory pool technology simplifies the memory allocation logic, reduces the DMA buffer migration overhead, and also avoids the memory allocation work for the DMA buffer affecting the memory allocation performance of other parts of the system.

[0070] like Figure 1 As shown, the present invention provides a performance optimization design method for pass-through I / O virtualization in a NUMA scenario, comprising:

[0071] I. I / O Page Table Configuration Steps: Fix the I / O page table allocation location on the NUMA node where the corresponding I / O device resides. Specifically, the original I / O page table allocation strategy in the Linux operating system is First-Touch. However, processes or threads using I / O often migrate between different NUMA nodes. This means that in a production environment, the I / O page table corresponding to a certain I / O device may be scattered across different NUMA nodes. The consequence is that if an IOTLBIS occurs during DMA operations on the I / O device, it will trigger multiple cross-node memory access operations, leading to a significant performance degradation in critical scenarios.

[0072] II. DMA Buffer Detection Step: The location and size information of the DMA buffer in the guest virtual machine (VM) is often invisible to the VM monitor, posing a significant information obstacle to the VM monitor's optimization of device I / O. The DMA buffer detection step proposed in this invention obtains the DMA buffer information in the guest VM by reading the I / O device's hardware configuration space. Specifically, taking the SRIOV device as an example, the VM monitor typically uses the PF (physical function) to directly control the I / O device, while directly assigning the VF to a guest VM. Normally, the guest VM has complete control over the VF, while the VM monitor does not operate on the VF. However, by adding a DMA buffer detection module to the VM monitor, the VM monitor can obtain the location and size information of the DMA buffer in the guest VM, providing a foundation for the VM monitor's optimization of device I / O.

[0073] III. Dynamic Migration Steps for DMA Buffers: Guest virtual machines (VMs) often possess only limited hardware topology information, such as NUMA topology information. Given this limited information, VMs need to allocate DMA buffers, often resulting in suboptimal DMA buffer locations. The dynamic migration steps for DMA buffers proposed in this invention can migrate DMA buffers from suboptimal to optimal locations with minimal performance overhead, without the guest VM being aware of it. Specifically, a real NUMA topology may have four fully interconnected NUMA nodes. The VM monitor can perceive the real NUMA topology and all NUMA nodes. However, guest VMs often cannot see the real NUMA topology; for example, they may only see one NUMA node. In reality, the guest VM's memory may be scattered across different NUMA nodes, determined by the guest VM's running state and the VM monitor's allocation strategy. In this case, the DMA buffers allocated by the guest VM may be scattered across different NUMA nodes. If the DMA buffer is located on a remote node, the DMA memory access overhead of the corresponding I / O device will increase, resulting in a significant performance impact for critical I / O applications. The dynamic DMA buffer migration procedure proposed in this invention can dynamically migrate the DMA buffer of a guest virtual machine to the device-local node (the NUMA node closest to the I / O device) without affecting the operation of the guest virtual machine. After the migration is completed, the DMA operation will be a near-end operation, which can eliminate the performance overhead caused by the remote DMA operation.

[0074] Based on the aforementioned optimized design method for pass-through I / O virtualization in a NUMA scenario, this invention also provides a real system employing the aforementioned optimized design method, comprising:

[0075] 1. I / O Page Table Configuration Module: Manages the allocation logic of I / O page tables. In the I / O page table allocation process, it checks the NUMA location of the corresponding device and allocates the I / O page table to the local node of the device.

[0076] II. DMA Buffer Detection Module: A DMA buffer detection module is added to the virtual machine monitor, enabling the monitor to detect the location and size of DMA buffers in guest virtual machines. This is achieved by directly reading the hardware configuration information from the I / O devices to obtain the guest virtual machine's DMA buffer information.

[0077] III. DMA Buffer Dynamic Migration Module: A DMA buffer dynamic migration module is added to the virtual machine monitor. Building upon the DMA buffer detection module, this module dynamically migrates DMA buffers located on the remote node of the device within the guest virtual machine to the near node. After migration, all device DMA memory access operations will be near-end memory access operations, significantly reducing memory access overhead.

[0078] Those skilled in the art can understand this embodiment as a more specific description of Embodiment 1 and Embodiment 2.

[0079] Those skilled in the art will understand that, besides implementing the system and its various devices, modules, and units provided by this invention in the form of purely computer-readable program code, the same functions can be achieved entirely through logical programming of the method steps, making the system and its various devices, modules, and units of this invention function in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, the system and its various devices, modules, and units provided by this invention can be considered as a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; alternatively, the devices, modules, and units for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0080] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A performance optimization method for virtualization device pass-through technology IOMMU and DMA buffer, characterized in that, The method includes the following steps: Step S1: Manage the allocation logic of I / O page tables. In the I / O page table allocation process, check the NUMA location of the corresponding device and allocate the I / O page table to the near-end node. Step S2: Add a DMA buffer detection step to the virtual machine monitor to obtain the guest virtual machine DMA buffer information by directly reading the hardware configuration information in the I / O device; Step S3: Add a dynamic migration step for the DMA buffer in the virtual machine monitor. Based on step S2, dynamically migrate the DMA buffer located on the remote node of the device in the guest virtual machine to the near node of the device. After the migration is completed, the device DMA memory access operation is a near-end memory access operation.

2. The performance optimization method for virtualization device pass-through technology IOMMU and DMA buffer according to claim 1, characterized in that, Step S1 fixes the I / O page table allocation location on the NUMA node where the corresponding I / O device is located.

3. The performance optimization method for virtualization device pass-through technology IOMMU and DMA buffer according to claim 1, characterized in that, Step S2 obtains the DMA buffer information in the client virtual machine by reading the I / O device hardware configuration space.

4. The performance optimization method for virtualization device pass-through technology IOMMU and DMA buffer according to claim 1, characterized in that, Step S3 migrates the DMA buffer with minimal performance overhead, without the guest virtual machine being aware of it; the guest virtual machine's DMA buffer is dynamically migrated to the near-end node without affecting the operation of the guest virtual machine. The DMA operation after the migration is complete is a near-end operation.

5. A performance optimization system for virtualization device pass-through technology IOMMU and DMA buffer, characterized in that, The system includes the following modules: Module M1: Manages the allocation logic of I / O page tables. In the I / O page table allocation process, it checks the NUMA location of the corresponding device and allocates the I / O page table to the near-end node. Module M2: Adds a DMA buffer detection module to the virtual machine monitor to obtain the DMA buffer information of the guest virtual machine by directly reading the hardware configuration information in the I / O device; Module M3: Adds a dynamic migration module for DMA buffers to the virtual machine monitor. Based on module M2, it dynamically migrates the DMA buffers located on the remote node of the device in the guest virtual machine to the near node of the device. After the migration is completed, the device DMA memory access operation is a near-end memory access operation.

6. The performance optimization system for virtualization device pass-through technology IOMMU and DMA buffer according to claim 5, characterized in that, The module M1 fixes the I / O page table allocation location on the NUMA node where the corresponding I / O device is located.

7. The performance optimization system for virtualization device pass-through technology IOMMU and DMA buffer according to claim 5, characterized in that, The module M2 obtains the DMA buffer information in the client virtual machine by reading the I / O device hardware configuration space.

8. The performance optimization system for virtualization device pass-through technology IOMMU and DMA buffer according to claim 5, characterized in that, The module M3 migrates the DMA buffer with minimal performance overhead, without the guest virtual machine being aware of it; it dynamically migrates the guest virtual machine's DMA buffer to the near-end node without affecting the guest virtual machine's operation. The DMA operation after the migration is complete is a near-end operation.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the performance optimization method for virtualization device pass-through technology IOMMU and DMA buffer as described in any one of claims 1-4.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the computer program is executed by the processor, it implements the steps of the performance optimization method for virtualization device pass-through technology IOMMU and DMA buffer as described in any one of claims 1-4.

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