PCIE high-performance digital signal processing board

Abstract

The application discloses a PCIE high-performance digital signal processing board and belongs to the technical field of signal processing, which comprises four DSPs, 40 DDR3 SDDRAMs, five SPI Flash chips, four NAND Flash chips, one GBE PHY chip, one FPGA, five temperature monitoring chips, one optical fiber module and external physical interfaces; the application can realize high-speed data processing, large-capacity high-speed data caching and high-speed data transmission and the like.

Description

Technical Field

[0001] This invention belongs to the technical field of signal processing, and specifically relates to a PCIe high-performance digital signal processing board. Background Technology

[0002] PCIe high-performance digital signal processing boards are primarily used in wideband radar signal processing, wideband radar signal simulation, and wideband signal reconnaissance and analysis. With the continuous increase in radar signal bandwidth, the growing complexity of processing algorithms, and the diversification of operating modes, the requirements for signal processing capabilities, data transmission capabilities, and data caching capabilities are constantly increasing. Different application needs also place higher demands on the standardization and versatility of digital signal processing boards. PCIe boards, based on the PCIe specification, are easy to integrate into CPU servers, achieving high-speed data transmission with the CPU through the high-bandwidth PCIe bus. Systems based on the PCIe bus offer strong hardware reconfigurability and software programmability, enabling their widespread application in various high-speed signal processing fields.

[0003] Therefore, it is necessary to develop a high-performance PCIe digital signal processing board. Summary of the Invention

[0004] In view of this, the present invention provides a PCIE high-performance digital signal processing board that can realize functions such as high-speed data processing, large-capacity high-speed data caching, and high-speed data transmission.

[0005] The technical solution for implementing the present invention is as follows: A PCIE high-performance digital signal processing board includes 4 DSP chips, 40 DDR3 SDDRAM chips, 5 SPI Flash chips, 4 NAND Flash chips, 1 GBE PHY chip, 1 FPGA chip, 5 temperature monitoring chips, 1 optical fiber module, and external physical interfaces.

[0006] Each DSP chip has four external DDR3 SDRAM chips, which are used to cache the data in the DSP chip.

[0007] Each DSP chip has an external SPI Flash chip, which is used to store the DSP program in the DSP chip.

[0008] Each DSP chip has an external NAND Flash chip, which is used to store the data in the DSP chip.

[0009] The four DSP chips are divided into two groups, with two DSP chips in each group interconnected via Hyperlink and PCIe.

[0010] Each DSP chip has one SRIO interface and one UART interface, both of which are interconnected with the FPGA.

[0011] The FPGA chip is interconnected with the GBE PHY chip via the SGMII interface, and the GBE PHY chip on the panel provides a Gigabit Ethernet port via the RJ45 interface.

[0012] The FPGA chip is interconnected with the fiber optic module via GTH to achieve a 1x fiber optic interface.

[0013] The FPGA chip is connected to three sets of 8GB DDR3 SDRAM chips, each set of 8GB DDR3 SDRAM chips consisting of eight 8-bit wide, 8Gb capacity DDR3 SDRAM chips.

[0014] An external SPI Flash chip is connected to the FPGA chip. The SPI Flash chip is used to load the FPGA program.

[0015] The FPGA chip is connected to the gold fingers via 8x GTH to realize an 8x PCIe 3.0 interface.

[0016] Five external temperature monitoring chips are connected to the FPGA chip to achieve temperature monitoring of one FPGA and four DSP chips.

[0017] Preferably, the DSP chip selected is the TMS320C6678 DSP; the DDR3 SDDRAM chip includes two models: the DDR3 SDDRAM chip externally connected to the DSP chip is a 16-bit wide DDR3 SDRAM, model SCB15H8G162BF-13KI; the DDR3 SDDRAM chip connected to the FPGA chip is an 8-bit wide DDR3 SDRAM, model SCB15H8G802BF-11MI. The SPI Flash chip is model MT25QU01GBBB8ESF-0SIT. The NAND Flash chip is model S34MS16G202BHI000. The GBE PHY chip is model 88E1111-B2-BAB2I000. The FPGA chip is model XC7VX690T-2FFG1927I. The temperature monitoring chip is model DS18B20U. The fiber optic module selected is model HTS8502-LH-003XX. External physical interfaces include one RJ45 interface and one J30J-21ZKW-J interface. The J30J-21ZKW-J interface defines DSP JTAG signals, FPGA JTAG signals, and RS232 signals for board debugging and program updates.

[0018] Beneficial effects:

[0019] 1. The PCIe high-performance digital signal processing board disclosed in this invention includes 4 DSPs, 40 DDR3 SDDRAMs, 5 SPI Flash chips, 4 NAND Flash chips, 1 GBE PHY chip, 1 FPGA, 5 temperature monitoring chips, 1 fiber optic module, and external physical interfaces; this invention can realize functions such as high-speed data processing, large-capacity high-speed data caching, and high-speed data transmission.

[0020] 2. The PCIE high-performance digital signal processing board disclosed in this invention uses four TMS320C6678 DSPs. Each DSP has eight cores with a core clock speed of up to 1.4 GHz. The theoretical processing capability of each DSP is 358.4 GMAC fixed-point operations per second or 179.2 GFLOP floating-point operations per second, achieving high-speed data processing capabilities. The FPGA (model XC7VX690T-2FFG1927I) has 3600 DSP slices and also possesses very powerful processing capabilities.

[0021] 3. The PCIe high-performance digital signal processing board disclosed in this invention has a large-capacity, high-speed data cache capability. Each DSP is externally connected to four 1GB DDR3 SDRAM chips, achieving a 4GB large-capacity data cache capability. The DDR3 interface of each DSP has a speed of 1.6Gbps and a bit width of 64bits, with a theoretical access bandwidth of 12.8GB / s, resulting in very high memory access speed. The FPGA is externally connected to three sets of DDR3 SDRAM; each set contains eight 1GB DDR3 SDRAM chips, achieving an 8GB large-capacity data cache capability. Each set of DDR3 SDRAM has a speed of 1.8Gbps and a bit width of 64bits, with a theoretical access bandwidth of 14.4GB / s, also resulting in very high memory access speed.

[0022] 4. The PCIE high-performance digital signal processing board disclosed in this invention has high-speed data transmission capabilities. The FPGA implements an 8x PCIE 3.0 interface on the PCIE gold finger connector. The PCIE 3.0 interface operates in 8Gbound full-duplex mode, which can theoretically achieve a transmission rate of 64Gbound. The FPGA is interconnected with the fiber optic module through GTH to implement a 1x fiber optic interface, which can theoretically achieve a transmission rate of 10Gbps. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the digital signal processing board of the present invention. Detailed Implementation

[0024] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0025] This invention uses DSP, FPGA, and high-capacity DDR3 SDRAM to build a high-performance PCIe digital signal processing board, which realizes functions such as high-speed data processing, high-capacity high-speed data caching, and high-speed data transmission.

[0026] Specifically, a PCIe high-performance digital signal processing board includes 4 DSP chips, 40 DDR3 SDDRAM chips, 5 SPI Flash chips, 4 NAND Flash chips, 1 GBE PHY chip, 1 FPGA chip, 5 temperature monitoring chips, 1 fiber optic module, and external physical interfaces.

[0027] Each DSP chip has four external DDR3 SDRAM chips, which are used to cache the data in the DSP chip.

[0028] Each DSP chip has an external SPI Flash chip, which is used to store the DSP program in the DSP chip.

[0029] Each DSP chip has an external NAND Flash chip, which is used to store the data in the DSP chip.

[0030] The four DSP chips are divided into two groups, with two DSP chips in each group interconnected via Hyperlink and PCIe.

[0031] Each DSP chip has one SRIO interface and one UART interface, both of which are interconnected with the FPGA.

[0032] The FPGA chip is interconnected with the GBE PHY chip via the SGMII interface, and the GBE PHY chip on the panel provides a Gigabit Ethernet port via the RJ45 interface.

[0033] The FPGA chip is interconnected with the fiber optic module via GTH to achieve a 1x fiber optic interface.

[0034] The FPGA chip is connected to three sets of 8GB DDR3 SDRAM chips, each set of 8GB DDR3 SDRAM chips consisting of eight 8-bit wide, 8Gb capacity DDR3 SDRAM chips.

[0035] An external SPI Flash chip is connected to the FPGA chip. The SPI Flash chip is used to load the FPGA program.

[0036] The FPGA chip is connected to the gold fingers via 8x GTH to realize an 8x PCIe 3.0 interface.

[0037] Five external temperature monitoring chips are connected to the FPGA chip to achieve temperature monitoring of one FPGA and four DSP chips.

[0038] In one embodiment of the present invention, the board structure is as follows: Figure 1 As shown, it mainly consists of four TI TMS320C6678 DSPs, 16 16-bit DDR3 SDRAMs (model SCB15H8G162BF-13KI) from Xi'an Unisplendour Corporation, 24 8-bit DDR3 SDRAMs (model SCB15H8G802BF-11MI) from Xi'an Unisplendour Corporation, five Micron SPI Flash chips (model MT25QU01GBBB8ESF-0SIT), four Cypress NAND Flash chips (model S34MS16G202BHI000), and one Marvell GBE chip. The system consists of a PHY chip (model 88E1111-B2-BAB2I000), a Xilinx V7 series FPGA (model XC7VX690T-2FFG1927I), five Maxim Integrated DS18B20U temperature monitoring chips, a AVIC Hisense fiber optic module (model HTS8502-LH-003XX), and external physical interfaces (one RJ45 interface and one J30J-21ZKW-J interface, with DSP JTAG, FPGA JTAG, and RS232 signals defined on the J30J-21ZKW-J) and other auxiliary circuits. Its software mainly includes: GBE data transmission, SRIO data transmission, PCIE data transmission, Hyperlink data transmission, DDR3 SDRAM memory access, NAND Flash memory access, SPI Flash memory access, and temperature monitoring chip data reading; board type: PCIE full height length 250mm; operating platform: server computer platform.

[0039] The high-speed data processing, large-capacity high-speed data caching, and high-speed data transmission functions of this invention are achieved through the following technical solutions:

[0040] To achieve high-speed data processing capabilities, four TI TMS320C6678 DSPs are used. These DSPs have eight cores with a core clock speed of up to 1.4 GHz, and each DSP has a theoretical processing capacity of 358.4 GMAC fixed-point operations per second or 179.2 GFLOP floating-point operations per second. The FPGA (model XC7VX690T-2FFG1927I) has 3600 DSP slices and also possesses very powerful processing capabilities.

[0041] To achieve high-capacity, high-speed data caching capabilities, each DSP is externally connected to four 1GB DDR3 SDRAM chips, enabling a 4GB data cache. Each DSP has a DDR3 interface speed of 1.6Gbps and a 64-bit bus width, with a theoretical access bandwidth of 12.8GB / s, resulting in extremely high memory access speeds. The FPGA is externally connected to three sets of DDR3 SDRAM; each set contains eight 1GB DDR3 SDRAM chips, enabling an 8GB data cache. Each DDR3 interface has a speed of 1.8Gbps and a 64-bit bus width, with a theoretical access bandwidth of 14.4GB / s, also resulting in extremely high memory access speeds.

[0042] To achieve high-speed data transmission, the FPGA implements an 8x PCIe 3.0 interface on the PCIe gold finger connector. The PCIe 3.0 interface operates in 8Gbound full-duplex mode, which can theoretically achieve a transmission rate of 64Gbound. The FPGA is interconnected with the fiber optic module through GTH to implement a 1x fiber optic interface, which can theoretically achieve a transmission rate of 10Gbps.

[0043] This invention constructs a high-performance digital signal processing board on a PCIe full-height board using the following hardware structure: Four TI TMS320C6678 DSPs are used to implement high-performance digital signal processing functions; each TMS320C6678 DSP is externally connected to a Micron SPI Flash chip (model MT25QU01GBBB8ESF-0SIT) for storing DSP programs; each TMS320C6678 DSP is externally connected to a Cypress NAND Flash chip (model S34MS16G202BHI000) for large-capacity data storage; to achieve high-speed data transmission capabilities, the four DSPs are divided into two groups, interconnected by Hyperlink and PCIe, with theoretical transmission bandwidths of 5GB / s and 1GB / s respectively; each DSP is interconnected with the FPGA through a 4x SRIO interface, which operates in 5Gbound full-duplex mode with a theoretical transmission bandwidth of 2GB / s. The FPGA (model XCKU035-1FBVA676FBGA) interconnects with the GBE PHY chip (model 88E1111-B2-BAB2I000) via an SGMII interface. A Gigabit Ethernet port is output via a front panel RJ45 port. The FPGA implements an 8x PCIe 3.0 interface on the PCIe gold finger connector. The PCIe 3.0 interface operates in 8Gb / s full-duplex mode, theoretically achieving a transmission rate of 64Gb / s. The FPGA interconnects with the fiber optic module via a GTH, implementing a 1x fiber optic interface, theoretically achieving a transmission rate of 10Gbps. The J30J-21ZKW-J interface on the front panel defines DSP JTAG signals, FPGA JTAG signals, and RS232 signals for board debugging and program updates.

[0044] In summary, the above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A PCIe high-performance digital signal processing board, characterized in that, It includes 4 DSP chips, 40 DDR3 SDRAM chips, 5 SPI Flash chips, 4 NAND Flash chips, 1 GBE PHY chip, 1 FPGA chip, 5 temperature monitoring chips, 1 fiber optic module, and external physical interfaces; Each DSP chip is externally connected to four DDR3 SDRAM chips, which are used to cache the data in the DSP chip; Each DSP chip is connected to an external SPI Flash chip, which is used to store the DSP program in the DSP chip; Each DSP chip is connected to an external NAND Flash chip, which is used to store data in the DSP chip; The four DSP chips are divided into two groups, with two DSP chips in each group interconnected via Hyperlink and PCIe. Each DSP chip has one SRIO interface and one UART interface, both of which are interconnected with the FPGA; The FPGA chip is interconnected with the GBE PHY chip through the SGMII interface, and the GBE PHY chip on the panel implements a gigabit Ethernet port through the RJ45 interface. The FPGA chip is interconnected with the fiber optic module via GTH to realize a 1x fiber optic interface; The FPGA chip is externally connected to three groups of 8GB DDR3 SDRAM chips, each group of 8GB DDR3 SDRAM chips including eight 8-bit wide and 8GB capacity DDR3 SDRAM chips. The FPGA chip is externally connected to an SPI Flash chip, which is used for loading the FPGA program; The FPGA chip is connected to the gold fingers via 8x GTH to realize an 8x PCIe 3.0 interface; The FPGA chip is connected to five external temperature monitoring chips, enabling temperature monitoring of one FPGA and four DSP chips.

2. The PCIe high-performance digital signal processing board as described in claim 1, characterized in that, The DSP chip selected is the TMS320C6678 DSP. The DDR3 SDRAM chip includes two models: the DDR3 SDRAM chip connected to the DSP chip is a 16-bit wide DDR3 SDRAM, model SCB15H8G162BF-13KI; the DDR3 SDRAM chip connected to the FPGA chip is an 8-bit wide DDR3 SDRAM, model SCB15H8G802BF-11MI. The selected SPI Flash chip is model MT25QU01GBBB8ESF-0SIT. The NAND Flash chip selected is model S34MS16G202BHI000; The selected GBE PHY chip is model 88E1111-B2-BAB2I000; The FPGA chip selected is model XC7VX690T-2FFG1927I; The temperature monitoring chip used is model DS18B20U; The fiber optic module selected is model HTS8502-LH-003XX; The external physical interfaces include one RJ45 interface and one J30J-21ZKW-J interface. The J30J-21ZKW-J interface defines DSP JTAG signals, FPGA JTAG signals and RS232 signals for board debugging and program updates.

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