Method and system for mapping memory models to on-chip memories of fpga

Abstract

The application discloses a method and system for mapping a memory model to an FPGA on-chip memory, the method comprising: identifying a two-dimensional array describing a memory from a hardware description language, identifying parameters of the memory and generating an instantiated memory module; selecting a corresponding specification FPGA according to the parameters of the memory and reconstructing a memory IP of the same specification using an FPGA on-chip memory primitive; instantiating the reconstructed memory IP and replacing the instantiated memory module. The method for mapping a memory model of a hardware description language to an FPGA on-chip memory can solve the technical problem that a memory model of a hardware description language cannot be mapped to an FPGA on-chip memory.

Description

Technical Field

[0001] This invention relates to the field of chip simulation design, and in particular to a method and system for mapping a memory model of a hardware description language to the on-chip memory of an FPGA. Background Technology

[0002] The IC chip industry is developing rapidly. To verify the proper functioning of chips, chip simulation verification is typically required in the early stages of chip development. When the chip is large-scale, pure software simulation can be very time-consuming. Using chip simulation accelerators can significantly shorten the simulation verification time. Chip simulation accelerators implement synthesizable code to run on FPGAs, greatly improving simulation speed, or they can directly use FPGAs for prototyping verification. Thanks to the powerful parallel computing capabilities of FPGAs, FPGA-based chip simulation accelerators or chip prototyping systems can greatly improve the speed of chip simulation verification.

[0003] In chip simulation acceleration and prototype verification systems, the traditional method of mapping RTL memory models to FPGA on-chip memory is to directly compile and generate them using EDA tools provided by the FPGA manufacturer. This method has the following drawbacks:

[0004] Multi-port read / write memory cannot be mapped to the FPGA on-chip memory; it can only be implemented using lookup tables or registers.

[0005] Asynchronous memory cannot be mapped to the FPGA's on-chip memory; it can only be implemented using lookup tables or registers.

[0006] When the design to be tested and verified is large in scale, there is uncertainty in mapping to FPGA resources.

[0007] When RTL memory cannot be mapped to FPGA on-chip memory, it consumes very limited and valuable FPGA lookup table or register resources, becoming a bottleneck in chip simulation acceleration and prototype verification systems, leading to compilation errors and verification failures. Therefore, how to provide a way to map RTL memory models to FPGA on-chip memory systems is a problem that the industry urgently needs to solve. Summary of the Invention

[0008] The purpose of this invention is to address the technical problem that memory models of some types of hardware description languages ​​in the prior art cannot be mapped to the on-chip memory of FPGAs. This invention proposes a method and system for mapping the memory models of hardware description languages ​​to the on-chip memory of FPGAs.

[0009] In this embodiment of the invention, a method for mapping a memory model of a hardware description language to on-chip memory of an FPGA is provided, comprising:

[0010] Identify the two-dimensional array describing the memory from the hardware description language, identify the parameters of the memory, and generate instantiated memory modules;

[0011] Select an FPGA of the appropriate specifications based on the memory parameters and reconstruct a memory IP of the same specifications using FPGA on-chip memory primitives.

[0012] The reconstructed memory IP is instantiated, and the instantiated memory module is replaced.

[0013] In this embodiment of the invention, the parameters of the memory include data width, address depth, read / write mode, and number of ports.

[0014] In this embodiment of the invention, selecting an FPGA of appropriate specifications based on the memory parameters and reconstructing a memory IP of the same specifications using FPGA on-chip memory primitives further includes:

[0015] Based on the number of ports of the identified memory, a fast clock is used to convert the multi-port parallel processing of the identified memory into single-port serial processing to adapt to the FPGA on-chip memory primitive interface.

[0016] In this embodiment of the invention, selecting an FPGA of appropriate specifications based on the memory parameters and reconstructing a memory IP of the same specifications using FPGA on-chip memory primitives further includes:

[0017] The memory is equivalently processed based on its read / write mode, and converted into a synchronous read / write mode for synthesizable FPGA on-chip memory.

[0018] In this embodiment of the invention, instantiating the reconstructed memory IP and replacing the instantiated memory module includes:

[0019] When instantiating the reconstructed memory IP, connect its internally added fast clock port to the system fast clock.

[0020] The write data, write address, and write enable ports are respectively connected to the write-side signals of the instantiated memory module;

[0021] The read data, read address, and read enable ports are also connected to the read-side signals of the instantiated memory module.

[0022] In this embodiment of the invention, a system for mapping a memory model of a hardware description language to on-chip memory of an FPGA is also provided, comprising:

[0023] The memory identification module is used to identify the two-dimensional array describing the memory from the hardware description language, identify the parameters of the memory, and generate an instantiated memory module.

[0024] The memory IP reconfiguration module is used to select an FPGA of the appropriate specifications based on the memory parameters and reconfigure a memory IP of the same specifications using the FPGA's on-chip memory primitives.

[0025] A memory replacement module is used to instantiate the reconstructed memory IP and replace the instantiated memory module.

[0026] In this embodiment of the invention, the parameters of the memory include data width, address depth, read / write mode, and number of ports.

[0027] In this embodiment of the invention, the memory IP reconfiguration module is further configured to convert the multi-port parallel processing of the identified memory into single-port serial processing using a fast clock, based on the number of ports of the identified memory, in order to adapt to the FPGA on-chip memory primitive interface.

[0028] In this embodiment of the invention, the memory IP reconfiguration module is further configured to perform equivalent processing on the memory according to the memory's read / write mode, converting it into a synchronous read / write mode of the synthesizable FPGA on-chip memory.

[0029] In this embodiment of the invention, the memory replacement module instantiates the reconstructed memory IP and replaces the instantiated memory module, including:

[0030] When instantiating the reconstructed memory IP, connect its internally added fast clock port to the system fast clock.

[0031] The write data, write address, and write enable ports are respectively connected to the write-side signals of the instantiated memory module;

[0032] The read data, read address, and read enable ports are also connected to the read-side signals of the instantiated memory module.

[0033] Compared with existing technologies, the method and system of the present invention for mapping the memory model of a hardware description language to the on-chip memory of an FPGA can automatically convert the memory model of a hardware description language into the on-chip memory of an FPGA, greatly reducing the use of FPGA lookup tables and register resources, thereby solving the technical problem that the memory models of some types of hardware description languages ​​cannot be mapped to the on-chip memory of an FPGA during chip simulation accelerators and prototype verification processes. Attached Figure Description

[0034] Figure 1 This is a flowchart of a method for mapping a memory model of a hardware description language to on-chip memory of an FPGA, according to an embodiment of the present invention.

[0035] Figure 2This is a schematic diagram of the system structure of the hardware description language memory model mapped to the FPGA on-chip memory according to an embodiment of the present invention. Detailed Implementation

[0036] like Figure 1 As shown in the figure, this embodiment of the invention provides a method for mapping a memory model of a hardware description language to the on-chip memory of an FPGA, which includes steps S1-S3. These are described below.

[0037] Step S1: Identify the two-dimensional array describing the memory from the hardware description language, identify the parameters of the memory, and generate an instantiated memory module.

[0038] It should be noted that integrated circuit hardware description languages ​​typically use RTL source code. Within the RTL source code, a two-dimensional array signal `user_memory` is defined to describe the memory. Write-side access signals consist of write clock, write data, write address, and write enable; read-side access signals consist of read clock, read data, read address, and read enable. In this embodiment of the invention, the user RTL source code is refined, the two-dimensional array `user_memory` is identified, relevant parameters are extracted, and corresponding instantiated memory modules are created. The write-side and read-side ports of the instantiated memory modules are fixed. The parameters of the memory include data width, address depth, read / write mode, and number of ports.

[0039] Step S2: Select an FPGA of the appropriate specifications according to the memory parameters and reconstruct the memory IP of the same specifications using the FPGA on-chip memory primitives.

[0040] It should be noted that FPGA on-chip memory mainly includes LUTRAM and BRAM. LUTRAM is characterized by its large quantity and high speed, but its overall capacity is relatively small, making it suitable for small-capacity memory. BRAM is block memory, with a minimum unit of 36Kbits or 20Kbits, and its overall capacity is moderate, making it suitable for medium-capacity memory. Here, user memory smaller than 8Kbits is set to LUTRAM, and otherwise to BRAM, thus ensuring that the selected FPGA on-chip memory is compatible with the memory specifications in the hardware description language. To ensure that the reconstructed memory IP is deterministically mapped to LUTRAM or BRAM, the physical portion of the memory needs to be implemented using the manufacturer's primitives.

[0041] Since FPGA on-chip memory typically has only one serial data port, to match the multi-port nature of the original memory, this embodiment of the invention uses a fast clock to convert the multi-port parallel processing of the identified memory into single-port serial processing, based on the identified number of memory ports, to adapt to the FPGA on-chip memory primitive interface. In this embodiment, a time-division multiplexing method is used, introducing a fast clock (fast_clk) to process multi-port memory operations in a time-division multiplexing mode, i.e., converting low-speed multi-port parallel processing into high-speed single-port serial processing. Furthermore, for asynchronous read operations, which require the IP to complete within a single clock cycle, a fast clock is used to achieve synchronous read and write operations on the reconstructed memory IP, achieving the same effect as asynchronous read behavior in the low-frequency clock domain.

[0042] Furthermore, in this step, the memory is equivalently processed according to its read / write mode, converting it into a synchronous read / write mode for synthesizable FPGA on-chip memory. This step requires generating a controller for the reconstructed memory IP. This controller generates fast clock domain signals to control the read and write operations of the reconstructed memory IP, specifically write-side channel control and read-side channel control, with the control methods as follows:

[0043] Write side channel

[0044] 1) Write data, write address, and write enable on each port are all synchronized with the write clock by one clock cycle;

[0045] 2) The rising edge of the slow write clock is extracted from the fast clock of each port and used as the fast clock domain write enable signal;

[0046] 3) Extract the write data corresponding to the effective time of the fast clock domain write enable signal from each port, and use it as the fast clock domain write data signal;

[0047] 4) Extract the write address corresponding to the effective time of the fast clock domain write enable signal for each port, and use it as the fast clock domain write address signal;

[0048] 5) Poll each port to generate fast clock domain serial write enable, write data and write address signals, and connect them to the memory storage entity port.

[0049] Read side channel

[0050] 1) The read enable and read address of each port are registered synchronously with a fast clock for one clock cycle;

[0051] 2) Poll each port to generate fast clock domain serial read enable and read address signal, and connect to the memory storage entity port;

[0052] 3) Generate the corresponding port read ID when polling each port;

[0053] 4) Recover the read data of each port by reading the serial read data of the ID and memory storage entity port.

[0054] Step S3: Instantiate the reconstructed memory IP and replace the instantiated memory module.

[0055] In this embodiment of the invention, instantiating the reconstructed memory IP and replacing the instantiated memory module includes:

[0056] When instantiating the reconstructed memory IP, connect its internally added fast clock port to the system fast clock.

[0057] The write data, write address, and write enable ports are respectively connected to the write-side signals of the instantiated memory module;

[0058] The read data, read address, and read enable ports are also connected to the read-side signals of the instantiated memory module.

[0059] like Figure 2 As shown in the figure, this embodiment of the invention also provides a system for mapping a memory model of a hardware description language to the on-chip memory of an FPGA, which includes a memory identification module 1, a memory IP reconstruction module 2, and a memory replacement module 3. These will be described below.

[0060] The memory identification module 1 is used to identify the two-dimensional array describing the memory from the hardware description language, identify the parameters of the memory, and generate an instantiated memory module. The parameters of the memory include data width, address depth, read / write mode, and number of ports.

[0061] The memory IP reconstruction module 2 is used to select an FPGA of the appropriate specifications according to the memory parameters and reconstruct a memory IP of the same specifications using FPGA on-chip memory primitives. The memory IP reconstruction module 2 is also used to convert the multi-port parallel processing of the identified memory into single-port serial processing using a fast clock, based on the number of ports of the identified memory, to adapt to the FPGA on-chip memory primitive interface. Furthermore, the memory IP reconstruction module 2 is also used to perform equivalent processing based on the memory's read / write mode, converting it into a synchronous read / write mode that can synthesize the FPGA on-chip memory. Specifically, if the memory read / write mode is synchronous, the original clock is first clocked before equivalent processing; if it is asynchronous, no clocking is required, and equivalent processing is performed directly.

[0062] The memory replacement module 3 is used to instantiate the reconstructed memory IP and replace the instantiated memory module.

[0063] In this embodiment of the invention, the memory replacement module 3 instantiates the reconstructed memory IP and replaces the instantiated memory module, including:

[0064] When instantiating the reconstructed memory IP, connect its internally added fast clock port to the system fast clock.

[0065] The write data, write address, and write enable ports are respectively connected to the write-side signals of the instantiated memory module;

[0066] The read data, read address, and read enable ports are also connected to the read-side signals of the instantiated memory module.

[0067] In summary, the method and system of the present invention for mapping the memory model of a hardware description language to the on-chip memory of an FPGA can automatically convert the memory model of a hardware description language into the on-chip memory of an FPGA, greatly reducing the use of FPGA lookup tables and register resources, thereby solving the technical problem that the memory models of some types of hardware description languages ​​cannot be mapped to the on-chip memory of an FPGA during chip simulation accelerators and prototype verification processes.

[0068] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for mapping a memory model to on-chip memory of an FPGA, characterized in that, include: Identify the two-dimensional array describing the memory from the hardware description language, identify the parameters of the memory, and generate instantiated memory modules; Select an FPGA of the appropriate specifications based on the memory parameters and reconstruct a memory IP of the same specifications using FPGA on-chip memory primitives. The reconstructed memory IP is instantiated, and the instantiated memory module is replaced; This includes selecting an FPGA of appropriate specifications based on the memory parameters and reconstructing a memory IP of the same specifications using FPGA on-chip memory primitives, including: Based on the number of ports of the identified memory, a fast clock is used to convert the multi-port parallel processing of the identified memory into single-port serial processing to adapt to the FPGA on-chip memory primitive interface. Based on the memory's read / write mode, perform equivalent processing to convert it into a synchronous read / write mode for synthesizable FPGA on-chip memory. Instantiating the reconstructed memory IP and replacing the instantiated memory module includes: When instantiating the reconstructed memory IP, connect the fast clock port added inside it to the system fast clock of the FPGA on-chip memory. The write data, write address, and write enable ports are respectively connected to the write-side signals of the instantiated memory module; The read data, read address, and read enable ports are also connected to the read-side signals of the instantiated memory module.

2. The method for mapping a memory model to FPGA on-chip memory as described in claim 1, characterized in that, The parameters of the memory include data width, address depth, read / write mode, and number of ports.

3. A system for mapping a memory model to on-chip memory of an FPGA, characterized in that, include: The memory identification module is used to identify the two-dimensional array describing the memory from the hardware description language, identify the parameters of the memory, and generate an instantiated memory module. The memory IP reconfiguration module is used to select an FPGA of appropriate specifications based on the memory parameters and reconfigure a memory IP of the same specifications using FPGA on-chip memory primitives. Specifically, it includes: Based on the number of ports of the identified memory, a fast clock is used to convert the multi-port parallel processing of the identified memory into single-port serial processing to adapt to the primitive interface of the FPGA on-chip memory. Based on the memory's read / write mode, perform equivalent processing to convert it into a synchronous read / write mode for synthesizable FPGA on-chip memory. A memory replacement module, used to instantiate the reconstructed memory IP and replace the instantiated memory module, specifically includes: When instantiating the reconstructed memory IP, connect the fast clock port added inside it to the system fast clock of the FPGA on-chip memory. The write data, write address, and write enable ports are respectively connected to the write-side signals of the instantiated memory module; The read data, read address, and read enable ports are also connected to the read-side signals of the instantiated memory module.

4. The system for mapping a memory model to FPGA on-chip memory as described in claim 3, characterized in that, The parameters of the memory include data width, address depth, read / write mode, and number of ports.

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