A Low-Power Physical Design Layout Method Based on Automatic Linking Scripts

Abstract

This invention discloses a low-power physical design layout method based on an automatic linking script, comprising the following steps: data import; UPF file configuration and import; macro module layout planning; setting switch unit layout scripts; setting automatic linking scripts to reconstruct the logical connections of the main and secondary chains of switch units; and setting power network planning scripts to achieve a specific power network structure and meet the requirements of a turn-off power supply scheme. This invention is applied to the FloorPlan stage of physical design, solving the problem of excessively long connection lines between switch units separated by macro units, resulting in excessive signal transitions, when the FFT module automatically adds switch unit chains using the INNOWUS tool.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a low-power physical design layout method based on an automatic chaining script. Background Technology

[0002] Physical design is a crucial component of integrated circuit design. It translates chip RTL-level code into GDSII layout. The quality of the physical design directly determines whether the chip can meet functional and performance requirements, fulfill fabrication and wafer fabrication needs, and achieve high yield. As system-on-a-chip (SoC) functions become increasingly complex, integration levels rise, and circuit scale expands, chip power consumption has become a growing concern. Low-power physical design has emerged as one solution to overcome the bottleneck of excessive power consumption.

[0003] In the physical implementation of digital back-end, the layout planning of switching units is crucial to achieving a power-off scheme to reduce static power consumption. In specific designs, a large number of such units need to be added to control the power rails. Although EDA tools can automatically add switching units in the design, the effect is often unsatisfactory. Due to the presence of large macrocells in the design, there will be problems such as excessively long connections between switching units separated by macrocells, resulting in excessive transitions. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a low-power physical design layout method based on an automatic chaining script, which features a short design cycle and high optimization efficiency.

[0005] The technical solution of this invention to solve the above-mentioned technical problems is: a low-power physical design layout method based on automatic linking scripts, comprising the following steps:

[0006] (1) Data import; Input files include: synthesized RTL netlist, design constraint file, macro cells, standard cell physical information library and timing library;

[0007] (2) UPF file configuration and import;

[0008] (3) Macro module layout planning; Macro modules are placed based on the INNOVUS tool. According to the macro module type, the principle is to centrally arrange modules of the same type and arrange different types of macro modules according to the data flow. The layout is planned in a regular and symmetrical manner based on the above principles, which facilitates the subsequent layout planning of switch units.

[0009] (4) Set up the switch unit layout script; add a main chain of switch units to the entire core area of ​​the design; add a secondary chain of switch units to the channel area between macro modules;

[0010] (5) Set up an automatic chaining script to realize the logical connection reconstruction of the main chain and sub-chain of the switch unit;

[0011] (6) Set up a power network planning script to realize a specific power network structure and meet the requirements of a power-off scheme.

[0012] In the above-mentioned low-power physical design layout method based on automatic chaining script, in step (1), the library file defines the area, pins, timing, power consumption, and logic function information of each unit involved in the layout and routing stage of physical design.

[0013] In the above-mentioned low-power physical design layout method based on automatic chaining script, in step (2), the UPF file is used to describe the low-power intention in the chip design; power domains are divided. In order to coordinate and control the voltage of each part during circuit design, different power domains are divided for the chip or module. All units in each power domain have the same power supply voltage, and each region is a power domain; power supply ports and power supply networks are defined on the boundary of each power domain. The power supply network runs through the entire power domain to provide power and can pass through multiple power domains to achieve the effect of overlapping. The power supply port is the power supply connection point between two power domains; a power switch is defined. A power switch includes an input power supply network, an output power supply network that can be connected or disconnected, and at least one input control signal; a power state table is described to define the voltage state of each power domain when the chip is working.

[0014] In the above-mentioned low-power physical design layout method based on automatic chaining script, in step (3), macro units are laid out, macro units of the same type are grouped together in modules, and macro units of different types are placed nearby according to the data flow relationship. When placing them, each macro unit follows the principle of vertical alignment and symmetrical placement; a channel with consistent spacing between the upper and lower halves of the module is formed, and the channel is reserved for the addition of the switch unit chain, and the middle of the upper and lower halves is reserved for the placement of standard units.

[0015] In the above-mentioned low-power physical design layout method based on automatic chaining script, the specific content of adding the main chain of switch units to the core area of ​​the design in step (4) is based on the INNOVUS command line to realize the addition of the switch unit chain: the switch unit chain is added by column, using a checkboard layout structure; specify the power domain name; specify the spacing between the bottom and left boundaries of the core area of ​​the design; specify the type of switch unit used; specify the number of rows skipped between two adjacent units; specify the end unit of the connection path; specify the main chain addition order as top to bottom.

[0016] The above-mentioned low-power physical design layout method based on automatic linking script, in step (4), the specific process of adding the switch unit sub-chain in the channel area between macro modules is as follows: two loop bodies are used to add from top to bottom and from bottom to top. The loop body is implemented by the TCL script command foreach. Before executing the loop body, the coordinates of the lower left corner and the upper right corner of the channel area are specified as the variable sram_channels; the initial value of the loop body counter variable sram_count is defined as 0; the specific implementation of the loop body is as follows: the value of the variable sram_channels is indexed by the TCL command lindex, and the index result is obtained. The coordinates ch_llx, ch_lly, ch_urx, and ch_ury are assigned to specify the physical location of the area where the switch units are added. Then, the method of adding the sub-chain is specified, which is also based on the INNOVUS command line. The setting method is roughly the same as that of adding the main chain, except that the sub-chain is added from top to bottom for odd-numbered columns and from bottom to top for even-numbered columns. After the sub-chain is added, the input and output of the first and last switch units are in a floating state. Two physical lines named EnNet_in and EnNet_out are specified for adding to the logical connection between the main chain and the sub-chain.

[0017] In the above-mentioned low-power physical design layout method based on automatic linking script, in step (4), the main chain and the sub-chain are added independently and sequentially, and do not have a holistic logical connection relationship. Therefore, in step (5), the original logical connection relationship of the main chain is interrupted by the automatic linking script and reconnected with the sub-chain. The area that needs to reconstruct the logical relationship is not unique, so a for loop can be used to reconstruct the logical relationship of each area one by one. When reconstructing the logical connection relationship, there are two different situations: the sub-chains in the odd-numbered columns are added from top to bottom, while the sub-chains in the even-numbered columns are added from bottom to top. When reconstructing the logical relationship through the script, an if conditional statement is used to judge the two situations, and then the corresponding interruption and reconnection operations are performed.

[0018] The above-mentioned low-power physical design layout method based on automatic linking scripts, the specific process of step (5) is as follows:

[0019] The automatic string - chain script is used to break and reconnect the original connection relationships among four types of switch units; the following definitions are made for four categories of switch units: the first switch unit of the sub - chain, with the variable name sram_switch_first_cell; the switch unit adjacent to sram_switch_first_cell on the main chain, with the variable name nearcell0; the switch unit connected sequentially to nearcell0 on the main chain, with the variable name near_sram_connect_cell; the switch unit at the end of the sub - chain, with the variable name sram_switch_chain_top; the logical relationship between each sub - chain and the main chain is re - connected in turn using a for loop. The termination judgment variable of the for loop is set as i, with an initial value of 0. When i < sram_count, i is incremented by 1 and the loop body is executed until the judgment condition is not satisfied. sram_count is the counting variable of the channels between macro - modules; set the content of the script loop body:

[0020] (5 - 1) Obtaining sram_switch_first_cell: [get_attribute [get_cells – of_obejects [all_connected EnNet_in] full_name] to obtain the unit name connected to the physical wire EnNet_in, which is sram_switch_first_cell; use the dbGet command to obtain the position coordinate variables loc_x and loc_y of the unit;

[0021] (5-2) Obtaining nearcell0: A rectangular region {box_llx, box_lly, box_upx, box_upy} is determined by an algorithm; the value of box_llx is [expr(loc_x-a)*1000]; the value of box_lly is [expr(loc_x-b)*1000]; the value of box_upx is [expr(loc_x-c)*1000]; the value of box_upy is [expr(loc_x-d)*1000]; the algorithm's core idea is to calculate the coordinates of a rectangular region using the coordinates of {loc_x, loc_y} as a reference point. loc_x and loc_y are offset upwards and downwards, and left and right by the given variables a, b, c, and d, respectively. The values ​​of variables a, b, c, and d are determined based on the current distribution of the switching units. To determine the specific values, a and c are the horizontal offset values; choose appropriate values. Since the spacing between adjacent vertical switch units in the actual layout is an integer multiple of the row height, set b and d to integer multiples of the row height. Then, use the dbGet command to obtain the instantiation names of all units within the rectangular area. Next, use the get_cells--filter "full_name=*" command (* is a wildcard) to match the instantiation names of the units and filter out the switch units on the adjacent main chain, defining them as the variable pgcells. Since the instantiation names of the units in the variable pgcells may not be unique, use the lindex command to get the first element in the variable pgcells and assign it to the variable nearcell0. Use dbGet to get the y-coordinate of the lower left corner of this element and assign it to the variable loc_y_nearcell0.

[0022] (5-3) Obtaining near_sram_connect_cell: Obtain the instantiation name of the cell logically connected to nearcell0 by using the combined command get_attribute and all_fanout, and mark it as the variable near_sram_connect_cell. Similarly, obtain its lower left y coordinate by dbGet and assign it to the variable loy_y_near_sram_connect_cell.

[0023] (5-4) Obtaining sram_switch_chain_top: A rectangular region {xx1, yy1, xx2, yy2} is obtained through an algorithm. The value of xx1 is [expr(loc_x-e)*1000]; the value of yy1 is [expr(loc_y_near_sram_connet_cell-f)*1000]; the value of xx2 is [expr(loc_x+g)*1000]; the value of yy2 is [expr(loc_y_near_sram_connet_cell+h)*1000]; the instantiation name of the cell within the rectangular region is obtained through the dbGet command, and then sram_switch_chain_top is filtered out using the same method as in (5-3). There are two cases when reconnecting logical relationships. The size of variables loc_y_nearcell0 and loy_y_near_sram_connect_cell is compared using an if conditional statement:

[0024] a.loc_y_nearcell0 <loc_y_near_sram_connect_cell

[0025] In this case, the switch cell chain is an even-numbered column, and the sub-chains are arranged from bottom to top; the variable f is a key value, which is determined according to the actual distribution of near_sram_connect_cell and sram_switch_chain_top in the graphical interface, and the value is defined as an integer multiple of the row between the two types of cells.

[0026] b.loc_y_nearcell0>loc_y_near_sram_connect_cell

[0027] In this case, the switch cell chain is an odd-numbered column, and the secondary chains are arranged from top to bottom; the variable h is a key value, which is determined according to the actual distribution of near_sram_connect_cell and sram_switch_chain_top in the graphical interface, and the value is defined as an integer multiple of the row between the two types of cells;

[0028] (5-5) The main chain and adjacent sub-chains are reconnected. The logical connection follows the principle that the HEADOUT1 pin of the upper-level switch unit is connected to the HEADEN1 pin of the lower-level switch unit; the HEADOUT2 pin of the lower-level switch unit is connected to the HEADEN2 pin of the upper-level switch unit.

[0029] (5-6) Use the INNOVUS commands detachTerm and attachTerm to break and reconnect logical relationships according to the principles described in (5-5).

[0030] The beneficial effects of this invention are as follows:

[0031] 1. This invention is applied to the FloorPlan stage of physical design for layout and routing. By supplementing links near macrocells, it realizes the automatic layout and logical connection of switch units in the low-power design of FFT modules. It solves the problem of excessive signal transition (climbing time) caused by excessively long connection between switch units separated by macrocells when the FFT module automatically adds switch unit chains through the INNOWUS tool.

[0032] 2. Reconstructing the logical connection relationships of the switch unit chain using traditional INNAVUS tools via basic commands is time-consuming and lacks versatility. If the FloorPlan changes, this work must be repeated, hindering project progress. This invention solves this problem with an automatic chaining script, reducing workload and avoiding the error-prone risks of mechanically repeating logical connection operations. Furthermore, this method is inheritable and can be extended to suit the specific needs of different projects. Attached Figure Description

[0033] Figure 1 This is a basic flowchart of an embodiment of the present invention.

[0034] Figure 2 This is a schematic diagram of the macro-unit layout method in step 3 of this invention.

[0035] Figure 3 This is a schematic diagram of the main chain addition in step 4 of this invention.

[0036] Figure 4 This is a schematic diagram of the addition of secondary chains and the reconstruction of logical relationships in steps 4 and 5 of this invention. Detailed Implementation

[0037] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0038] like Figure 1 As shown, a low-power physical design layout method based on automatic linking scripts includes the following steps:

[0039] (1) Data import; Input files include: synthesized RTL (Register Transfer Level) netlist, design constraint files, macro cells, standard cell physical information library, and timing library. The library files define the area, pins, timing, power consumption, and logic function information of each cell involved in the placement and routing stage of physical design.

[0040] (2) UPF (United Power Format) file configuration and import; UPF files are used to describe the low-power intentions in chip design; power domain division is performed. In order to coordinate and control the voltage of each part during circuit design, different power domains are divided for the chip or module. All units in each power domain have the same power supply voltage. Each region is a power domain; power supply ports and power supply networks are defined on the boundary of each power domain. The power supply network runs through the entire power domain to provide power and can pass through multiple power domains to achieve the effect of overlapping. The power supply port is the power supply connection point between two power domains; power switches are defined. A power switch includes an input power supply network, an output power supply network that can be connected or disconnected, and at least one input control signal; power state table is described to define the voltage state of each power domain when the chip is working.

[0041] (3) Macro module layout planning; such as Figure 2 As shown, macro modules are aligned vertically and symmetrically according to data interaction relationships, forming channels with consistent spacing between the upper and lower halves of the modules. The blank area in the middle is the standard unit placement area. After completing the macro module placement, since the switch unit is twice the height of a row (row), and the standard unit is once the height of a row, there will be rows with both once and twice the site height in the design. A "fix row" operation is required. Before adding the switch unit chain, the rows automatically created during data import are deleted, and rows with both once and twice the site height are recreated.

[0042] (4) Set up the switch unit layout script; The layout of the switch units in the whole design is divided into two parts. The first is to add the main chain of switch units to the core area of ​​the design. The main chain addition script is based on the engineering command in INNOVUS to make the switch units cover most areas in the design. The second is to add the secondary chain of switch units in the channel area between macro modules to avoid the transition problem and excessive voltage drop caused by insufficient coverage of switch units.

[0043] like Figure 3As shown, add the main chain of switch units. In step (4), the specific content of adding the main chain of switch units to the entire core area of ​​the design is based on the INNOVUS command line to realize the addition of the switch unit chain: the switch unit chain is added by column, using a checkboard layout structure; specify the power domain name; specify the spacing between the bottom and left boundaries of the core area of ​​the design; specify the type of switch unit used; specify the number of adjacent units to skip; specify the end unit of the connection path; specify the order of adding the main chain from top to bottom.

[0044] like Figure 4 As shown, a secondary chain of switching units is added to the channel area between macro modules. The specific script is set up as follows: two loops are used to add switches from top to bottom and from bottom to top. The loops are implemented using the TCL script command `foreach`. Before executing the loops, the coordinates of the lower left and upper right corners of the channel area are specified as the variable `sram_channels`. The initial value of the loop counter variable `sram_count` is defined as 0. The specific implementation of the loops is as follows: the value of the variable `sram_channels` is indexed using the TCL command `lindex`, and the index result is assigned to four coordinate variables `ch_llx`, `ch_lly`, `ch_urx`, and `ch_ury` to specify the physical location of the area where the switch unit is added. Then, the addition method of the sub-chain is specified, which is also based on the INNOVUS command line. The setting method is roughly the same as the main chain addition method. The difference is that for odd-numbered columns, the sub-chain addition order is from top to bottom, while for even-numbered columns, the sub-chain addition order is from bottom to top. After the sub-chain is added, the input and output of the first and last switch units are in a floating state. Two physical connections named `EnNet_in` and `EnNet_out` are specified for logical connection between the main chain and the sub-chain.

[0045] (5) Set up an automatic linking script to realize the logical connection reconstruction of the main chain and sub-chain of the switch unit.

[0046] In step (4), the main chain and the sub-chain are added independently and sequentially, and they are not integrated in terms of logical connection. Therefore, in step (5), the original logical connection of the main chain is broken by the automatic chaining script and reconnected with the sub-chain. The area that needs to be reconstructed in terms of logical relationship is not unique. The logical relationship is reconstructed one by one by using a for loop. When reconstructing the logical connection, there are two different situations. The sub-chains in the odd-numbered columns are added from top to bottom, while the sub-chains in the even-numbered columns are added from bottom to top. When reconstructing the logical relationship through the script, the if conditional statement is used to judge the two situations and then the corresponding break and reconnection operations are performed.

[0047] like Figure 4 As shown, comparison Figure 3 The main chain and the sub-chain have achieved the reconstruction of the logical relationship. The logical connection relationship reconstruction script is used to interrupt and reconnect the original connection relationship between four types of switch units; the following definitions are made for four categories of switch units: the first switch unit of the sub-chain, with the variable name sram_switch_first_cell; the switch unit adjacent to sram_switch_first_cell on the main chain, with the variable name nearcell0; the switch unit sequentially connected to nearcell0 on the main chain, with the variable name near_sram_connect_cell; the switch unit at the end of the sub-chain, with the variable name sram_switch_chain_top; the logical relationship between each sub-chain and the main chain is reconnected in turn by using a for loop. The judgment condition of the for loop is set as the variable i, with an initial value of 0. When i < sram_count, it is incremented by 1 and the loop body is executed until the judgment condition is not satisfied. sram_count is the counting variable of the channels between macro modules; the content of the script loop body is set as follows:

[0048] (5-1) Acquisition of sram_switch_first_cell: [get_attribute [get_cells – of_obejects [all_connected EnNet_in] full_name] to obtain the unit name connected to the physical wire EnNet_in, that is, sram_switch_first_cell; use the dbGet command to obtain the position coordinate variables loc_x and loc_y of the unit;

[0049] (5-2) Obtaining nearcell0: A rectangular region {box_llx, box_lly, box_upx, box_upy} is determined by an algorithm; the value of box_llx is [expr(loc_x-a)*1000]; the value of box_lly is [expr(loc_x-b)*1000]; the value of box_upx is [expr(loc_x-c)*1000]; the value of box_upy is [expr(loc_x-d)*1000]; the algorithm's core idea is to calculate the coordinates of a rectangular region using the coordinates of {loc_x, loc_y} as a reference point. loc_x and loc_y are offset upwards and downwards, and left and right by the given variables a, b, c, and d, respectively. The values ​​of variables a, b, c, and d are specifically determined based on the current distribution of the switching units. a and c are horizontal... Choose an appropriate value for the offset. Since the spacing between adjacent switch units in the actual layout is an integer multiple of the row height, set the values ​​of b and d to integer multiples of the row height. Then, use the dbGet command to obtain the instantiation names of all units within the rectangular area. Then, use the get_cells-filter "full_name=*" command (* is a wildcard, used in conjunction with the instantiation names of switch units in the design) to match the instantiation names of the units and filter out the switch units on the adjacent main chain, defining them as the variable pgcells. Since the instantiation names of the units in the variable pgcells may not be unique, use the lindex command to get the first element in the variable pgcells and assign it to the variable nearcell0. Use dbGet to get the y-coordinate of the lower left corner of this element and assign it to the variable loc_y_nearcell0.

[0050] (5-3) Obtaining near_sram_connect_cell: Obtain the instantiation name of the cell logically connected to nearcell0 by using the combined command get_attribute and all_fanout, and mark it as the variable near_sram_connect_cell. Similarly, obtain its lower left y coordinate by dbGet and assign it to the variable loy_y_near_sram_connect_cell.

[0051] (5-4) Obtaining sram_switch_chain_top: A rectangular region {xx1, yy1, xx2, yy2} is obtained through an algorithm. The value of xx1 is [expr(loc_x-e)*1000]; the value of yy1 is [expr(loc_y_near_sram_connet_cell-f)*1000]; the value of xx2 is [expr(loc_x+g)*1000]; the value of yy2 is [expr(loc_y_near_sram_connet_cell+h)*1000]; the instantiation name of the cell within the rectangular region is obtained through the dbGet command, and then sram_switch_chain_top is filtered out using the same method as in (5-3). There are two cases when reconnecting logical relationships. The size of variables loc_y_nearcell0 and loy_y_near_sram_connect_cell is compared using an if conditional statement:

[0052] a.loc_y_nearcell0 <loc_y_near_sram_connect_cell

[0053] In this case, the switch unit chain is an even-numbered column, and the secondary chains are arranged from bottom to top; the variable f is a key value, which is determined according to the actual distribution of near_sram_connect_cell and sram_switch_chain_top in the graphical interface, and the value is defined as an integer multiple of the row (row) between the two types of units.

[0054] b.loc_y_nearcell0>loc_y_near_sram_connect_cell

[0055] In this case, the switch unit chain is an odd-numbered column, and the secondary chains are arranged from top to bottom; the variable h is a key value, which is determined according to the actual distribution of near_sram_connect_cell and sram_switch_chain_top in the graphical interface, and the value is defined as an integer multiple of the row (row) between the two types of units;

[0056] (5-5) The main chain and adjacent secondary chains are reconnected, such as... Figure 3 The pin connection diagram shows that the logic connection follows the principle that the HEADOUT1 pin of the previous level switch unit is connected to the HEADEN1 pin of the next level switch unit; the HEADOUT2 pin of the next level switch unit is connected to the HEADEN2 pin of the previous level switch unit.

[0057] (5-6) Use the INNOVUS commands detachTerm and attachTerm to break and reconnect logical relationships according to the principles described in (5-5).

[0058] (6) Set up a power network planning script to realize a specific power network structure and meet the requirements of a power-off scheme.

[0059] In step (6), the design uses an 11-layer metal process M1-M11. From layer M11 to layer M6, three types of power strips, namely VDD_FFT, VDD, and VSS, are added sequentially. Among them, VDD_FFT is the power strip under the FFT_PSD power domain, and VDD is the constant power strip. The addition of the M5 power strip is divided into four parts:

[0060] (1) Add VDD_FFT and VSS power bars to the macro module area and mark M5 routing blockage.

[0061] (2) Add a set of VDD_FFT and VSS power strips to each channel between macro modules to ensure the power supply of the standard unit in the middle of the channel;

[0062] (3) Add a VDD power strip to the power pin VDDG of each column of switch unit chains and punch a power hole from M5 to M2.

[0063] (4) Add power rails VDD, VDD_FFT and VSS to the area outside the macro module in sequence; finally, add horizontal power rails M1 and M2 to the entire core area: VDD_FFT and VSS.

Claims

1. A low power physical design layout method based on automatic chaining scripts, characterized by: Comprise the following steps: (1) data import; Input file includes: comprehensive RTL netlist, design constraint file, macro unit, standard unit physical information base and timing library; (2) UPF file configuration and import; (3) macro module layout planning; Based on INNOVUS tool, the macro module is placed, according to the type of macro module, with the same type of module centralized layout, different type of macro module is laid out according to the data flow condition as the principle; On the basis of the above principle, the layout is regular, symmetrical layout planning, which is convenient for the layout planning of switch unit; (4) set switch unit layout script; The core region of the design is added with switch unit main chain; The channel region between macro modules is added with switch unit secondary chain; In step (4), the specific content of adding switch unit main chain to the core region of the design is based on INNOVUS command line, realizing the addition of switch unit chain: the switch unit chain is added by column, adopting checkboard arrangement structure; The power domain name is specified; The distance between the bottom and the left boundary of the core region of the design is specified; The type of switch unit used is specified; The number of row skipped by the upper and lower adjacent two units is specified; The terminal unit of the connection path is specified; The main chain addition sequence is specified from top to bottom; The specific process of adding switch unit secondary chain to the channel region between macro modules is: two loop bodies are used to add from top to bottom and from bottom to top, and the loop body is realized by TCL script command foreach; Before executing the loop body, the lower left corner and the upper right corner coordinates of the channel region are specified as variables sram_channels; The initial value of the loop body counting variable sram_count is defined as 0; The specific implementation of the loop body is as follows: the value of the variable sram_channels is indexed by TCL command lindex, and the indexing result is assigned to four coordinate variables ch_llx, ch_lly, ch_urx and ch_ury, which specify the physical position of the region where the switch unit is added; Then specify the addition mode of the secondary chain, also based on INNOVUS command line, set the addition form, the difference between the setting mode and the main chain addition mode is that when the column is odd, the secondary chain addition sequence is from top to bottom, while the secondary chain in the even column is added from bottom to top; After the secondary chain is added, the input and output of the first and last switch units are in floating state, and two physical connections with line names EnNet_in and EnNet_out are added, which are used for the logical connection of the main chain and the secondary chain; The main chain and the secondary chain are added independently in sequence, and are not integral in logical connection relationship, so the original logical connection relationship of the main chain is broken in step (5) by an automatic string chain script, and is reconnected with the secondary chain; the area requiring logical relationship reconstruction is not unique, and the reconstruction of the logical relationship of each area is realized one by one by a for loop; when the logical connection relationship is reconstructed, there are two different cases, the secondary chain in the odd column is added from top to bottom, and the secondary chain in the even column is added from bottom to top, and when the reconstruction of the logical relationship is realized by a script, an if conditional judgment statement is used to judge the two cases, and then the corresponding breaking and reconnecting operations are performed; (5) setting an automatic string chain script to realize the logical connection reconstruction of the main chain and the secondary chain of the switch unit; (6) setting a power network planning script to realize the power network structure and the requirement of the power-off scheme through the power network planning script.

2. The method of claim 1, wherein: In the step (1), the library file defines the area, pin, timing, power consumption, and logical function information of each unit involved in the layout and routing stage of the physical design.

3. The method of claim 1, wherein: In the step (2), the UPF file is used to describe the low-power intention in the chip design. The power domains are divided, and the circuit is designed to control the voltage of each part as a whole, and different power domains are divided for the chip or module, and the supply voltage of all units in each power domain is consistent, and each region is a power domain; the supply port and the supply network are defined on the boundary of each power domain, the supply network penetrates the entire power domain to provide power, and penetrates multiple power domains to achieve the effect, and the supply port is the connection point of the power supply of two power domains; a power switch is defined, which includes an input supply network, an output supply network connected or cut off, and at least one input control signal; A power state table is described, and the voltage state of each power domain of the chip in operation is defined.

4. The method of claim 1, wherein: In the step (3), the layout of the macro unit is performed, the same type of macro unit is placed in a module, different types of macro units are placed nearby according to the data flow relationship, and each macro unit is placed according to the principle of up-down alignment and symmetrical placement; a channel with consistent spacing between the upper and lower parts of the module is formed, the channel is reserved as an area for adding a switch unit chain, and the middle of the upper and lower parts is reserved as a standard unit placement area.

5. The method of claim 1, wherein: The specific process of the step (5) is: The automatic string script is used to realize the breaking and reconnection of the original connection relationship between the four types of switch units. The following definitions are made for the four categories of switch units: the first switch unit of the secondary chain, the variable name is sram_switch_first_cell; the switch unit adjacent to sram_switch_first_cell on the main chain, the variable name is nearcell0; the switch unit sequentially connected with nearcell0 on the main chain, the variable name is near_sram_connect_cell; the switch unit at the end of the secondary chain, the variable name is sram_switch_chain_top; the for loop is used to realize the reconnection of the logical relationship between each secondary chain and the main chain, the termination judgment variable of the for loop is set as i, the initial value is 0, when i < sram_count, add 1 and execute the loop body until the judgment condition is not met, sram_count is the channel count variable between macro modules; the script loop body content is set as: (5-1) sram_switch_first_cell acquisition: [get_attribute [get_cells – of_obejects [all_connected EnNet_in] full_name] obtains the unit name connected with the physical connection EnNet_in, that is, sram_switch_first_cell; the location coordinate variables loc_x and loc_y of the unit are obtained by using the dbGet command; (5-2) Obtaining nearcell0: A rectangular region {box_llx, box_lly, box_upx, box_upy} is determined by an algorithm; the value of box_llx is [expr (loc_x - a)]. 1000]; The value of box_lly is [expr (loc_x-b)] 1000]; The value of box_upx is [expr (loc_x -c)] 1000]; The value of box_upy is [expr (loc_x-d)] [1000]; The algorithm's core idea is to calculate the coordinates of a rectangular region using the coordinates {loc_x, loc_y} as a reference point. loc_x and loc_y are offset upwards and downwards, and left and right by given variables a, b, c, and d, respectively. The values ​​of variables a, b, c, and d are determined based on the current distribution of the switch cells. a and c are the horizontal offset values; appropriate values ​​can be selected. Since in actual layouts, the interval between adjacent vertical switch cells is an integer multiple of the row height, the values ​​of b and d are set to integer multiples of the row height. Then, the instantiation names of all cells within the rectangular region are obtained using the dbGet command, and then the values ​​are obtained using get_cells –filter "full_name= Command , The wildcard is used to match the instantiation names of the cells and filter out the switch cells on the adjacent main chain, which are defined as variables pgcells. Since the instantiation names of the cells in the variable pgcells may not be unique, the lindex command is used to get the first element in the variable pgcells and assign it to the variable nearcell0. dbGet gets the y-coordinate of the lower left corner of the element and assigns it to the variable loc_y_nearcell0. (5-3) near_sram_connect_cell acquisition: the instantiation name of the unit logically connected with nearcell0 is obtained by the get_attribute and all_fanout combination commands, marked as variable near_sram_connect_cell, similarly, the lower left y coordinate of it is obtained by dbGet, and assigned to variable loc_y_near_sram_connect_cell; (5-4) sram_switch_chain_top: get a rectangle region {xx1, yy1, xx2, yy2} by algorithm, xx1 = [expr (loc_x -e) 1000]; yy1 = [expr (loc_y_near_sram_connet_cell -f) 1000]; xx2 = [expr (loc_x +g) 1000]; yy2 = [expr (loc_y_near_sram_connet_cell +h) 1000]; get the instantiation name of the cell in the rectangle region by dbGet command, and then filter out sram_switch_chain_top in the same way as (5-3). There are two cases when reconnecting the logical relationship, and the if conditional statement is used to compare the size of variables loc_y_nearcell0 and loc_y_near_sram_connect_cell: a. loc_y_nearcell0 < loc_y_near_sram_connect_cell In this case, the switch unit chain is even, and the secondary chain is arranged from bottom to top; variable f is a key value, which is determined according to the actual distribution of near_sram_connect_cell and sram_switch_chain_top in the graphical interface, and the value is defined as an integer multiple of the row distance between the two units; b. loc_y_nearcell0 > loc_y_near_sram_connect_cell In this case, the switch cell chain is an odd number of columns, and the arrangement order of the secondary chain is from top to bottom. The variable h is a key value, which is defined as an integer multiple of the row distance between the two types of cells according to the actual distribution of near_sram_connect_cell and sram_switch_chain_top in the graphical interface. (5-5) The main chain and the adjacent secondary chain are reconnected, and the principle followed by the logical connection is that the HEADOUT1 pin of the upper-level switch cell is connected to the HEADEN1 pin of the lower-level switch cell, and the HEADOUT2 pin of the lower-level switch cell is connected to the HEADEN2 pin of the upper-level switch cell. (5-6) The detachTerm and attachTerm commands of INNOVUS are used to break and reconnect the logical relationship according to the principle described in (5-5).

6. The method of claim 1, wherein: In the step (6), the process M1-M11 of 11 metal layers is used, and the VDD_FFT, VDD and VSS three types of power bars are added from the M11 layer to the M6 layer, wherein the VDD_FFT is the power bar under the FFT_PSD power domain, and the VDD is the normal power bar; the addition of the M5 power bar is divided into four parts: (1) VDD_FFT and VSS power bars are added to the macro module area and marked with the routing blockage of the M5 winding blockage area; (2) A group of VDD_FFT and VSS power bars are added to each channel between the macro modules to ensure the power supply of the standard cells in the middle of the channel; (3) A VDD power bar is added to the power pin VDDG of each column of switch cell chain and marked with the power hole from M5 to M2; (4) The core area outside the macro module is sequentially added with VDD, VDD_FFT and VSS power bars; finally, the M1 and M2 horizontal power rails VDD_FFT and VSS are added to the entire core area.

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