Establishment method of test model, test method and detection device

Abstract

Embodiments of the present application relate to the field of semiconductor testing, and particularly relate to a test model establishing method, a test method and a detection device. The method comprises: providing a semiconductor structure, the semiconductor structure stacking N chip structures, each chip structure comprising: a semiconductor layer and M metal layers stacked on the semiconductor layer; selecting one metal layer from the M metal layers or selecting the semiconductor layer as a preset test layer of the chip structure, and obtaining an interval time of each chip structure based on the preset test layer; obtaining the interval time of the chip structure comprises: applying an excitation signal to the preset test layer, the preset test layer generating an indication signal based on the excitation signal, detecting the indication signal on the top of the semiconductor structure, and obtaining an interval time from applying the excitation signal to detecting the indication signal; taking a frequency of the excitation signal as a first coordinate and the interval time as a second coordinate, establishing a first sub-test image of the chip structure, and integrating the first sub-test image of each chip structure in a test image.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor testing, and in particular to a test model establishing method, a test method and a detection device. BACKGROUND

[0002] With the development of advanced 3D packaging processes (such as Stack process, TSV process, etc.), the number of chips stacked on the same substrate is increasing, the capacity of the memory chip is also increasing, and the speed is also increasing.

[0003] In addition, with the continuous reduction of semiconductor process size, the probability of chip failure caused by defects in devices and manufacturing processes also increases; at the same time, due to the increase in the number of chips stacked on the substrate, it is more and more difficult to locate the defects in the semiconductor device.

[0004] Therefore, a simple and feasible and low-cost defect positioning method is needed to locate the defects in the semiconductor device. SUMMARY

[0005] The embodiments of the present application provide a test model establishing method, a test method and a detection device, which provide a simple, easy-to-use, efficient and convenient defect analysis method for 3D stacked semiconductor chips.

[0006] The embodiments of the present application provide a test model establishing method, which comprises: providing a semiconductor structure, the semiconductor structure is stacked with N chip structures, the chip structure comprises: a semiconductor layer and M metal layers stacked on the semiconductor layer, N and M are both natural numbers greater than or equal to 2; selecting a metal layer from the M metal layers or selecting the semiconductor layer as a preset test layer of the chip structure, the selection mode of the preset test layer of each chip structure is the same, and the interval time of each chip structure is obtained based on the preset test layer; obtaining the interval time of the chip structure comprises: applying an excitation signal to the preset test layer, the preset test layer generates an indication signal based on the excitation signal, detecting the indication signal at the top of the semiconductor structure, and obtaining the interval time from applying the excitation signal to detecting the indication signal; taking the frequency of the excitation signal as a first coordinate and the interval time as a second coordinate, establishing a first sub-test image of the chip structure, and integrating the first sub-test image of each layer of the chip structure in a test image.

[0007] By selecting a preset test layer, the interval time of each chip in the semiconductor structure is obtained, and a sub-test image corresponding to the chip structure is obtained based on the interval time. By integrating the sub-test images corresponding to each chip into a single test image, the test image reflects the interval time required for each chip in the semiconductor structure to generate an indication signal under normal conditions. When using the test image for subsequent judgment, the chip location of the defect in the semiconductor structure can be quickly determined. In addition, the establishment of the test image does not require precise consideration of the thermal parameters of the internal dielectric layer of each chip, the thermal parameters of the dielectric layer between chips, and the thermal parameters of the packaging layer, which is beneficial to industrial production.

[0008] In addition, obtaining the interval time of the chip structure also includes: changing the frequency of the excitation signal to obtain L kinds of adjustment signals at different frequencies, where L is a natural number greater than or equal to 2; based on the adjustment signal at each frequency, obtaining the interval time of each layer of the chip structure at different frequencies. By changing the frequency of the excitation signal, test images at more frequencies can be obtained, improving the accuracy of the established test model.

[0009] In addition, the preset test layer is the semiconductor layer. The semiconductor layer is the bottom layer of the chip structure, indicating that the signal transmission time to the top of the semiconductor structure is the longest, which facilitates subsequent failure localization using the established test model.

[0010] In addition, the preset test layer is the top metal layer in the M-layer metal layer. The top metal layer is the top structure of the chip structure, indicating that the signal transmission time to the top of the semiconductor structure is the shortest, which facilitates subsequent failure localization using the established test model.

[0011] In addition, a first test image and a second test image are acquired. The first test image is acquired based on a preset test layer of a semiconductor layer; the second test image is acquired based on the top metal layer in an M-layer metal layer preset as the test layer. A test image is acquired based on the first test image, the second test image, and corresponding weights for the first and second test images. The test image is obtained by weighting the first and second test images, that is, by combining the weights of the longest and shortest times of the chip structure indication signal, to further ensure the accuracy of the established test model.

[0012] In addition, the time difference between the first reference time and the second reference time is obtained; the first reference time is the interval when the preset test layer is a semiconductor layer; the second reference time is the interval when the preset test layer is the top metal layer in the M-layer metal layer; the first layer number is obtained, which is the number of metal layers between the preset test layer and the semiconductor layer; the second layer number is obtained, which is the number of metal layers between the preset test layer and the top metal layer in the M-layer metal layer; based on the time difference and the ratio of the first layer number to the sum of the first and second layer numbers, the upward range of the test image is obtained; based on the time difference and the ratio of the second layer number to the sum of the first and second layer numbers, the downward range of the test image is obtained. By determining the upward and downward ranges, the range of time required for the indication signal emitted by the chip structure under normal conditions to reach the top of the semiconductor structure is accurately obtained, which facilitates subsequent failure location using the established test model and ensures the accuracy of the established test model.

[0013] In addition, the indication signals include: a thermal signal generated by the preset test layer based on the excitation signal or an optical signal generated by the preset test layer based on the excitation signal.

[0014] This application provides a testing method, comprising: obtaining a test image of a standard semiconductor structure based on the above-described test model establishment method; obtaining a provided semiconductor structure to be tested, and obtaining a detection image of the semiconductor structure to be tested, wherein the detection image is a test image corresponding to the semiconductor structure to be tested obtained based on the above-described test model establishment method; plotting the detection image into the test image, and determining whether there is an anomaly in the semiconductor structure to be tested, and determining the chip structure where the anomaly is located; extracting the chip structure where the anomaly is located, and locating the anomaly location in the chip structure.

[0015] By establishing test images and combining them with the detection images of the semiconductor structure under test, it is possible to quickly determine whether there are defects in the semiconductor structure under test and the chip location of the defects. If there are defects in the semiconductor structure under test, the corresponding defective chip is removed, and the specific location of the defect is located by instruments such as PEM and Thermal. This method is simple, efficient, and convenient, which is beneficial to industrial production.

[0016] Furthermore, the preset test layer used to acquire the test image is the same as the preset test layer used to acquire the inspection image. Both the test image and the inspection image are acquired based on the same preset test layer to ensure the accuracy of subsequent defect location determination.

[0017] In addition, the preset test layer is a semiconductor layer; the detection image is drawn into the test image to determine the chip structure where the abnormal position is located, including: obtaining a first sub-test image in the test image with an interval time less than that of the detection image and the closest to the detection image; the chip structure represented by the first sub-test image is taken as the location of the abnormal position.

[0018] In addition, the preset test layer is the top metal layer in the M-layer metal layer; the detection image is drawn into the test image to determine the chip structure where the abnormal position is located, including: obtaining the first sub-test image in the test image with an interval time greater than that of the detection image and the closest to the detection image; the chip structure represented by the first sub-test image is taken as the location of the abnormal position.

[0019] In addition, the preset test layer is any one of the M metal layers; the upper and lower floating ranges of the test image are obtained; the detection image is drawn into the test image, and the chip structure where the abnormal position is located is determined, including: based on the test image and the upper and lower floating ranges, the interval to which the detection image belongs is determined, and the first sub-test image representing the corresponding interval is obtained based on the interval to which the detection image belongs; the chip structure represented by the first sub-test image is used as the location of the abnormal position.

[0020] Furthermore, the frequency of the excitation signal used to acquire the test image is the same as the frequency of the excitation signal used to acquire the inspection image. Both the test and inspection images are acquired based on the same frequency of excitation signal to ensure the accuracy of subsequent defect location determination.

[0021] This application provides a detection device, comprising: a storage module for storing test images obtained according to the above-described test model establishment method; an excitation module for providing an excitation signal to a semiconductor structure under test; a first detection module for acquiring an indication signal at the top of the semiconductor structure under test; a processing module connected to the excitation module and the first detection module for acquiring the interval time between applying the excitation signal and acquiring the indication signal; an analysis module connected to the storage module and the processing module for determining whether there is an anomaly in the semiconductor structure under test based on the test image and the interval time, and analyzing the chip structure where the anomaly is located in the semiconductor structure under test; an acquisition module connected to the analysis module for acquiring the chip structure where the anomaly is located in the semiconductor structure under test; and a second detection module connected to the acquisition module for locating the anomaly location in the chip structure.

[0022] In addition, the excitation module includes: an excitation unit for providing an excitation signal to the semiconductor structure under test; and a control unit connected to the excitation unit for adjusting the frequency of the excitation signal provided by the excitation unit. Attached Figure Description

[0023] Figure 1 A flowchart illustrating each step in the method for establishing a test model according to an embodiment of this application;

[0024] Figure 2 This is a schematic diagram of a semiconductor structure provided in an embodiment of this application;

[0025] Figure 3A schematic diagram illustrating the principle of obtaining the interval time according to an embodiment of this application;

[0026] Figure 4 A schematic diagram of a test image provided in an embodiment of this application;

[0027] Figure 5 A flowchart illustrating each step in a test method provided in another embodiment of this application;

[0028] Figure 6 This is a schematic diagram of the virtual structure of a testing device provided in another embodiment of this application. Detailed Implementation

[0029] Defects in semiconductor chips often cause short circuits, open circuits, or transistor leakage in a certain area of ​​electrical connection. Devices in this area will generate obvious light and heat signals after the chip is powered on. Based on this, instruments such as PEM and Thermal can be used to locate the location of the defect. However, the above methods cannot determine the depth of the defect on multi-layer stacked chips.

[0030] To address the aforementioned issues, those skilled in the art typically employ a method of artificially creating a defect of known depth within a stacked chip structure, measuring the time it takes for the light and heat signals generated by this defect to reach the surface after passing through each layer of dielectric material, then changing the depth of the defect and measuring the corresponding time again, repeating this process multiple times and making corrections to establish a standard model.

[0031] The applicant found that the process of establishing the standard model requires careful consideration of the thermal parameters of the internal dielectric layer of each chip, the thermal parameters of the dielectric layer between chips and the packaging layer, which makes the modeling difficult and is not conducive to industrial production in terms of cost and time. Therefore, there is an urgent need for a simple, feasible and low-cost defect localization method.

[0032] One embodiment of this application provides a method for establishing a test model, comprising: providing a semiconductor structure, wherein N chip structures are stacked in the semiconductor structure, and the chip structure includes: a semiconductor layer and M metal layers stacked on the semiconductor layer, where N and M are both natural numbers greater than or equal to 2; selecting one metal layer or a semiconductor layer from the M metal layers as a preset test layer of the chip structure, wherein the selection method of the preset test layer is the same for each chip structure; obtaining the interval time of each chip structure based on the preset test layer; obtaining the interval time of the chip structure includes: applying an excitation signal to the preset test layer, wherein the preset test layer generates an indication signal based on the excitation signal, detecting the indication signal at the top of the semiconductor structure, and obtaining the interval time from applying the excitation signal to detecting the indication signal; establishing a first sub-test image of the chip structure with the frequency of the excitation signal as the first coordinate and the interval time as the second coordinate, and integrating the first sub-test image of each chip structure layer into the test image.

[0033] Those skilled in the art will understand that many technical details have been presented in the various embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0034] Figure 1 This is a flowchart illustrating the steps involved in establishing the test model provided in this embodiment. Figure 2 This is a schematic diagram of the semiconductor structure provided in this embodiment. Figure 3 This is a schematic diagram illustrating the principle of obtaining the interval time provided in this embodiment. Figure 4 The following is a schematic diagram of the test image provided in this embodiment. The method for establishing the test model provided in this embodiment will be further described in detail below with reference to the accompanying drawings:

[0035] refer to Figure 1 The methods for establishing the test model include:

[0036] Step S1: Provide a semiconductor substrate and select a preset test layer.

[0037] Specifically, refer to Figure 2 A semiconductor structure 100 is provided, in which N chip structures 200 are stacked. The chip structure 200 includes a semiconductor layer 101 and M metal layers stacked on the semiconductor layer, wherein N and M are both natural numbers greater than or equal to 2.

[0038] It should be noted that, in this embodiment, the semiconductor structure 100 is specifically described using N=4 and M=3 as an example. That is, the semiconductor structure 100 has four chip structures stacked (starting from the substrate 201, from bottom to top, they are chip A1, chip A2, chip A3 and chip A4). In the chip structure, three metal layers are stacked on the semiconductor layer 101 (starting from the semiconductor layer 101, from bottom to top, they are first metal layer 102, second metal layer 103 and third metal layer 104). The interconnection between the metal layers and the interconnection between the metal layers and the semiconductor layer are achieved through the contact portion 105, which does not constitute a limitation of this embodiment. In specific applications, the specific values ​​of N and M are set according to the semiconductor structure to be tested.

[0039] in addition Figure 2 The semiconductor structure shown does not represent the dielectric layer structure and the packaging structure. As those skilled in the art will know, the dielectric layer structure is used to fill the gap between the metal layer and the semiconductor layer 101, and the packaging layer is used to package the semiconductor structure 100.

[0040] After providing the semiconductor structure 100, a metal layer is selected from the M-layer metal layer or the semiconductor layer 101 is selected as the preset test layer of the chip structure 200. For the semiconductor structure 100, the selection method of the preset test layer of each chip structure 200 in the semiconductor structure 100 is the same.

[0041] In one example, the preset test layer can be semiconductor layer 101. Semiconductor layer 101 is the bottom layer of chip structure 200, indicating that the signal transmission time to the top of semiconductor structure 100 is the longest, which facilitates subsequent failure location using the established test model.

[0042] In one example, the preset test layer can be selected as the top metal layer in the M-layer metal layers. The top metal layer is the top structure of the chip structure 200, indicating that the signal transmission time to the top of the semiconductor structure 100 is the shortest, which facilitates subsequent failure location using the established test model.

[0043] Continue to refer to Figure 1 Step S2: Obtain the interval between applying the excitation signal and detecting the indication signal.

[0044] Specifically, the interval time of each chip structure 200 is obtained based on a preset test layer. Obtaining the interval time of the chip structure 200 includes: applying an excitation signal to the preset test layer, the preset test layer generating an indication signal based on the excitation signal, detecting the indication signal on the top of the semiconductor structure 100, and obtaining the interval time from applying the excitation signal to detecting the indication signal.

[0045] The excitation signal and indication signal provided in this embodiment are specifically illustrated using a square wave as an example. (Refer to...) Figure 2 and Figure 3 The preset test layer is provided with an excitation signal of known frequency. When the excitation signal is low, the preset test layer does not work and does not generate an indication signal. When the excitation signal is high, the preset test layer works and generates an indication signal. The indication signal is detected by a detection device located on top of the semiconductor structure 100. At this time, the indication signal emitted by the preset test layer needs a certain transmission time to be transmitted to the semiconductor structure 100. This transmission time is the interval time Δt.

[0046] It should be noted that the use of a square wave as the excitation signal and the indication signal in this embodiment does not constitute a limitation on this embodiment. In other embodiments, the excitation signal can be a signal of any waveform, and the indication signal is generated based on the excitation signal, with a waveform similar to the excitation signal. In this case, the interval time Δt is the time interval between the corresponding rising edges of the excitation signal and the indication signal.

[0047] Continue to refer to Figure 1Step S3: Establish a coordinate system with the frequency of the excitation signal as the first coordinate and the interval time as the second coordinate, and draw a test image of the chip structure.

[0048] Specifically, based on the acquired interval time Δt, the frequency of the excitation signal is used as the first coordinate and the interval time is used as the second coordinate to establish the first sub-test image of the chip structure 200, and the first sub-test image of each layer of the chip structure is integrated into the test image.

[0049] In one example, obtaining the interval time of the chip structure also includes: changing the frequency of the excitation signal, obtaining L adjustment signals at different frequencies, where L is a natural number greater than or equal to 2, and obtaining the interval time of each layer of the chip structure at different frequencies based on the adjustment signal at each frequency. By changing the frequency of the excitation signal, test images at more frequencies can be obtained, improving the accuracy of the established test model.

[0050] After sequentially testing each chip structure 200 in the semiconductor structure 100, the obtained test image reference Figure 4 The principle behind subsequent testing using test images is as follows:

[0051] If the preset test layer is semiconductor layer 100, and the test image is used to characterize the longest interval time Δt of the chip structure, then if the actual test image is located below A1 and above A2, it proves that the defect in semiconductor structure 100 is highly likely to appear in chip A1; if the actual test image is located below A2 and above A3, it proves that the defect in semiconductor structure 100 is highly likely to appear in chip A2; if the actual test image is located below A3 and above A4, it proves that the defect in semiconductor structure 100 is highly likely to appear in chip A3; and if the actual test image is located below A4, it proves that the defect in semiconductor structure 100 is highly likely to appear in chip A4.

[0052] If the preset test layer is the top metal layer in the M-layer metal layer, and the test image is used to characterize the shortest interval time Δt of the chip structure, then if the actual test image is above A1, it proves that the defect in the semiconductor structure 100 is highly likely to appear in chip A1; if the actual test image is below A1 and above A2, it proves that the defect in the semiconductor structure 100 is highly likely to appear in chip A2; if the actual test image is below A2 and above A3, it proves that the defect in the semiconductor structure 100 is highly likely to appear in chip A3; if the actual test image is below A3 and above A4, it proves that the defect in the semiconductor structure 100 is highly likely to appear in chip A4.

[0053] In one example, the two testing methods mentioned above can be combined, namely, to obtain a first test image and a second test image. The first test image is obtained based on the preset test layer being a semiconductor layer, and the second test image is obtained based on the preset test layer being the top metal layer in the M-layer metal layer. That is, the first test image is used to characterize the longest interval time Δt of the chip structure, and the second test image is used to characterize the shortest interval time Δt of the chip structure.

[0054] After acquiring the first and second test images, a test image is obtained based on the first and second test images and their corresponding weights. The test image is obtained by weighting the first and second test images, specifically by combining the weighted sum of the longest and shortest times of the chip structure indication signal, further ensuring the accuracy of the established test model. At this point, the closer the curve of the actual test image is to the curve in the test image, the more likely a defect in the semiconductor structure 100 is to occur in the chip structure 200 corresponding to that curve.

[0055] In another example, if the preset test layer is neither the semiconductor layer 101 nor the top metal layer in the M-layer metal layer, after acquiring the test image, the process further includes: acquiring the time difference between the first reference time and the second reference time, wherein the first reference time is the interval time Δt when the preset test layer is the semiconductor layer, and the second reference time is the interval time Δt when the preset test layer is the top metal layer in the M-layer metal layer; acquiring the first layer number and the second layer number, wherein the first layer number is the number of metal layers between the preset test layer and the semiconductor layer, and the second layer number is the number of metal layers between the preset test layer and the top metal layer in the M-layer metal layer; acquiring the upward range of the test image based on the time difference and the ratio of the first layer number to the sum of the first and second layer numbers, and acquiring the downward range of the test image based on the time difference and the ratio of the second layer number to the sum of the first and second layer numbers. By determining the upward and downward floating ranges, the range of time required for the indicator signal emitted by the chip structure under normal conditions to reach the top of the semiconductor structure can be accurately obtained. This facilitates subsequent failure location using the established test model and ensures the accuracy of the established test model.

[0056] Additionally, it should be noted that in this embodiment, the indication signal includes: a thermal signal generated by the preset test layer based on the excitation signal or an optical signal generated by the preset test layer based on the excitation signal. Using optical or thermal signals as indication signals facilitates continued signal detection using existing equipment, eliminating the need to purchase new equipment and saving costs.

[0057] In addition, it should be noted that in this embodiment, the interval time Δt is used as the test data as the basis for judgment; in other embodiments, phase shift can also be used as the test data as the basis for judgment. The phase shift is the phase difference between the excitation signal and the indication signal, which is actually the same as the content represented by the interval time Δt of the corresponding rising edge. That is, whether the interval time Δt or the phase shift is used as the basis for judgment, it should be within the protection scope of this application.

[0058] By selecting a preset test layer, the interval time of each chip in the semiconductor structure is obtained, and a sub-test image corresponding to the chip structure is obtained based on the interval time. By integrating the sub-test images corresponding to each chip into a single test image, the test image reflects the interval time required for each chip in the semiconductor structure to generate an indication signal under normal conditions. When using the test image for subsequent judgment, the chip location of the defect in the semiconductor structure can be quickly determined. In addition, the establishment of the test image does not require precise consideration of the thermal parameters of the internal dielectric layer of each chip, the thermal parameters of the dielectric layer between chips, and the thermal parameters of the packaging layer, which is beneficial to industrial production.

[0059] The various steps described above are only for clarity. In practice, they can be combined into one step or some steps can be broken down into multiple steps. Adding insignificant modifications or introducing insignificant designs to the process, without changing the core design of the process, are all within the scope of protection of this patent.

[0060] Another embodiment of this application provides a testing method, comprising: acquiring a test image of a standard semiconductor structure based on the above-described test model establishment method; acquiring a provided semiconductor structure to be tested, and acquiring a detection image of the semiconductor structure to be tested, wherein the detection image is a test image corresponding to the semiconductor structure to be tested acquired based on the above-described test model establishment method; plotting the detection image into the test image, and determining whether there is an abnormality in the semiconductor structure to be tested, and determining the chip structure where the abnormality is located; extracting the chip structure where the abnormality is located, and locating the abnormality location in the chip structure.

[0061] It should be noted that the "standard semiconductor structure" mentioned above refers to the semiconductor structure under test without defects.

[0062] Figure 5 The following is a flowchart illustrating each step of the testing method provided in this embodiment. The testing method provided in this embodiment will be further described in detail below with reference to the accompanying drawings:

[0063] refer to Figure 5 Test methods for obtaining abnormal locations in the semiconductor structure under test, including:

[0064] Step S11: Obtain a test image of a standard semiconductor structure.

[0065] Specifically, test images of standard semiconductor structures are obtained based on the test model establishment method provided in the above embodiments.

[0066] Step S12: Obtain the provided semiconductor structure to be tested and obtain the detection image of the semiconductor structure to be tested.

[0067] Specifically, the provided semiconductor structure to be tested is obtained, and a test image of the semiconductor structure to be tested is obtained based on the test model establishment method provided in the above embodiments.

[0068] In one example, a preset test layer is set for acquiring a test image of a standard semiconductor structure, and a preset test layer is set for acquiring an inspection image of the semiconductor structure under test. Both the test image and the inspection image are acquired based on the same preset test layer to ensure the accuracy of subsequent defect location determination.

[0069] In one example, the frequency of the excitation signal used to acquire the test image of the standard semiconductor structure is the same as the frequency of the excitation signal used to acquire the inspection image of the semiconductor structure under test. The test and inspection images are acquired based on the same frequency of excitation signal to ensure the accuracy of subsequent defect location determination.

[0070] Step S13: Draw the detection image into the test image, determine whether there is an abnormality in the semiconductor structure under test, and determine the chip structure where the abnormality is located.

[0071] In one example, the preset test layer is a semiconductor layer. The detection image is drawn into the test image, and the chip structure where the abnormal location is located is determined. This includes: obtaining a first sub-test image in the test image with an interval time less than that of the detection image and the closest to the detection image; and using the chip structure represented by the first sub-test image as the location of the abnormal location.

[0072] In one example, the preset test layer is the top metal layer in the M-layer metal layer. The detection image is drawn into the test image to determine the chip structure where the abnormal location is located, including: obtaining the first sub-test image in the test image with an interval time greater than that of the detection image and the closest to the detection image; and taking the chip structure represented by the first sub-test image as the location of the abnormal location.

[0073] In one example, the preset test layer is any one of the M metal layers. The upper and lower floating ranges of the test image are obtained. The detection image is plotted onto the test image, and the chip structure where the abnormal location is located is determined, including: based on the test image and the upper and lower floating ranges, determining the interval to which the detection image belongs; obtaining the first sub-test image representing the corresponding interval based on the interval to which the detection image belongs; and using the chip structure represented by the first sub-test image as the location of the abnormal location.

[0074] Step S14: Extract the chip structure where the abnormal location is located, and locate the abnormal location in the chip structure.

[0075] Since the depth of the defect has been determined from the multi-layer stacked chip in steps S11 to S12, it is necessary to determine the specific location of the defect after the defective chip is removed. This can be done by using instruments such as PEM and Thermal to locate the location of the defect.

[0076] By establishing test images and combining them with the detection images of the semiconductor structure under test, it is possible to quickly determine whether there are defects in the semiconductor structure under test and the chip location of the defects. If there are defects in the semiconductor structure under test, the corresponding defective chip is removed, and the specific location of the defect is located by instruments such as PEM and Thermal. This method is simple, efficient, and convenient, which is beneficial to industrial production.

[0077] The various steps described above are only for clarity. In practice, they can be combined into one step or some steps can be broken down into multiple steps. Adding insignificant modifications or introducing insignificant designs to the process, without changing the core design of the process, are all within the scope of protection of this patent.

[0078] Since the above embodiments correspond to this embodiment, this embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments remain valid in this embodiment, and the technical effects achievable in the above embodiments can also be achieved in this embodiment. To reduce repetition, they will not be repeated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0079] Another embodiment of this application provides a detection device, comprising: a storage module for storing test images obtained according to the above-described test model establishment method; an excitation module for providing an excitation signal to a semiconductor structure under test; a first detection module for acquiring an indication signal at the top of the semiconductor structure under test; a processing module connected to the excitation module and the first detection module for acquiring the interval time between applying the excitation signal and acquiring the indication signal; an analysis module connected to the storage module and the processing module for determining whether there is an anomaly in the semiconductor structure under test based on the test image and the interval time, and analyzing the chip structure where the anomaly is located in the semiconductor structure under test; an acquisition module connected to the analysis module for acquiring the chip structure where the anomaly is located in the semiconductor structure under test; and a second detection module connected to the acquisition module for locating the anomaly location in the chip structure.

[0080] Figure 6 This is a virtual structural diagram of the detection device provided in this embodiment. The detection device provided in this embodiment will be further described in detail below with reference to the accompanying drawings:

[0081] refer to Figure 6 300 testing devices, including:

[0082] Storage module 305 is used to store the test images obtained by the resume method of the test model provided in the above implementation.

[0083] Excitation module 302 is used to provide excitation signals to the semiconductor structure under test.

[0084] In one example, the excitation module 302 includes an excitation unit (not shown) and a control unit (not shown), wherein the excitation unit is used to provide an excitation signal to the semiconductor structure under test, and the control unit is connected to the excitation unit and is used to adjust the frequency of the excitation signal provided by the excitation unit.

[0085] The first detection module 301 is used to acquire the indication signal on the top of the semiconductor structure under test.

[0086] The processing module 303 is connected to the excitation module 302 and the first detection module 301, and is used to obtain the interval time from applying the excitation signal to obtaining the indication signal.

[0087] The analysis module 304, connected to the storage module 305 and the processing module 303, is used to determine whether the semiconductor structure under test is abnormal based on the test image and the interval time, and to analyze the chip structure where the abnormal position is located in the semiconductor structure under test.

[0088] The acquisition module 306 is connected to the analysis module 304 and is used to acquire the chip structure where the abnormal location is located in the semiconductor structure under test.

[0089] The second detection module 307 is connected to the acquisition module 306 and is used to locate abnormal positions in the chip structure.

[0090] It is worth mentioning that all units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this application; however, this does not mean that other units are absent in this embodiment.

[0091] Since the above embodiments correspond to this embodiment, this embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments remain valid in this embodiment, and the technical effects achievable in the above embodiments can also be achieved in this embodiment. To reduce repetition, they will not be repeated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments. Those skilled in the art will understand that the above embodiments are specific embodiments for implementing this application, and in practical applications, various changes can be made in form and detail without departing from the spirit and scope of this application.

Claims

1. A method for establishing a test model, characterized in that, include: A semiconductor structure is provided, wherein N chip structures are stacked in the semiconductor structure, and the chip structure includes: a semiconductor layer and M metal layers stacked on the semiconductor layer, wherein N and M are both natural numbers greater than or equal to 2; One metal layer or the semiconductor layer is selected from the M-layer metal layer as the preset test layer of the chip structure. The selection method of the preset test layer is the same for each chip structure. The interval time of each chip structure is obtained based on the preset test layer. The interval time for obtaining the chip structure includes: An excitation signal is applied to the preset test layer, the preset test layer generates an indication signal based on the excitation signal, the indication signal is detected on the top of the semiconductor structure, and the interval time from applying the excitation signal to detecting the indication signal is obtained; Using the frequency of the excitation signal as the first coordinate and the interval time as the second coordinate, a first sub-test image of the chip structure is established, and the first sub-test images of each layer of the chip structure are integrated into the test image; Acquire the first test image and the second test image; The first test image was acquired based on the preset test layer being the semiconductor layer; The second test image is obtained based on the top metal layer of the metal layers in the preset test layer M; The test image is obtained based on the first test image, the second test image, and the weights corresponding to the first test image and the second test image; Obtain the time difference between the first reference time and the second reference time; The first reference time is the interval time when the preset test layer is the semiconductor layer; The second reference time is the interval time when the preset test layer is the top metal layer in the M-layer metal layer; Obtain the first layer number, where the first layer number is the number of metal layers between the preset test layer and the semiconductor layer; Obtain the second layer number, which is the number of metal layers between the preset test layer and the top metal layer in the M layer; Based on the time difference and the ratio of the first number of layers to the sum of the first number of layers and the second number of layers, the floating range of the test image is obtained; The floating range of the test image is obtained based on the time difference and the ratio of the second layer number to the sum of the first layer number and the second layer number.

2. The method for establishing a test model according to claim 1, characterized in that, The interval time for acquiring the chip structure further includes: By changing the frequency of the excitation signal, L kinds of adjustment signals with different frequencies are obtained, where L is a natural number greater than or equal to 2; Based on the adjustment signal at each frequency, the interval time of each layer of the chip structure at different frequencies is obtained.

3. The method for establishing a test model according to claim 1, characterized in that, The preset test layer is the semiconductor layer.

4. The method for establishing a test model according to claim 1, characterized in that, The preset test layer is the top metal layer in the M-layer metal layer.

5. The method for establishing a test model according to claim 1, characterized in that, The indication signal includes: a thermal signal generated by the preset test layer based on the excitation signal or an optical signal generated by the preset test layer based on the excitation signal.

6. A testing method for obtaining abnormal locations in a semiconductor structure under test, characterized in that, include: Test images of standard semiconductor structures are obtained based on the method for establishing the test model according to any one of claims 1-5; The provided semiconductor structure to be tested is obtained, and a detection image of the semiconductor structure to be tested is obtained, wherein the detection image is a test image corresponding to the semiconductor structure to be tested obtained based on the method of establishing the test model according to any one of claims 1-5. The detection image is plotted into the test image, and it is determined whether there is an abnormality in the semiconductor structure under test, and the chip structure where the abnormality is located is determined. Extract the chip structure where the abnormal location is located, and locate the abnormal location within the chip structure.

7. The test method according to claim 6, characterized in that, The preset test layer set for acquiring the test image is the same as the preset test layer set for acquiring the detection image.

8. The test method according to claim 7, characterized in that, include: The preset test layer is a semiconductor layer; The step of drawing the detection image into the test image and determining the chip structure where the abnormal location is located includes: obtaining a first sub-test image in the test image whose interval time is less than that of the detection image and which is closest to the detection image; The chip structure characterized by the first sub-test image is used as the location of the abnormal position.

9. The test method according to claim 7, characterized in that, include: The preset test layer is the top metal layer in the M-layer metal layer; The step of drawing the detection image into the test image and determining the chip structure where the abnormal location is located includes: obtaining a first sub-test image in the test image that has an interval time greater than that of the detection image and is closest to the detection image; The chip structure characterized by the first sub-test image is used as the location of the abnormal position.

10. The test method according to claim 7, characterized in that, include: The preset test layer is any one of the M metal layers; Obtain the upward and downward ranges of the test image; The step of plotting the detection image into the test image and determining the chip structure where the abnormal location is located includes: determining the interval to which the detection image belongs based on the test image, the upward range, and the downward range; obtaining a first sub-test image representing the corresponding interval based on the interval to which the detection image belongs; and using the chip structure represented by the first sub-test image as the location of the abnormal location.

11. The test method according to any one of claims 6-10, characterized in that, The frequency of the excitation signal used to acquire the test image is the same as the frequency of the excitation signal used to acquire the detection image.

12. A testing device, characterized in that, include: A storage module is used to store test images obtained by the method for establishing the test model according to any one of claims 1-5; The excitation module is used to provide excitation signals to the semiconductor structure under test. The first detection module is used to acquire the indication signal at the top of the semiconductor structure under test; A processing module, connected to the excitation module and the first detection module, is used to acquire the interval time from applying the excitation signal to acquiring the indication signal; An analysis module, connected to the storage module and the processing module, is used to determine whether there is an anomaly in the semiconductor structure under test based on the test image and the interval time, and to analyze the chip structure where the anomaly is located in the semiconductor structure under test. The acquisition module, connected to the analysis module, is used to acquire the chip structure where the abnormal location is located in the semiconductor structure under test; The second detection module, connected to the acquisition module, is used to locate the abnormal position in the chip structure.

13. The detection device according to claim 12, characterized in that, The incentive module includes: The excitation unit is used to provide excitation signals to the semiconductor structure under test. A control unit, connected to the excitation unit, is used to adjust the frequency of the excitation signal provided by the excitation unit.

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