Nor flash and method of erasing the same

Abstract

The application discloses a Nor flash and an erasing method thereof. The erasing method performs over-erase correction on a first storage part with larger capacity by a first over-erase correction voltage with a lower threshold voltage, and performs over-erase correction on the first storage part with larger capacity by a second over-erase correction voltage with a higher threshold voltage. Since the first over-erase correction voltage is smaller, the first over-erase correction voltage can be reached faster, so that the completion time of over-erase correction is shortened, and the time required for over-erase correction is reduced.

Description

Technical Field

[0001] This application relates to the field of storage technology, specifically to a Nor Flash and its erasure method. Background Technology

[0002] In Nor Flash (or non-flash memory), the same preset voltage is usually used to perform over-erasure correction on each memory section. Since the number of memory cells in different types of memory sections is different, it takes more time to perform over-erasure correction on memory sections with a large number of memory cells.

[0003] Specifically, such as Figure 1 The diagram shows a comparison of different memory sections using the same preset voltage for over-erasure correction in the related technologies shown. The horizontal axis Vt represents the threshold voltage of the memory cell, in volts (V); the vertical axis Bit Count represents the number of memory cells in different memory sections. Curve CVt` represents the normal distribution of the threshold voltage of the memory cells in the entire memory array after over-erasure correction, curve BVt` represents the normal distribution of the threshold voltage of the memory cells in the memory block after over-erasure correction, and curve SVt` represents the normal distribution of the threshold voltage of the memory cells in the sector after over-erasure correction.

[0004] from Figure 1 It can be seen that the number of memory cells in the entire memory array, the number of memory cells in the memory block, and the number of memory cells in the sector decrease sequentially. However, the entire memory array, memory block, and sector all use the same preset voltage for over-erasure correction. This preset voltage is as follows: Figure 1 The intersection of the curves CVt`, BVt`, and SVt` on the horizontal axis Vt will cause the over-erasure correction of the entire memory array or memory block to take a long time. Summary of the Invention

[0005] This application provides a Nor Flash and its erasure method to alleviate the technical problem of excessive time spent on over-erasure correction.

[0006] In a first aspect, this application provides an erasure method for Nor Flash, the erasure method comprising: constructing Nor Flash including a first storage unit and a second storage unit, wherein the number of storage cells in the first storage unit is greater than the number of storage cells in the second storage unit; using a first over-erasure correction voltage as the target voltage for performing over-erasure correction on the first storage unit; and using a second over-erasure correction voltage as the target voltage for performing over-erasure correction on the second storage unit, wherein the second over-erasure correction voltage is greater than the first over-erasure correction voltage.

[0007] In some embodiments, the erasing method further comprises: configuring the Nor Flash to further comprise a third storage part, the number of storage units in the second storage part being greater than the number of storage units in the third storage part; and configuring the second over-erase correction voltage as the target voltage for performing over-erase correction on the third storage part.

[0008] In some embodiments, the erasing method further comprises: configuring the first storage part, the second storage part, and the third storage part to be a full storage array, a storage block, and a sector in sequence, respectively, the full storage array being all storage units in the Nor Flash; configuring the first over-erase correction voltage to be greater than or equal to 80% of a preset voltage and less than the preset voltage; and configuring the second over-erase correction voltage to be greater than the preset voltage and less than or equal to 120% of the preset voltage.

[0009] In some embodiments, the erasing method further comprises: configuring the first storage part, the second storage part, and the third storage part to be a full storage array, a storage block, and a sector in sequence, respectively, the full storage array being all storage units in the Nor Flash; configuring the first over-erase correction voltage to be greater than or equal to 80% of a preset voltage and less than the preset voltage; and configuring the second over-erase correction voltage to be equal to the preset voltage.

[0010] In some embodiments, the erasing method further comprises: configuring the Nor Flash to further comprise a third storage part, the number of storage units in the second storage part being greater than the number of storage units in the third storage part; and configuring the third over-erase correction voltage as the target voltage for performing over-erase correction on the third storage part, the third over-erase correction voltage being greater than the second over-erase correction voltage.

[0011] In some embodiments, the erasing method further comprises: configuring the first storage part, the second storage part, and the third storage part to be a full storage array, a storage block, and a sector in sequence, respectively, the full storage array being all storage units in the Nor Flash; configuring the first over-erase correction voltage to be greater than or equal to 80% of a preset voltage and less than the preset voltage; configuring the second over-erase correction voltage to be equal to the preset voltage; and configuring the third over-erase correction voltage to be greater than the preset voltage and less than or equal to 120% of the preset voltage.

[0012] In a second aspect, the present application provides an erase method of a Nor Flash, the erase method comprising: configuring the Nor Flash to comprise a first storage part, a second storage part and a third storage part, the number of storage units in the first storage part, the number of storage units in the second storage part and the number of storage units in the third storage part decreasing in turn; taking a second over-erase correction voltage as a target voltage for performing over-erase correction on the first storage part; taking a third over-erase correction voltage as a target voltage for performing over-erase correction on the second storage part and the third storage part, the second over-erase correction voltage being greater than the first over-erase correction voltage and less than the third over-erase correction voltage.

[0013] In a third aspect, the present application provides an erase method of a Nor Flash, the erase method comprising: configuring the Nor Flash to comprise a first storage part, a second storage part and a third storage part, the number of storage units in the first storage part, the number of storage units in the second storage part and the number of storage units in the third storage part decreasing in turn; taking a first over-erase correction voltage as a target voltage for performing over-erase correction on the first storage part and the second storage part; taking a third over-erase correction voltage as a target voltage for performing over-erase correction on the third storage part, the second over-erase correction voltage being greater than the first over-erase correction voltage and less than the third over-erase correction voltage, the second over-erase correction voltage being a preset voltage.

[0014] In some embodiments, the erase method further comprises: configuring the first storage part, the second storage part and the third storage part to be a full storage array, a storage block and a sector in turn respectively, the full storage array being all storage units in the Nor Flash.

[0015] In a fourth aspect, the present application provides a Nor Flash, the Nor Flash performing the erase method in at least one of the embodiments described above during over-erase correction.

[0016] The Nor Flash and the erase method thereof provided by the present application perform over-erase correction on the first storage part with a larger capacity by using a first over-erase correction voltage with a lower threshold voltage, which is faster than performing over-erase correction on the first storage part with a larger capacity by using a second over-erase correction voltage with a higher threshold voltage, because the first over-erase correction voltage is smaller, the first over-erase correction voltage can be reached faster, thereby shortening the completion time of over-erase correction, and further reducing the time required for over-erase correction.

[0017] In addition, the Nor Flash and the erasing method thereof provided by the application corrects the over-erase of the first storage unit with a second over-erase correction voltage with a lower threshold voltage, compared with correcting the over-erase of the first storage unit with a third over-erase correction voltage with a higher threshold voltage, since the second over-erase correction voltage is smaller, the second over-erase correction voltage can be reached faster, thereby shortening the completion time of the over-erase correction, and further reducing the time required for the over-erase correction. BRIEF DESCRIPTION OF DRAWINGS

[0018] The technical solutions and other beneficial effects of the application will be apparent from the following detailed description of the specific embodiments of the application, combined with the accompanying drawings.

[0019] Figure 1 A comparison diagram for the over-erase correction of different storage units with the same preset voltage in the related art.

[0020] Figure 2 A structure diagram of the Nor Flash in the related art.

[0021] Figure 3 A flow diagram of the erasing method provided by the embodiment of the application.

[0022] Figure 4 A comparison diagram for the over-erase correction of different storage units with different over-erase correction voltages provided by the embodiment of the application.

[0023] Figure 5 A comparison diagram of the erasing time of the full chip storage array under different over-erase targets provided by the embodiment of the application.

[0024] Figure 6 A comparison diagram of the page programming time under different over-erase targets provided by the embodiment of the application.

[0025] Figure 7 Another comparison diagram of the page programming time under different over-erase targets provided by the embodiment of the application. DETAILED DESCRIPTION

[0026] The technical solutions and other beneficial effects of the application will be apparent from the following detailed description of the specific embodiments of the application, combined with the accompanying drawings.

[0027] Figure 2As shown in FIG. 1, a structure diagram of a Nor Flash in the related art is shown, the Nor Flash includes word lines, bit lines BL0...BLn, a source line SL, and memory cells as shown in the dashed box, wherein the word lines WL0, WL1...WLn are connected with the gates of the corresponding memory cells, the bit lines BL0...BLn are connected with the drains of the corresponding memory cells, the source line SL is connected with the sources of the corresponding memory cells, n is a positive integer, and the number of the word lines can be the same as or different from the number of the bit lines.

[0028] It is found through a large number of researches of the present inventor that, due to the leakage problem of one or more memory cells connected with the same bit line, which will affect the read operation and programming of other memory cells connected with the bit line, in order to reduce the above-mentioned leakage current, the present application adopts an important step in the erasing process, i.e. over-erase correction, to improve the above-mentioned leakage current phenomenon.

[0029] However, through a large number of analyses of the present inventor, it is found that the time spent on over-erase correction increases with the increase of the number of memory cells in the storage part, and the time spent on over-erase correction accounts for a large proportion of the erasing time required in the entire erasing process, especially the over-erase correction time required by the Nor Flash in the initial state (factory state or a state without any erase-write-read cycle) may account for more than 30% of the erasing time.

[0030] Therefore, if the over-erase correction of all memory blocks in the erasing process is all added to the erasing process of the full-chip storage array, it will cause the erasing time of the full-chip storage array to be too long.

[0031] As for the small block such as sector, the number of memory cells requiring over-erase correction is small, and the time impact is small; at the same time, due to the high frequency of erase-write-read cycling of the small block, the leakage current needs to be reduced to a certain level before each erasing, so as not to affect the programming time after the erase-write-read cycling. That is to say, the over-erase correction of the small block needs to reach a relatively high level.

[0032] Based on the above analysis, in order to reduce the over-erase correction time or the erasing time, the present embodiment provides a Nor Flash erasing method, as shown in FIG. 2, the erasing method includes the following steps: Figure 3

[0033] Step S10: constructing the Nor Flash to include a first storage part and a second storage part, the number of memory cells in the first storage part is greater than the number of memory cells in the second storage part.

[0034] Step S20: taking the first over-erase correction voltage as the target voltage for performing over-erase correction on the first storage part.​

[0035] Step S30: taking the second over-erase correction voltage as the target voltage for performing over-erase correction on the second storage part, the second over-erase correction voltage being greater than the first over-erase correction voltage.

[0036] It can be understood that the erasing method provided by the embodiment performs over-erase correction on the first storage part with a larger capacity by using the first over-erase correction voltage with a lower threshold voltage, and compared with performing over-erase correction on the first storage part with a larger capacity by using the second over-erase correction voltage with a higher threshold voltage, the first over-erase correction voltage is smaller, and the first over-erase correction voltage can be reached faster, thereby shortening the completion time of over-erase correction and reducing the time required for over-erase correction.

[0037] It should be noted that in the embodiment, the first storage part can be a full chip storage array, and correspondingly, the second storage part can be a storage block or a sector; or the first storage part can also be a storage block, and correspondingly, the second storage part can be a sector.

[0038] It should be noted that the steps S20 and S30 can be executed in any order, for example, the step S20 can be executed earlier than the step S30, or the step S20 can be executed later than the step S30, or the steps S20 and S30 can also be executed synchronously. The steps S20 and S30 are executed independently.

[0039] It should be noted that in the embodiment, the first storage part and the third storage part with different numbers of storage units are all subjected to over-erase correction by using the first over-erase correction voltage, which also shortens the completion time of over-erase correction and reduces the time required for over-erase correction.

[0040] In one of the embodiments, the erasing method further comprises: constructing the Nor Flash to further include a third storage part, the number of storage units in the second storage part being greater than the number of storage units in the third storage part; and taking the second over-erase correction voltage as the target voltage for performing over-erase correction on the third storage part.

[0041] It should be noted that in the embodiment, the second storage part and the third storage part with different numbers of storage units are all subjected to over-erase correction by using the second over-erase correction voltage, which also shortens the completion time of over-erase correction and reduces the time required for over-erase correction.

[0042] In one of the embodiments, the erasing method further comprises: configuring the first storage unit, the second storage unit and the third storage unit to be a full chip storage array, a storage block and a sector in sequence respectively, and the full chip storage array is all storage units in the Nor Flash; configuring the first over-erase correction voltage to be greater than or equal to 80% of the preset voltage and less than the preset voltage; and configuring the second over-erase correction voltage to be greater than the preset voltage and less than or equal to 120% of the preset voltage.

[0043] It should be noted that, through in-depth research, it is found that configuring the first over-erase correction voltage to be greater than or equal to 80% of the preset voltage and less than the preset voltage can shorten the over-erase correction time or the erasing time of the storage unit with a large number of storage units without affecting the programming time; and configuring the second over-erase correction voltage to be greater than the preset voltage and less than or equal to 120% of the preset voltage is to consider that the frequency of the erase-read-write of the storage unit with a small number of storage units is high, and the leakage current needs to be reduced to a certain level each time the erasing is performed, so that configuring a higher second over-erase correction voltage for the small block can avoid affecting the programming time after the erase-read-write cycle.

[0044] In one of the embodiments, the erasing method further comprises: configuring the first storage unit, the second storage unit and the third storage unit to be a full chip storage array, a storage block and a sector in sequence respectively, and the full chip storage array is all storage units in the Nor Flash; configuring the first over-erase correction voltage to be greater than or equal to 80% of the preset voltage and less than the preset voltage; and configuring the second over-erase correction voltage to be equal to the preset voltage.

[0045] It should be noted that, through in-depth research, it is found that configuring the first over-erase correction voltage to be greater than or equal to 80% of the preset voltage and less than the preset voltage can shorten the over-erase correction time or the erasing time of the storage unit with a large number of storage units without affecting the programming time; and configuring the second over-erase correction voltage to be equal to the preset voltage is to consider that the frequency of the erase-read-write of the storage unit with a small number of storage units is high, and the leakage current needs to be reduced to a certain level each time the erasing is performed, so that configuring a higher second over-erase correction voltage for the small block can avoid affecting the programming time after the erase-read-write cycle.

[0046] In one of the embodiments, the erasing method further comprises: configuring the first over-erase correction voltage to be greater than or equal to 0.8V and less than 1V; and configuring the second over-erase correction voltage to be greater than 1V and less than or equal to 1.2V.

[0047] It should be noted that, after in-depth research, it was found that for Nor Flash with a storage capacity of 64Mb or more, setting the first over-erasure correction voltage to be greater than or equal to 0.8V and less than 1V can shorten the over-erasure correction time or erasure time for memory cells with a large number of storage units without affecting the programming time. Setting the second over-erasure correction voltage to be greater than 1V and less than or equal to 1.2V is because memory cells with a small number of storage units are erased, written, and read frequently. Each erase requires reducing the leakage current to a certain level. Therefore, setting a higher second over-erasure correction voltage for small blocks can avoid affecting the programming time after the erase, write, and read cycle.

[0048] The values ​​of the over-erasure correction voltage in the above embodiments are for illustrative purposes only and are not intended to limit the solution.

[0049] In one embodiment, such as Figure 3 , Figure 4 As shown, the erasure method further includes: constructing a Nor Flash that includes a third storage section, wherein the number of storage cells in the second storage section is greater than the number of storage cells in the third storage section; using a third over-erasure correction voltage as the target voltage for performing over-erasure correction in the third storage section, wherein the third over-erasure correction voltage is greater than the second over-erasure correction voltage.

[0050] It should be noted that in this embodiment, as the storage capacity of the storage unit decreases, the over-erasure correction voltage used is larger. This can not only reduce the over-erasure correction time or erasure time of the storage unit with a larger storage capacity, but also avoid affecting the programming time of the storage unit with a smaller capacity after the erase-write-read cycle, and meet the high-frequency erase-write-read requirements of the storage unit with a smaller capacity.

[0051] Specifically, such as Figure 4 As shown, the horizontal axis Vt represents the threshold voltage of the memory cell, in volts (V); the vertical axis Bit Count represents the number of memory cells in different memory sections. Curve CVt represents the normal distribution of the threshold voltage of the memory cells in the entire memory array after erasure correction; curve BVt represents the normal distribution of the threshold voltage of the memory cells in the memory block after erasure correction; curve SVt represents the normal distribution of the threshold voltage of the memory cells in the sector after erasure correction; and curve AVt represents the normal distribution of the threshold voltage of the corresponding memory cell after erasure but before erasure correction.

[0052] from Figure 4It can be seen that the threshold voltage of the memory cell after erasure and before erasure correction is relatively low, and is less than the over-erasure correction voltage set by any of the curves CVt, BVt, and SVt. Curve CVt uses the smallest first over-erasure correction voltage for the entire memory array with the largest storage capacity, curve BVt uses the second smallest second over-erasure correction voltage for the second largest storage block, and curve SVt uses the largest third over-erasure correction voltage for the smallest sector.

[0053] In one embodiment, the erasure method further includes: constructing a first storage unit, a second storage unit, and a third storage unit, which are respectively a full-chip storage array, a storage block, and a sector, wherein the full-chip storage array comprises all storage cells in the Nor Flash; configuring a first over-erasure correction voltage that is greater than or equal to 80% of a preset voltage and less than a preset voltage; configuring a second over-erasure correction voltage that is equal to the preset voltage; and configuring a third over-erasure correction voltage that is greater than the preset voltage and less than or equal to 120% of the preset voltage.

[0054] It should be noted that, after in-depth research, it has been found that setting more specific over-erasure correction voltages for storage units with different storage capacities is beneficial to shorten the over-erasure correction time or erasure time for storage units with a large number of storage units without affecting the programming time. At the same time, considering that storage units with a small number of storage cells have a high frequency of erase, write, and read operations, and that leakage current needs to be reduced to a certain level for each erase, setting a higher second over-erasure correction voltage for small blocks can also avoid affecting the programming time after the erase, write, and read cycle.

[0055] In one embodiment, the erasure method further includes: constructing a first storage unit, a second storage unit, and a third storage unit, which are respectively a full-chip storage array, a storage block, and a sector, wherein the full-chip storage array comprises all storage cells in the Nor Flash; configuring a first over-erasure correction voltage that is greater than or equal to 80% of a preset voltage and less than a preset voltage; configuring a second over-erasure correction voltage that is greater than or equal to the preset voltage and less than or equal to 110% of the preset voltage; and configuring a third over-erasure correction voltage that is greater than 110% of the preset voltage and less than or equal to 120% of the preset voltage.

[0056] It should be noted that further research has revealed that setting more specific over-erasure correction voltages for storage units with different storage capacities can help to further shorten the over-erasure correction time or erase time for storage units with a large number of storage units without affecting the programming time. At the same time, considering that storage units with a small number of storage cells have a high frequency of erase, write, and read operations, each erase operation needs to reduce the leakage current to a certain level. Therefore, setting a higher second over-erasure correction voltage for small blocks can also further avoid affecting the programming time after the erase, write, and read cycle.

[0057] In one embodiment, the erasure method further includes configuring a preset voltage of 1V.

[0058] It should be noted that, after analyzing the process and design of Nor Flash and conducting numerous experiments, it was found that setting the preset voltage to 1V can better improve the aforementioned issues. Figure 1 , Figure 2 The shortcomings in the analysis.

[0059] The values ​​of the over-erasure correction voltage in the above embodiments are for illustrative purposes only and are not intended to limit the solution.

[0060] In one embodiment, this embodiment provides an erasure method for Nor Flash, the erasure method comprising: constructing Nor Flash including a first storage unit, a second storage unit, and a third storage unit, wherein the number of storage cells in the first storage unit, the number of storage cells in the second storage unit, and the number of storage cells in the third storage unit decrease sequentially; using a second over-erasure correction voltage as the target voltage for over-erasure correction of the first storage unit; and using a third over-erasure correction voltage as the target voltage for over-erasure correction of the second and third storage units, wherein the second over-erasure correction voltage is greater than the first over-erasure correction voltage and less than the third over-erasure correction voltage.

[0061] It is understood that the erasure method provided in this embodiment performs over-erasure correction on the first storage unit with a larger capacity by using a second over-erasure correction voltage with a lower threshold voltage. Compared with performing over-erasure correction on the first storage unit with a larger capacity by using a third over-erasure correction voltage with a higher threshold voltage, the second over-erasure correction voltage is smaller and can be reached more quickly, thereby shortening the completion time of over-erasure correction and reducing the time required for over-erasure correction.

[0062] Furthermore, the second and third storage units use the same target voltage to perform over-erasure correction, which reduces the types of target voltages required for over-erasure correction and helps to simplify the required hardware circuitry.

[0063] In one embodiment, this embodiment provides a method for erasing Nor Flash, the method comprising: constructing Nor Flash including a first storage unit, a second storage unit, and a third storage unit, wherein the number of storage cells in the first storage unit, the number of storage cells in the second storage unit, and the number of storage cells in the third storage unit decrease sequentially; using a first over-erasure correction voltage as the target voltage for over-erasure correction of the first and second storage units; using a third over-erasure correction voltage as the target voltage for over-erasure correction of the third storage unit, wherein the second over-erasure correction voltage is greater than the first over-erasure correction voltage and less than the third over-erasure correction voltage, and the second over-erasure correction voltage is a preset voltage.

[0064] It is understood that the erasure method provided in this embodiment performs over-erasure correction on the first and second storage units with larger capacity using a first over-erasure correction voltage with a lower threshold voltage. Compared with performing over-erasure correction on the third storage unit with smaller capacity using a third over-erasure correction voltage with a higher threshold voltage, the first over-erasure correction voltage is smaller and can be reached more quickly, thereby shortening the completion time of over-erasure correction and reducing the time required for over-erasure correction.

[0065] In one embodiment, the erasure method further includes: constructing a first storage unit, a second storage unit, and a third storage unit, which are respectively a full-chip storage array, a storage block, and a sector, wherein the full-chip storage array is all the storage units in the Nor Flash.

[0066] It should be noted that by setting the same and smaller over-erasure correction voltage for storage units with different storage capacities, for Nor Flash with storage capacities of 64Mb or more, storage units of different capacities can reach the target voltage for over-erasure correction more quickly, thereby shortening the completion time of over-erasure correction and thus reducing the time required for over-erasure correction.

[0067] Among them, it is possible, but not limited to, configuring an over-erasure correction voltage greater than or equal to 0.8V and less than 1V.

[0068] The values ​​of the over-erasure correction voltage in the above embodiments are for illustrative purposes only and are not intended to limit the solution.

[0069] Figures 5-7 Further verification and explanation of the aforementioned improvements in this application are provided, in which, Figure 5 This is a schematic diagram comparing the erase time of a full-chip storage array under different over-erasure targets, as provided in the embodiments of this application. Figure 5The horizontal axis represents the sample number, and the vertical axis represents the erase time (ms) of the entire memory array. Curve T1 represents the erase time variation curve of different samples with the first over-erasure correction voltage, curve T2 represents the erase time variation curve of different samples with the second over-erasure correction voltage, and curve T3 represents the erase time variation curve of different samples with the third over-erasure correction voltage.

[0070] from Figure 5 It can be seen that during the erasure process of the entire memory array, for the same sample, the erasure time for curves T1, T2, and T3 increases sequentially due to the different over-erasure correction voltages used. This indicates that using a smaller over-erasure correction voltage can significantly shorten the over-erasure correction time or the erasure time. Especially for erasing the entire memory array in its initial state, using a lower over-erasure correction voltage can significantly improve the overall erasure time (>20%) without affecting the correctness of reading or the programming time.

[0071] Therefore, for the onboard programming process, the erase algorithm provided in this application is particularly important for improving the erase time of the entire memory array in the initial state for Nor Flash or flash memory with a capacity of 64Mb or more.

[0072] Figure 6 The diagram shows a comparison of page programming times in the initial state under different erasure targets. Figure 7 The diagram shows another comparison of page programming time after 600,000 erase / read / write cycles under different erase targets. The horizontal axis represents the sample number, and the vertical axis represents the page programming time in milliseconds (ms).

[0073] exist Figure 6 In the diagram, curve T4 represents the programming time trend after over-erasure correction with the first over-erasure correction voltage, curve T5 represents the programming time trend after over-erasure correction with the second over-erasure correction voltage, and curve T6 represents the programming time trend after over-erasure correction with the third over-erasure correction voltage. Figure 6 It can be seen that the trends of curves T4, T5 and T6 are highly consistent. In other words, if each sample performs over-erasure correction with any of the first over-erasure correction voltage, the second over-erasure correction voltage or the third over-erasure correction voltage, it will not affect the page programming time of Nor Flash in the initial state.

[0074] exist Figure 7In the diagram, curve T7 represents the programming time trend of the corresponding sample after 600,000 erase / read / write cycles with the first over-erasure correction voltage; curve T8 represents the programming time trend of the corresponding sample after 600,000 erase / read / write cycles with the second over-erasure correction voltage; and curve T9 represents the programming time trend of the corresponding sample after 600,000 erase / read / write cycles with the third over-erasure correction voltage. Figure 7 It can be seen that the changing trends of curves T7, T8, and T9 are compared to... Figure 6 The difference between them is widened, but this difference is small and can be ignored. In other words, even if each sample performs over-erasure correction with any of the first, second, or third over-erasure correction voltages, it will not significantly affect the page programming time of the Nor Flash after 600,000 erase / read / write cycles.

[0075] After the above Figure 6 , Figure 7 Analysis shows that the memory sections with the highest to lowest erase / write / read frequencies in Nor Flash are sectors, memory blocks, and the entire memory array. However, the probability of the erase / write / read cycles for the entire memory array exceeding 10,000 is very low. Even if the erase / write / read cycles for some small blocks exceed 10,000 or even 100,000, the use of a lower first over-erasure correction voltage during the erasure of the entire memory array will not cause read failure, and the impact on programming time is also very limited.

[0076] In one embodiment, this embodiment provides a Nor Flash that performs the erasure method of at least one of the above embodiments during the over-erasure correction process.

[0077] It is understood that the Nor Flash provided in this embodiment performs over-erasure correction on the first storage unit with a larger capacity using a first over-erasure correction voltage with a lower threshold voltage. Compared to performing over-erasure correction on the first storage unit with a second over-erasure correction voltage with a higher threshold voltage, the first over-erasure correction voltage is smaller and can be reached more quickly, thereby shortening the completion time of over-erasure correction and reducing the time required for over-erasure correction.

[0078] Furthermore, the Nor Flash provided in this embodiment performs over-erasure correction on the first and second memory sections with larger capacities using a first over-erasure correction voltage with a lower threshold voltage. Compared to performing over-erasure correction on the third memory section with smaller capacity using a third over-erasure correction voltage with a higher threshold voltage, the first over-erasure correction voltage is smaller and can be reached more quickly, thereby shortening the over-erasure correction completion time and reducing the time required for over-erasure correction.

[0079] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0080] The Nor Flash and its erasure method provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for erasing Nor Flash, characterized in that, The erasure method includes: The Nor Flash is constructed by including a first storage section and a second storage section, wherein the number of storage cells in the first storage section is greater than the number of storage cells in the second storage section; The first over-erasure correction voltage is used as the target voltage for the first storage unit to perform over-erasure correction. The second over-erasure correction voltage is used as the target voltage for the second storage unit to perform over-erasure correction, and the second over-erasure correction voltage is greater than the first over-erasure correction voltage.

2. The erasing method according to claim 1, characterized in that, The erasure method further includes: The Nor Flash also includes a third storage unit, wherein the number of storage cells in the second storage unit is greater than the number of storage cells in the third storage unit; The second over-erasure correction voltage is used as the target voltage for the third storage unit to perform over-erasure correction.

3. The erasure method according to claim 2, characterized in that, The erasure method further includes: The first storage unit, the second storage unit, and the third storage unit are constructed as a full-chip storage array, a storage block, and a sector, respectively, wherein the full-chip storage array is all the storage units in the Nor Flash. The first over-erasure correction voltage is configured to be greater than or equal to 80% of the preset voltage and less than the preset voltage; The second over-erasure correction voltage is configured to be greater than the preset voltage and less than or equal to 120% of the preset voltage.

4. The erasing method according to claim 2, characterized in that, The erasure method further includes: The first storage unit, the second storage unit, and the third storage unit are constructed as a full-chip storage array, a storage block, and a sector, respectively, wherein the full-chip storage array is all the storage units in the Nor Flash. The first over-erasure correction voltage is configured to be greater than or equal to 80% of the preset voltage and less than the preset voltage; Configure the second over-erasure correction voltage to be equal to the preset voltage.

5. The erasing method according to claim 1, characterized in that, The erasure method further includes: The Nor Flash also includes a third storage unit, wherein the number of storage cells in the second storage unit is greater than the number of storage cells in the third storage unit; The third over-erasure correction voltage is used as the target voltage for performing over-erasure correction on the third storage unit, and the third over-erasure correction voltage is greater than the second over-erasure correction voltage.

6. The erasing method according to claim 5, characterized in that, The erasure method further includes: The first storage unit, the second storage unit, and the third storage unit are constructed as a full-chip storage array, a storage block, and a sector, respectively, wherein the full-chip storage array is all the storage units in the Nor Flash. The first over-erasure correction voltage is configured to be greater than or equal to 80% of the preset voltage and less than the preset voltage; Configure the second over-erasure correction voltage to be equal to the preset voltage; The third over-erasure correction voltage is configured to be greater than the preset voltage and less than or equal to 120% of the preset voltage.

7. A method for erasing Nor Flash, characterized in that, The erasure method includes: The Nor Flash is constructed by comprising a first storage unit, a second storage unit, and a third storage unit, wherein the number of storage cells in the first storage unit, the number of storage cells in the second storage unit, and the number of storage cells in the third storage unit decrease sequentially. The second over-erasure correction voltage is used as the target voltage for the first storage unit to perform over-erasure correction; The third over-erasure correction voltage is used as the target voltage for the second storage unit and the third storage unit to perform over-erasure correction. The second over-erasure correction voltage is greater than the first over-erasure correction voltage and less than the third over-erasure correction voltage.

8. The erasure method according to claim 7, characterized in that, The erasure method further includes: The first storage unit, the second storage unit, and the third storage unit are constructed as a full-chip storage array, a storage block, and a sector, respectively, wherein the full-chip storage array is all the storage units in the Nor Flash. The first over-erasure correction voltage is configured to be greater than or equal to 80% of the preset voltage and less than the preset voltage; Configure the second over-erasure correction voltage to be equal to the preset voltage; The third over-erasure correction voltage is configured to be greater than the preset voltage and less than or equal to 120% of the preset voltage.

9. A method for erasing Nor Flash, characterized in that, The erasure method includes: The Nor Flash is constructed by comprising a first storage unit, a second storage unit, and a third storage unit, wherein the number of storage cells in the first storage unit, the number of storage cells in the second storage unit, and the number of storage cells in the third storage unit decrease sequentially. The first over-erasure correction voltage is used as the target voltage for the first storage unit and the second storage unit to perform over-erasure correction. The third over-erasure correction voltage is used as the target voltage for the third storage unit to perform over-erasure correction. The second over-erasure correction voltage is greater than the first over-erasure correction voltage and less than the third over-erasure correction voltage. The second over-erasure correction voltage is a preset voltage.

10. The erasure method according to claim 9, characterized in that, The erasure method further includes: The first storage unit, the second storage unit, and the third storage unit are constructed as a full-chip storage array, a storage block, and a sector, respectively, and the full-chip storage array is all the storage units in the Nor Flash.

11. A Nor Flash, characterized in that, The Nor Flash performs the erasure method as described in any one of claims 1 to 10 during the over-erasure correction process.

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