Method, device, computer device and readable storage medium for chip repair

Abstract

Embodiments of the present disclosure provide a method and device for chip repair, computer equipment and a readable storage medium. The method for chip repair comprises: determining a target fault group in a chip to be repaired, each target fault group comprising at least one faulty unit; obtaining a target path of the target fault group; obtaining a target repair mode of the target fault group according to the target path; and obtaining a target repair mode of the chip to be repaired according to the target repair mode of the target fault group. The method of the embodiments of the present disclosure can efficiently and accurately repair the faulty units in the chip to be repaired.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and particularly relates to a method and device for chip repair, a computer device and a readable storage medium. BACKGROUND

[0002] With the increase of storage chip capacity and density, the number of faulty units on the storage chip also increases, in order to ensure the yield of the storage chip, it is necessary to repair the faulty units on the storage chip. However, the repair method in the prior art cannot achieve efficient and accurate repair.

[0003] The above information disclosed in the background section is only used to enhance the understanding of the background of the present disclosure, and therefore it can include information that does not constitute the related art known to those of ordinary skill in the art. SUMMARY

[0004] The embodiments of the present disclosure provide a method and device for chip repair, a computer device and a computer readable storage medium, which can efficiently and accurately repair faulty units in a chip.

[0005] The embodiments of the present disclosure provide a method for chip repair, comprising: determining a target fault group in a chip to be repaired, each target fault group comprising at least one faulty unit; obtaining a target path of the target fault group; obtaining a target repair mode of the target fault group according to the target path; and obtaining a target repair mode of the chip to be repaired according to the target repair mode of the target fault group.

[0006] According to the exemplary embodiments of the present disclosure, the target fault group in the chip to be repaired is determined, comprising: obtaining faulty units in the chip to be repaired; determining a must-repair faulty unit from the faulty units; repairing the must-repair faulty unit using a spare resource to obtain a remaining spare resource; and grouping remaining faulty units other than the must-repair faulty unit to obtain the target fault group.

[0007] According to the exemplary embodiments of the present disclosure, the must-repair faulty unit is determined from the faulty units, comprising: obtaining a spare row and a spare column in the spare resource; if the number of the spare columns is greater than the number of the spare rows, obtaining a must-repair faulty column in the chip to be repaired, the must-repair faulty unit comprising faulty units in the must-repair faulty column, and the number of the faulty units in the must-repair faulty column being greater than the number of the spare rows; and if the number of the spare rows is greater than the number of the spare columns, obtaining a must-repair faulty row in the chip to be repaired, the must-repair faulty unit comprising faulty units in the must-repair faulty row, and the number of the faulty units in the must-repair faulty row being greater than the number of the spare columns.

[0008] According to an example embodiment of the present disclosure, grouping the remaining faulty units other than the mandatory repair faulty units to obtain the target faulty group comprises: grouping the remaining faulty units having the same row address or the same column address into a group to obtain a non-standardized faulty group; and standardizing the non-standardized faulty group to obtain the target faulty group.

[0009] According to an example embodiment of the present disclosure, grouping the remaining faulty units having the same row address or the same column address into a group to obtain a non-standardized faulty group comprises: constructing a first non-standardized faulty group and determining a first grouping information list of the first non-standardized faulty group; obtaining a row address and a column address of a first remaining faulty unit; if the first grouping information list is empty or a row address or a column address of a second remaining faulty unit already existing in the first grouping information list is the same as the row address or the column address of the first remaining faulty unit, adding the row address and the column address of the first remaining faulty unit to the first grouping information list; if the row address and the column address of the second remaining faulty unit are both different from the row address and the column address of the first remaining faulty unit, constructing a second non-standardized faulty group and determining a second grouping information list of the second non-standardized faulty group; wherein the non-standardized faulty group comprises the first non-standardized faulty group and the second non-standardized faulty group, and the remaining faulty units comprise the first remaining faulty unit and the second remaining faulty unit.

[0010] According to an example embodiment of the present disclosure, standardizing the non-standardized faulty group to obtain the target faulty group comprises: arranging the target faulty group in ascending order according to row addresses and column addresses of faulty units in the non-standardized faulty group in a row direction and a column direction of the target faulty group, respectively, to generate the target faulty group, wherein a first value represents a faulty unit and a second value represents a normal unit in the target faulty group.

[0011] According to an example embodiment of the present disclosure, standardizing the non-standardized faulty group to obtain the target faulty group comprises: determining a minimum required spare resource of the non-standardized faulty group; and if the remaining spare resource is greater than or equal to the minimum required spare resource, standardizing the non-standardized faulty group to obtain the target faulty group.

[0012] According to an example embodiment of the present disclosure, obtaining a target path of the target fault group comprises: if the total number of fault units in the target fault group is greater than 1, starting from a starting fault unit in the target fault units, sequentially searching for an associated fault unit in a preset direction order for each fault unit in the target fault group, and calculating a step length from a current fault unit to an associated next fault unit, until all fault units in the target fault group are completely traversed; and obtaining the target path of the target fault group according to the direction from the current fault unit to the associated next fault unit and the step length.

[0013] According to an example embodiment of the present disclosure, obtaining a target repair mode of the target fault group according to the target path comprises: obtaining a matching library, the matching library comprising candidate paths and corresponding candidate repair modes; searching for the candidate paths according to the target path, and determining the target repair mode from the candidate repair modes.

[0014] According to an example embodiment of the present disclosure, the target path comprises a first target path that does not match the candidate path, the first target path corresponding to a first target fault group, and the target fault group comprising the first target fault group; and obtaining a target repair mode of the target fault group according to the target path further comprises: obtaining a fault row number m' and a fault column number n' of the first target fault group, wherein m' and n' are both positive integers; if the fault column number of the first target fault group is greater than the fault row number, using a spare column in a spare resource to repair a fault column in the first target fault group, and the number of spare columns decreasing in repair times from n' to 0, and after each repair using the spare column, using a spare row in the spare resource to repair remaining fault units in the first target fault group that are not repaired by the spare column.

[0015] According to an example embodiment of the present disclosure, the target fault group includes a first target fault group and a second target fault group, the target repair mode of the first target fault group includes a first level target repair mode, and the repair mode of the second target fault group includes a second level target repair mode; the number of required spare resources in the first level target repair mode is the same, and the number of required spare resources in the second level target repair mode is the same; wherein obtaining the target repair mode of the chip to be repaired according to the target repair mode of the target fault group includes: combining the first level target repair mode and the second level target repair mode to obtain a first required spare row resource number and a first required spare column resource number of the chip to be repaired; obtaining a remaining spare row resource number and a remaining column resource number in the remaining spare resources; and if the first required spare row resource number is less than or equal to the remaining spare row resource number and the first required spare column resource number is less than or equal to the remaining spare column resource number, determining that the target repair mode includes the first level target repair mode and the second level target repair mode.

[0016] According to an example embodiment of the present disclosure, the first target fault group further includes a third level target repair mode, the number of required spare resources in the third level target repair mode is the same, and the number of required spare resources in the third level target repair mode is greater than the number of required spare resources in the first level target repair mode; wherein obtaining the target repair mode of the chip to be repaired according to the target repair mode of the target fault group further includes: if the first required spare row resource number is greater than the remaining spare row resource number or the first required spare column resource number is greater than the remaining spare column resource number, combining the third level target repair mode and the second level target repair mode to obtain a second required spare row resource number and a second required spare column resource number of the chip to be repaired; and if the second required spare row resource number is less than or equal to the remaining spare row resource number and the second required spare column resource number is less than or equal to the remaining spare column resource number, determining that the target repair mode includes the third level target repair mode and the second level target repair mode.

[0017] The example embodiments of the present disclosure further provide a device for chip repair, including a determination module and a processing module. The determination module is configured to determine a target fault group in a chip to be repaired, each target fault group including at least one faulty unit; the processing module is configured to obtain a target path of the target fault group; the processing module is further configured to obtain a target repair mode of the target fault group according to the target path; and the processing module is further configured to obtain a target repair mode of the chip to be repaired according to the target repair mode of the target fault group.

[0018] The embodiment of the present disclosure further provides a computer device, comprising a processor, a memory and an input and output interface; the processor is connected with the memory and the input and output interface respectively, wherein the input and output interface is used for receiving and outputting data, the memory is used for storing a computer program, and the processor is used for calling the computer program so that the computer device executes the method in any of the above embodiments.

[0019] The embodiment of the present disclosure further provides a computer readable storage medium, which stores a computer program, and the computer program is suitable for being loaded and executed by a processor so that a computer device with the processor executes the method in any of the above embodiments.

[0020] According to the above technical solution, the method for chip repair in the embodiment of the present disclosure has at least one of the following advantages and positive effects:

[0021] In the embodiment of the present disclosure, by obtaining the target path of the target fault group and the target repair mode matched with the target path, the repair scheme can be efficiently and accurately found out under limited spare resources, the time cost of analysis is reduced, and the production capacity is improved. BRIEF DESCRIPTION OF DRAWINGS

[0022] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0023] Figure 1 A flowchart of the method for chip repair shown in some embodiments of the present disclosure;

[0024] Figure 2 A flowchart of determining a target fault group shown in some embodiments of the present disclosure;

[0025] Figure 3 A schematic diagram of a fault unit in a chip to be repaired shown in some embodiments of the present disclosure;

[0026] Figure 4 A framework diagram of determining a fault unit to be repaired shown in some embodiments of the present disclosure;

[0027] Figure 5 A schematic diagram of determining a fault unit to be repaired shown in some embodiments of the present disclosure;

[0028] Figure 6 A schematic diagram of grouping the remaining fault units shown in some embodiments of the present disclosure;

[0029] Figure 7 A schematic diagram of obtaining a minimum two-dimensional matrix binary graph of each standardized fault group shown in some embodiments of the present disclosure;

[0030] Figure 8 A framework diagram for determining the relationship between the remaining spare resources and the required spare resources, shown for some embodiments of the present disclosure;

[0031] Figure 9 A schematic diagram for obtaining a target path of a target fault group, shown for some embodiments of the present disclosure;

[0032] Figure 10 A flowchart for obtaining a target path of a target fault group, shown for some embodiments of the present disclosure;

[0033] Figure 11 A candidate path and a candidate repair method in a matching library obtained according to a preset region, shown for some embodiments of the present disclosure;

[0034] Figure 12 A schematic diagram for determining a target repair method of a target path according to a candidate path, shown for some embodiments of the present disclosure;

[0035] Figure 13 A schematic diagram for obtaining a candidate repair method, shown for some embodiments of the present disclosure;

[0036] Figure 14 Target repair methods corresponding to different fault groups, shown for some embodiments of the present disclosure;

[0037] Figure 15 A flowchart of a method for chip repair, shown for some embodiments of the present disclosure;

[0038] Figure 16 A block diagram of an apparatus for chip repair, shown for some embodiments of the present disclosure;

[0039] Figure 17 A schematic diagram of a computer device, shown for some embodiments of the present disclosure;

[0040] Figure 18 A schematic diagram of a computer readable storage medium, shown for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0041] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations may, however, be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example implementations to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and descriptions of the same elements will be omitted from descriptions of the other figures.

[0042] In the following description of different example embodiments of the present disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration various example structures in which aspects of the present disclosure can be implemented. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps can be utilized and structural and functional modifications can be made without departing from the scope of the present disclosure. Also, while the terms "over," "between," "inside," "on," "under," and the like, can be used in this specification to describe different example features and elements of the present disclosure, these terms are used herein simply for convenience and are not intended to limit the position of the features and elements to which they are used. Nothing in this specification should be construed as requiring a specific three dimensional orientation of structures as shown in the figures.

[0043] The flowcharts shown in the drawings are only illustrative, and do not necessarily include all contents and operations / steps, nor are they necessarily executed in the order described. For example, some operations / steps can be further decomposed, and some operations / steps can be combined or partially combined, so the actual execution order can be changed according to actual conditions.

[0044] In addition, in the description of the present disclosure, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise explicitly specifically limited.

[0045] With the increase of storage chip capacity and density, the number of failed units on the storage chip also increases, in order to repair these failed units to improve the yield of the chip, the related technology uses spare circuit architecture and repair analysis algorithm for repair. The spare circuit architecture includes spare rows and spare columns, since the number of spare rows and spare columns in the spare circuit architecture is limited, it can be realized by RA (Redundancy Analysis) algorithm, for the rows and columns with faults, the number of failed units is counted respectively, and the spare rows and spare columns in the spare circuit architecture are assigned in descending order for repair. But in the case of real solution, the assignment result of the spare rows and spare columns fails to successfully repair all the failed units, and the chip becomes a waste product due to the remaining faults, resulting in a decrease in yield.

[0046] Based on this, the embodiment of the present disclosure provides a method for chip repair, as shown in the figure, the method for chip repair of the embodiment of the present disclosure includes the following steps: S110-S140. Figure 1

[0047] S110: Determine the target fault group in the chip to be repaired, each target fault group includes at least one failed unit.

[0048] ​The chip to be repaired is a faulty chip, which can be a memory chip such as a dynamic random access memory (DRAM) chip, and is not specially limited herein. The target fault group is a fault group of faulty units in the chip to be repaired, which is repaired by using the method of the embodiments of the present disclosure.

[0049] In some embodiments, as shown in FIG. 11, the step of determining the target fault group in the chip to be repaired in S110 includes the following steps: S210-S240. Figure 2

[0050] S210: Obtain the faulty units in the chip to be repaired.

[0051] A fault counter is installed in the chip in advance, which can count the number and addresses of the faulty units. As shown in FIG. 21, the faulty units in the chip to be repaired in some embodiments are shown. In the figure, the solid circles represent the faulty units. Figure 3

[0052] S220: Determine the faulty units to be repaired from the faulty units.

[0053] Figure 4 A framework diagram for determining the faulty units to be repaired in some embodiments of the present disclosure is shown. In the embodiments of the present disclosure, the faulty units to be repaired are determined from the faulty units, including the steps: S410-S430.

[0054] S410: Obtain the spare rows and spare columns in the spare resource.

[0055] As shown in FIG. 41, the spare resource is a predetermined number of spare circuits pre-set in the chip storage array area, including spare rows and spare columns, which are used to repair the faulty units in the chip. In the embodiments of the present disclosure, the spare rows are denoted as ASR, and the spare columns are denoted as ASC. Figure 3 S420: If the number of spare columns ASC is greater than the number of spare rows ASR, obtain the faulty columns to be repaired in the current chip to be repaired. The faulty units to be repaired include the faulty units in the faulty columns to be repaired, and the number of the faulty units in the faulty columns to be repaired is greater than the number of the spare rows.

[0056] S430: If the number of spare rows ASR is greater than the number of spare columns ASC, obtain the faulty rows to be repaired in the current chip to be repaired. The faulty units to be repaired include the faulty units in the faulty rows to be repaired, and the number of the faulty units in the faulty rows to be repaired is greater than the number of the spare columns.

[0057]

[0058] ​​​In S420, after obtaining the necessary repair fault column in the current chip to be repaired, S421 of judging whether to trigger the acquisition of the necessary repair fault row can also be included. That is, after obtaining the necessary repair fault column in S420, the fault column and the spare column are updated, and then the number relationship between ASR and ASC is judged after the update. If the number of spare rows ASR is greater than the number of spare columns ASC in S430, S430 is executed. After executing S430, S431 of judging whether to trigger the acquisition of the necessary repair fault column can also be included. That is, after obtaining the necessary repair fault row in S430, the fault row and the spare fault row are updated, and then the number relationship between ASR and ASC is judged after the update. If the number of spare columns ASC is greater than the number of spare rows ASR in S420, S420 is executed until the above conditions are not met.

[0059] Specifically, in some embodiments, as shown in Figure 4 and Figure 5 in S420, the number relationship between the spare row ASR and the spare column ASC in the spare resource is judged. If the number of spare columns ASC is greater than the number of spare rows ASR, the chip to be repaired is repaired by column first, that is, the necessary repair fault column is obtained first, and the number of fault units in the necessary repair fault column is greater than the number of spare rows ASR.

[0060] After the necessary repair fault column is determined, the number of fault units and spare columns ASC is updated, and whether to obtain the necessary repair fault row is judged. In S430, if the number of current spare rows ASR is less than or equal to the number of current spare columns ASC (updated spare columns ASC), it is ended; if the number of current spare rows ASR is greater than the number of current spare columns ASC (updated spare columns ASC), the chip to be repaired is repaired by row, that is, the necessary repair fault row is obtained at this time, and the number of fault units in the necessary repair fault row is greater than the number of current spare columns ASC. After the necessary repair fault row is determined, the number of fault units and spare rows ASR is updated, and whether the condition of S420 is met is judged again. If yes, the above S420 step is continued to execute, if no, it is ended.

[0061] For example, as shown in Figure 5 , the chip to be repaired has 8 rows and 8 columns in the repair area to be repaired, the number of spare rows ASR is 4, and the number of spare columns ASC is 3. The number of spare rows ASR is greater than the number of spare columns ASC, so the necessary repair fault row is determined first, and the number of fault units in the necessary repair fault row needs to be greater than the number of spare columns ASC, from Figure 5It can be concluded that the number of faulty units in the first row (row address 0) is 4, and the number of faulty units in the sixth row (row address 5) is 5, both of which are greater than the number of spare columns ASC 3, so it is determined that the first row and the sixth row are mandatory repair rows. The number of faulty units and the number of spare rows are updated, that is, the faulty units in the mandatory repair rows are removed, and two spare rows are also removed. At this time, the number of current spare rows ASR is 2, the number of spare columns ASC is 3, and it is determined that the current number of spare columns ASC is greater than the number of spare rows ASR, so it is determined that the faulty column must be repaired. It is found that there are 4 faulty units in the sixth column (column address 5), which is greater than the current number of spare rows ASR 2, so it is determined that the sixth column is a mandatory repair column. The number of faulty units and the number of spare columns ASC are updated at this time, and the current number of spare columns ASC is 2, and the current number of spare rows ASR is 2. It is determined that the number of ASC and ASR is equal, and the process ends. Through the above method, it is determined that Figure 5 the mandatory repair rows in the chip to be repaired in the above table are the first row and the sixth row, and the mandatory repair column is the sixth column.

[0062] S230: Repair the mandatory repair unit with the spare resource to obtain the remaining spare resource.

[0063] After the mandatory repair row and the mandatory repair column are determined, the mandatory repair row and the mandatory repair column can be repaired using the spare row ASR and the spare column ASC first, as shown by the dashed line in Figure 5 . In this way, the number of faulty units in the chip to be repaired is reduced, and the complexity of subsequent repair is reduced.

[0064] S240: Grouping the remaining faulty units except the mandatory repair unit to obtain a target fault group.

[0065] After removing the mandatory repair unit, there are still remaining faulty units in the chip to be repaired. Grouping the remaining faulty units can include: grouping the remaining faulty units with the same row address or the same column address into a group to obtain a non-standardized fault group; and standardizing the non-standardized fault group to obtain a target fault group.

[0066] Specifically, grouping the remaining faulty units with the same row address or the same column address into a group to obtain a non-standardized fault group includes the following steps: A1-A4.

[0067] The non-standardized fault group includes a first non-standardized fault group and a second non-standardized fault group, and the remaining faulty units include a first remaining faulty unit and a second remaining faulty unit.

[0068] A1: Construct a first non-standardized fault group and determine a first grouping information list of the first non-standardized fault group.

[0069] Specifically, the first non-standardized fault group can be G0, and the first grouping information list is used to store the row address and the column address of the remaining fault units classified into the first non-standard fault group.

[0070] A2: Obtain the row address and the column address of the first remaining fault unit.

[0071] Wherein, the address of the remaining fault unit includes the row address and the column address.

[0072] A3: If the first grouping information list is empty or the row address or the column address of the second remaining fault unit already existing in the first grouping information list is the same as the row address or the column address of the first remaining fault unit, the row address and the column address of the first remaining fault unit are added to the first grouping information list.

[0073] In one case, the first grouping information list is empty when there is no remaining fault unit to be classified in the first information list, and the row address and the column address of the first remaining fault unit can be added to the first grouping information list. If the second remaining fault unit has the same row address or column address as the first remaining fault unit, the second remaining fault unit can also be classified into the first information list. In another case, the first grouping information list is not empty, and the second remaining fault unit already exists in the first information list, and the first remaining fault unit having the same row address or column address as the second remaining fault unit is classified into the first information list.

[0074] A4: If the row address and the column address of the second remaining fault unit are different from the row address and the column address of the first remaining fault unit, a second non-standardized fault group is newly created, and a second grouping information list of the second non-standardized fault group is determined.

[0075] Of course, the non-standardized fault groups in the embodiments of the present disclosure are not limited to only having the first non-standardized fault group and the second non-standardized fault group, but can also have a third non-standardized fault group, a fourth non-standardized fault group, etc. The above grouping description is only taken as an example of the first non-standardized fault group, the second non-standardized fault, the first remaining fault unit and the second remaining fault unit. If there are other non-standardized fault groups and remaining fault units, the grouping method is the same as the above, which will not be described here.

[0076] For example, the method for obtaining the non-standardized fault group can include the following steps. According to the address of the starting remaining fault unit, the addresses of the remaining fault units having the same row address or column address as the starting remaining fault unit are added to the same grouping information list, and the remaining fault units are updated.

[0077] Specifically, the fault group number is initialized to zero, and the first group is G0. An information group list is initialized, which is used to store the addresses of the remaining fault units of each non-standardized fault group, including row addresses and column addresses. The starting remaining fault unit can be understood as the first remaining fault unit added to each information group list. When traversing the remaining fault units, the address of the remaining fault unit with the same row address or the same column address as the starting remaining fault unit can be added to the information group list. After the address of the remaining fault unit is added to the information group list, it indicates that the current remaining fault unit has been grouped, and then it is updated so that the remaining fault unit will not be traversed again, thereby reducing unnecessary workload.

[0078] If the address of the current remaining fault unit exists in the existing grouping information list, the remaining fault unit is updated.

[0079] If the address of the current remaining fault unit exists in the existing grouping information list, it indicates that the current remaining fault unit has been grouped, that is, the update was not successful when it was grouped, and then it is updated after this traversal. Of course, the number of remaining fault units Nf can also be updated at the same time. According to the number of fault rows Nfr and the number of fault columns Nfc in the current non-standardized fault group obtained from the current information group list, as well as the number of multi-fault rows Nmr and the number of multi-fault columns Nmc in the current non-standardized fault group, all information of each non-standardized fault group is updated synchronously, thereby facilitating subsequent analysis and repair.

[0080] If the address of the current remaining fault unit cannot be added to the existing grouping information list, another grouping information list is created, and the address of the current remaining fault unit is added to the other grouping information list. The current remaining unit is taken as the starting remaining fault unit of the other grouping information list, and the remaining fault unit is updated.

[0081] Specifically, if the address of the current remaining fault unit cannot be added to the existing grouping information list, it indicates that the current remaining fault unit does not have the same row address or column address as the remaining fault units in the existing grouping information list, and the current remaining fault unit needs to be divided into another new fault group. Another grouping information list is created, the address of the current remaining fault unit is added to the other grouping information list, and the current remaining fault unit is taken as the starting remaining fault unit of the other grouping information list. When the traversed remaining fault unit has the same row address or the same column address as the current remaining fault unit, it is divided into a group.

[0082] After all the remaining faulty units are traversed completely, the grouping ends, the number of non-standardized fault groups is determined according to the number of grouping information lists, and the two are one-to-one corresponding, and the remaining faulty units in each grouping information list are the remaining faulty units in the non-standardized fault group.

[0083] After obtaining the non-standardized fault group, the non-standardized fault group is standardized to obtain a target fault group, including: in the row direction and the column direction of the target fault group, the row address and the column address of the faulty unit in the non-standardized fault group are arranged in ascending order respectively, to generate the target fault group, wherein the first value represents the faulty unit in the target fault group, and the second value represents the normal unit.

[0084] That is, the faulty units in the non-standardized fault group are arranged in ascending order according to the row address and the column address, the non-standardized fault group is standardized, and the target fault group is obtained.

[0085] Figure 6 Each fault group shown in FIG. 1 is a standardized fault group. In order to display more fault groups, in order to facilitate the description of the embodiments of the present disclosure, Figure 6 The number of remaining faulty units in FIG. 1 is different from Figure 5 The number of faulty units shown in FIG. 1 is not the same, which can be understood as Figure 6 The remaining faulty units on the chip to be repaired are different from Figure 5 As an example, Figure 6 Three target fault groups G0, G1, and G2 are shown in FIG. 1. After standardization, each fault group can be more compact, solving the problem that the address information of the faulty units in the fault group is different from the spatial position relationship, which causes differentiation in subsequent operations, while ensuring the uniqueness of each target path generated in subsequent operations, facilitating the generation and matching of subsequent target paths.

[0086] In some embodiments, after the non-standardized fault group is standardized, the standardized fault group can also be processed to generate a minimum two-dimensional matrix binary graph to obtain a target fault group.

[0087] As shown in FIG. 1, Figure 7 In the minimum two-dimensional matrix binary graph, the numbers in the uppermost region and the leftmost region represent index values, and the regions other than the index value region are the to-be-repaired regions, wherein 1 can be the first value, representing the faulty unit, and 0 can be the second value, representing the normal unit. The minimum two-dimensional matrix binary graph is represented by B, and the three minimum two-dimensional matrix binary graphs corresponding to the three target fault groups G0, G1, and G2 are B0, B1, and B2, respectively. Generating a minimum two-dimensional matrix binary graph can arrange the faulty rows and columns in the standardized fault group more compactly, facilitating subsequent analysis.

[0088] In some embodiments, as shown in FIG. 1,Figure 8 As shown, the non-standardized fault group is standardized to obtain the target fault group, and further includes: determining the required minimum spare resource of the non-standardized fault group. If the remaining spare resource is greater than or equal to the required minimum spare resource, the non-standardized fault group is standardized to obtain the target fault group.

[0089] That is, before obtaining the target fault group, the required minimum spare resource for repairing the non-standardized fault group is determined, and if the remaining spare resource (i.e. the remaining spare resource after repairing the mandatory repairable fault unit in the spare resource) is greater than or equal to the required minimum spare resource, it means that the remaining spare resource is sufficient to repair the fault unit in the non-standardized fault group in the to-be-repaired chip, and then the process can continue, thereby obtaining the target fault group. If the remaining spare resource is less than the required minimum spare resource, it means that the remaining spare resource is insufficient to repair the fault unit in the to-be-repaired chip, and the repair work of the to-be-repaired chip is stopped to save energy consumption.

[0090] As an example, as shown in the figure, a framework diagram for obtaining the required minimum spare resource Nmsc is shown. The following steps can be included: S810-S8150. Figure 8

[0091] S810: For each non-standard fault group, determine whether the number of multi-fault rows Nmr (i.e. the number of fault rows with multiple fault units) or the number of multi-fault columns Nmc (i.e. the number of fault columns with multiple fault units) of the current non-standard fault group is zero; if yes, execute S820; if no, execute S830.

[0092] S820: Output the required minimum spare resource number Nmsc as 1.

[0093] When Nmr or Nmc is zero, all fault units are in a certain fault row or fault column, at this time, one spare row or spare column is required for repair, and therefore the required minimum spare resource number Nmsc is 1.

[0094] S830: Determine whether the number of multi-fault rows Nmr is less than the number of multi-fault columns Nmc; if yes, execute S840; if no, execute S870.

[0095] S840: Continue to determine whether the number of fault rows Nfr of the current non-standard fault group is greater than the number of multi-fault rows Nmr; if yes, execute S850; if no, execute S860.

[0096] S850: The required minimum spare resource number Nmsc can be output as the number of multi-fault rows Nmr plus 1.

[0097] S850: The required minimum spare resource number Nmsc can be output as the number of multi-fault rows Nmr plus 1.

[0098] ​S860: output the required minimum spare resource number Nmsc as the number of multi-failure rows Nmr.

[0099] S870: continue to determine whether Nmr is equal to Nmc; if yes, execute S880; if no, execute S890.

[0100] S880: continue to determine whether the number of failure rows Nfr of the current non-standard failure group is equal to the number of multi-failure rows Nmr or the number of failure columns Nfc of the current non-standard failure group is equal to the number of multi-failure columns Nmc; if yes, execute S860; if no, execute S850.

[0101] S890: determine whether the number of failure columns Nfc of the current non-standard failure group is greater than the number of multi-failure columns Nmc; if yes, execute S8100; if no, execute S8110.

[0102] S8100: output the required minimum spare resource number Nmsc as the number of multi-failure columns Nmc plus 1.

[0103] S8110: output the required minimum spare resource number Nmsc as the number of multi-failure columns Nmc.

[0104] S8120: after obtaining the required minimum spare resource number Nmsc of each non-standard failure group, sum the required minimum spare resource numbers of all non-standard failure groups, as shown in the following formula (1),

[0105]

[0106] wherein M represents the number of non-standard failure groups in the chip to be repaired, which is a positive integer; and C represents the ordinal number of the current non-standard failure group, which is a positive integer.

[0107] According to the summation formula, the total number N of the required minimum spare resources required by the entire chip to be repaired is obtained.

[0108] S8130: determine whether the total number N of the required minimum spare resources is greater than the number of remaining spare resources (ASR+ASC); if yes, execute step S8140; if no, execute step 8150.

[0109] S8140: output unrepairable and end.

[0110] S8150: output repairable.

[0111] Through the above method, the number of the minimum spare resources required for repairing all faulty units of the chip to be repaired can be obtained, and by comparing with the number of the remaining spare resources, if the number of the remaining spare resources is insufficient, the repairing can be stopped as early as possible to avoid subsequent invalid repairing work, thereby saving energy consumption.

[0112] S120: obtaining a target path of the target fault group.

[0113] After obtaining the target fault group, the target path of the target fault group can be further obtained. As shown in Figure 9 and Figure 10 Exemplary target fault groups G (G0, G1, G2) and corresponding minimum two-dimensional matrix binary graphs B (B0, B1, B2), target paths P (P0, P1, P2) are shown. Obtaining the target path of the target fault group includes the following steps: S1010-S1020.

[0114] S1010: If the number of total faulty units in the target fault group is greater than 1, starting from the starting faulty unit in the target faulty unit, sequentially searching for the associated faulty unit in the target fault group according to the preset direction order, and calculating the step from the current faulty unit to the associated next faulty unit, until all the faulty units in the target fault group are completely traversed.

[0115] S1020: obtaining the target path of the target fault group according to the direction and step from the current faulty unit to the associated next faulty unit.

[0116] In the embodiments of the present disclosure, when the faulty units are traversed, the four directions of the faulty units are traversed to explore the next faulty unit associated with the current faulty unit in the current target fault group. The preset direction refers to the traversal of the current faulty unit in the order of the four directions. In some embodiments, from the current faulty unit, first explore upwards, which can be represented by U, then explore to the right, which can be represented by R, then explore to the left, which can be represented by L, and finally explore downwards, which can be represented by B. Of course, other orders are also possible, which are not specially limited here. The first direction in the preset direction can be any one of the four directions.

[0117] After traversing to the next faulty unit, if the next faulty unit cannot be traversed to the faulty unit according to the preset direction, return to the current faulty unit; continue to traverse from the current faulty unit according to the second direction in the preset direction until all the faulty units in the target fault group are completely traversed to obtain the target path of the target fault group.

[0118] Wherein, when the next fault unit cannot be traversed to the fault unit according to the preset direction, it can be understood that the next fault unit cannot be explored according to the above four directions, at this time, the path is returned from the next fault unit to the current fault unit, and this path can be represented by N. That is, when any fault unit cannot explore the next fault unit according to the above four directions, the path is returned, or when the fault group has only one fault unit, the path is N. In addition, the second direction refers to any direction in the preset direction except the first direction.

[0119] As shown in Figure 9 , in the target fault group, starting from the starting point (0, 0), each fault unit is traversed according to the first direction in the preset direction (which can be upward U first, then right R, then left L, and finally downward B in the above embodiment), and the step length from the current fault unit to the next fault unit is calculated. Then repeat the above steps for the next fault unit, that is, traverse the next fault unit according to the preset direction, if the next fault unit cannot be explored according to the preset direction, return (represented by N), and then continue to traverse along the second direction in the preset direction until all fault units are completely traversed, and the target path is generated. As in Figure 9 , the target path of the target fault group G0 is R2NB1R1, the target path of the target fault group G1 is R1B1L1NB1R1, and the target path of the target fault group G2 is N. In the figure, G represents the target fault group, B represents the minimum two-dimensional matrix binary graph, and P represents the path.

[0120] Wherein, the step length can be understood as the relative offset position of the current fault unit and the next fault unit in any direction in the preset direction in the standardized minimum two-dimensional matrix binary graph of the target fault group. For example, in the minimum two-dimensional matrix binary graph, the two-dimensional address of one fault unit is (0, 0), and the two-dimensional address of another fault unit is (2, 0), and the step length of the two fault units is 2. Wherein, the two-dimensional address is the column address and the row address in the minimum two-dimensional matrix binary graph as shown in Figure 9 . By calculating the step length, the uniqueness of the target path of each target fault group can be ensured, and the accuracy of the repair can be improved.

[0121] S130: Obtain the target repair mode of the target fault group according to the target path.

[0122] In some embodiments, obtaining the target repair mode of the target fault group according to the target path includes: obtaining a matching library, the matching library including candidate paths and their corresponding candidate repair modes; searching for candidate paths according to the target path, and determining the target repair mode from the candidate repair modes.

[0123] Wherein, the matching library has pre-obtained candidate paths with different candidate repair methods. The repair method refers to the number of spare rows and the number of spare columns required for repairing the path corresponding thereto.

[0124] As shown in Figure 11 , a preset area is selected, which may be a q*q matrix for example, where q may be a positive integer greater than 1. The preset area may include a plurality of candidate fault groups (see Figure 9 ).

[0125] Any candidate fault group is obtained, which has m fault rows and n fault columns, where m and n are positive integers. The candidate path of the candidate fault group is obtained according to the method of obtaining the target path in the above embodiment.

[0126] The candidate repair method of the candidate fault group is obtained. Specifically, the sizes of the fault row number m and the fault column number n are judged, and the smaller one is repaired. According to the permutation combination C j min(m，n) , j∈[0,min(m,n)], spare rows / columns are assigned to repair the selected j rows / columns, where j is the number of fault rows or fault columns in the candidate fault group that need to be repaired in one repair; then spare columns / rows are used to repair the remaining fault units, and the number of spare rows and spare columns required is recorded to obtain the candidate repair method of this time; wherein C is the permutation combination, min(m,n) is the minimum value of the number of fault columns and the number of fault rows in the candidate fault group, and j is a positive integer from 0 to min(m,n). According to the above permutation combination, the candidate fault group is repaired multiple times to obtain multiple candidate repair methods. The repeated repair methods and redundant repair methods in the candidate repair methods are filtered to obtain the final candidate repair method.

[0127] The above-mentioned candidate repair method of the candidate fault group can also be described as follows: if the number of fault columns of the candidate fault group is greater than the number of fault rows, i.e. m

[0128] It should be noted that the spare rows and spare columns used to repair the fault rows and fault columns in the candidate fault group are not the spare rows and spare columns in the spare resources used to repair the to-be-repaired chip, and do not occupy the spare resources.

[0129] As an example embodiment, referring to Figure 12 , suppose the number of fault rows m and the number of fault columns n of the candidate fault group are both 3, the fault rows or the fault columns can be repaired first. According to the distribution of the fault units, the candidate path P can be obtained as R1B1L1NB1R1. Wherein, Figure 12 B C in the above formula represents the minimum two-dimensional matrix binary graph of the current candidate fault group, the solid lines arranged by columns in the minimum two-dimensional matrix binary graph represent that the candidate fault group is repaired using spare columns, and the dashed lines arranged by rows represent that the candidate fault group is repaired using spare rows. The obtaining of the candidate repair mode can include the following contents A-E.

[0130] A: the candidate fault group is repaired using three spare columns, and the repair mode obtained is (Nsr: 0, Nsc: 3). Wherein, Nsr is the number of spare rows required, and Nsc is the number of spare columns required. This step is equivalent to C j min(m，n) =C 3 3.

[0131] B: then cancel one spare column in turn according to the order of the fault columns {0, 1, 2}, the fault units of the cancelled spare column are repaired using spare rows, and the number of spare columns and spare rows required is obtained. The candidate repair mode obtained is three (Nsr: 2, Nsc: 2). This step is equivalent to C j min(m，n) =C 1 3.

[0132] C: continue to cancel two spare columns of the fault columns (0, 1), (0, 2), (1, 2) in turn, the fault units of the cancelled spare columns are repaired using spare rows, the number of spare columns and spare rows required is obtained, and the candidate repair mode obtained is (Nsr: 2, Nsc: 1) (Nsr: 3, Nsc: 1), (Nsr: 3, Nsc: 1).

[0133] D: all spare columns are cancelled, only spare rows are used for repair, the number of spare rows required is obtained, and the candidate repair mode obtained is (Nsr: 3, Nsc: 0).

[0134] E: the repeated repair modes and the redundant repair modes in the above candidate repair modes are filtered to obtain the final repair mode of the candidate fault group.

[0135] Wherein, the repeated repair mode refers to that in at least two repair modes, the number of spare rows required is completely equal, and the number of spare columns required is completely equal. In order to simplify the process, the repeated repair mode is filtered out, and only one is retained. For example, inFigure 12 In the repeated repair mode, three (Nsr: 2, Nsc: 2) filters are retained, and only one is retained. The redundant repair mode refers to a repair mode in which the number of required spare rows or the number of required spare columns is equal to the number of required spare rows or the number of required spare columns in another repair mode, and the sum of the number of required spare rows and the number of spare columns in the redundant repair mode is greater than the sum of the number of required spare rows and the number of required spare columns in another repair mode. For example, in the q*q matrix in Figure 12 In the q*q matrix, the redundant repair modes are (Nsr: 2, Nsc: 2) and (Nsr: 3, Nsc: 1), and these two repair modes are filtered out. Filtering out the redundant repair mode can reduce the complexity and reduce the use of spare rows and spare columns.

[0136] Figure 12 In the candidate path P of the candidate fault group, R1B1L1NB1R1, the candidate repair mode corresponding to the candidate path is {(Nsr: 0, Nsc: 3), (Nsr: 2, Nsc: 1), (Nsr: 3, Nsc: 0)}. The candidate path and the candidate repair mode are stored in the matching library.

[0137] Through the above method, the candidate repair mode of each candidate fault group in the preset area can be obtained, and the candidate repair mode corresponds to the candidate path of the candidate fault group. In the preset area, such as Figure 11 In the q*q matrix in the q*q matrix, it can include a plurality of candidate fault groups, each fault group has a candidate path, according to the above method, the candidate repair mode corresponding to the candidate path is obtained, and the candidate path and the candidate repair mode of all candidate fault groups are stored in the matching library, so as to search and obtain when repairing the to-be-repaired chip.

[0138] As shown in Figure 13 After obtaining the target path P (P0, P1, P2) of the target fault group of the to-be-repaired chip, the candidate path corresponding to the target path is searched in the matching library, and the candidate repair mode corresponding to the candidate path is the target repair mode. Therefore, by setting the matching library in advance, the target repair mode can be directly obtained according to the matching of the target path and the candidate path when repairing the to-be-repaired chip, so that the repair time is greatly reduced, the analysis efficiency is improved, and the power consumption is saved.

[0139] In some embodiments, the target path of the chip to be repaired includes a first target path that does not match the candidate path, and the first target path corresponds to a first target fault group. The target fault group includes the first target fault group. Wherein, the target repair method of the target fault group is obtained according to the target path, further comprising: obtaining the number of fault rows m' and the number of fault columns n' of the first target fault group, wherein m' and n' are both positive integers; if the number of fault columns of the first target fault group is greater than the number of fault rows, then the spare columns in the spare resource are used to repair the fault columns in the first target fault group, and the number of spare columns decreases from n' to 0 according to the repair times, and after each repair using the spare column, the spare row in the spare resource is used to repair the remaining fault units in the first target fault group that have not been repaired by the spare column.

[0140] That is, when no candidate path matching the target path can be searched in the matching library, the target repair method cannot be directly obtained, at this time, the target repair method of the target fault group needs to be obtained separately to ensure that all fault units can be completely repaired. The method for obtaining the target repair method of the target fault is the same as the method for obtaining the candidate repair method of the candidate fault group in the above-mentioned embodiments, which will not be described here.

[0141] In other embodiments, the matching library can also not be preset, and after obtaining the target path of the target fault group, the target repair method of the target fault group is obtained according to the method for obtaining the candidate repair method in the above-mentioned embodiments, which will not be described here.

[0142] S140: obtaining the target repair method of the chip to be repaired according to the target repair method of the target fault group.

[0143] After obtaining the target repair method of each target fault group of the chip to be repaired, the repair methods of all target fault groups are combined and added to the set to obtain the target repair method. That is, the target repair method is the set of all target repair methods of the entire chip to be repaired.

[0144] In combination with Figure 13 and Figure 14 It is shown that in some embodiments, in order to repair the fault units in the chip to be repaired using the least spare resource, the target fault groups in the chip to be repaired include a first target fault group G0 and a second target fault group G1. The target repair method of the first target fault group G0 includes a first-level target repair method [(Nsr: 0, Nsc: 2)], and the repair method of the second target fault group G1 includes a second-level target repair method [(Nsr: 0, Nsc: 3), (Nsr: 2, Nsc: 1), (Nsr: 3, Nsc: 0)]. Wherein, the number of required spare resources in the first-level target repair method is the same as Figure 14The number of required spare resources in the second level target repair mode is the same as that in the first level target repair mode. Figure 14 The number of required spare resources in the second level target repair mode is the same as that in the first level target repair mode.

[0145] The target repair mode of the target fault group is obtained according to the target repair mode of the target fault group, including: combining the first level target repair mode [(Nsr: 0, Nsc: 2)] and the second level target repair mode [(Nsr: 0, Nsc: 3), (Nsr: 2, Nsc: 1), (Nsr: 3, Nsc: 0)], obtaining the first required spare row resource quantity and the first required spare column resource quantity of the chip to be repaired, and the quantity is 5; obtaining the remaining spare row resource quantity and the remaining column resource quantity in the remaining spare resource; if the first required spare row resource quantity is less than or equal to the remaining spare row resource quantity, and the first required spare column resource quantity is less than or equal to the remaining spare column resource quantity, it is determined that the target repair mode includes the first level target repair mode and the second level target repair mode. That is, the spare row in the spare resource is sufficient to repair the faulty row in the chip to be repaired, the spare column is sufficient to repair the faulty column in the chip to be repaired, and the target repair mode at this time is the mode using the least spare resource, which is determined as the final target repair mode of the chip to be repaired.

[0146] In some embodiments, the first target fault group further includes a third level target repair mode [(Nsr: 2, Nsc: 1), (Nsr: 3, Nsc: 0)], the number of required spare resources in the third level target repair mode is the same, the number is 3, and the required spare resources in the third level target repair mode are greater than the required spare resources in the first level target repair mode. That is, in each target fault group, the target repair mode is divided according to the level, the greater the level number, the greater the sum of the required spare row and the required spare column, that is, the greater the required spare resource quantity.

[0147] If the first required spare row resource quantity is greater than the remaining spare row resource quantity, or the first required spare column resource quantity is greater than the remaining spare column resource quantity, that is, the spare row or the spare column is insufficient to repair the faulty row or the faulty column in the target fault group, then it is highly possible that the spare resource is insufficient to repair the target fault group. The third-level target repair mode [(Nsr:2, Nsc:1), (Nsr:3, Nsc:0)] and the second-level target repair mode [(Nsr:0, Nsc:3), (Nsr:2, Nsc:1), (Nsr:3, Nsc:0)] are combined to obtain a second required spare row resource quantity and a second required spare column resource quantity of the chip to be repaired, and the quantity is 6.

[0148] If the second required spare row resource quantity is less than or equal to the remaining spare row resource quantity, and the second required spare column resource quantity is less than or equal to the remaining spare column resource quantity, then the target repair mode includes the third-level target repair mode and the second-level target repair mode. Otherwise, other target repair modes are combined in ascending order of level according to the above method. If the quantity of required spare resources (that is, the sum of the quantity of required spare rows and the quantity of required spare columns) in the finally obtained target repair mode is greater than the quantity of spare resources, then the repair is ended. Through the above method, the quantity of required spare resources is minimized, and the use amount of spare resources is saved.

[0149] In the above embodiments, only two target fault groups in Figure 14 are combined for description. In order to more clearly illustrate, three target fault groups in Figure 14 and Figure 15 are combined for description.

[0150] Specifically, as shown in Figure 15 , the target repair mode of the chip to be repaired is obtained according to the target repair mode of the target fault group, including the following steps: H1-H5.

[0151] The chip to be repaired includes a first target fault group G0, a second target fault group G1 and a third target fault group G2. The list of the target repair mode of the chip to be repaired is Lcs=[x, y, z], wherein x, y and z represent the level of the selected target repair mode in each target fault group.

[0152] H1: For each target fault group, arrange in ascending order according to the quantity of required spare resources (Nsr+Nsc), and then grade according to the quantity of required spare resources. The repair modes with equal quantity of required spare resources are divided into the same level.

[0153] Wherein, Nsr represents the quantity of spare rows, and Nsc represents the quantity of spare columns. As shown inFigure 14 As shown, the target repair methods for the first target fault group G0 are divided into two levels, the target repair methods for the second target fault group G1 are divided into two levels, and the target repair methods for the third target fault group G2 are divided into one level. For ease of description, the first level of the target repair method in each target fault group is represented by 0, the second level by 1, the third level by 2, and so on.

[0154] H2: Initialize the list of target patch schemes Lcs = [0, 0, 0].

[0155] The initialization target repair scheme list refers to initializing x, y, z to 0, i.e., Lcs = [0, 0, 0], which means that the first level of target repair method for each target fault group will be combined first.

[0156] H3: Combine the target repair methods in each target fault group in ascending order of their level to obtain a repair set, and determine whether the repair set satisfies Nsr≤ASR and Nsc≤ASC. If yes, proceed to step H4; otherwise, proceed to step H5.

[0157] H4: Determine this patch set as the target patch method.

[0158] Specifically, such as Figure 14 As shown, the target repair method for the first target fault group G0 is: Level 1 0: [(Nsr: 0, Nsc: 2)], Level 2 1: [(Nsr: 2, Nsc: 1), (Nsr: 3, Nsc: 0). The required number of backup resources for Level 1 is 2, and the required number of backup resources for Level 2 is 3.

[0159] The target repair method for the second target fault group G1 is as follows: Level 1 0: [(Nsr: 0, Nsc: 3), (Nsr: 2, Nsc: 1), (Nsr: 3, Nsc: 0)], Level 2 1: [(Nsr: 2, Nsc: 2), (Nsr: 3, Nsc: 1). The required number of backup resources for Level 1 is 3, and the required number of backup resources for Level 2 is 4.

[0160] The target repair method for the third target fault group G2 is: Level 1 0: [(Nsr: 1, Nsc: 0), (Nsr: 0, Nsc: 1)]. The required number of spare resources for Level 1 is 1.

[0161] Update Lcs = [0, 0, 0], combine the first-level target repair methods in each target fault group to obtain the first repair set S1.

[0162] S1={[(N sr: 0, N sc : 2), (N sr : 0, N sc : 3), (N sr : 1, N sc : 0)][(N sr : 0, N sc : 2), (N sr : 0, N sc : 3), (N sr : 0, N sc : 1)]' [(N sr : 0, N sc : 2), (N sr : 2, N sc : 1), (N sr : 1, N sc : 0)]' [(N sr : 0, N sc : 2), (N sr : 2, N sc : 1), (N sr : 0, N sc : 1)]' [(N sr : 0, N sc : 2), (N sr : 3, N sc : 0), (N sr : 1, N sc : 0)]' [(N sr : 0, N sc : 2), (N sr : 3, N sc : 0), (N sr : 0, N sc : 1)]'

[0163] The number of required spare rows and the number of required spare columns in any repair mode in the first repair set S1 are calculated. For example, in the repair mode [(Nsr: 0, Nsc: 2), (Nsr: 0, Nsc: 3), (Nsr: 1, Nsc: 0)], the minimum number of required spare rows is 1, and the minimum number of required spare columns is 5. If the number of required spare rows is less than or equal to the number of spare rows, and the number of required spare columns is less than or equal to the number of spare columns, it can be determined that the first repair set S1 is the target repair set, and the number of required spare resources is the least.

[0164] H5: Update the list Lcs of target repair schemes = [1, 0, 0], and combine the target repair modes of the target fault groups according to the list.

[0165] Specifically, the target repair mode of the second level in the first target fault group G0 is combined with the target repair mode of the first level in the second target fault group G1, the target repair mode of the second level in the third target fault group G2, to obtain a second repair set S2.

[0166] S2 = [(N sr : 2, N sc : 1), (N sr : 0, N sc : 3), (N sr : 1, N sc : 0)][(N sr : 2, N sc : 1), (N sr : 0, N sc : 3), (N sr : 0, N sc : 1)]'( [N sr : 2, N sc : 1), (N sr : 2, N sc : 1), (N sr : 1, N sc : 0)]'( [N sr : 2, N sc : 1), (N sr : 2, N sc : 1), (N sr : 0, N sc : 1)]'( [N sr : 2, N sc : 1), (N sr : 3, N sc : 0), (N sr : 1, N sc : 0)]'( [N sr : 2, N sc : 1), (N sr : 3, N sc : 0), (N sr : 0, N sc : 1)]'( [N sr : 3, N sc : 0), (N sr : 0, N sc : 3), (N sr : 1, N sc : 0)]'( [N sr : 3, N sc : 0), (N sr : 0, N sc : 3), (N sr : 0, N sc : 1)]'( [Nsr : 3, N sc : 0), (N sr : 2, N sc : 1), (N sr : 1, N sc : 0)]' [(N sr : 3, N sc : 0), (N sr : 2, N sc : 1), (N sr : 0, N sc : 1)]' [(N sr : 3, N sc : 0), (N sr : 3, N sc : 0), (N sr : 1, N sc : 0)]' [(N sr : 3, N sc : 0), (N sr : 3, N sc : 0), (N sr : 0, N sc : 1)]'

[0167] The number of required spare rows and the number of required spare columns in any repair in the second repair set S2 are calculated. For example, in the repair [(Nsr: 2, Nsc: 1), (Nsr: 0, Nsc: 3), (Nsr: 1, Nsc: 0)], the minimum number of required spare rows is 3, and the minimum number of required spare columns is 4. If the number of required spare rows ≤ the number of spare rows, and the number of required spare columns ≤ the number of spare columns, then the second repair set S2 can be determined as the target repair set, and the number of required spare resources is the least.

[0168] If the second repair set S2 still does not satisfy the above condition, continue to update Lcs= [1, 1, 0], and judge according to the above steps until a repair set that meets the condition is obtained as the target repair set. The target repair set obtained in this way requires the least number of spare resources.

[0169] In some embodiments, after each obtained repair set does not meet the condition that the number of required spare rows ≤ the number of spare rows and the number of required spare columns ≤ the number of spare columns, it can be further determined whether the sum of the number of required spare rows and the number of required spare columns is greater than the number of remaining spare resources. If so, it means that the remaining spare resources are insufficient to repair the faulty cells in the chip to be repaired, and the repair is stopped. Therefore, subsequent processing is not required, saving time and power consumption.

[0170] In some embodiments, as Figure 15As shown, the chip repair method of this disclosure includes steps S10 to S101.

[0171] S10: Identify and repair the faulty units that must be repaired. Specific methods can be found in S230 of the above embodiments, and will not be repeated here.

[0172] S20: After repairing the mandatory faulty units, group the remaining faulty units. For specific methods, refer to S240 in the above embodiment.

[0173] S30: Determine whether the required number of backup resources is greater than the number of remaining backup resources. If yes, execute S40; otherwise, execute S50.

[0174] S40: End.

[0175] S50: Generate the target fault group. The specific method is the same as S240 in the above embodiment, and will not be repeated here.

[0176] S60: Generate the target path corresponding to the target fault group. The specific method is the same as S120 in the above embodiment, and will not be repeated here.

[0177] S70: Match the target path with candidate paths in the matching library and obtain the target repair method.

[0178] S80: Determine whether the target path matches the candidate path. If yes, execute S100; otherwise, execute S90.

[0179] S90: Obtain the target repair method for the unmatched target path, and then execute S100;

[0180] S100: Determine whether all target fault groups have obtained the target repair method. If yes, execute S101; otherwise, execute S50.

[0181] S101: Target patching method that obtains the minimum required spare resources.

[0182] like Figure 15 As shown, the chip repair method of this disclosure can stop in time when the spare resources are insufficient to repair the faulty units in the target fault group, avoiding subsequent processing and saving energy. When the spare resources are sufficient, the target repair method with the minimum required spare resources can be obtained, saving spare resources and improving the repair accuracy.

[0183] The method for chip repair provided in the embodiments of the present disclosure can obtain the spatial dimension information of the fault units by obtaining the target path of the target fault group, can improve the number of fault groups, for example, in a 4*4 target fault group, the number of target paths that can be generated reaches 40,000, and in theory, can be infinitely expanded, can greatly improve the analysis and repair efficiency, save time cost, improve production capacity, and based on the target path, greatly improve the accuracy of repair.

[0184] To sum up, the method for chip repair provided in the embodiments of the present disclosure can efficiently and accurately find out the repair scheme under limited spare resources, reduce the time cost of analysis, and improve production capacity.

[0185] The embodiments of the present disclosure also provide a device 1600 for chip repair, as shown in the figure, the device comprises a determination module 1610 and a processing module 1620. Figure 16 The determination module 1610 is configured to determine a target fault group in a chip to be repaired, each target fault group comprising at least one fault unit.

[0186] The determination module 1610 is configured to determine a target fault group in a chip to be repaired, each target fault group comprising at least one fault unit.

[0187] The processing module 1620 is configured to obtain a target path of the target fault group; the processing module 1620 is further configured to obtain a target repair method of the target fault group according to the target path; and the processing module 1620 is further configured to obtain a target repair method of the chip to be repaired according to the target repair method of the target fault group.

[0188] In some embodiments, the determination module 1610 is further configured to obtain fault units in the chip to be repaired; determine a fault column to be repaired from the fault units; repair the fault units in the fault column to be repaired using spare resources to obtain remaining spare resources; and group the remaining fault units other than the fault units in the fault column to be repaired to obtain the target fault group. In this way, the number of fault units in the chip to be repaired is reduced, and the complexity of subsequent repair is reduced.

[0189] In some embodiments, the determination module 1610 is further configured to obtain spare rows and spare columns in the spare resources; if the number of spare columns is greater than the number of spare rows, obtain a fault column to be repaired in the chip to be repaired, the fault units to be repaired comprising fault units in the fault column to be repaired, and the number of fault units in the fault column to be repaired being greater than the number of spare rows; and if the number of spare rows is greater than the number of spare columns, obtain a fault row to be repaired in the chip to be repaired, the fault units to be repaired comprising fault units in the fault row to be repaired, and the number of fault units in the fault row to be repaired being greater than the number of spare columns.

[0190] In some embodiments, the determining module 1610 is further configured to divide the remaining faulty units with the same row address or the same column address into a group to obtain a non-standardized fault group; and standardize the non-standardized fault group to obtain the target fault group. In this way, the complexity of analysis and repair is reduced.

[0191] In some embodiments, the determining module 1610 is further configured to construct a first non-standardized fault group, and determine a first grouping information list of the first non-standardized fault group; obtain a row address and a column address of a first remaining faulty unit; if the first grouping information list is empty or the row address or the column address of a second remaining faulty unit already existing in the first grouping information list is the same as the row address or the column address of the first remaining faulty unit, add the row address and the column address of the first remaining faulty unit to the first grouping information list; if the row address and the column address of the second remaining faulty unit are both different from the row address and the column address of the first remaining faulty unit, construct a second non-standardized fault group, and determine a second grouping information list of the second non-standardized fault group; wherein the non-standardized fault group includes the first non-standardized fault group and the second non-standardized fault group, and the remaining faulty units include the first remaining faulty unit and the second remaining faulty unit.

[0192] In some embodiments, the determining module 1610 is further configured to arrange the target fault group in ascending order of row address and column address of a faulty unit in the non-standardized fault group in a row direction and a column direction, respectively, to generate the target fault group, wherein a first value represents a faulty unit and a second value represents a normal unit in the target fault group.

[0193] In some embodiments, the determining module 1610 is further configured to determine a minimum required spare resource of the non-standardized fault group; and if the remaining spare resource is greater than or equal to the minimum required spare resource, standardize the non-standardized fault group to obtain the target fault group. If the remaining spare resource is less than the minimum required spare resource, it indicates that the remaining spare resource is insufficient to repair the faulty units in the chip to be repaired, and the repair work of the chip to be repaired is stopped to save energy consumption.

[0194] In some embodiments, the processing module 1620 is further configured to, if the total number of faulty units in the target fault group is greater than 1, sequentially search for an associated faulty unit in a preset direction order from a starting faulty unit in the target fault group, and calculate a step length from a current faulty unit to a next associated faulty unit, until all the faulty units in the target fault group are completely traversed; and obtain the target path of the target fault group according to the direction and the step length from the current faulty unit to the next associated faulty unit.

[0195] In some embodiments, the processing module 1620 is further configured to obtain a matching library including candidate paths and corresponding candidate repair manners thereof, and determine the target repair manner from the candidate repair manners according to searching the candidate paths from the target path. By setting the matching library, the target repair manner can be directly obtained according to matching the target path with the candidate path when repairing the chip to be repaired, so that the repair time is greatly reduced, the analysis efficiency is improved, and the power consumption is saved.

[0196] In some embodiments, the target path includes a first target path that does not match the candidate path, and the first target path corresponds to a first target fault group. The target fault group includes the first target fault group. The processing module 1620 is further configured to obtain a fault row number m' and a fault column number n' of the first target fault group, where m' and n' are positive integers. If the fault column number of the first target fault group is greater than the fault row number, the spare columns in the spare resource are used to repair the fault columns in the first target fault group, and the number of spare columns decreases from n' to 0 according to the repair times. After each repair using the spare columns, the spare rows in the spare resource are used to repair the remaining fault units in the first target fault group that are not repaired by the spare columns. It is ensured that all fault units can be completely repaired.

[0197] In some embodiments, the target fault group includes a first target fault group and a second target fault group. The target repair manner of the first target fault group includes a first-level target repair manner, and the repair manner of the second target fault group includes a second-level target repair manner. The number of required spare resources in the first-level target repair manner is the same, and the number of required spare resources in the second-level target repair manner is the same. The processing module 1620 is further configured to combine the first-level target repair manner and the second-level target repair manner to obtain a first required spare row resource number and a first required spare column resource number of the chip to be repaired, obtain a remaining spare row resource number and a remaining column resource number in the remaining spare resource, and determine that the target repair manner includes the first-level target repair manner and the second-level target repair manner if the first required spare row resource number is less than or equal to the remaining spare row resource number and the first required spare column resource number is less than or equal to the remaining column resource number. The number of required spare resources can be obtained to be the least, and the use amount of spare resources is saved.

[0198] In some embodiments, the first target fault group further includes a third level target repair mode, the required spare resources in the third level target repair mode are the same in number, and the required spare resources in the third level target repair mode are greater than the required spare resources in the first level target repair mode. The processing module 1620 is further configured to combine the third level target repair mode and the second level target repair mode to obtain a second required spare row resource number and a second required spare column resource number of the chip to be repaired, if the first required spare row resource number is greater than the remaining spare row resource number, or the first required spare column resource number is greater than the remaining spare column resource number; and determine that the target repair mode includes the third level target repair mode and the second level target repair mode, if the second required spare row resource number is less than or equal to the remaining spare row resource number, and the second required spare column resource number is less than or equal to the remaining spare column resource number.

[0199] In summary, the device for chip repair in the embodiments of the present disclosure can efficiently and accurately find out a repair scheme under limited spare resources, reduce the time cost of analysis, and improve productivity, by the processing module 1620 obtaining the target path of the target fault group and the target repair mode matched with the target path.

[0200] The embodiments of the present disclosure further provide a computer device. As shown in Figure 17 The computer device in the embodiments of the present disclosure can include one or more processors 1701, a memory 1702, and an input output interface 1703. The processor 1701 is connected with the memory 1702 and the input output interface 1703, as shown in Figure 9 The processor 1701, the memory 1702, and the input output interface 1703 are connected through a bus 1704. The memory 1702 is configured to store a computer program, and the computer program includes program instructions. The input output interface 1703 is configured to receive and output data, such as to perform data interaction between a host and the computer device, or to perform data interaction between virtual machines in the host. The processor 1701 is configured to execute the program instructions stored in the memory 1702.

[0201] The processor 1701 can perform the following operations: determining a target fault group in a chip to be repaired, each target fault group including at least one faulty unit; obtaining a target path of the target fault group; obtaining a target repair mode of the target fault group according to the target path; and obtaining a target repair mode of the chip to be repaired according to the target repair mode of the target fault group.

[0202] In some feasible implementations, the processor 1701 may be a central processing unit (CPU) 1620. The processor may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0203] The memory 1702 may include read-only memory and random access memory, and provides instructions and data to the processor 1701 and input / output interface 1703. A portion of the memory 1702 may also include non-volatile random access memory. For example, the memory 1702 may also store device type information.

[0204] In practice, the computer device can execute the implementation methods provided by each step in any of the above method embodiments through its built-in functional modules. For details, please refer to the implementation methods provided by each step in the figure shown in the above method embodiments, which will not be repeated here.

[0205] This disclosure provides a computer device including a processor 1701, an input / output interface 1703, and a memory 1702. The processor 1701 obtains a computer program from the memory 1702 and executes the steps of the method shown in any of the above embodiments.

[0206] This disclosure also provides a computer-readable storage medium 1800, such as... Figure 18 As shown, the computer-readable storage medium 1800 stores a computer program that is adapted to be loaded by the processor 1701 and executed by the chip repair method provided in each step of any of the above embodiments. For details, please refer to the implementation of each step in any of the above embodiments, which will not be repeated here.

[0207] Furthermore, the beneficial effects of using the same method will not be repeated here. For technical details not disclosed in the embodiments of the computer-readable storage medium 1800 involved in this disclosure, please refer to the description of the method embodiments of this disclosure. As an example, a computer program may be deployed to execute on a single computer device, or on multiple computer devices located in one location, or on multiple computer devices distributed in multiple locations and interconnected via a communication network.

[0208] The computer readable storage medium 1800 can be an internal storage unit of the computer device provided in any of the foregoing embodiments, for example, a hard disk or a memory of the computer device. The computer readable storage medium 1800 can also be an external storage device of the computer device, for example, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, and the like equipped on the computer device. Further, the computer readable storage medium 1800 can include both an internal storage unit and an external storage device of the computer device. The computer readable storage medium 1800 is used to store the computer program and other programs and data required by the computer device. The computer readable storage medium 1800 can also be used to temporarily store data that has been output or will be output.

[0209] The embodiments of the present disclosure further provide a computer program product or computer program, which includes computer instructions stored in the computer readable storage medium 1800. The processor of the computer device reads the computer instructions from the computer readable storage medium 1800, and the processor executes the computer instructions, so that the computer device executes the method provided in any of the various optional manners of the foregoing embodiments.

[0210] The computer device, the computer readable storage medium, and the computer program product or computer program provided by the embodiments of the present disclosure can obtain the target path of the target fault group of the chip to be repaired and the target repair mode matched with the target path, efficiently and accurately find out the repair scheme under limited spare resources, reduce the time cost of analysis, and improve productivity.

[0211] It should be understood that the present disclosure does not limit its application to the detailed structure and arrangement of the components set forth in the specification. The present disclosure can have other embodiments and can be implemented and executed in various ways. The foregoing variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in the specification extends to all alternative combinations of two or more individual features mentioned or obvious from the text and / or drawings. All these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments described in the specification illustrate the best mode currently known for implementing the present disclosure and will enable a person skilled in the art to utilize the present disclosure.

Claims

1. A method for chip repair, comprising: determining target fault groups in a chip to be repaired, each target fault group comprising at least one faulty cell; obtaining target paths of the target fault groups; obtaining target repair manners of the target fault groups according to the target paths; obtaining a target repair manner of the chip to be repaired according to the target repair manners of the target fault groups; wherein determining the target fault groups in the chip to be repaired comprises: obtaining faulty cells in the chip to be repaired; determining necessary repair faulty cells from the faulty cells; repairing the necessary repair faulty cells using spare resources to obtain remaining spare resources; and grouping remaining faulty cells other than the necessary repair faulty cells to obtain the target fault groups.

2. The method of claim 1, wherein grouping the remaining faulty cells other than the necessary repair faulty cells to obtain the target fault groups comprises: grouping the remaining faulty cells having the same row address or the same column address into a non-standardized fault group; and standardizing the non-standardized fault group to obtain the target fault group.

3. The method of claim 2, wherein grouping the remaining faulty cells having the same row address or the same column address into a non-standardized fault group comprises: constructing a first non-standardized fault group and determining a first grouping information list of the first non-standardized fault group; obtaining a row address and a column address of a first remaining faulty cell; adding the row address and the column address of the first remaining faulty cell to the first grouping information list if the first grouping information list is empty or the row address or the column address of a second remaining faulty cell already existing in the first grouping information list is the same as the row address or the column address of the first remaining faulty cell; constructing a second non-standardized fault group and determining a second grouping information list of the second non-standardized fault group if the row address and the column address of the second remaining faulty cell are different from the row address and the column address of the first remaining faulty cell; wherein the non-standardized fault group comprises the first non-standardized fault group and the second non-standardized fault group, and the remaining faulty cells comprise the first remaining faulty cell and the second remaining faulty cell.

4. The method of claim 2, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ standardizing the non-standardized fault group to obtain the target fault group, comprising: arranging the target fault group in ascending order in the row direction and the column direction of the target fault group according to the row address and the column address of the fault units in the non-standardized fault group, to generate the target fault group, wherein the target fault group uses a first value to represent a fault unit and a second value to represent a normal unit.

5. The method of claim 4, wherein standardizing the non-standardized fault group to obtain the target fault group, comprising: determining the minimum required spare resource of the non-standardized fault group; if the remaining spare resource is greater than or equal to the minimum required spare resource, standardizing the non-standardized fault group to obtain the target fault group.

6. The method of claim 1, wherein obtaining the target path of the target fault group, comprising: if the total number of fault units in the target fault group is greater than 1, starting from a starting fault unit in the target fault units, sequentially searching for associated fault units in a preset direction order for each fault unit in the target fault group, and calculating the step length from the current fault unit to the associated next fault unit, until all fault units in the target fault group are completely traversed; obtaining the target path of the target fault group according to the direction from the current fault unit to the associated next fault unit and the step length.

7. The method of claim 1, wherein obtaining the target repair mode of the target fault group according to the target path, comprising: obtaining a matching library, the matching library comprising candidate paths and their corresponding candidate repair modes; searching for the candidate paths according to the target path, and determining the target repair mode from the candidate repair modes.

8. The method of claim 7, wherein the target path includes a first target path that does not match the candidate path, the first target path corresponds to a first target fault group, and the target fault group includes the first target fault group; wherein obtaining the target repair mode of the target fault group according to the target path further comprises: obtaining the number of fault rows m' and the number of fault columns n' of the first target fault group, wherein m' and n' are both positive integers; if the number of fault columns of the first target fault group is greater than the number of fault rows, using a spare column in the spare resource to repair the fault columns in the first target fault group, and the number of spare columns decreases by repair times from n' to 0, and after each repair using the spare column, using a spare row in the spare resource to repair the remaining fault units in the first target fault group that have not been repaired by the spare column.

9. The method of claim 1, wherein the target fault group includes a first target fault group and a second target fault group, the target repair mode of the first target fault group includes a first-level target repair mode, and the repair mode of the second target fault group includes a second-level target repair mode. The first target repair mode and the second target repair mode are combined to obtain a first required spare row resource quantity and a first required spare column resource quantity of the chip to be repaired. The target repair mode of the target fault group is obtained according to the target repair mode of the target fault group. The first target repair mode and the second target repair mode are combined to obtain a first required spare row resource quantity and a first required spare column resource quantity of the chip to be repaired. The first target repair mode and the second target repair mode are combined to obtain a first required spare row resource quantity and a first required spare column resource quantity of the chip to be repaired.

10. The method of claim 9, wherein The first target fault group further comprises a third target repair mode, the required spare resources in the third target repair mode are the same, and the required spare resources in the third target repair mode are greater than the required spare resources in the first target repair mode. The target repair mode of the target fault group is obtained according to the target repair mode of the target fault group. If the first required spare row resource quantity is greater than the remaining spare row resource quantity, or the first required spare column resource quantity is greater than the remaining spare column resource quantity, the third target repair mode and the second target repair mode are combined to obtain a second required spare row resource quantity and a second required spare column resource quantity of the chip to be repaired. If the second required spare row resource quantity is less than or equal to the remaining spare row resource quantity, and the second required spare column resource quantity is less than or equal to the remaining spare column resource quantity, it is determined that the target repair mode comprises the third target repair mode and the second target repair mode.

11. An apparatus for chip repair, comprising: A determination module is configured to determine a target fault group in a chip to be repaired, each target fault group comprising at least one faulty unit. A processing module is configured to obtain a target path of the target fault group. The processing module is further configured to obtain a target repair mode of the target fault group according to the target path. The processing module is further configured to obtain a target repair mode of the chip to be repaired according to the target repair mode of the target fault group. The target fault group in the chip to be repaired is determined, comprising: A faulty unit in the chip to be repaired is obtained. A mandatory repair faulty unit is determined from the faulty unit. The mandatory repair faulty unit is repaired using spare resources to obtain remaining spare resources. The remaining faulty units other than the mandatory repair faulty unit are grouped to obtain the target fault group. The mandatory repair faulty unit is determined from the faulty unit, comprising: A spare row and a spare column in the spare resources are obtained. ​ ​ if the number of the spare columns is greater than the number of the spare rows, obtaining a must-repair faulty column in the chip to be repaired, the must-repair faulty cells including faulty cells in the must-repair faulty column, and the number of the faulty cells in the must-repair faulty column being greater than the number of the spare rows; if the number of the spare rows is greater than the number of the spare columns, obtaining a must-repair faulty row in the chip to be repaired, the must-repair faulty cells including faulty cells in the must-repair faulty row, and the number of the faulty cells in the must-repair faulty row being greater than the number of the spare columns.

12. A computer device, characterized in that, comprising a processor, a memory, and an input / output interface; the input / output interface is configured to receive and output data, the memory is configured to store a computer program, and the processor is configured to invoke the computer program, so that the computer device executes the method in any one of claims 1 to 10.

13. A computer readable storage medium, characterized in that, the computer readable storage medium stores a computer program, and the computer program is adapted to be loaded and executed by a processor, so that a computer device with the processor executes the method in any one of claims 1 to 10.

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