Semiconductor structure preparation method and device, and semiconductor structure

Abstract

The application relates to a semiconductor structure preparation method and device and a semiconductor structure. The semiconductor structure preparation method comprises the following steps: according to preset parameters of a first trench on a chip in an initial wafer, a first semiconductor machine is controlled to form a second trench on the initial wafer according to preset rules, so that the warping of the initial wafer is towards the same direction; the extension direction of the second trench is perpendicular to the extension direction of the first trench; the warping degree of the initial wafer is obtained; in the case that the warping degree is greater than or equal to a warping threshold value, an initial stress combination is determined according to the warping state and the warping degree of the initial wafer; a second semiconductor machine is controlled to form a target layer on the initial wafer according to the initial stress combination, the target layer is used for providing a target stress combination to the initial wafer, and the target stress combination at least partially offsets the warping stress of the initial wafer. The warping of the initial wafer is towards the same direction through the first trench and the second trench which are perpendicular to each other, and the warping problem is simplified.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a semiconductor structure preparation method and device and a semiconductor structure. BACKGROUND

[0002] In the manufacturing process of a semiconductor wafer, wafer warpage is a key parameter affecting wafer stability and product yield. After different processes such as etching or thin film deposition, the wafer will warp to different degrees. In the current semiconductor process, the wafer warpage is first monitored, and then adjusted in the subsequent process to keep the wafer flat.

[0003] However, different process methods will cause different wafer warping directions and warping degrees, resulting in complex process steps to solve the wafer warping problem and low efficiency. SUMMARY

[0004] Based on the necessity to solve the problems in the background art, a semiconductor structure preparation method, device and semiconductor structure are provided, which unifies the warping shape in the wafer preparation process and then offsets the warping stress, thereby improving the efficiency, yield and reliability of the prepared wafer.

[0005] To achieve the above object and other objects, according to various embodiments of the present application, a first aspect of the present application provides a semiconductor structure preparation method, comprising: according to preset parameters of a first trench on a chip in an initial wafer, controlling a first semiconductor machine to form a second trench on the initial wafer according to a preset rule, so that the warping of the initial wafer is towards the same direction; the extension direction of the second trench is perpendicular to the extension direction of the first trench; obtaining the warping degree of the initial wafer, and in the case that the warping degree is greater than or equal to a warping threshold, determining an initial stress combination according to the warping state and the warping degree of the initial wafer; controlling a second semiconductor machine to form a target layer on the initial wafer according to the initial stress combination, the target layer being used to provide a target stress combination to the initial wafer, and the target stress combination at least partially offsetting the warping stress of the initial wafer.

[0006] In the semiconductor structure preparation method of the above embodiment, first, according to preset parameters of the first trench on the chip in the initial wafer, a first semiconductor machine is controlled to form a second trench on the initial wafer according to preset rules, and the extension direction of the second trench is perpendicular to the extension direction of the first trench. During the wafer preparation process, etching the second trench will cause the initial wafer to curl along the extension direction of the second trench, and the second trench is perpendicular to the first trench, so the stress of the two trenches counteracts each other, causing the initial wafer to warp in the same direction. Then, the warping degree of the initial wafer is obtained, and in the case that the warping degree is greater than or equal to a warping threshold, an initial stress combination is determined according to the warping state and the warping degree of the initial wafer, and a second semiconductor machine is controlled to form a target layer on the initial wafer according to the initial stress combination. The target layer is used to provide a target stress combination to the initial wafer, and the target stress combination at least partially offsets the warping stress of the initial wafer. Compared with the traditional process which needs to identify the warping direction of the wafer first and then adjust the warping degree, the semiconductor structure preparation method of the embodiment simplifies the warping problem by directing the warping of the initial wafer in the same direction through the first trench and the second trench perpendicular to each other, reduces the process steps, and improves the efficiency of preparing the wafer. The embodiment also improves the warping problem of the initial wafer, avoids the problem of fragments caused by warping, and improves the yield and reliability of the prepared wafer.

[0007] In some embodiments, the first semiconductor machine is controlled to generate the initial wafer according to preset parameters and preset rules, including generating a target layout according to preset parameters and preset rules, the target layout having a first trench pattern and a second trench pattern, the first trench pattern being used to define the first trench of the initial wafer, and the second trench pattern being used to define the second trench of the initial wafer; and the first semiconductor machine is controlled to generate the initial wafer according to the target layout, so as to direct the warping of the initial wafer in the same direction, simplify the warping problem, reduce the process steps, and improve the efficiency of preparing the wafer.

[0008] In some embodiments, the first trench extends along a first direction and is spaced apart along a second direction; the second trench is located in a scribe lane of the initial wafer; the second trench extends along the second direction and is spaced apart along the first direction; the preset parameters include the width of the first trench and the spacing of the first trenches adjacent along the second direction; the width of the second trench pattern is associated with the width of the first trench, and the spacing of the second trench patterns adjacent along the first direction is associated with the spacing of the first trenches adjacent along the second direction; the second trench pattern has a first preset spacing from the adjacent chip region; and the second trench pattern between the chip regions adjacent along the first direction has a second preset spacing from the second trench pattern between the chip regions adjacent along the second direction.

[0009] In some embodiments, the second grooves are located on the chip; the first grooves include first reference grooves located on opposite sides of the reference structure along the second direction, the first reference grooves extending along the first direction and being spaced apart along the second direction; the second grooves include first target grooves located on opposite sides of the reference structure along the first direction, the first target grooves extending along the second direction and being spaced apart along the first direction; or the first grooves include second reference grooves located on opposite sides of the reference structure along the first direction, the second reference grooves extending along the second direction and being spaced apart along the first direction; the second grooves include second target grooves located on opposite sides of the reference structure along the second direction, the second target grooves extending along the first direction and being spaced apart along the second direction. The first grooves and the second grooves of the chip region are perpendicular to each other, the warping of the initial wafer is directed to the same direction, the warping problem is simplified, the process steps are reduced, and the efficiency of preparing the wafer is improved.

[0010] In some embodiments, controlling the second semiconductor machine to form the target layer on the back surface of the initial wafer according to the initial stress combination includes determining a material type and / or a thickness of the target layer according to the initial stress combination; and controlling the second semiconductor machine to form the target layer with the material type and the thickness on the back surface of the initial wafer.

[0011] In some embodiments, the target layer includes an oxide film; and controlling the second semiconductor machine to form the target layer on the initial wafer according to the initial stress combination includes: controlling the second semiconductor machine to form the oxide film on the back surface of the initial wafer according to the initial stress combination, the oxide film being used to provide a target stress combination to the initial wafer, the target stress combination being associated with the initial stress combination. The warping stress of the front surface of the initial wafer is offset by the target stress combination, so that the warping state of the initial wafer is adjusted by the target stress combination acting on the initial wafer through the oxide film.

[0012] In some embodiments, the target stress combination includes a first suction force for being applied to a middle region of the initial wafer, and a second suction force for being applied to an edge region of the initial wafer; the edge region surrounds the middle region; the first suction force is smaller than the second suction force, so as to generate a compressive stress on the back surface of the initial wafer, which is directed from the edge to the center, offsetting the warping stress of the front surface of the initial wafer, improving the warping problem of the initial wafer, avoiding the wafer breakage caused by the warping, and improving the yield and reliability of the prepared wafer.

[0013] In some embodiments, obtaining the warping degree of the initial wafer includes: obtaining distance data between a plurality of measurement points on the initial wafer and a warping detection probe; wherein the measurement points are distributed at least in a center region and an edge region of the initial wafer; and determining the warping state of the initial wafer according to the distance data, and calculating the warping degree.

[0014] The second aspect of the present application provides a semiconductor structure preparation device, comprising an initial wafer generation module, a stress combination determination module, and a target wafer generation module. The initial wafer generation module is configured to control a first semiconductor machine to generate an initial wafer according to preset parameters of a first trench on a chip of the initial wafer and a preset rule. The initial wafer has a first trench and a second trench formed thereon. The extension direction of the second trench is perpendicular to the extension direction of the first trench. The stress combination determination module is configured to obtain a warping degree of the initial wafer. In a case where the warping degree is greater than or equal to a warping threshold, the initial stress combination is determined according to a warping state and the warping degree of the initial wafer. The target wafer generation module is configured to control a second semiconductor machine to form a target layer on the initial wafer according to the initial stress combination. The target layer is configured to provide a target stress combination to the initial wafer. The target stress combination at least partially offsets the warping stress of the initial wafer.

[0015] In the semiconductor structure preparation device of the above embodiment, the initial wafer generation module forms the first trench and the second trench on the initial wafer. The first trench and the second trench perpendicular to each other balance the stress in the initial wafer, so that the warping of the initial wafer is towards the same direction. The target wafer generation module forms the target layer on the initial wafer to provide the target stress combination to the initial wafer, which partially offsets the warping stress of the initial wafer and improves the warping degree of the initial wafer. The semiconductor structure preparation device of the present embodiment balances the warping of the initial wafer towards the same direction by the first trench and the second trench perpendicular to each other, simplifies the warping problem, reduces the process steps, and improves the efficiency of preparing the wafer. The present embodiment also improves the warping problem of the initial wafer, avoids the fragmentation problem caused by the warping, and improves the yield and reliability of the prepared wafer.

[0016] The third aspect of the present application provides a semiconductor structure, comprising an initial wafer. A first trench is formed on a chip in the initial wafer. A second trench is formed in the initial wafer to make the warping of the initial wafer towards the same direction. The extension direction of the second trench is perpendicular to the extension direction of the first trench.

[0017] In the semiconductor structure of the above embodiment, the first trench and the second trench are formed on the initial wafer. The extension direction of the second trench is perpendicular to the extension direction of the first trench. The warping of the initial wafer is towards the same direction, which simplifies the warping problem, reduces the process steps, and improves the efficiency of preparing the wafer. The target layer provides the target stress combination to the initial wafer, which at least partially offsets the warping stress of the initial wafer, improves the warping problem of the initial wafer, avoids the fragmentation problem caused by the warping, and improves the yield and reliability of the prepared wafer. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor based on these drawings.

[0019] Figure 1 A flowchart of a semiconductor structure preparation method provided in an embodiment of the present application;

[0020] Figure 2 A semiconductor structure layout of a semiconductor structure preparation method provided in an embodiment of the present application;

[0021] Figure 3 A schematic diagram of a semiconductor structure preparation method provided in an embodiment of the present application;

[0022] Figure 4 A semiconductor structure layout of a semiconductor structure preparation method provided in another embodiment of the present application;

[0023] Figure 5 A semiconductor structure layout of a semiconductor structure preparation method provided in another embodiment of the present application;

[0024] Figure 6 A schematic diagram of a semiconductor structure preparation method provided in another embodiment of the present application;

[0025] Figure 7 An architectural schematic diagram of a semiconductor structure preparation device provided in an embodiment of the present application; the description of the reference signs is as follows:

[0026] 10, chip region; 11, first trench pattern; 20, scribe lane region; 21, second trench pattern; 30, initial wafer; 100, semiconductor structure preparation device; 110, initial wafer generation module; 120, stress combination determination module; 130, target wafer generation module; 12, first reference trench pattern; 22, first target trench pattern; 13, second reference trench pattern; 23, second target trench pattern. DETAILED DESCRIPTION

[0027] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the related drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms, and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0029] In the case of using "include", "have", and "contain" described herein, unless an explicit limiting term is used, such as "only", "consisting of", and the like, another component can be added. Unless otherwise mentioned, the singular form of the term can include the plural form and cannot be understood as the number of one.

[0030] In this application, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting", "fixing" and the like should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0031] In addition, the terms "first", "second", and the like are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated.

[0032] In the wafer preparation process, with the deep trench etching of the wafer surface and the accumulation of various thin films, various stresses will be generated on the wafer surface. The stress direction and size caused by different processes and thin films are different. Affected by the uneven stress, the wafer will form various asymmetric warping. Wafer warping can cause many problems, such as nitrogen oxygen stack layer falling off, wafer cracking, pattern misalignment, and poor photolithography precision; and in etching, thinning and other processes that require adsorption of wafers, warping will cause problems such as wafer fragments or process failure due to the inability to fix the wafer. Therefore, in the wafer preparation process, the problem of warping needs to be solved urgently.

[0033] Different process methods and thin film deposition produce different stress directions and sizes, resulting in different wafer warping directions and warping degrees. Such different warping forms also increase the complexity of the problem. The traditional process needs to identify the warping direction of the wafer first, and then adjust the warping degree. The process steps are complex and the efficiency is low.

[0034] Based on this, please refer to Figure 1 The embodiment provides a semiconductor structure preparation method, which comprises the following steps:

[0035] Step S202: According to the preset parameters of the first trench on the chip in the initial wafer, a second trench is formed on the initial wafer by the first semiconductor machine according to the preset rule, so that the warping of the initial wafer is towards the same direction; the extension direction of the second trench is perpendicular to the extension direction of the first trench;

[0036] Step S204: Obtain the warping degree of the initial wafer, and determine the initial stress combination according to the warping state and the warping degree of the initial wafer when the warping degree is greater than or equal to the warping threshold.

[0037] Step S206: Form a target layer on the initial wafer according to the initial stress combination, the target layer is used to provide a target stress combination to the initial wafer, and the target stress combination at least partially offsets the warping stress of the initial wafer.

[0038] As an example, please refer to Figure 1 The semiconductor structure preparation method of the embodiment can control the first semiconductor machine to form a second trench on the initial wafer according to the preset parameters of the first trench on the chip in the initial wafer and according to the preset rule, and the extension direction of the second trench is perpendicular to the extension direction of the first trench. During the preparation of the wafer, etching the second trench will cause the initial wafer to curl along the direction in which the second trench extends, and the second trench is perpendicular to the first trench, so the stresses of the two trenches balance each other, causing the warping of the initial wafer to be towards the same direction, for example, the warping of the initial wafer is upwards and presents a bowl-shaped structure in which the middle region is concave downwards and the edge region is curved upwards. Then, the warping degree of the initial wafer is obtained, and the initial stress combination is determined according to the warping state and the warping degree of the initial wafer when the warping degree is greater than or equal to the warping threshold. The target layer is formed on the initial wafer according to the initial stress combination, the target layer is used to provide a target stress combination to the initial wafer, and the target stress combination at least partially offsets the warping stress of the initial wafer. Compared with the traditional process which needs to identify the warping direction of the initial wafer and then adjust the warping degree, the semiconductor structure preparation method of the embodiment can simplify the warping problem by making the warping of the initial wafer towards the same direction through the first trench and the second trench which are perpendicular to each other, reduce the process steps, and improve the efficiency of preparing the wafer. The embodiment also improves the warping problem of the initial wafer, avoids the problem of fragments caused by warping, and improves the yield and reliability of the prepared wafer.

[0039] In some embodiments, the step S202 of controlling the first semiconductor machine to generate the initial wafer according to the preset parameters and according to the preset rule includes:

[0040] Step S2021: Generate a target layout according to the preset parameters and according to the preset rule, the target layout has a first trench pattern and a second trench pattern, the first trench pattern is used to define the first trench of the initial wafer, and the second trench pattern is used to define the second trench of the initial wafer.

[0041] Step S2022: generating the initial wafer according to the target layout by controlling the first semiconductor machine.

[0042] In some embodiments, referring to Figure 2 , the first trenches extend along the first direction and are spaced along the second direction; the second trenches are located in the scribe lanes of the initial wafer; the second trenches extend along the second direction and are spaced along the first direction; the preset parameters include the width of the first trenches and the spacing of the first trenches adjacent along the second direction; the width of the second trench pattern 21 is related to the width of the first trenches, and the spacing of the second trench patterns 21 adjacent along the first direction is related to the spacing of the first trenches adjacent along the second direction; the second trench pattern 21 has a first preset spacing from the adjacent chip region 10; the second trench pattern 21 between the chip regions 10 adjacent along the first direction has a second preset spacing from the chip regions 10 adjacent along the second direction; the first preset spacing can be set to be greater than the second preset spacing.

[0043] In some embodiments, the step S202 of generating the initial wafer according to the preset parameters and the preset rules by controlling the first semiconductor machine includes:

[0044] Step S2021a: generating a target layout according to preset parameters and preset rules, the chip region of the target layout has a first trench pattern, and the scribe lane region of the target layout has a second trench pattern, the first trench pattern is used to define the first trench of the initial wafer, and the second trench pattern is used to define the second trench of the initial wafer;

[0045] Step S2022: generating the initial wafer according to the target layout by controlling the first semiconductor machine.

[0046] As an example, referring to Figures 2-3 , the embodiment generates a target layout according to preset parameters and preset rules, the chip region 10 of the target layout has a first trench pattern 11, and the scribe lane region 20 of the target layout has a second trench pattern 21, the first trench pattern 11 is used to define the first trench of the initial wafer 30, and the second trench pattern 21 is used to define the second trench of the initial wafer 30, the initial wafer 30 generated according to the target layout has the first trench of the chip region and the second trench of the scribe lane region perpendicular to each other, the warping of the initial wafer 30 is directed to the same direction, the warping problem is simplified, the process steps are reduced, and the efficiency of preparing the wafer is improved.

[0047] As an example, referring to Figure 2 , the width of the second trench pattern 21 is approximately equal to the width of the first trench, and the spacing of the second trench patterns 21 adjacent along the first direction is approximately equal to the spacing of the first trenches adjacent along the second direction.

[0048] In some embodiments, please continue to refer to Figure 2 , the pitch of the first trenches adjacent along the second direction is 9.5-10.5 μm, for example, the pitch of the first trenches adjacent along the second direction can be 9.5 μm, 9.6 μm, 9.7 μm, 9.8 μm, 9.9 μm, 10.0 μm, 10.1 μm, 10.2 μm, 10.3 μm, 10.4 μm or 10.5 μm, and the like; the pitch of the second trenches and the adjacent chips is 9.5-10.5 μm, for example, the pitch of the second trenches and the adjacent chips can be 9.5 μm, 9.6 μm, 9.7 μm, 9.8 μm, 9.9 μm, 10.0 μm, 10.1 μm, 10.2 μm, 10.3 μm, 10.4 μm or 10.5 μm, and the like; the pitch of the second trenches between the chips adjacent along the first direction and the second trenches between the chips adjacent along the second direction is 4.5-5.5 μm, for example, the pitch of the second trenches between the chips adjacent along the first direction and the second trenches between the chips adjacent along the second direction can be 4.5 μm, 4.6 μm, 4.7 μm, 4.8 μm, 4.9 μm, 5.0 μm, 5.1 μm, 5.2 μm, 5.3 μm, 5.4 μm or 5.5 μm, and the like.

[0049] In some embodiments, the second trenches are located on the chips; the first trenches include first reference trenches located on opposite sides of the reference structure along the second direction, the first reference trenches extend along the first direction and are spaced apart along the second direction; the second trenches include first target trenches located on opposite sides of the reference structure along the first direction, the first target trenches extend along the second direction and are spaced apart along the first direction. The first direction can be the ox direction, and the second direction can be the oy direction. The reference structure includes a gate pad. The initial wafer is perpendicular to the first trenches and the second trenches in the chip region, the warping of the initial wafer is directed to the same direction, which simplifies the warping problem, reduces the process steps, and improves the efficiency of preparing the wafer.

[0050] As an example, please refer to Figure 4 , in step S202, the initial wafer is generated by the first semiconductor machine according to the preset parameters and the preset rules, including:

[0051] Step S2021b: generating a target layout according to the preset parameters and the preset rules, the chip region of the target layout has a first reference trench pattern 12 and a first target trench pattern 22, the first reference trench pattern 12 is used to define the first reference trench of the initial wafer, and the first target trench pattern 22 is used to define the first target trench of the initial wafer;

[0052] Step S2022: generating the initial wafer by the first semiconductor machine according to the target layout.

[0053] In some embodiments, the second trenches are located on the chip; the first trenches include second reference trenches located on opposite sides of the reference structure along a first direction, the second reference trenches extending along a second direction and being spaced apart along the first direction; the second trenches include second target trenches located on opposite sides of the reference structure along the second direction, the second target trenches extending along the first direction and being spaced apart along the second direction. The first direction can be the ox direction, and the second direction can be the oy direction. The initial wafer has the first trenches and the second trenches of the chip region perpendicular to each other, so that the warping of the initial wafer is directed to the same direction, simplifying the warping problem, reducing the process steps, and improving the efficiency of preparing the wafer.

[0054] As an example, refer to Figure 5 In step S202, the first semiconductor machine is controlled according to the preset parameters and the preset rules to generate an initial wafer, including:

[0055] Step S2021c: generating a target layout according to the preset parameters and the preset rules, the chip region of the target layout having a second reference trench pattern 13 and a second target trench pattern 23, the second reference trench pattern 13 being used to define the second reference trenches of the initial wafer, and the second target trench pattern 23 being used to define the second target trenches of the initial wafer.

[0056] Step S2022: controlling the first semiconductor machine to generate the initial wafer according to the target layout.

[0057] In some embodiments, refer to Figure 3 In step S204, the warping degree of the initial wafer 30 is obtained by obtaining distance data between a plurality of measurement points on the initial wafer 30 and a warping detection probe; wherein the measurement points are distributed at least in the central region and the edge region of the initial wafer 30; the warping state of the initial wafer is determined according to the distance data, and the warping degree is calculated.

[0058] In some embodiments, refer to Figure 3 In step S204, if the warping degree is less than a preset threshold, the initial wafer 30 does not need to be improved in warping degree, and the small warping will not affect the subsequent process.

[0059] In some embodiments, refer to Figure 6 In step S206, the second semiconductor machine is controlled to form a target layer on the back surface of the initial wafer 30 according to the initial stress combination, including: determining the material type and / or thickness of the target layer according to the initial stress combination; controlling the second semiconductor machine to form the target layer with the material type and the thickness on the back surface of the initial wafer. In some embodiments, refer to Figure 4, the target layer includes an oxide film; forming the target layer on the initial wafer 30 by the second semiconductor machine according to the initial stress combination includes: forming the oxide film on the back surface of the initial wafer 30 by the second semiconductor machine according to the initial stress combination, the oxide film is used to provide the initial wafer 30 with a target stress combination, the target stress combination is associated with the initial stress combination. As an example, please continue to refer to Figure 4 , forming the oxide film on the back surface of the initial wafer 30 by the second semiconductor machine according to the initial stress combination includes: placing the initial wafer 30 in a closed chamber, and clamping the initial wafer 30 by a clamping device, the back surface of the initial wafer 30 is provided with a plasma generating device in the direction where the oxide film needs to be formed, so as to form the oxide film on the back surface of the initial wafer 30, a heating and protection module is provided on the side of the front surface of the initial wafer 30 where the oxide film does not need to be formed, the initial wafer 30 is heated to maintain the temperature required for the deposition of the oxide film, and a protection gas is provided on the front surface of the initial wafer 30 to prevent the formation of unnecessary oxide film on the front surface of the initial wafer 30, and a plasma enhanced chemical vapor deposition process can be used to form the oxide film. The oxide film can be a silicon dioxide film, a silicon hydroxide film, a silicon nitride film or other dielectric material film such as a high temperature nylon film.

[0060] As an example, please continue to refer to Figure 6 , the oxide film is used to provide the initial wafer 30 with a target stress combination, specifically: the main cause of the warping of the initial wafer 30 is stress, and the oxide film will generate a controllable target stress combination during the formation process, after the oxide film is formed on the back surface of the initial wafer 30, the corresponding target stress combination can be applied to the back surface of the initial wafer 30, and the warping stress of the front surface of the initial wafer 30 can be offset by using the target stress combination, so as to adjust the warping state of the initial wafer 30 by the target stress combination applied by the oxide film. The target stress combination is approximately equal to the initial stress combination.

[0061] Table 1: Improvement amount of BOW value of USG and HTN with different thickness

[0062]

[0063] As an example, please refer to Figure 6 and Table 1, Table 1 shows the improvement amount of the bending degree (BOW) of the initial wafer 30 by undoped silicon dioxide glass (USG) with a thickness of 11 KA, USG with a thickness of 6.8 KA, high temperature nylon (HTN) with a thickness of 6.8 KA and HTN with a thickness of 3.5 KA, the different film quality and film thickness of the oxide film formed on the initial wafer 30 are determined according to the BOW value measured in step S206, so as to adjust the warping state of the initial wafer 30 by the target stress combination applied by the oxide film.

[0064] As an example, warpage refers to the maximum deviation of any location of the wafer from a plane passing through the center of gravity of the wafer installed without external force. The accurate definition of this parameter can be found in the standard ASTM F1390. Bow refers to the maximum deviation of any location of the wafer installed without external force from a plane determined by three points on the wafer. The definition of this parameter can be found in the standard ASTM F534. Bow is usually included in warpage and cannot be greater than warpage.

[0065] In some embodiments, please refer to Figure 6 , the target stress combination includes a first suction force for applying to a middle region of the initial wafer 30, and a second suction force for applying to an edge region of the initial wafer 30; the edge region surrounds the middle region; the first suction force is smaller than the second suction force. Since the initial wafer 30 is warped upward and the middle region is concave downward and the edge region is curved upward in the same direction, the back surface of the initial wafer 30 is subjected to a tensile stress from the center to the edge. In order to reduce this tensile stress, a larger second suction force can be applied to the edge region of the initial wafer 30 by forming an oxide film on the back surface of the initial wafer 30, and a smaller first suction force can be applied to the middle region of the initial wafer 30, so as to generate a compressive stress from the edge to the center on the back surface of the initial wafer 30, offsetting the warpage stress on the front surface of the initial wafer 30, improving the warpage problem of the initial wafer 30, avoiding the wafer breakage problem caused by warpage, and improving the yield and reliability of the wafer.

[0066] In some embodiments, please refer to Figure 7 , the present application provides a semiconductor structure preparation device 100, including an initial wafer generation module 110, a stress combination determination module 120 and a target wafer generation module 130. The initial wafer generation module 110 is used to control a first semiconductor machine to generate an initial wafer according to a preset parameter of a first trench on the chip of the initial wafer and a preset rule. The initial wafer has a first trench and a second trench formed thereon, and the extension direction of the second trench is perpendicular to the extension direction of the first trench. The stress combination determination module 120 is used to obtain the warpage of the initial wafer, and in the case that the warpage is greater than or equal to a warpage threshold, to determine an initial stress combination according to the warpage state and the warpage of the initial wafer. The target wafer generation module 130 is used to control a second semiconductor machine to form a target layer on the initial wafer according to the initial stress combination. The target layer is used to provide a target stress combination to the initial wafer, and the target stress combination at least partially offsets the warpage stress of the initial wafer.

[0067] As an example, please refer to Figure 7The semiconductor structure preparation device 100 of the embodiment forms the first groove and the second groove on the initial wafer through the initial wafer generation module 110, and the mutually perpendicular first groove and the second groove balance the stress in the initial wafer with each other, so that the warping of the initial wafer is towards the same direction, for example, the warping of the initial wafer is upwards, and the middle region is concave downwards and the edge region is curved upwards in a bowl-shaped structure. Then, the target layer is formed on the initial wafer through the target wafer generation module 130 to provide the target stress combination to the initial wafer to offset the warping stress of the initial wafer and improve the warping degree of the initial wafer. The semiconductor structure preparation device 100 of the embodiment simplifies the warping problem by making the warping of the initial wafer towards the same direction through the mutually perpendicular first groove and the second groove, reduces the process steps, and improves the efficiency of preparing the wafer. The embodiment also improves the warping problem of the initial wafer, avoids the fragmentation problem caused by the warping, and improves the yield and reliability of preparing the wafer.

[0068] In some embodiments, the present application provides a semiconductor structure including an initial wafer, and a first groove formed on a chip in the initial wafer. A second groove is formed in the initial wafer to make the warping of the initial wafer towards the same direction. The extension direction of the second groove is perpendicular to the extension direction of the first groove. As an example, the semiconductor structure of the embodiment forms the first groove and the second groove on the initial wafer, and the extension direction of the second groove is perpendicular to the extension direction of the first groove, so that the warping of the initial wafer is towards the same direction, for example, the warping of the initial wafer is upwards, and the middle region is concave downwards and the edge region is curved upwards in a bowl-shaped structure. The warping problem is simplified, the process steps are reduced, and the efficiency of preparing the wafer is improved. Then, the target layer is formed on the initial wafer to provide the target stress combination to the initial wafer to at least partially offset the warping stress of the initial wafer, improve the warping problem of the initial wafer, avoid the fragmentation problem caused by the warping, and improve the yield and reliability of preparing the wafer.

[0069] As an example, the second groove can be formed on the chip in the initial wafer or in the scribe lane of the initial wafer. For details, refer to the above semiconductor structure preparation method, which will not be described here.

[0070] In some embodiments, the present application also provides a semiconductor structure preparation device, which further includes a computer program. When the computer program is executed by a processor, the steps of any one of the above semiconductor structure preparation methods are implemented.

[0071] In some embodiments, the present application also provides a computer device including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the steps of any one of the above semiconductor structure preparation methods are implemented.

[0072] In some embodiments, the present application also provides a computer readable storage medium, having stored thereon a computer program, which when executed by a processor implements the steps of the method of any one of the above semiconductor structure preparation methods.

[0073] In some embodiments, the present application also provides a computer program product comprising a computer program which when executed by a processor implements the steps of the method of any one of the above semiconductor structure preparation methods.

[0074] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. Any reference to memory, database or other medium in the embodiments provided by the present application can include non-volatile, volatile memory or a combination thereof. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric memory (FRAM), phase change memory (PCM) or graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided by the present application can include a relational database, a non-relational database or a combination thereof. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided by the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device or a data processing logic device based on quantum computing, etc., without being limited thereto.

[0075] Any technical features in the above embodiments can be combined, and for the sake of brevity, not all possible combinations are described above, however, as long as the combinations do not conflict with each other, they should be considered to be within the scope of the present disclosure.

[0076] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the disclosed patent scope. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method of fabricating a semiconductor structure, comprising: Comprise: According to the preset parameters of the first trench on the chip in the initial wafer, a first semiconductor machine is controlled to form a second trench on the initial wafer according to a preset rule, the second trench causes the initial wafer to curl along the direction in which the second trench extends, so that the warping of the initial wafer is towards the same direction; the extension direction of the second trench is perpendicular to the extension direction of the first trench; Obtain the warping degree of the initial wafer, and in the case that the warping degree is greater than or equal to a warping threshold, determine an initial stress combination according to the warping state and warping degree of the initial wafer; According to the initial stress combination, a second semiconductor machine is controlled to form a target layer on the initial wafer, the target layer is used to provide a target stress combination to the initial wafer, and the target stress combination at least partially offsets the warping stress of the initial wafer.

2. The method of claim 1, wherein According to the preset parameters, a first semiconductor machine is controlled to generate the initial wafer according to a preset rule, comprising: According to the preset parameters, a target layout is generated according to a preset rule, the target layout has a first trench pattern and a second trench pattern in it, the first trench pattern is used to define the first trench of the initial wafer, and the second trench pattern is used to define the second trench of the initial wafer; According to the target layout, the first semiconductor machine is controlled to generate the initial wafer.

3. The method of claim 2, wherein the step of forming the semiconductor structure is performed by a method selected from the group consisting of: epitaxial growth, ion implantation, and a combination thereof. The first trench extends along a first direction and is spaced along a second direction; the second trench is located in a scribe lane of the initial wafer; the second trench extends along the second direction and is spaced along the first direction; The preset parameters include the width of the first trench and the pitch of the first trenches adjacent along the second direction; the width of the second trench pattern is related to the width of the first trench, and the pitch of the second trench patterns adjacent along the first direction is related to the pitch of the first trenches adjacent along the second direction; The second trench pattern has a first preset pitch with the adjacent chip region; The second trench pattern between the chip regions adjacent along the first direction has a second preset pitch with the second trench pattern between the chip regions adjacent along the second direction.

4. The method of claim 3, wherein the semiconductor structure is prepared by a method comprising: The second trench is located on the chip; The first trench includes first reference trenches located on opposite sides of a reference structure along the second direction, the first reference trenches extend along the first direction and are spaced along the second direction; the second trench includes first target trenches located on opposite sides of the reference structure along the first direction, the first target trenches extend along the second direction and are spaced along the first direction; Or The first trench includes second reference trenches located on opposite sides of the reference structure along the first direction, the second reference trenches extend along the second direction and are spaced along the first direction; the second trench includes second target trenches located on opposite sides of the reference structure along the second direction, the second target trenches extend along the first direction and are spaced along the second direction.

5. The method of any of claims 1-4, wherein, According to the initial stress combination, a second semiconductor machine is controlled to form a target layer on the back of the initial wafer, comprising: determining a material type and / or a thickness of the target layer according to the initial stress combination; controlling the second semiconductor machine to form the target layer with the material type and thickness on the back surface of the initial wafer.

6. The method of claim 5, wherein the step of forming the semiconductor structure is performed by a method selected from the group consisting of: epitaxial growth, ion implantation, and photolithography. the target layer includes an oxide film; and controlling the second semiconductor machine to form the oxide film on the back surface of the initial wafer according to the initial stress combination, the oxide film being used to provide the initial wafer with the target stress combination associated with the initial stress combination.

7. The method of claim 5, wherein the step of forming the semiconductor structure is performed by a method selected from the group consisting of: epitaxial growth, chemical vapor deposition, physical vapor deposition, and combinations thereof. the target stress combination includes a first attractive force for being applied to a middle region of the initial wafer and a second attractive force for being applied to an edge region of the initial wafer; the edge region surrounds the middle region; the first attractive force is smaller than the second attractive force.

8. The method of claim 1-4, wherein, the obtaining the warpage of the initial wafer includes: obtaining distance data between a plurality of measurement points on the initial wafer and a warpage detection probe; wherein the measurement points are distributed at least in a center region and an edge region of the initial wafer; determining a warpage state of the initial wafer according to the distance data and calculating a warpage.

9. A semiconductor structure fabrication apparatus, characterized in that, including: an initial wafer generating module configured to control a first semiconductor machine to form a second trench on an initial wafer according to a preset parameter of a first trench on a chip in the initial wafer and according to a preset rule, the second trench causing the initial wafer to curl along a direction in which the second trench extends, so that warpage of the initial wafer is directed to the same direction; and the direction in which the second trench extends is perpendicular to a direction in which the first trench extends; a stress combination determining module configured to obtain a warpage of the initial wafer, and determine an initial stress combination according to a warpage state and the warpage of the initial wafer when the warpage is greater than or equal to a warpage threshold; a target wafer generating module configured to control a second semiconductor machine to form a target layer on the initial wafer according to the initial stress combination, the target layer being used to provide the initial wafer with a target stress combination that at least partially offsets a warpage stress of the initial wafer.

10. A semiconductor structure, characterized by an initial wafer in which a first trench is formed on a chip in the initial wafer, and a second trench is formed in the initial wafer to cause warpage of the initial wafer to be directed to the same direction; and the direction in which the second trench extends is perpendicular to a direction in which the first trench extends.

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