An IGBT device and a manufacturing method thereof
By forming deep and shallow trenches in IGBT devices and creating a virtual gate on the inner sidewall of the shallow trench, the problem of increased parasitic capacitance in small-sized IGBT devices is solved, thereby improving switching speed and recovery capability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-12
- Publication Date
- 2026-03-27
AI Technical Summary
As IGBT device size decreases, trench density increases, leading to increased parasitic capacitance, which in turn results in high conduction losses and poor switching recovery capability.
Deep trenches and shallow trenches are formed in a semiconductor substrate, and a virtual gate is formed on the inner sidewall of the shallow trench to reduce the trench depth and number. By forming the gate in the deep trench with a small linewidth in the semiconductor substrate, the capacitance from the gate to the emitter is reduced.
The input capacitance of the IGBT device is reduced, which improves the switching speed and switching recovery capability, and reduces switching losses.
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Figure CN115763248B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to an IGBT device and a manufacturing method thereof. BACKGROUND
[0002] Insulated Gate Bipolar Transistor (IGBT) is a common power device, and an ideal IGBT has the advantages of high breakdown voltage, low on-state voltage drop, short turn-off time, long short-circuit resistance time, etc.
[0003] With the progress of technology, IGBT devices are developing towards small size. On the one hand, as the size of IGBT devices becomes smaller, more chips can be processed on the same wafer to obtain greater benefits; on the other hand, when the pitch of IGBT devices becomes smaller, the density of the trenches becomes larger, and the current density on the same area becomes larger, and the current capacity of the IGBT device is greatly improved. However, the increase in the density of the trenches leads to an increase in the parasitic capacitance of the small-size IGBT device, which in turn leads to a large on-state loss and poor switching recovery capability of the IGBT device.
[0004] Therefore, it is necessary to propose a new IGBT device and a manufacturing method thereof to solve the above technical problems. SUMMARY
[0005] A series of simplified concepts are introduced in the summary section, which will be further described in detail in the specific embodiment section. The summary section of the present application does not mean to attempt to limit the key features and necessary technical features of the claimed technical solution, nor to attempt to determine the protection scope of the claimed technical solution.
[0006] The present application provides a manufacturing method of an IGBT device, comprising the following steps:
[0007] providing a semiconductor substrate, forming a deep trench and a shallow trench in the semiconductor substrate, the line width of the deep trench being smaller than the line width of the shallow trench;
[0008] forming a gate dielectric layer covering the semiconductor substrate, the gate dielectric layer being formed on the bottom and sidewall of the deep trench and the shallow trench;
[0009] forming a gate material layer covering the semiconductor substrate to fill the gate material in the deep trench and the shallow trench;
[0010] etching back the gate material layer to form a gate in the deep trench and a virtual gate on the inner sidewall of the shallow trench.
[0011] Further, the forming the deep trenches and the shallow trenches in the semiconductor substrate comprises:
[0012] forming a patterned mask layer on the semiconductor substrate;
[0013] etching the semiconductor substrate with the patterned mask layer as a mask to form the deep trenches and the shallow trenches in the semiconductor substrate.
[0014] Further, the semiconductor substrate comprises one or more gate regions and one or more dummy gate regions, each of the gate regions comprises at least two adjacent deep trenches, each of the dummy gate regions comprises at least two adjacent shallow trenches, and the gate regions are spaced apart from the dummy gate regions.
[0015] Further, after forming the gate and the dummy gate, the method further comprises the steps of:
[0016] forming a body region and a source / drain region between the adjacent deep trenches; and
[0017] forming a body region between the adjacent shallow trenches.
[0018] Further, after forming the body region and the source / drain region, the method further comprises the steps of:
[0019] forming an interlayer dielectric layer covering the semiconductor substrate;
[0020] etching the interlayer dielectric layer and the body region to form a contact hole;
[0021] filling the contact hole to form a contact plug;
[0022] forming a metal layer covering the interlayer dielectric layer.
[0023] Further, after forming the metal layer covering the interlayer dielectric layer, the method further comprises the step of forming a back metal layer.
[0024] Further, a ratio of a line width of the shallow trench to a line width of the deep trench ranges from 3 to 5.
[0025] The present application also provides an IGBT device, comprising:
[0026] a semiconductor substrate, the semiconductor substrate having deep trenches and shallow trenches formed therein, a line width of the deep trenches being smaller than a line width of the shallow trenches;
[0027] the deep trenches and the shallow trenches each having the gate dielectric layer formed on a bottom and a sidewall thereof;
[0028] the deep trenches having a gate formed therein, and the shallow trenches having a dummy gate formed on an inner sidewall thereof.
[0029] Further, the semiconductor substrate comprises one or more gate regions and one or more dummy gate regions, each of the gate regions comprises at least two adjacent deep trenches, each of the dummy gate regions comprises at least two adjacent shallow trenches, the gate regions are arranged apart from the dummy gate regions.
[0030] Further, a body region and a source-drain region are formed between adjacent deep trenches, a body region is formed between adjacent shallow trenches.
[0031] According to the IGBT device and the manufacturing method thereof provided by the present application, the gate is formed in the deep trench with small line width of the semiconductor substrate, and the dummy gate is formed on the inner sidewall of the shallow trench with large line width, the dummy gate on the inner sidewall of the shallow trench serves as the emitter of the IGBT device, compared with the emitter of the traditional IGBT device, the trench depth is reduced and the number of trenches is reduced, so that the capacitance from the gate to the emitter is reduced, and then the input capacitance of the IGBT device is reduced, thereby reducing the switching loss of the IGBT device and improving the switching speed and the switching recovery capability of the IGBT device. BRIEF DESCRIPTION OF DRAWINGS
[0032] The following drawings for the present application are hereby incorporated as a part of the present application for the purpose of understanding the present application. The embodiments of the present application and the description thereof as set forth in the drawings, serve to explain the principles of the present application.
[0033] In the drawings:
[0034] Figure 1 Process flow chart for the manufacturing method of the IGBT device according to one embodiment of the present application;
[0035] Figures 2A-2F Structure schematic diagram of the device obtained by the related steps of the manufacturing method of the IGBT device according to one embodiment of the present application;
[0036] Figure 3 Equivalent capacitance schematic diagram of the IGBT device. DETAILED DESCRIPTION
[0037] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious for those skilled in the art that the present application can be implemented without one or more of these details. In other examples, some technical features known in the art are not described in order not to obscure the present application.
[0038] It is to be understood that the application can assume various alternative embodiments, and that it is not to be limited to what is presented herein. Rather, the embodiments presented herein are provided to give a thorough and complete disclosure of the application and to fully convey the scope of the application to those skilled in the art. In the drawings, the size and relative sizes of layers and regions can be exaggerated for clarity. Like reference numerals can be used to denote like elements throughout.
[0039] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
[0040] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.
[0042] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and a surface through which the implant was performed. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the application.
[0043] For a thorough understanding of the present application, reference should be made to the following detailed description together with the accompanying drawings, in which:
[0044] When the IGBT device pitch is reduced, the trench density is increased, the current density on the same area is increased, and the current capability of the IGBT device is greatly improved. However, the increased trench density increases the parasitic capacitance of the small-size IGBT device, and further causes large conduction loss and poor switching recovery capability of the IGBT device.
[0045] In view of the above problems, the present application provides a manufacturing method of an IGBT device, as shown in the figure, which mainly comprises the following steps: Figure 1
[0046] Step S101: providing a semiconductor substrate, forming a deep trench and a shallow trench in the semiconductor substrate, the line width of the deep trench being smaller than the line width of the shallow trench;
[0047] Step S102: forming a gate dielectric layer covering the semiconductor substrate, the gate dielectric layer being formed on the bottom and sidewall of the deep trench and the shallow trench;
[0048] Step S103: forming a gate material layer covering the semiconductor substrate, so as to fill the deep trench and the shallow trench with gate material;
[0049] Step S104: etching back the gate material layer, so as to form a gate in the deep trench and a dummy gate on the inner sidewall of the shallow trench.
[0050] Hereinafter, the manufacturing method of the IGBT device of the present application will be described in detail with reference to the accompanying drawings. In the drawings, Figures 2A to 2F Fig. 1 shows a schematic structure of a device obtained by the related steps of the manufacturing method of the IGBT device according to an embodiment of the present application.
[0051] Firstly, step S101 is performed, as shown in Fig. 1, a semiconductor substrate 200 is provided, in which a deep trench 2001 and a shallow trench 2002 are formed, the line width of the deep trench 2001 is smaller than that of the shallow trench 2002. Figure 2A
[0052] Exemplarily, forming the deep trench 2001 and the shallow trench 2002 in the semiconductor substrate 200 comprises:
[0053] forming a patterned mask layer (not shown) on the semiconductor substrate 200;
[0054] etching the semiconductor substrate 200 with the patterned mask layer as a mask, so as to form the deep trench 2001 and the shallow trench 2002 in the semiconductor substrate.
[0055] Firstly, a patterned mask layer is formed on the semiconductor substrate 200.
[0056] Exemplarily, the semiconductor substrate 200 can be any suitable semiconductor material known to those skilled in the art, such as germanium or silicon or a combination thereof, etc. The semiconductor substrate 200 has a first conductive type, such as N type or P type, which is reasonably selected according to the type of the device to be prepared.
[0057] In one embodiment, the semiconductor substrate 200 can be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-silicon (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), etc. As an example, in the present embodiment, the semiconductor substrate 200 is made of single crystal silicon, which has a first conductivity type, and in the present embodiment, the semiconductor substrate 200 has an N-type conductivity.
[0058] As an example, the material of the mask layer can use any applicable insulating material, and optionally, the material of the mask layer can include one or more of SiO2, SiCN, SiN, SiC, SiOF, SiON, and in the present embodiment, the material of the mask layer includes an oxide, such as silicon oxide.
[0059] In one embodiment, the mask layer can be formed using a chemical vapor deposition method, an atomic layer deposition method, or a physical vapor deposition method, etc. In the present embodiment, when the mask layer is silicon oxide, the mask layer 201 can be formed by thermal oxidation of the surface of the semiconductor substrate 200.
[0060] Next, the mask layer is patterned to form a first via and a second via in the mask layer.
[0061] In one embodiment, a patterned photoresist layer (not shown) is first formed on the mask layer. The photoresist layer can be spin-coated on the mask layer, and then the photoresist layer is patterned using a photolithography process (including steps such as exposure and development) to form a patterned photoresist layer, wherein the patterned photoresist layer defines a pattern of the mask layer to be formed. Next, the mask layer is etched using the patterned photoresist layer as a mask. The mask layer can be etched using an etching method known to those skilled in the art, including but not limited to dry etching or wet etching, to stop at the surface of the semiconductor substrate 200 to form the patterned mask layer. Subsequently, the photoresist layer is removed. The patterned photoresist layer can be removed using an ashing method, and finally a patterned mask layer is formed on the surface of the semiconductor substrate 200.
[0062] Further, the cross-sectional shape of the patterned mask layer is rectangular. The cross-sectional shape refers to the shape obtained by cutting the patterned mask layer with a plane perpendicular to the surface of the semiconductor substrate 200. The top view shape of the patterned mask layer having a rectangular cross-sectional shape can be any suitable shape, such as a circular shape, an elliptical shape, a rectangular shape, or other polygonal shapes or irregular shapes.
[0063] Further, the patterned mask layer includes through holes with different line widths. In this embodiment, the patterned mask layer includes first through holes and second through holes, the line width of the second through holes is greater than the line width of the first through holes, for example, the ratio of the line width of the second through holes to the line width of the first through holes ranges from 3 to 5.
[0064] Next, the semiconductor substrate 200 is etched with the patterned mask layer as a mask to form deep trenches 2001 corresponding to the first through holes and shallow trenches 2002 corresponding to the second through holes in the semiconductor substrate 200, the etching depth of the deep trenches 2001 is greater than the etching depth of the shallow trenches 2002.
[0065] For example, the semiconductor substrate 200 can be etched by dry etching or wet etching. Dry etching processes include but are not limited to reactive ion etching (RIE), ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method can also be used, or more than one etching method can also be used.
[0066] In one embodiment, since the line width of the first through holes is smaller than the line width of the second through holes, during dry etching, the semiconductor substrate 200 under the first through holes is etched deeper, and the semiconductor substrate 200 under the second through holes is etched shallower, thereby forming deep trenches 2001 and shallow trenches 2002 under the first through holes and the second through holes, respectively, wherein the deep trenches 2001 and the shallow trenches 2002 are formed synchronously, and the etching depth of the deep trenches 2001 is greater than the etching depth of the shallow trenches 2002.
[0067] Next, step S102 is performed, as shown in Figure 2B The gate dielectric layer 201 is formed covering the semiconductor substrate 200, and the bottom and sidewall of the deep trenches 2001 and the shallow trenches 2002 are formed with the gate dielectric layer 201.
[0068] In one embodiment, before forming the gate dielectric layer 201, a step of removing the mask layer is further included. A global etching step is performed to remove the mask layer on the surface of the semiconductor substrate 200. The mask layer can be removed by etching using any prior art known to those skilled in the art, including dry etching or wet etching, preferably dry etching.
[0069] In one embodiment, the gate dielectric layer 201 includes, but is not limited to, an oxide layer, such as a silicon dioxide (SiO2) layer. Exemplarily, the forming method of the gate dielectric layer 201 can employ any prior art known to those skilled in the art, preferably a chemical vapor deposition (CVD) method, such as a low temperature chemical vapor deposition (LTCVD), a low pressure chemical vapor deposition (LPCVD), a rapid thermal chemical vapor deposition (RTCVD), a plasma enhanced chemical vapor deposition (PECVD).
[0070] Next, step S103 is performed, as shown in Figure 2C The gate material layer 202 is formed to cover the semiconductor substrate 200, so as to fill the gate material in the deep trench 2001 and the shallow trench 2002.
[0071] Exemplarily, the gate material layer 202 includes one or more of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer, and a metal silicide layer, wherein the constituent material of the metal layer can be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride layer includes a titanium nitride (TiN) layer; the conductive metal oxide layer includes an iridium oxide (IrO2) layer; and the metal silicide layer includes a titanium silicide (TiSi) layer. In the present embodiment, the material of the gate material layer 202 includes polysilicon (Poly).
[0072] Exemplarily, the forming method of the gate material layer 202 can employ any prior art known to those skilled in the art, preferably a chemical vapor deposition (CVD) method, such as a low temperature chemical vapor deposition (LTCVD), a low pressure chemical vapor deposition (LPCVD), a rapid thermal chemical vapor deposition (RTCVD), a plasma enhanced chemical vapor deposition (PECVD).
[0073] Next, step S104 is performed, as shown in Figure 2D The gate material layer 202 is etched back, so as to form a gate 2021 in the deep trench 2001 and a virtual gate 2022 on the inner sidewall of the shallow trench 2002.
[0074] Exemplarily, the etching of the gate material layer 202 can be performed by a dry etching method or a wet etching method. The dry etching process includes, but is not limited to, a reactive ion etching (RIE), an ion beam etching, a plasma etching, a laser ablation, or any combination of these methods. A single etching method can be used, or more than one etching method can be used.
[0075] In one embodiment, as shown in Figure 2DAs shown, since the dummy gates 2022 are respectively located on the inner sidewalls of the oppositely arranged shallow trenches 2002, the dummy gates 2022 are also called sidewall gates in some embodiments. Further, the width of the dummy gates 2022 is smaller than the width of the gates 2021, and specifically, the ratio of the width of the bottom of the dummy gates 2022 to the width of the gates 2021 ranges from 0.5 to 1.
[0076] It should be noted that the semiconductor substrate 200 includes one or more gate regions and one or more dummy gate regions, each of the gate regions includes at least two adjacent deep trenches 2001, and each of the dummy gate regions includes at least two adjacent shallow trenches 2002, and the gate regions and the dummy gate regions are arranged in a spaced manner.
[0077] Due to the design structure, there are many parasitic capacitances in the IGBT device, which can be simplified as the capacitances between the stages of the IGBT, such as Figure 3 As shown. Among them, the input capacitance Cies=C GC +C GE When the input capacitance is charged to the threshold voltage, the device can be turned on, and when it is discharged to a certain value, the device can be turned off, so the input capacitance mainly affects the switching speed and switching loss of the device.
[0078] The size of the input capacitance (Cies) is determined by the gate capacitance, collector capacitance and emitter capacitance. Among them, the size of the emitter capacitance depends on the trench depth, number and gate line width size.
[0079] Through the above steps, the gate 2021 is formed in the deep trench 2001 with a smaller line width of the semiconductor substrate 200, and the dummy gate 2022 is formed on the inner sidewall of the shallow trench 2002 with a larger line width. The dummy gate on the inner sidewall of the shallow trench serves as the emitter of the IGBT device, and the trench depth thereof is significantly reduced compared with the emitter of the conventional IGBT device, being about one-half to one-fifth of the trench depth of the conventional IGBT device; and the line width size of the dummy gate is comparable to the line width size of the gate of the conventional IGBT device. At the same time, the dummy gate on the inner sidewall of the shallow trench serves as the emitter of the IGBT device, which can significantly reduce the number of trenches, being about one-half to one-fourth of the number of trenches of the conventional IGBT device. Therefore, the capacitance from the gate to the emitter is significantly reduced, so that the input capacitance (parasitic capacitance) is reduced, achieving the effect of significantly reducing the switching loss of the IGBT, greatly improving the switching speed and switching recovery capability of the IGBT.
[0080] Next, as shown in Figure 2EAs shown, the method further includes a step of forming body regions 203 and source-drain regions 204 in the semiconductor substrate 200. Specifically, the body regions 203 and the source-drain regions 204 are formed between the deep trenches 2001, and the body regions 203 are formed between the shallow trenches 2002.
[0081] As an example, a P-well is formed in the semiconductor substrate 200 as the body region 203. As an example, the P-well is formed in the semiconductor substrate by a standard well implantation process. The P-well can be formed by a high-energy implantation process, or can be formed by a low-energy implantation process in combination with a high-temperature thermal annealing process.
[0082] As an example, the source-drain regions 204 are then formed in the body regions 203 between the deep trenches 2001, and the source-drain regions 204 respectively include a source region and a drain region, and the source and the drain can be respectively led out. As an example, the source-drain regions 204 are formed in the body regions 203 between the deep trenches 2001 by implanting N-type impurities, and the source region and the drain region can have the same doping concentration, and thus can be doped synchronously.
[0083] Next, as shown in FIG. 2B, after the body regions 203 and the source-drain regions 204 are formed, the method further includes the following steps: Figure 2F
[0084] An interlayer dielectric layer 205 is formed to cover the semiconductor substrate 200;
[0085] The interlayer dielectric layer 205 and the body regions 203 are etched to form contact holes;
[0086] The contact holes are filled to form contact plugs 206;
[0087] A metal layer 207 is formed to cover the interlayer dielectric layer 205.
[0088] As an example, the interlayer dielectric layer 205 is formed to cover the gate 2021, the dummy gate 2022, and the exposed gate dielectric layer or the semiconductor substrate, etc. The interlayer dielectric layer 205 can be formed using an inorganic insulating layer such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, or an insulating layer such as an insulating layer containing polyvinyl phenol, polyimide, or siloxane, etc. The interlayer dielectric layer 205 can be formed using a method of selective epitaxial growth, and the selective epitaxial growth can use one of low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE).
[0089] Exemplarily, the interlayer dielectric layer 205 can be etched by a photolithography process. First, a patterned photoresist layer (not shown) is formed on the interlayer dielectric layer 205. The photoresist layer can be spin-coated on the interlayer dielectric layer 205, and then the photoresist layer is patterned by a photolithography process including exposure and development steps, so as to form a patterned photoresist layer. The patterned photoresist layer defines a pattern of the contact hole to be formed, and the pattern of the contact hole is located above the body region 203. Then, the interlayer dielectric layer 205 and the body region 203 are etched with the patterned photoresist layer as a mask, so as to form the contact hole. Subsequently, the photoresist layer is removed.
[0090] Exemplarily, the contact plug 206 is filled with a metal material in the contact hole. The material of the contact plug 206 includes, but is not limited to, copper, tungsten, gold, silver, aluminum, etc.
[0091] Exemplarily, the method for forming the metal layer 207 covering the interlayer dielectric layer 205 can adopt any prior art known to those skilled in the art, and preferably a chemical vapor deposition (CVD) method, such as low-temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), and plasma-enhanced chemical vapor deposition (PECVD).
[0092] Next, after the metal layer 207 covering the interlayer dielectric layer 205 is formed, a step of forming a back metal layer (not shown) is further included.
[0093] Exemplarily, a back anode structure is first formed on the back of the semiconductor substrate 200, which includes forming an implanted region (not shown) on the back of the semiconductor substrate 200. The implanted region has a second conductive type, for example, a P type, and the implanted region serves as a collector region, which can be a P type heavily doped. The implanted region can be formed on the back of the semiconductor substrate 200 by an ion implantation method. Further, a buffer region (not shown) is also formed in a substrate region between the implanted region and the back of the semiconductor substrate, which can be realized by ion implantation on the back of the substrate, and the depth of ion implantation is controlled by controlling the energy of implantation. The buffer region has an opposite conductive type to the implanted region, for example, when the collector region is a P type heavily doped, the buffer region can be an N type heavily doped.
[0094] Exemplarily, the method for forming the back metal layer can adopt any prior art known to those skilled in the art, and preferably a chemical vapor deposition (CVD) method, such as low-temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), and plasma-enhanced chemical vapor deposition (PECVD). Then, the back metal layer is subjected to chemical mechanical polishing until the back metal layer reaches a target thickness.
[0095] The key steps of the trench IGBT device manufacturing method of the present application are introduced above. Other processes may be needed for the complete device preparation, which are not described here.
[0096] The present application also provides an IGBT device, as shown in the accompanying drawings, comprising: Figure 2F
[0097] A semiconductor substrate 200, in which a deep trench and a shallow trench are formed, the line width of the deep trench is smaller than that of the shallow trench;
[0098] The bottom and sidewall of the deep trench and the shallow trench are both formed with the gate dielectric layer 201;
[0099] The deep trench is formed with a gate 2021, and the shallow trench is formed with a virtual gate 2022 on the sidewall.
[0100] Exemplarily, the semiconductor substrate 200 can be any suitable semiconductor material known to those skilled in the art, such as germanium or silicon or a combination thereof, etc. The semiconductor substrate 200 has a first conductivity type, such as N-type or P-type, which is reasonably selected according to the actual device type to be prepared.
[0101] In one embodiment, the semiconductor substrate 200 can be at least one of the following materials: silicon, silicon on insulator (SOI), silicon on stacked silicon (SSOI), silicon on stacked germanium silicon (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), etc. As an example, in the present embodiment, the constituent material of the semiconductor substrate 200 is selected to be monocrystalline silicon, which has a first conductivity type. In the present embodiment, the conductivity type of the semiconductor substrate 200 is N-type.
[0102] Exemplarily, the semiconductor substrate 200 is formed with a deep trench and a shallow trench, the line width of the deep trench is smaller than that of the shallow trench, and the etching depth of the deep trench is greater than that of the shallow trench. In one embodiment, the ratio of the line width of the shallow trench to that of the deep trench ranges from 3 to 5.
[0103] Exemplarily, between the gate 2021 and the semiconductor substrate 200, and between the virtual gate 2022 and the semiconductor substrate 200, a gate dielectric layer 201 covering the semiconductor substrate 200 is also formed. The gate dielectric layer 201 includes an oxide layer, such as a silicon dioxide (SiO2) layer.
[0104] Exemplarily, the material of the gate 2021 and the dummy gate 2022 includes one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. In the embodiment, the material of the gate 2021 and the dummy gate 2022 includes polysilicon (Poly).
[0105] Exemplarily, since the dummy gate 2022 is respectively located on the inner sidewall of the oppositely arranged shallow trench 2002, in some embodiments, the dummy gate 2022 is also called a sidewall gate. Further, the width of the dummy gate 2022 is less than the width of the gate 2021, and specifically, the ratio of the width of the bottom of the dummy gate 2022 to the width of the gate 2021 ranges from 0.5 to 1.
[0106] It should be noted that the semiconductor substrate 200 includes one or more gate regions and one or more dummy gate regions, each of the gate regions includes at least two adjacent deep trenches 2001, and each of the dummy gate regions includes at least two adjacent shallow trenches 2002, and the gate regions and the dummy gate regions are arranged in a spaced manner.
[0107] Exemplarily, the body region 203 and the source-drain region 204 are formed between the deep trenches 2001, and the body region 203 is formed between the shallow trenches 2002. Further, the source-drain region 204 includes a source region and a drain region, and the source and the drain can be respectively led out.
[0108] Exemplarily, an interlayer dielectric layer 205 covering the semiconductor substrate 200 is further formed on the gate 2021 and the dummy gate 2022; a contact plug 206 is formed in the interlayer dielectric layer 205 and the body region 203; a metal layer 207 covering the interlayer dielectric layer 205 is further formed on the metal plug; and a back metal layer is further formed on the back surface of the semiconductor substrate 200.
[0109] Exemplarily, the interlayer dielectric layer 205 covers the above-mentioned gate 2021, dummy gate 2022, and exposed gate dielectric layer or semiconductor substrate, etc. The interlayer dielectric layer 205 can be formed using an inorganic insulating layer such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, an insulating layer such as an insulating layer containing polyvinyl phenol, polyimide, or siloxane, etc.
[0110] Exemplarily, the material of the contact plug 206, the metal layer 207, and the back metal layer includes but is not limited to copper, tungsten, gold, silver, aluminum, etc.
[0111] Exemplarily, the back surface of the semiconductor substrate 200 is also formed with a back surface anode structure, which includes an injection region (not shown) formed on the back surface of the semiconductor substrate 200. The injection region has a second conductive type, for example, P type, and the injection region serves as a collector region, which can be P type heavily doped. Further, a buffer region (not shown) is also formed in a substrate region between the injection region and the back surface of the semiconductor substrate. The buffer region has an opposite conductive type to the injection region, for example, when the collector region is P type heavily doped, the buffer region can be N type heavily doped.
[0112] According to the IGBT device and the manufacturing method thereof provided by the present application, the gate is formed in the deep trench with a small line width and the virtual gate is formed on the inner sidewall of the shallow trench with a large line width, and the virtual gate on the inner sidewall of the shallow trench serves as the emitter of the IGBT device. Compared with the emitter of the conventional IGBT device, the trench depth is reduced and the number of trenches is reduced, so that the capacitance from the gate to the emitter is reduced, and then the input capacitance of the IGBT device is reduced, thereby reducing the switching loss of the IGBT device and improving the switching speed and the switching recovery capability of the IGBT device.
[0113] The present application has been described by the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of example and illustration, and are not intended to limit the present application to the scope of the described embodiments. Furthermore, those skilled in the art can understand that the present application is not limited to the above-mentioned embodiments, and more kinds of variations and modifications can be made according to the teachings of the present application, which all fall within the scope of the present application claimed. The protection scope of the present application is defined by the attached claims and their equivalent scope.
Claims
1. A method for manufacturing an IGBT device, characterized in that, Includes the following steps: A semiconductor substrate is provided in which deep trenches and shallow trenches are formed, wherein the linewidth of the deep trenches is smaller than the linewidth of the shallow trenches. A gate dielectric layer is formed covering the semiconductor substrate, and the gate dielectric layer is formed on the bottom and sidewalls of both the deep trench and the shallow trench; A gate material layer is formed over the semiconductor substrate to fill the deep trench and the shallow trench with gate material; The gate material layer is etched back to form a gate in the deep trench and a dummy gate is formed on the inner sidewall of the shallow trench, the dummy gate filling a portion of the shallow trench and covering a portion of the bottom of the shallow trench.
2. The method as described in claim 1, characterized in that, Forming deep trenches and shallow trenches in the semiconductor substrate includes: A patterned mask layer is formed on the semiconductor substrate; The semiconductor substrate is etched using the patterned mask layer as a mask to form deep trenches and shallow trenches in the semiconductor substrate.
3. The method as described in claim 1, characterized in that, The semiconductor substrate includes one or more gate regions and one or more dummy gate regions. Each gate region includes at least two adjacent deep trenches, and each dummy gate region includes at least two adjacent shallow trenches. The gate regions and the dummy gate regions are spaced apart.
4. The method as described in claim 3, characterized in that, After forming the gate and the dummy gate, the method further includes the following steps: A body region and a source / drain region are formed between adjacent deep trenches; and A body region is formed between adjacent shallow trenches.
5. The method as described in claim 4, characterized in that, After forming the body region and the source / drain region, the following steps are also included: An interlayer dielectric layer is formed covering the semiconductor substrate; The interlayer dielectric layer and the body region are etched to form contact holes; Fill the contact hole to form a contact plug; A metal layer is formed covering the interlayer dielectric layer.
6. The method as described in claim 5, characterized in that, After forming a metal layer covering the interlayer dielectric layer, the step of forming a back metal layer is also included.
7. The method as described in claim 1, characterized in that, The ratio of the line width of the shallow trench to the line width of the deep trench is in the range of 3 to 5.
8. An IGBT device, characterized in that, include: A semiconductor substrate in which deep trenches and shallow trenches are formed, wherein the linewidth of the deep trenches is smaller than the linewidth of the shallow trenches; A gate dielectric layer is formed on the bottom and sidewalls of both the deep trench and the shallow trench; A gate is formed in the deep trench, and a virtual gate is formed on the inner sidewall of the shallow trench. The virtual gate fills part of the shallow trench and covers part of the bottom of the shallow trench.
9. The IGBT device as described in claim 8, characterized in that, The semiconductor substrate includes one or more gate regions and one or more dummy gate regions. Each gate region includes at least two adjacent deep trenches, and each dummy gate region includes at least two adjacent shallow trenches. The gate regions and the dummy gate regions are spaced apart.
10. The IGBT device as described in claim 9, characterized in that, A volume region and a source / drain region are formed between adjacent deep trenches, and a volume region is formed between adjacent shallow trenches.
Citation Information
Patent Citations
IGBT device and preparation method thereof
CN106997899A