A high-voltage MOSFET device and its manufacturing method

Abstract

The present invention provides a high-voltage MOSFET device and a method for manufacturing the same. The method includes the following steps: forming a first stacked structure and a second stacked structure on a semiconductor layer, wherein the first stacked structure is located in the high-voltage region and includes a stacked high-voltage region gate oxide layer and a first hard mask layer, and the second stacked structure is located in the core region and includes a stacked core region gate oxide layer, a polysilicon dummy gate layer, and second and third hard mask layers; forming a sidewall protection layer; forming a grinding stop layer and a first interlayer dielectric layer and thinning them until the top surfaces of the high-voltage region gate oxide layer and the polysilicon dummy gate layer are exposed; replacing the polysilicon dummy gate to obtain a core region metal gate and performing CMP on the same; and forming a compensation oxide layer and a high-voltage region metal gate. In the present invention, after replacing the polysilicon dummy gate with a metal gate, the film layer height difference between the high-voltage region and the core region is not much different, which does not affect the load of the core region metal gate CMP. The EOT required for the high-voltage region can be compensated by subsequently re-laying the compensation oxide layer.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuits and relates to a high-voltage MOSFET device and a manufacturing method thereof. Background Art

[0002] The main semiconductor device in integrated circuits, especially very large-scale integrated circuits, is the Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). With the continuous development of integrated circuit manufacturing technology, the technical nodes of semiconductor devices are constantly decreasing, and the geometric dimensions of semiconductor devices are shrinking in accordance with Moore's Law. When the size of semiconductor devices is reduced to a certain extent, various secondary effects caused by the physical limitations of semiconductor devices appear one after another, and it becomes increasingly difficult to scale down the characteristic dimensions of semiconductor devices. Among them, in the field of semiconductor manufacturing, the most challenging issue is how to solve the problem of large leakage current in semiconductor devices. The large leakage current of semiconductor devices is mainly caused by the continuous reduction in the thickness of the traditional gate dielectric layer.

[0003] With the development of semiconductor technology, high-dielectric constant (high-K) materials are usually used in the gate structure of semiconductor devices with high process nodes to replace traditional silicon dioxide materials as the gate dielectric layer, and metal is used as the gate electrode to form a high-K metal gate (HKMG) structure to avoid the Fermi level pinning effect and boron penetration effect between the high-K material and the traditional gate electrode material, thereby reducing the leakage current of the semiconductor device.

[0004] The gate structure of HKMG is usually realized using a gate replacement process. That is, a dummy gate structure is first formed in the gate structure formation area using deposition, lithography and etching processes. The dummy gate structure is usually composed of a gate oxide layer and a polysilicon gate stacked together. Then, sidewalls are formed on the side of the dummy gate structure. The source and drain regions are formed on both sides of the dummy gate structure using a source-drain ion implantation process. After all the front-side processes before HKMG are completed, the dummy gate structure is removed, and a groove is formed in the area where the dummy gate structure is removed. Then, HKMG is formed in the groove.

[0005] High-voltage MOSFETs (HV-MOSFETs) require a very thick effective oxide thickness (EOT) to withstand ultra-high operating voltages, making the gate height of high-voltage devices much higher than that of general components. In HKMG processes below 28nm, chemical mechanical polishing (CMP) must be used to flatten the metal gate. At this time, the gate height of the high-voltage device not only affects the CMP load, but also affects the film layer in the high-voltage area. For example, in one manufacturing process, when forming a dummy gate in the core area, polysilicon material is also covered on the gate oxide layer in the high-voltage area. After removing the dummy gate structure in the core area and forming the metal gate, the CMP process for the metal gate in the core area will also completely grind away the polysilicon layer on the gate oxide layer in the high-voltage area.

[0006] Therefore, how to improve the manufacturing process of high-voltage MOSFET to avoid affecting the chemical mechanical polishing of the core metal gate while ensuring that the EOT of the high-voltage area meets the high-voltage requirements has become an important technical problem that needs to be solved urgently by those skilled in the art.

[0007] It should be noted that the above introduction to the technical background is merely intended to provide a clear and complete description of the technical solutions of this application and facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0008] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a high-voltage MOSFET device and a manufacturing method thereof, which is used to solve the problem in the prior art that the height of the high-voltage region film layer affects the chemical mechanical polishing of the core region metal gate, and the high-voltage performance of the high-voltage region is affected by the height of the core region metal gate.

[0009] To achieve the above-mentioned and other related objects, the present invention provides a method for manufacturing a high-voltage MOSFET device, comprising the following steps:

[0010] A semiconductor layer is provided, and a first stacked structure and a second stacked structure are formed on the semiconductor layer. The semiconductor layer includes a high-voltage region and a core region spaced apart in a horizontal direction. The first stacked structure is located in the high-voltage region and includes a high-voltage region gate oxide layer and a first hard mask layer stacked sequentially from bottom to top. The second stacked structure is located in the core region and includes a core region gate oxide layer, a polysilicon dummy gate layer, a second hard mask layer, and a third hard mask layer stacked sequentially from bottom to top.

[0011] forming a sidewall protection layer on the sidewalls of the first stacking structure and the sidewalls of the second stacking structure;

[0012] forming a grinding stop layer and a first interlayer dielectric layer on the semiconductor layer in sequence, wherein the grinding stop layer covers the first stacked structure, the second stacked structure, and the exposed surface of the sidewall protection layer, and the first interlayer dielectric layer covers the grinding stop layer, and then thinning the first interlayer dielectric layer until the top surface of the high-voltage region gate oxide layer and the top surface of the polysilicon dummy gate layer are exposed;

[0013] removing the polysilicon dummy gate to obtain a groove located in the core area and sandwiched between the sidewall protection layers;

[0014] forming a core metal gate in the groove, and performing chemical mechanical polishing on the core metal gate;

[0015] A compensation oxide layer is formed on the high-voltage region gate oxide layer, and a high-voltage region metal gate is formed on the compensation oxide layer.

[0016] Optionally, a top surface of the first stacking structure is lower than a top surface of the second stacking structure.

[0017] Optionally, in the step of forming the first stacking structure and the second stacking structure on the semiconductor layer, the high-voltage region gate oxide layer and the first hard mask layer are formed first, and then the polysilicon pseudo gate, the second hard mask layer and the third hard mask layer are formed, and the polysilicon layer is not retained on the first hard mask layer.

[0018] Optionally, thinning the first interlayer dielectric layer until the top surface of the high-voltage region gate oxide layer and the top surface of the polysilicon dummy gate layer are exposed comprises the following steps:

[0019] Performing chemical mechanical polishing on the first interlayer dielectric layer and stopping at the polishing stop layer on the first hard mask layer and the third hard mask layer;

[0020] etching back the first interlayer dielectric layer and stopping at the first hard mask layer and the second hard mask layer;

[0021] Chemical mechanical polishing is performed on the first interlayer dielectric layer and stops at the high-voltage region gate oxide layer and the polysilicon dummy gate layer.

[0022] Optionally, after chemical mechanical polishing is performed on the first interlayer dielectric layer and stops at the high-voltage region gate oxide layer and the polysilicon dummy gate layer, the top surfaces of the high-voltage region gate oxide layer and the polysilicon dummy gate layer are at the same height.

[0023] Optionally, after chemical mechanical polishing is performed on the core region metal gate, the high voltage region gate oxide layer is at the same height as the top surface of the core region metal gate.

[0024] Optionally, the method further includes the following steps: forming a second interlayer dielectric layer covering the high-voltage region metal gate on the compensation oxide layer.

[0025] The present invention also provides a high-voltage MOSFET device, comprising:

[0026] semiconductor layer;

[0027] A high-voltage region high-K metal gate structure is located on the semiconductor layer and includes a high-voltage region gate oxide layer, a compensation oxide layer and a high-voltage region metal gate stacked sequentially from bottom to top;

[0028] A core region high-K metal gate structure is located on the semiconductor layer and includes a core region gate oxide layer and a core region metal gate stacked sequentially from bottom to top;

[0029] The sidewall protection layer is located on the sidewalls of the gate oxide layer in the high-voltage region, the sidewalls of the gate oxide layer in the core region, and the sidewalls of the metal gate in the core region.

[0030] As described above, the manufacturing method of the high-voltage MOSFET device of the present invention includes the following steps: forming a first stacking structure and a second stacking structure on a semiconductor layer, the first stacking structure is located in the high-voltage area and includes a high-voltage area gate oxide layer and a first hard mask layer stacked in sequence from bottom to top, and the second stacking structure is located in the core area and includes a core area gate oxide layer, a polysilicon pseudo gate layer, a second hard mask layer and a third hard mask layer stacked in sequence from bottom to top; forming a sidewall protection layer on the side walls of the first and second stacking structures; forming a grinding stop layer and a first interlayer dielectric layer and thinning the first interlayer dielectric layer until the top surface of the high-voltage area gate oxide layer and the top surface of the polysilicon pseudo gate layer are exposed; replacing the polysilicon pseudo gate to obtain a core area metal gate, and performing chemical mechanical grinding on the core area metal gate; forming a compensation oxide layer on the high-voltage area gate oxide layer, and forming a high-voltage area metal gate on the compensation oxide layer. The present invention only uses the high-voltage area gate oxide layer to define the high-voltage gate in the front-end process, and the high-voltage area gate oxide layer and the polysilicon pseudo gate in the core area can be controlled to have the same top surface height through CMP. The sidewall protection layer can protect the high-voltage area gate oxide layer in the intermediate process. After the polysilicon pseudo gate in the core area is replaced by a metal gate, the film layer height difference between the high-voltage area and the core area is not much, which will not affect the load of the CMP of the metal gate in the core area. The gate oxide layer in the high-voltage area and the metal gate in the core area can be controlled to be the same height through CMP. Subsequently, the required EOT of the high-voltage area can be supplemented by re-laying the compensation oxide layer on the gate oxide layer in the high-voltage area. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic diagram showing a polysilicon layer covering a gate oxide layer in a high-voltage region during a high-voltage MOSFET manufacturing process.

[0032] Figure 2It is a schematic diagram showing that after the dummy gate in the core area is replaced with a metal gate, the CMP process for the metal gate in the core area will also completely grind away the polysilicon layer on the gate oxide layer in the high-voltage area.

[0033] Figure 3 Shown is a process flow chart of a method for manufacturing a high-voltage MOSFET device according to the present invention.

[0034] Figure 4 It is a schematic cross-sectional view of the structure obtained after forming a high-voltage region gate oxide layer, a first hard mask layer and a core region gate oxide layer on a semiconductor layer according to the manufacturing method of the high-voltage MOSFET device of the present invention.

[0035] Figure 5 It is a schematic cross-sectional view of a structure obtained after forming a polysilicon dummy gate, a second hard mask layer and a third hard mask layer according to the manufacturing method of the high-voltage MOSFET device of the present invention.

[0036] Figure 6 It is a schematic cross-sectional view of a structure obtained after forming sidewall protection layers on the sidewalls of the first stacked structure and the sidewalls of the second stacked structure according to the manufacturing method of the high-voltage MOSFET device of the present invention.

[0037] Figure 7 The cross-sectional view of the structure obtained after chemical mechanical polishing is performed on the first interlayer dielectric layer 213 and the polishing stop layer is stopped on the first hard mask layer and the third hard mask layer 208 in the manufacturing method of the high voltage MOSFET device of the present invention.

[0038] Figure 8 It is a cross-sectional view of a structure obtained after etching back the first interlayer dielectric layer and stopping at the first hard mask layer and the second hard mask layer according to the manufacturing method of the high-voltage MOSFET device of the present invention.

[0039] Figure 9 It shows a cross-sectional view of the structure obtained after the manufacturing method of the high-voltage MOSFET device of the present invention further performs chemical mechanical polishing on the first interlayer dielectric layer and stops at the high-voltage region gate oxide layer and the polysilicon dummy gate layer.

[0040] Figure 10 The cross-sectional view of the structure obtained after removing the polysilicon dummy gate 206 to obtain a groove located in the core region and sandwiched between the sidewall protection layers is shown in the manufacturing method of the high-voltage MOSFET device of the present invention.

[0041] Figure 11 It is a schematic cross-sectional view of the structure obtained after forming a core metal gate in a groove and performing chemical mechanical polishing according to the manufacturing method of the high-voltage MOSFET device of the present invention.

[0042] Figure 12It is a schematic cross-sectional view of the structure obtained after forming a compensation oxide layer on the high voltage region gate oxide layer according to the manufacturing method of the high voltage MOSFET device of the present invention.

[0043] Figure 13 It is a schematic cross-sectional view of the structure obtained after forming a high-voltage region metal gate on a compensation oxide layer according to the manufacturing method of the high-voltage MOSFET device of the present invention.

[0044] Figure 14 It is a cross-sectional schematic diagram of the structure obtained after forming the second interlayer dielectric layer, the gate contact portion, the source contact portion and the drain contact portion according to the manufacturing method of the high-voltage MOSFET device of the present invention.

[0045] Component number description

[0046]

[0047] DETAILED DESCRIPTION

[0048] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] See also Figures 1 to 14 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0050] like Figure 1 FIG. 1 is a schematic diagram showing a manufacturing process of a high-voltage MOSFET in which a polysilicon layer 103 is also covered on a gate oxide layer 102 in the high-voltage region when forming a dummy gate 101 in the core region. Since the gate oxide layer 102 in the high-voltage region is very thick, there is a large height difference between the film layer in the high-voltage region and the film layer in the core region. Figure 1 The dotted line A shows the plane where the top surface of the high-pressure area membrane layer is located. Figure 2 As shown, after the dummy gate of the core area is replaced with the metal gate 104, the CMP process for the metal gate of the core area will also completely grind away the polysilicon layer on the gate oxide layer 103 of the high voltage area, wherein, Figure 2(The polysilicon layer 103 between dashed lines B and C will be completely removed during the CMP process.) In the above-described high-voltage MOSFET manufacturing process, the large height difference between the high-voltage region and the core region affects the CMP load and may affect the high-voltage performance of the high-voltage region. The present invention improves the high-voltage MOSFET manufacturing process to avoid affecting the chemical mechanical polishing of the core region metal gate, while ensuring that the EOT of the high-voltage region meets high-voltage requirements.

[0051] Example 1

[0052] This embodiment provides a method for manufacturing a high-voltage MOSFET device. Figure 3 , shown as a process flow diagram of the method, comprising the following steps:

[0053] S1: providing a semiconductor layer, forming a first stacked structure and a second stacked structure on the semiconductor layer, wherein the semiconductor layer includes a high-voltage region and a core region spaced apart in a horizontal direction, the first stacked structure being located in the high-voltage region and including a high-voltage region gate oxide layer and a first hard mask layer stacked sequentially from bottom to top, and the second stacked structure being located in the core region and including a core region gate oxide layer, a polysilicon dummy gate layer, a second hard mask layer, and a third hard mask layer stacked sequentially from bottom to top;

[0054] S2: forming a sidewall protection layer on the sidewalls of the first stacked structure and the sidewalls of the second stacked structure;

[0055] S3: sequentially forming a grinding stop layer and a first interlayer dielectric layer on the semiconductor layer, wherein the grinding stop layer covers the first stacked structure, the second stacked structure, and exposed surfaces of the sidewall protection layer, and the first interlayer dielectric layer covers the grinding stop layer, and then thinning the first interlayer dielectric layer until a top surface of the high-voltage region gate oxide layer and a top surface of the polysilicon dummy gate layer are exposed;

[0056] S4: removing the polysilicon dummy gate to obtain a groove located in the core area and sandwiched between the sidewall protection layers;

[0057] S5: forming a core metal gate in the groove, and performing chemical mechanical polishing on the core metal gate;

[0058] S6: forming a compensation oxide layer on the high-voltage region gate oxide layer, and forming a high-voltage region metal gate on the compensation oxide layer.

[0059] First see Figures 4 and 5, perform step S1: provide a semiconductor layer 201, form a first stacking structure and a second stacking structure on the semiconductor layer 201, the semiconductor layer 201 includes a high-voltage region and a core region spaced apart in a horizontal direction, the first stacking structure is located in the high-voltage region and includes a high-voltage region gate oxide layer 203 and a first hard mask layer 204 stacked sequentially from bottom to top, the second stacking structure is located in the core region and includes a core region gate oxide layer 205, a polysilicon pseudo gate layer 206, a second hard mask layer 207 and a third hard mask layer 208 stacked sequentially from bottom to top.

[0060] As an example, the semiconductor layer 201 may be a Si substrate, a Ge substrate, a SiGe substrate, a SiC substrate, a III-V compound substrate, or other suitable semiconductor substrate known in the art. A P-well and / or an N-well and other required structures may be prefabricated in the semiconductor layer 201. In this embodiment, a shallow trench isolation structure 202 is prefabricated in the semiconductor layer 201. The shallow trench isolation structure 202 is used to define an active area in the semiconductor layer 201.

[0061] As an example, the high-voltage region gate oxide layer 203 and the core region gate oxide layer 205 both include high-K dielectrics, wherein high-K dielectrics refer to dielectrics having a relative dielectric constant greater than that of silicon oxide, including but not limited to one or more of HfO2, HfSiO, HfSiON, HfTaO layer, HfTiO, HfZrO, ZrO2 and Al2O3.

[0062] As an example, an interface layer (not shown) may be provided between the high-voltage region gate oxide layer 203 and the semiconductor layer 201, and an interface layer (not shown) may be provided between the core region gate oxide layer 205 and the semiconductor layer 201. The material of the interface layer may include at least one of SiO2 and SiON. The function of the interface layer is to provide a good interface foundation for the subsequent formation of a high-K dielectric layer to improve the quality of the high-K dielectric layer, reduce the interface state density between the high-K dielectric layer and the underlying semiconductor layer, and avoid adverse effects caused by direct contact between the high-K dielectric layer and the substrate layer. The thickness of the interface layer can be reasonably set based on actual needs and must meet the structural and performance requirements of the device.

[0063] As an example, the materials of the first hard mask layer 204, the second hard mask layer 207 and the third hard mask layer 208 include but are not limited to one or more of silicon oxide, silicon nitride and silicon oxynitride, wherein the second hard mask layer 207 and the third hard mask layer 208 are made of different materials.

[0064] As an example, one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition and oxidation methods can be selected to form the high-voltage area gate oxide layer 203 and the core area gate oxide layer 205, and one or more of chemical vapor deposition, physical vapor deposition and atomic layer deposition methods can be selected to form the first hard mask layer 204, the polysilicon pseudo gate 207, the second hard mask layer 207 and the third hard mask layer 208.

[0065] As an example, the high-voltage region gate oxide layer 203 is formed using semiconductor patterning processes such as photolithography and etching. During this process, the first hard mask layer 204 acts as an etching mask, that is, the oxide layer (used to form the high-voltage region gate oxide layer) not covered by the first hard mask layer 204 is etched away. Similarly, the polysilicon dummy gate 206 is also formed using semiconductor patterning processes such as photolithography and etching. During this process, the second hard mask layer 207 and the third hard mask layer 208 act as etching masks, that is, the polysilicon layer (used to form the polysilicon dummy gate 206) not covered by the second hard mask layer 207 and the third hard mask layer 208 is etched away.

[0066] Specifically, in this embodiment, when forming the first stacking structure and the second stacking structure, the high-voltage region gate oxide layer 203 and the first hard mask layer 204 are first formed in the high-voltage region, and then the polysilicon pseudo gate 206, the second hard mask layer 207 and the third hard mask layer 208 are formed in the core region. No polysilicon layer is retained on the first hard mask layer 208, and ultimately the top surface of the first stacking structure is controlled to be lower than the top surface of the second stacking structure. Figure 4 , which is a cross-sectional view of the structure obtained after forming the high-voltage region gate oxide layer 203, the first hard mask layer 204 and the core region gate oxide layer 205 on the semiconductor layer 201, as shown in FIG. Figure 5 , which is a schematic cross-sectional view of the structure obtained after forming the polysilicon dummy gate 206 , the second hard mask layer 207 and the third hard mask layer 208 .

[0067] See also Figure 6 , performing the step S2: forming a sidewall protection layer 209 on the sidewalls of the first stacking structure and the sidewalls of the second stacking structure.

[0068] Specifically, the sidewall protection layer 209 is used to protect the high voltage region gate oxide layer 203 in the subsequent process. The sidewall protection layer 209 can be a single layer or a composite film structure, including but not limited to one or more of silicon oxide layer, silicon nitride layer, and silicon oxynitride layer.

[0069] As an example, after forming the sidewall protection layer 209 , a source region 210 and a drain region 211 of a transistor are further formed in the semiconductor layer 201 .

[0070] See also Figures 7 to 9 , perform the step S3: use chemical vapor deposition, physical vapor deposition, atomic layer deposition or other suitable methods to sequentially form a grinding stop layer 212 and a first interlayer dielectric layer 213 on the semiconductor layer 201, the grinding stop layer 212 covers the first stacking structure, the second stacking structure and the exposed surface of the sidewall protection layer 209, the first interlayer dielectric layer 213 covers the grinding stop layer 212, and then thin the first interlayer dielectric layer 213 until the top surface of the high-voltage region gate oxide layer 203 and the top surface of the polysilicon pseudo gate layer 206 are exposed.

[0071] Specifically, the grinding stop layer 212 and the first interlayer dielectric layer 213 are made of different materials. For example, the grinding stop layer 212 includes a silicon nitride layer or other suitable dielectric material layer, and the first interlayer dielectric layer 213 includes a silicon oxide layer, a low-K dielectric layer or other suitable dielectric material layer.

[0072] Specifically, such as Figure 7 As shown, after forming the grinding stop layer 212 and the first interlayer dielectric layer 213 , the first interlayer dielectric layer 213 is chemically mechanically polished and stops at the grinding stop layer 212 on the first hard mask layer 204 and the third hard mask layer 208 .

[0073] like Figure 8 As shown, the first interlayer dielectric layer 213 is then etched back and stops at the first hard mask layer 204 and the second hard mask layer 207 .

[0074] like Figure 9 As shown, the first interlayer dielectric layer 213 is chemically mechanically polished and stops at the high voltage region gate oxide layer 203 and the polysilicon dummy gate layer 206 .

[0075] In this embodiment, after chemical mechanical polishing is performed on the first interlayer dielectric layer 213 and stops at the high voltage region gate oxide layer 203 and the polysilicon dummy gate layer 206 , the top surfaces of the high voltage region gate oxide layer 203 and the polysilicon dummy gate layer 206 are at the same height.

[0076] See also Figure 10 , performing the step S4: using wet etching or dry etching or other suitable methods to remove the polysilicon dummy gate 206 to obtain a groove 214 located in the core area and sandwiched between the sidewall protection layers 209.

[0077] See also Figure 11 , executing step S5: forming a core metal gate 215 in the groove 214, and performing chemical mechanical polishing on the core metal gate 215.

[0078] In this embodiment, after chemical mechanical polishing of the core metal gate 215, the high voltage region gate oxide layer 203 is at the same height as the top surface of the core metal gate 215. For example, the thickness of the high voltage region gate oxide layer 203 is about 400 angstroms, but is not limited to this thickness.

[0079] It should be noted that in the aforementioned steps S3, S4 and S5, the thickness of the gate oxide layer 203 in the high voltage region is reduced, and thus cannot meet the high voltage requirement of the high voltage region.

[0080] See also Figure 12 and Figure 13 , performing step S6: forming a compensation oxide layer 216 on the high voltage region gate oxide layer 203 , and forming a high voltage region metal gate 217 on the compensation oxide layer 216 .

[0081] Specifically, such as Figure 12 FIG. 2 is a schematic cross-sectional view of the structure obtained after forming a compensation oxide layer 216 on the high-voltage region gate oxide layer 203. The thickness of the compensation oxide layer 216 can be adjusted according to actual high-voltage requirements and is not particularly limited herein. The material of the compensation oxide layer 216 is preferably the same as that of the high-voltage region gate oxide layer 203.

[0082] In this embodiment, the compensation oxide layer 216 also extends to the core region, serving as a part of the interlayer dielectric layer.

[0083] Specifically, such as Figure 13 FIG. 2 is a schematic cross-sectional view of the structure obtained after forming a high-voltage metal gate 217 on the compensation oxide layer 203. The high-voltage metal gate 217 may include a bottom barrier layer, a top barrier layer, and a work function layer sandwiched between the bottom and top barrier layers. Typically, an N-type work function layer, such as TiAl, is used in N-type semiconductor devices. The work function of the N-type work function layer is close to the conduction band of a semiconductor substrate, such as a silicon substrate, which helps lower the threshold voltage of the N-type semiconductor device. A P-type work function layer, such as TiN, is used in P-type semiconductor devices. The work function of the P-type work function layer is close to the valence band of a semiconductor substrate, such as a silicon substrate, which helps lower the threshold voltage, i.e., the absolute value, of the threshold voltage of the P-type semiconductor device. In this embodiment, the specific structure and composition of the high-voltage metal gate 217 can be adjusted according to actual needs and are not particularly limited herein.

[0084] See also Figure 14, continue to perform the following steps: forming a second interlayer dielectric layer 218 covering the high-voltage area metal gate 217 on the compensation oxide layer 216, and forming a gate contact portion 219 that penetrates the second interlayer dielectric layer 218 and contacts the high-voltage area metal gate 217, forming a source contact portion 220 that penetrates the second interlayer dielectric layer 218, the compensation oxide layer 216 and the first interlayer dielectric layer 213 and contacts the source region 210, and forming a drain contact portion 221 that penetrates the second interlayer dielectric layer 218, the compensation oxide layer 216 and the first interlayer dielectric layer 213 and contacts the drain region 211.

[0085] At this point, a high-voltage MOSFET device is manufactured. In the manufacturing method of the high-voltage MOSFET device of this embodiment, only the high-voltage area gate oxide layer is used to define the high-voltage gate in the front-end process, and the high-voltage area gate oxide layer and the polysilicon pseudo gate in the core area can be controlled to have the same top surface height through CMP. The sidewall protection layer can protect the high-voltage area gate oxide layer in the intermediate process. After the polysilicon pseudo gate in the core area is replaced by the metal gate, the film layer height of the high-voltage area and the core area is not much different, which will not affect the load of the CMP of the metal gate in the core area, and the high-voltage area gate oxide layer and the metal gate in the core area can be controlled to be the same height through CMP. Subsequently, the required EOT of the high-voltage area can be supplemented by re-laying the compensation oxide layer on the high-voltage area gate oxide layer.

[0086] Example 2

[0087] This embodiment provides a high voltage MOSFET device, which can be manufactured using the manufacturing method of the MOSFET device described in the first embodiment or other suitable methods. Figure 14 , which is a schematic diagram of the cross-sectional structure of the high-voltage MOSFET device of this embodiment, includes a semiconductor layer 201, a high-voltage region high-K metal gate structure, a core region high-K metal gate structure and a sidewall protection layer 209, wherein the high-voltage region high-K metal gate structure is located on the semiconductor layer 201 and includes a high-voltage region gate oxide layer 203, a compensation oxide layer 216 and a high-voltage region metal gate 217 stacked sequentially from bottom to top; the core region high-K metal gate structure is located on the semiconductor layer 201 and includes a core region gate oxide layer 205 and a core region metal gate 215 stacked sequentially from bottom to top; the sidewall protection layer 209 is located on the sidewalls of the high-voltage region gate oxide layer 203, the sidewalls of the core region gate oxide layer 205 and the sidewalls of the core region metal gate 215.

[0088] In summary, the manufacturing method of the high-voltage MOSFET device of the present invention includes the following steps: forming a first stacking structure and a second stacking structure on a semiconductor layer, the first stacking structure is located in the high-voltage area and includes a high-voltage area gate oxide layer and a first hard mask layer stacked in sequence from bottom to top, and the second stacking structure is located in the core area and includes a core area gate oxide layer, a polysilicon pseudo gate layer, a second hard mask layer and a third hard mask layer stacked in sequence from bottom to top; forming a sidewall protection layer on the side walls of the first and second stacking structures; forming a grinding stop layer and a first interlayer dielectric layer and thinning the first interlayer dielectric layer until the top surface of the high-voltage area gate oxide layer and the top surface of the polysilicon pseudo gate layer are exposed; replacing the polysilicon pseudo gate to obtain a core area metal gate, and performing chemical mechanical grinding on the core area metal gate; forming a compensation oxide layer on the high-voltage area gate oxide layer, and forming a high-voltage area metal gate on the compensation oxide layer. In the front-end process, the present invention uses only the high-voltage region gate oxide layer to define the high-voltage gate. CMP can be used to control the high-voltage region gate oxide layer and the polysilicon dummy gate in the core region to have the same top surface height. A sidewall protection layer can protect the high-voltage region gate oxide layer during the intermediate process. After the polysilicon dummy gate in the core region is replaced with a metal gate, the film layer height difference between the high-voltage region and the core region is minimal, which does not affect the CMP load of the core region metal gate. Furthermore, the high-voltage region gate oxide layer can be controlled to be the same height as the metal gate in the core region through CMP. Subsequently, by re-laying a compensation oxide layer on the high-voltage region gate oxide layer, the required EOT of the high-voltage region can be compensated. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial application value.

[0089] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for manufacturing a high-voltage MOSFET device, characterized in that: The following steps are involved: A semiconductor layer is provided, and a first stacked structure and a second stacked structure are formed on the semiconductor layer. The semiconductor layer includes a high-voltage region and a core region spaced apart in a horizontal direction. The first stacked structure is located in the high-voltage region and includes a high-voltage region gate oxide layer and a first hard mask layer stacked sequentially from bottom to top. The second stacked structure is located in the core region and includes a core region gate oxide layer, a polysilicon dummy gate layer, a second hard mask layer, and a third hard mask layer stacked sequentially from bottom to top. forming a sidewall protection layer on the sidewalls of the first stacking structure and the sidewalls of the second stacking structure; forming a grinding stop layer and a first interlayer dielectric layer on the semiconductor layer in sequence, wherein the grinding stop layer covers the first stacked structure, the second stacked structure, and the exposed surface of the sidewall protection layer, and the first interlayer dielectric layer covers the grinding stop layer, and then thinning the first interlayer dielectric layer until the top surface of the high-voltage region gate oxide layer and the top surface of the polysilicon dummy gate layer are exposed; removing the polysilicon dummy gate to obtain a groove located in the core area and sandwiched between the sidewall protection layers; forming a core metal gate in the groove, and performing chemical mechanical polishing on the core metal gate; A compensation oxide layer is formed on the high-voltage region gate oxide layer, and a high-voltage region metal gate is formed on the compensation oxide layer.

2. The method for manufacturing a high-voltage MOSFET device according to claim 1, wherein: A top surface of the first stacking structure is lower than a top surface of the second stacking structure.

3. The method for manufacturing a high-voltage MOSFET device according to claim 1, wherein: In the step of forming the first stacking structure and the second stacking structure on the semiconductor layer, the high-voltage region gate oxide layer and the first hard mask layer are formed first, and then the polysilicon pseudo gate, the second hard mask layer and the third hard mask layer are formed, and the polysilicon layer is not retained on the first hard mask layer.

4. The method for manufacturing a high-voltage MOSFET device according to claim 1, wherein: The thinning of the first interlayer dielectric layer until the top surface of the high-voltage region gate oxide layer and the top surface of the polysilicon dummy gate layer are exposed comprises the following steps: Performing chemical mechanical polishing on the first interlayer dielectric layer and stopping at the polishing stop layer on the first hard mask layer and the third hard mask layer; etching back the first interlayer dielectric layer and stopping at the first hard mask layer and the second hard mask layer; Chemical mechanical polishing is performed on the first interlayer dielectric layer and stops at the high-voltage region gate oxide layer and the polysilicon dummy gate layer.

5. The method for manufacturing a high-voltage MOSFET device according to claim 4, wherein: After chemical mechanical polishing is performed on the first interlayer dielectric layer and stops at the high-voltage region gate oxide layer and the polysilicon dummy gate layer, the top surfaces of the high-voltage region gate oxide layer and the polysilicon dummy gate layer are at the same height.

6. The method for manufacturing a high-voltage MOSFET device according to claim 1, wherein: After chemical mechanical polishing is performed on the core area metal gate, the high voltage area gate oxide layer is at the same height as the top surface of the core area metal gate.

7. The method for manufacturing a high-voltage MOSFET device according to claim 1, wherein: The following steps are also included: A second interlayer dielectric layer covering the high voltage region metal gate is formed on the compensation oxide layer.

8. A high voltage MOSFET device, characterized in that: include: semiconductor layer; A high-voltage region high-K metal gate structure is located on the semiconductor layer and includes a high-voltage region gate oxide layer, a compensation oxide layer and a high-voltage region metal gate stacked sequentially from bottom to top; A core region high-K metal gate structure is located on the semiconductor layer and includes a core region gate oxide layer and a core region metal gate stacked sequentially from bottom to top; A sidewall protection layer is located on the sidewalls of the gate oxide layer in the high-voltage region, the sidewalls of the gate oxide layer in the core region, and the sidewalls of the metal gate in the core region; The high-voltage MOSFET device is formed by using the method for manufacturing a high-voltage MOSFET device according to any one of claims 1 to 7.

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