Semiconductor device and method for manufacturing the same

Abstract

This application relates to semiconductor devices and their fabrication methods. The method involves creating a first trench on the upper surface of a substrate between two adjacent device regions, forming a first well region in the substrate between the two adjacent device regions (located below the first trench), forming a first trench isolation structure within the first trench, and then forming the device region, thereby fabricating the semiconductor device. The first well region, utilizing the first trench as an implantation channel, effectively increases the implantation depth, improves the isolation effect between devices, shortens the diffusion distance between adjacent device regions, reduces the depletion region, further reduces the device area, and improves chip integration.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to semiconductor devices and their fabrication methods. Background Technology

[0002] In electronic devices, deep well isolation offers advantages such as reducing leakage current, increasing breakdown voltage, and minimizing spacing between adjacent devices. However, due to limitations in instrument-side injection capability, the depth of deep well injection is limited in some electronic devices, leading to reduced deep well isolation effectiveness, increased device footprint, and decreased chip integration density. Summary of the Invention

[0003] Therefore, it is necessary to provide a semiconductor device and its fabrication method to increase the depth of deep well implantation, improve the effect of deep well isolation, and increase the integration density of the device.

[0004] To achieve the objectives of this application, the following technical solution is adopted:

[0005] A method for fabricating a semiconductor device, comprising:

[0006] A substrate is provided, the substrate including a plurality of device regions, the substrate having a first conductivity type;

[0007] A first trench is formed on the upper surface of the substrate between two adjacent device regions;

[0008] A first well region is formed in the substrate between two adjacent device regions, the first well region being located below the first trench, and the first well region having a first conductivity type;

[0009] A first groove isolation structure is formed in the first groove;

[0010] A device is formed in the device region.

[0011] In one embodiment, forming a first well region in the substrate between two adjacent device regions includes:

[0012] Ion implantation of a first conductivity type is performed on the substrate between two adjacent device regions to form the first well region, wherein at least a portion of the ions are implanted into the substrate through the first trench.

[0013] In one embodiment, the first trench is tangent to the edge of the adjacent device region, or the first trench is partially formed on the adjacent device region.

[0014] In one embodiment, the number of first trenches between two adjacent device regions is at least two, and the first trench near the device region is tangent to the edge of the device region, or the first trench near the device region is partially formed on the device region.

[0015] In one embodiment, the depth of the first trench is 4000 Å to 6000 Å.

[0016] In one embodiment, forming a semiconductor device in the device region includes:

[0017] A second well region is formed in the device region, the second well region having a second conductivity type, the second conductivity type being opposite to the first conductivity type;

[0018] A third well region is formed on the upper surface layer of the second well region, and the third well region has a first conductivity type.

[0019] In one embodiment, the doping concentration of the first well region is greater than the doping concentration of the substrate, and the doping concentration of the first well region is less than the doping concentration of the third well region.

[0020] In one embodiment, the preparation method further includes:

[0021] A second trench is formed on the upper surface of the substrate, the second trench being located between the second well region and the third well region;

[0022] A second trench isolation structure is formed in the second trench.

[0023] In one embodiment, forming a semiconductor device in the device region further includes:

[0024] A fourth well region is formed on the upper surface of the substrate between two adjacent second well regions, the fourth well region having a first conductivity type.

[0025] In one embodiment, the preparation method further includes:

[0026] The first slot isolation structure and the first well region are annealed.

[0027] In one embodiment, the annealing temperature is 900℃~1200℃ and the annealing time is 80min~150min.

[0028] A semiconductor device, comprising:

[0029] A substrate, the substrate comprising a plurality of device regions, the substrate having a first conductivity type;

[0030] The first trench isolation structure is located on the upper surface of the substrate between two adjacent device regions;

[0031] A first well region is located in the substrate between two adjacent device regions, the first well region is located below the first trench isolation structure, and the first well region has a first conductivity type.

[0032] The device is located in the device region;

[0033] In the direction perpendicular to the upper surface of the substrate, the depth of the device is less than the depth of the first well region.

[0034] In one embodiment, the device includes:

[0035] A second well region is located in the device region, and the second well region has a second conductivity type that is opposite to the first conductivity type.

[0036] A third well region is located on the upper surface of the second well region, and the third well region has a first conductivity type;

[0037] In the direction perpendicular to the upper surface of the substrate, the depth of the second well region is less than the depth of the first well region.

[0038] In one embodiment, the projection area of ​​the first well region onto the substrate is tangent to or overlaps with the projection area of ​​the second well region onto the substrate.

[0039] In one embodiment, the semiconductor device further includes:

[0040] The second trench isolation structure is located between the second well region and the third well region.

[0041] In one embodiment, the number of first trench isolation structures between two adjacent device regions is at least two, and the first trench isolation structure near the device region is tangent to or overlaps with the edge of the device region.

[0042] In one embodiment, the first well region is formed in the following manner:

[0043] A substrate is provided, the substrate including a plurality of device regions, the substrate having a first conductivity type;

[0044] A first trench is formed on the upper surface of the substrate between two adjacent device regions;

[0045] A first well region is formed in the substrate between two adjacent device regions, the first well region being located below the first trench, and the first well region having a first conductivity type.

[0046] The semiconductor device and its fabrication method described above fabricate a semiconductor device by forming a first trench on the upper surface of a substrate between two adjacent device regions, forming a first well region in the substrate between the two adjacent device regions and the first well region being located below the first trench, forming a first trench isolation structure in the first trench, and forming a device in the device region. The first well region, using the first trench as an injection channel, effectively increases the injection depth, improves the isolation effect between devices, and simultaneously shortens the diffusion distance between adjacent device regions, reduces the depletion region, further reduces the device area, and improves chip integration. Attached Figure Description

[0047] Figure 1 This is a flowchart of a method for fabricating a semiconductor device in one embodiment;

[0048] Figure 2 This is a schematic diagram of the structure of a semiconductor device in one embodiment;

[0049] Figure 3 This is a schematic diagram of the structure of a semiconductor device in one embodiment;

[0050] Figure 4 This is a schematic diagram of the structure of a semiconductor device in one embodiment;

[0051] Figure 5 This is a schematic diagram of the structure of a semiconductor device in one embodiment;

[0052] Figure 6 This is a schematic diagram of the structure of a semiconductor device in one embodiment;

[0053] Figure 7 This is a schematic diagram of the structure of a semiconductor device in one embodiment;

[0054] Figure 8 This is a flowchart of step 105 in one embodiment;

[0055] Figure 9 This is a schematic diagram of the structure of a semiconductor device in one embodiment;

[0056] Figure 10 This is a schematic diagram of the structure of a semiconductor device in one embodiment;

[0057] Figure 11 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment;

[0058] Figure 12 A schematic diagram of the structure of a semiconductor device prepared by an existing fabrication method;

[0059] Figure 13 This is a cross-sectional view of a simulation diagram of a semiconductor device in one embodiment;

[0060] Figure 14 This is a cross-sectional view of a simulation diagram of an existing semiconductor device in one embodiment;

[0061] Figure 15 This is a cross-sectional view of a simulation diagram of a semiconductor device in one embodiment;

[0062] Figure 16 This is a cross-sectional view of a simulation diagram of an existing semiconductor device in one embodiment. Detailed Implementation

[0063] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0064] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0065] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, conductivity types, and / or portions, these elements, components, areas, layers, conductivity types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, conductivity type, or portion from another element, component, area, layer, conductivity type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first conductivity type may be referred to as the second conductivity type, and similarly, the second conductivity type may be referred to as the first conductivity type; the first conductivity type and the second conductivity type are different conductivity types, for example, the first conductivity type may be P-type and the second conductivity type may be N-type, or the first conductivity type may be N-type and the second conductivity type may be P-type.

[0066] Spatial relation terms such as “below,” “under,” “below,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0067] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0068] In electronic devices, deep well isolation offers advantages such as reducing leakage current, increasing breakdown voltage, and minimizing spacing between adjacent devices. Therefore, deep wells are typically used for isolation between adjacent devices. However, due to limitations in instrument-side injection capabilities, the depth of deep well injection is limited in some electronic devices, leading to reduced deep well isolation effectiveness, increased device footprint, and decreased chip integration density.

[0069] For example, in photodiode devices, light absorption relies on the collection of photogenerated carriers near the depletion region of the photodiode under reverse bias. Different wavelengths of light have different absorption distances in silicon; longer wavelengths require longer absorption distances, necessitating deeper junctions to collect photogenerated carriers. For long wavelengths, the photodiode depth often needs to reach the limit of the instrument's injection capability. However, due to the extremely low doping concentration of the substrate, the depletion region is very wide under reverse bias, and adjacent photodiode depletion regions can easily connect, causing the photodiode to malfunction. To ensure that the depletion regions between photodiodes do not connect during photodiode operation, sufficient distance must be maintained between devices, leading to reduced chip integration and decreased light absorption efficiency. Deep-well injection is typically used to reduce the required distance between photodiodes. However, because the photodiode itself uses a deep-well process to reach the limit of the instrument's injection capability, the depth of the deep-well injection is limited, reducing the deep-well isolation effect. A relatively wide distance is still required between photodiodes, increasing the device's footprint and reducing chip integration.

[0070] To address the aforementioned issues, this embodiment provides a semiconductor device and its fabrication method.

[0071] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment. The fabrication method includes steps 101, 102, 103, 104, and 105.

[0072] Step 101: Provide a substrate, the substrate including multiple device regions, the substrate having a first conductivity type.

[0073] The conductivity type of the first conductivity type doping is either P-type or N-type. For example, in this embodiment, the first conductivity type is P-type, and the substrate conductivity type is also P-type. A substrate with P-type conductivity can be formed by light ion implantation or doping, wherein the type of implanted ions is selected according to actual needs.

[0074] The device area is used to form devices, and the specific type of device can be set according to actual needs. For example, the device can be a diode or a transistor. Multiple device areas are spaced apart to achieve the spacing of multiple devices.

[0075] Step 102: Create a first trench on the substrate surface between two adjacent device regions.

[0076] The first trench is formed between two adjacent device regions, and in subsequent steps, the first well region is formed between two adjacent device regions and below the first trench. Therefore, the first trench can serve as an injection channel for the subsequent formation of the first well region. The injection medium injected during the formation of the first well region is injected into the substrate at least partially through the first trench. At the same time, the first trench can also be used to form a first trench isolation structure by filling with isolation material in subsequent steps.

[0077] On the one hand, since the first trench is a groove, its bottom must be located inside the substrate. Therefore, the first trench serves as the injection channel for the first well region. The depth of the first trench is beneficial for increasing the injection depth of the first well region even under the limitations of the instrument's injection process, achieving deeper deep-well isolation, improving the isolation effect of the first well region, thereby reducing the device footprint and increasing chip integration density. It should be noted that in this embodiment, the depth of the first well region can be further increased even under the limitations of the instrument's injection process. Therefore, when both the first well region and related well regions in the device region formed using the same deep-well process are injected using the instrument's injection limit, the injection depth of the first well region is deeper than that of other well regions in the device region due to the increased injection depth. In particular, the deeper the first trench, the more beneficial it is to increasing the injection depth of the first well region, thereby achieving a better isolation effect.

[0078] On the other hand, after the first trench is formed in the first well region, a trench isolation structure can be formed by filling it with isolation material to isolate the surface areas between device regions, which is beneficial to the isolation effect between device regions, while avoiding the first trench becoming an idle space or avoiding additional steps to remove it.

[0079] The shape of the first trench is not limited, and the projection shape of the first trench on the cross-sections perpendicular to the adjacent device regions can be rectangular, inverted trapezoidal, etc. Optionally, the opening size of the first trench is greater than or equal to the bottom size of the first trench, so that more injection medium uses the first trench as an injection channel, and so that as much of the injection medium injected into the first trench is injected into the bottom substrate region as possible.

[0080] In some embodiments, the depth of the first trench is 4000 Å to 6000 Å, which simplifies the trenching process and allows the first trench isolation structure to be formed in subsequent steps. Furthermore, the depth of the first trench increases the implantation depth of the first well region. In other embodiments, the depth of the first trench can be selected from other ranges. Without affecting the performance of the device region, a deeper first trench is more beneficial for increasing the implantation depth of the first well region, thereby improving the isolation effect between the device regions.

[0081] In some embodiments, the first trench is tangent to the edge of an adjacent device region, or the first trench is partially formed on an adjacent device region.

[0082] Wherein, when the first trench is tangent to the edge of the adjacent device region, the injection channel of the first well region includes at least the first trench channel tangent to the edge of the device region, so that the injection depth of the first well region is deepened at least in the region tangent to the edge of the device region, thereby improving the isolation effect.

[0083] When the first trench is formed on an adjacent device region, the injection channel of the first well region includes at least a portion of the device region and the substrate region surrounding the device region. As a result, the injection depth of the first well region is deepened in at least a portion of the device region and the substrate region surrounding the device region. At the same time, the width of the first well region in the direction of the adjacent device region is widened, which can better wrap the bottom of the adjacent device region, shorten the diffusion distance of the adjacent device region, reduce the depletion region, further reduce the device area, and improve the chip integration.

[0084] It should be noted that, without affecting the device lead-out and isolation effects on adjacent device regions, in other embodiments, the first trench can also be completely formed on the upper surface layer of the device region, thereby further widening the width range of the first well region in the direction of adjacent device regions. Furthermore, to improve the isolation effect of the surface areas between device regions, when the first trench is completely formed on the device region, one sidewall of the first trench can be tangent to the edge of the device region simultaneously.

[0085] In some embodiments, the number of first trenches between two adjacent device regions is at least two, the first trench near the device region is tangent to the edge of the device region, or the first trench near the device region is partially formed on the device region.

[0086] For example, there are two first trenches, and the two first trenches are tangent to the first trench of the adjacent device area and the edge of the device area (please refer to the reference). Figure 2 Where 100 is the substrate, 101 is the first trench, 110 is the device region, and 120 is the first well region, or the portion of the first trench near the device region is formed on the device region (please refer to the reference). Figure 3 Wherein, 100 is the substrate, 101 is the first trench, 110 is the device region, and 120 is the first well region. When the two first trenches are tangent to the edges of the first trench and device region of the adjacent device region, the depth of at least both sides of the first well region is increased. When the two first trenches are partially formed on the adjacent device region, the depth of at least both sides of the first well region is increased, and the two sides of the first well region diffuse laterally towards the adjacent device region. The width of the first well region in the direction of the adjacent device region increases, which can better enclose the bottom of the adjacent device region, shorten the diffusion distance of the adjacent device region, reduce the depletion region, further reduce the device area, and improve the chip integration density.

[0087] For example, there are three first trenches, with the two first trenches closest to the device area being tangent to the edge of the device area (see [reference]). Figure 4 Wherein, 100 is the substrate, 101 is the first trench, 110 is the device region, and 120 is the first well region), or the portion of the first trench near the device region is formed on the device region (see...). Figure 5 In this diagram, 100 represents the substrate, 101 represents the first trench, 110 represents the device region, and 120 represents the first well region. The third first trench is located between the other two first trenches. With two first trenches, the depth of the middle region of the first well region can also be increased, thereby further improving the isolation effect, reducing the device area, and increasing the chip integration density.

[0088] It should be noted that the multiple first trenches are spaced apart, with at least two first trenches spaced apart, to expose at least a portion of the upper surface area of ​​the substrate. This facilitates the subsequent placement of lead-out terminals on the exposed substrate surface area to bring the substrate out. The width of the first trenches in the direction of adjacent device regions is not limited. Without increasing the spacing between adjacent device regions and ensuring that at least a portion of the upper surface area of ​​the substrate is exposed, the larger the sum of the widths of the multiple first trenches, the larger the injection channel range of the first well region. This is more conducive to increasing the injection depth of the first well region, further improving the isolation effect, reducing device area, and increasing chip integration density.

[0089] Step 103: A first well region is formed in the substrate between two adjacent device regions. The first well region is located below the first trench and has a first conductivity type.

[0090] The first well region is a deep-well isolation structure for adjacent devices, used to isolate them. The first well region and the substrate have the same conductivity type, both being of the first conductivity type. When the substrate has a P-type conductivity type, the first well region also has a P-type conductivity type.

[0091] The first well region is located between adjacent device regions and below the first trench. The first well region is formed using an implantation process, whereby at least a portion of the implanted medium is injected into the substrate through the first trench during its formation. This increases the implantation depth due to the depth of the first trench. Optionally, the implanted medium is ions. Step 103 includes: performing ion implantation of a first conductivity type on the substrate between two adjacent device regions to form the first well region, wherein at least a portion of the ions are implanted into the substrate through the first trench, thereby further deepening the depth of the portion of the first well region formed by the first trench implantation.

[0092] In step 102, the injection depth and width of the first well region in the direction of the adjacent device region are affected by the depth, width and number of the first trenches. For a related description, please refer to the relevant description in step 102.

[0093] Step 104: Form the first trench isolation structure in the first trench.

[0094] In this process, after the first trench is formed in the first well region, it can be filled with an insulating material to form a first trench isolation structure. The first trench isolation structure is used to isolate the surface area between device regions, which is beneficial to the isolation effect between device regions.

[0095] The location of the first trench isolation structure is determined by the location of the first trench. For example, when there are two first trenches between adjacent device areas and the first trench portion is located within the device area, the first trench isolation structure is as follows: Figure 6 As shown ( Figure 6 (130 is the first slot isolation structure). Optionally, as shown in 7 ( Figure 7 In the figure, 130 represents the first trench isolation structure (only the substrate 100, the first trench isolation structure 130, and the device 110 area are shown). The first trench isolation structure surrounds the device area, and its orthographic projection onto the upper surface of the substrate is annular. Optionally, the upper surface of the first trench isolation structure is flush with the substrate surface.

[0096] In some embodiments, the fabrication method further includes the step of annealing the first trench isolation structure and the first well region. Annealing facilitates the formation of the first trench isolation structure and also promotes the thermal activation and further diffusion of the implanted medium, such as implanted ions, in the first well region, thereby increasing the depth and width of the first well region. It should be noted that existing methods for fabricating the first trench isolation structure include both trench creation and annealing. Therefore, in this embodiment, the formation step of the first well region is placed after the creation of the first trench and before the annealing of the first trench isolation structure. This not only facilitates increasing the depth and width of the first well region but also avoids adding additional steps, thus improving the device isolation effect while avoiding increased fabrication costs.

[0097] In some embodiments, the annealing temperature is 900°C to 1200°C, and the annealing time is 80 min to 150 min. Under these annealing conditions, deeper deep-well isolation is achieved, increasing the depth by 0.5 μm to 1 μm compared to the injection limit of existing equipment.

[0098] Step 105: Form the device in the device region.

[0099] The device area is formed into corresponding devices according to the actual application. The devices typically include other functional well regions using deep well technology. Isolation is achieved by setting a first trench isolation structure on the substrate surface area between adjacent devices, and by a first well region in the middle area of ​​the substrate between adjacent devices. Therefore, the isolation effect between adjacent devices in this embodiment is excellent, which can reduce the area between adjacent devices and improve chip integration.

[0100] Figure 6 It shows the basis Figure 1 A schematic diagram of the structure of one of the semiconductor devices 10 prepared by the preparation method of the related embodiments.

[0101] In this embodiment, the semiconductor device 10 includes a substrate 100, a device 110, a first well region 120, and a first trench isolation structure 130.

[0102] The substrate 100 includes multiple device regions 110 and has a first conductivity type.

[0103] The first trench isolation structure 130 is located on the upper surface of the substrate 100 between two adjacent device 110 regions. In some embodiments, the number of first trench isolation structures 130 between two adjacent device 110 regions is at least two, and the first trench isolation structure 130 near the device 110 region is tangent to or overlaps with the edge of the device 110 region.

[0104] The first well region 120 is located in the substrate 100 between two adjacent device 110 regions and is located below the first trench isolation structure 130. The first well region 120 has a first conductivity type. In some embodiments, the projection area of ​​the first well region 120 onto the substrate 100 is tangent to or overlaps with the two adjacent device 110 regions.

[0105] In this device 110, the device 110 is located in the device 110 region, and in the direction perpendicular to the upper surface of the substrate 100, the depth of the device 110 is less than the depth of the first well region 120.

[0106] In some embodiments, the device includes a second well region and a third well region. See also Figure 8 Step 105 includes steps 201 and 202.

[0107] Step 201: Form a second well region in the device region. The second well region has a second conductivity type, which is opposite to the first conductivity type.

[0108] Step 202: A third well region is formed on the upper surface of the second well region, the third well region having a first conductivity type.

[0109] In this system, the second conductivity type is opposite to the first conductivity type; when the first conductivity type is P-type, the second conductivity type is N-type. The conductivity type of the second well region is opposite to that of the substrate, while the conductivity type of the bottom of the third well region is the same. Figure 9 As shown ( Figure 9 In this configuration, 210 is the second well region, 220 is the third well region, and the first trench isolation structure 130 is partially located on the second well region 210. PN junctions are formed between the second and third well regions and between the second well region and the substrate. Under reverse bias, photogenerated carriers are collected, thereby forming a photodiode with the second well region, the third well region, and the substrate. Adjacent photojunctions are isolated by the first well region. In some embodiments, the second well region is located on the upper surface layer of the substrate, and the third well region is located on the upper surface layer of the second well region. The second well region surrounds the third well region to form a bowl-shaped structure enclosing the third well region. In one embodiment, as... Figure 10 As shown ( Figure 10 The embodiment shown is an example of this, where the orthographic projection of the second well region onto the upper surface of the substrate is annular, and the orthographic projection of the third well region onto the upper surface of the substrate is rectangular.

[0110] In this design, the doping concentration of the first well region is greater than that of the substrate, while the doping concentration of the first well region is less than that of the third well region. This creates a doping concentration gradient between the first and third well regions, which have the same conductivity type, and the substrate. The first well region effectively isolates the depletion regions between adjacent second well regions, ensuring the normal operation of the photodiode device.

[0111] In some embodiments, after the second well region is formed, an annealing process can be performed to activate the injection medium in the second well region, while also facilitating further diffusion of the injection medium in the first well region. Although the injection medium in both the first and second well regions diffuses further during this annealing process, the first well region undergoes an additional thermal process compared to the second well region, and the injection depth in the first well region begins to increase, ensuring that the depth of the first well region is always greater than that of the second well region. The conditions for this annealing process can be set according to actual needs and are not limited here.

[0112] In some embodiments, such as Figure 9 and Figure 10 As shown (where 230 is the fourth well region), the device also includes a fourth well region, and step 105 includes step 203.

[0113] Step 203: A fourth well region is formed on the upper surface of the substrate between two adjacent second well regions, the fourth well region having a first conductivity type.

[0114] The fourth well region is formed on the upper surface of the substrate between adjacent device regions, above the first well region, and has the same conductivity type as the substrate. The fourth well region is used to bring out the substrate. Specifically, the doping concentration of the fourth well region is greater than that of the first well region, and the doping concentration of the first well region is greater than that of the substrate. Thus, there is a doping concentration gradient between the fourth well region, the first well region, and the substrate, and the fourth well region can effectively bring out the substrate.

[0115] The fourth well region has the same conductivity type as the third well region. Optionally, the injection medium of the fourth well region can also be the same as the injection medium of the third well region, so that the fourth well region can be formed simultaneously with the third well region. Further, the injection depth of the fourth well region can also be the same as the injection depth of the third well region.

[0116] It should be noted that, depending on the actual application requirements, step 105 may include other steps in addition to steps 201-203. For example, it may include forming a fifth well region on the upper surface of the second well region and a sixth well region on the upper surface of the third well region. The fifth well region has the same conductivity type as the second well region, but its doping concentration is higher than that of the second well region. The fifth well region serves as the lead-out region of the second well region to act as a cathode. Similarly, the sixth well region has the same conductivity type as the third well region, but its doping concentration is higher than that of the third well region. The sixth well region serves as the lead-out region of the third well region to act as an anode.

[0117] In some embodiments, such as Figure 11 As shown, the preparation method also includes steps 106 and 107.

[0118] Step 106: A second trench is formed on the upper surface of the substrate, the second trench being located between the second well region and the third well region. The shape and size of the second trench may be the same as or different from the first trench. The formation method of the second trench is the same as that of the first trench, as described in the relevant description of the first trench. Optionally, step 106 may be performed simultaneously with or sequentially with step 102.

[0119] Step 107: Form a second trench isolation structure in the second trench (e.g.) Figure 9 and Figure 10 As shown, Figure 9 and Figure 10 140 in the middle is the second slot isolation structure).

[0120] The second slot isolation structure can be used to isolate the surface areas of the second and third well regions, so that when lead-out terminals are subsequently installed on the surface areas of the second and third well regions, the lead-out terminals are isolated from each other, achieving a better lead-out effect.

[0121] The steps for forming the second trench isolation structure are the same as those for forming the first trench isolation structure, and can be found in the relevant description of the first trench isolation structure. Optionally, the first and second isolation trench structures can be formed simultaneously, that is, steps 107 and 104 can be performed concurrently. In this embodiment, when the second trench and the first trench have the same shape and size, the step of forming the second trench isolation structure precedes the step of forming the second well region.

[0122] It should be noted that the methods for creating the first trench, the first trench isolation structure, the second trench isolation structure, the first well region, the second well region, the third well region, the fourth well region, the fifth well region, and the sixth well region in the above steps can all adopt conventional preparation methods. In this embodiment, the methods for forming the above structures are not further limited.

[0123] In some embodiments, such as Figure 9 As shown, device 110 is a diode device, and device 110 includes a second well region 210 and a third well region 220.

[0124] A second well region 210 is located in region 110 of device 110. The second well region 210 has a second conductivity type, which is opposite to the first conductivity type. The depth of the second well region 210 is less than the depth of the first well region 120 in the direction perpendicular to the upper surface of the substrate 100. In some embodiments, the projection area of ​​the first well region 120 onto the substrate 100 is tangent to or overlaps with the projection area of ​​the second well region 210 onto the substrate 100.

[0125] The third well region 220 is located on the upper surface of the second well region 210, and the third well region 220 has a first conductivity type.

[0126] In some embodiments, such as Figure 9 As shown, device 110 is a diode device. Device 110 also includes a fourth well region 230. The fourth well region 230 is located on the upper surface of substrate 100 between two adjacent second well regions 210. The fourth well region 230 has a first conductivity type and is used to lead out of substrate 100.

[0127] In some embodiments, depending on actual application requirements, the device 110 may further include a fifth well region formed on the upper surface of the second well region 210 and a sixth well region formed on the upper surface of the third well region 220. The fifth well region has the same conductivity type as the second well region 210, and its doping concentration is greater than that of the second well region 210. The fifth well region is led out as a cathode from the second well region 210. The sixth well region has the same conductivity type as the third well region 220, and its doping concentration is greater than that of the third well region 220. The sixth well region is led out as an anode from the third well region 220.

[0128] In some embodiments, such as Figure 9 As shown, the semiconductor device 10 also includes a second trench isolation structure 140 located between the second well region 210 and the third well region 220, for isolating the second well region 210 and the third well region 220.

[0129] The specific descriptions of the substrate 100, the first trench isolation structure 130, the second trench isolation structure 140, the first well region 120, the second well region 210, the third well region 220, the fourth well region 230, the fifth well region, and the sixth well region in the above-described semiconductor device 10 embodiments can be found in the relevant descriptions of the above-described fabrication method embodiments, and will not be repeated here.

[0130] The semiconductor device 10 provided in this embodiment includes a substrate 100, a first trench isolation structure 130, a first well region 120, and a device 110. The first trench isolation structure 130 is located on the upper surface of the substrate 100 between two adjacent device 110 regions. The first well region 120 is located in the substrate 100 between two adjacent device 110 regions and is located below the first trench isolation structure 130. The device 110 is located in the device 110 region. In the direction perpendicular to the upper surface of the substrate 100, the depth of the first well region 120 is greater than the depth of the device 110. The first well region 120 improves the isolation effect between devices 110, and at the same time can shorten the diffusion distance between adjacent device 110 regions, reduce the depletion region, further reduce the area of ​​device 110, and improve chip integration.

[0131] The following are Figure 9 Semiconductor devices prepared by the example preparation method and semiconductor devices prepared by existing preparation methods (e.g.) Figure 12 Simulations were performed (as shown), and the simulation results are as follows: Figure 13 (correspond Figure 9 Example, Figure 13 (The deeper the shading in each region, the higher the doping concentration.) Figure 14 (correspond Figure 12 , Figure 14 As shown in the figure, the deeper the shading in each region, the higher the doping concentration. Figure 14 , Figure 13 The first well region is significantly deeper, better separating the second well region, especially at the bottom (marked by the dashed box). The increased density of the first well region at the bottom greatly reduces the width of the depletion region, which helps to reduce the distance between adjacent second well regions. Simultaneously, due to the increased diffusion distance of the first well region, the outward diffusion distance of the second well region decreases. With the neutralization effect of the first well region, the PN junction shrinks away from adjacent second well regions. This reduction in the diffusion distance of the second well region also significantly reduces the required isolation distance between junctions. Specifically, the diffusion reduction in the second well region and the reduction in the depletion region are both 1.1µm. If the size of a single optojunction is 13µm and the distance between optojunctions is 5µm, the area of ​​a single optojunction (including the isolation area) is reduced by 23%, effectively improving device utilization and reducing costs.

[0132] To better demonstrate the effects of the embodiments of this application, a cross-sectional doping pattern was further simulated with a smaller distance between the second well regions. Figure 15 and Figure 16 All other things being equal, Figure 15 This is a cross-sectional doped image of the structure prepared using the method described in the embodiments of this application. Figure 16 This is a cross-sectional doped image of the structure prepared using existing methods. Figure 16 In the middle, due to insufficient implantation depth, the isolation depth is weakened, and adjacent second well regions are connected at the bottom, resulting in direct interconnection of the devices and device failure; in Figure 15 In this design, the first well region achieves isolation between adjacent second well regions, enabling the device to operate normally under a certain voltage, which greatly improves the chip's integration and yield.

[0133] The fabrication method provided in this embodiment involves creating a first trench on the upper surface of a substrate between two adjacent device regions, forming a first well region in the substrate between the two adjacent device regions and the first well region located below the first trench, forming a first trench isolation structure in the first trench, and forming a device in the device region to achieve the fabrication of a semiconductor device. The first well region, using the first trench as an injection channel, effectively increases the injection depth, improves the isolation effect between devices, and simultaneously shortens the diffusion distance between adjacent device regions, reduces the depletion region, further reduces the device area, and improves chip integration.

[0134] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the above flowcharts may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps. It should be noted that the different embodiments described above can be combined with each other.

[0135] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0136] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate including a plurality of device regions, the substrate having a first conductivity type; A first trench is formed on the upper surface of the substrate between two adjacent device regions; A first well region is formed in the substrate between two adjacent device regions, the first well region being located below the first trench, and the first well region having a first conductivity type; A first groove isolation structure is formed in the first groove; A device is formed in the device region; The process of forming a device in the device region includes: A second well region is formed in the device region, the second well region having a second conductivity type, the second conductivity type being opposite to the first conductivity type; A third well region is formed on the upper surface layer of the second well region, and the third well region has a first conductivity type; Wherein, at least a portion of the injection medium injected during the formation of the first well region is injected into the substrate through the first trench, the doping concentration of the first well region is greater than the doping concentration of the substrate, and the doping concentration of the first well region is less than the doping concentration of the third well region.

2. The preparation method according to claim 1, characterized in that, The formation of a first well region in the substrate between two adjacent device regions includes: Ion implantation of a first conductivity type is performed on the substrate between two adjacent device regions to form the first well region, wherein at least a portion of the ions are implanted into the substrate through the first trench.

3. The preparation method according to claim 1, characterized in that, The first trench is tangent to the edge of the adjacent device region, or the first trench is partially formed on the adjacent device region.

4. The preparation method according to claim 1, characterized in that, The number of first trenches between two adjacent device areas is at least two, and the first trench near the device area is tangent to the edge of the device area, or the first trench near the device area is partially formed on the device area.

5. The preparation method according to claim 1, characterized in that, The depth of the first trench is 4000A to 6000A.

6. The preparation method according to claim 1, characterized in that, The preparation method further includes: A second trench is formed on the upper surface of the substrate, the second trench being located between the second well region and the third well region; A second trench isolation structure is formed in the second trench.

7. The preparation method according to claim 1, characterized in that, The process of forming a device in the device region further includes: A fourth well region is formed on the upper surface of the substrate between two adjacent second well regions, the fourth well region having a first conductivity type.

8. The preparation method according to any one of claims 1-7, characterized in that, The preparation method further includes: The first slot isolation structure and the first well region are annealed.

9. The preparation method according to claim 8, characterized in that, The annealing temperature is 900℃~1200℃, and the annealing time is 80min~150min.

10. A semiconductor device, characterized in that, include: A substrate, the substrate comprising a plurality of device regions, the substrate having a first conductivity type; The first trench isolation structure is located on the upper surface of the substrate between two adjacent device regions; A first well region is located in the substrate between two adjacent device regions, the first well region is located below the first trench isolation structure, and the first well region has a first conductivity type. The device is located in the device region. The device includes a second well region and a third well region. The second well region is located in the device region. The third well region is located on the upper surface of the second well region. The second well region has a second conductivity type. The third well region has a first conductivity type. The second conductivity type is opposite to the first conductivity type. In the direction perpendicular to the upper surface of the substrate, the depth of the device is less than the depth of the first well region. The injection medium injected during the formation of the first well region is at least partially injected into the substrate through the first trench. The first trench is located on the upper surface of the substrate between two adjacent device regions. The first well region is located below the first trench. The first trench isolation structure is formed in the first trench. The doping concentration of the first well region is greater than the doping concentration of the substrate. The doping concentration of the first well region is less than the doping concentration of the third well region.

11. The semiconductor device according to claim 10, characterized in that, In the direction perpendicular to the upper surface of the substrate, the depth of the second well region is less than the depth of the first well region.

12. The semiconductor device according to claim 10, characterized in that, The projection area of ​​the first well region onto the substrate is tangent to or overlaps with the projection area of ​​the second well region onto the substrate.

13. The semiconductor device according to claim 10, characterized in that, The semiconductor device further includes: The second trench isolation structure is located between the second well region and the third well region.

14. The semiconductor device according to claim 10, characterized in that, The number of first slot isolation structures between two adjacent device areas is at least two, and the first slot isolation structure near the device area is tangent to or overlaps with the edge of the device area.

15. The semiconductor device according to claim 10, characterized in that, The depth of the first trench is 4000A to 6000A.

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