Method for preparing semiconductor structure with ESD protection device

Abstract

The present application provides a method for preparing a semiconductor structure having an ESD protection device, wherein an ESD protection device including an ESD gate structure located on the semiconductor substrate is formed on a semiconductor substrate, and then an interlayer dielectric structure covering the semiconductor substrate and the ESD protection device is formed, wherein the interlayer dielectric structure includes a BPSG layer formed by a deposition process and a reflow process, and the weight percentage of the B element and the P element in the BPSG layer are both greater than 4%, and then a patterned photoresist layer is formed on the interlayer dielectric structure, and the interlayer dielectric structure is etched to form contact holes. The BPSG layer prepared in the present application has good fluidity and can effectively reduce the slope of the interlayer dielectric structure at the corner area of the ESD protection device after the reflow process, thereby increasing the thickness of the photoresist layer at the corner area of the ESD protection device and reducing the risk of damage to the interlayer dielectric structure during the etching process.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure with an ESD protection device. Background Art

[0002] Electrostatic discharge (ESD) is the primary cause of electrical overstress (EOS) damage to electronic components and integrated circuit systems. Because static electricity typically causes extremely high instantaneous voltages, this damage is devastating and permanent, potentially burning out circuits.

[0003] In the semiconductor field, ESD events may occur in various links such as chip manufacturing, testing, dicing, packaging, assembly, transportation, board-level and system-level assembly, and the use of finished products. Due to the inevitable contact and friction between equipment and materials, a large amount of charge will accumulate. If the accumulated charge is not discharged in time, it will cause damage to the device. Therefore, ESD failure has become one of the important factors affecting the reliability of current semiconductor devices.

[0004] In the prior art, an ESD protection device is usually provided in a semiconductor device, such as a grounded-gate NMOS (GGNMOS) or a gate-coupled NMOS (GCNMOS) structure. Figure 1 This is a traditional GGNMOS device for ESD protection. The GGNMOS device is formed on a P-type silicon substrate and has a gate (G) and an N-type doped source terminal (S) and drain terminal (D) located on both sides of the gate, as well as a body terminal (B). The drain terminal is connected to the I / O port (Anode), and the gate, source terminal, and body terminal are connected to the ground (Cathode). The drain contact hole is located in the inter-level dielectric (ILD) covering the gate, source, and drain, and is used to fill metal to achieve electrical connection with the corresponding gate, source, and drain terminals. However, in the prior art, after the ILD is formed, the surface of the ILD has a large height difference. In the subsequent process of preparing the contact holes, the coated photoresist has fluidity, which will cause the photoresist in the corner area of the ESD protection device to be relatively thin. During etching, the photoresist in the corner area of the ESD protection device is insufficient and cannot play a good blocking role, which will cause damage to the ILD, making it difficult for the ESD protection device to achieve good performance.

[0005] Therefore, it is necessary to provide a method for preparing a semiconductor structure with an ESD protection device. Summary of the Invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a method for preparing a semiconductor structure with an ESD protection device, so as to solve the problem of etching damage in the corner area of the ESD protection device in the prior art.

[0007] To achieve the above-mentioned and other related objectives, the present application provides a method for preparing a semiconductor structure having an ESD protection device, comprising the following steps:

[0008] providing a semiconductor substrate;

[0009] forming an ESD protection device, the ESD protection device comprising an ESD gate structure located on the semiconductor substrate;

[0010] forming an interlayer dielectric structure covering the semiconductor substrate and the ESD protection device, wherein the interlayer dielectric structure includes a BPSG layer, the BPSG layer is formed by a deposition process and a reflow process, and the weight percentages of the B element and the P element in the BPSG layer are both greater than 4%;

[0011] forming a photoresist layer on the interlayer dielectric structure and patterning the photoresist layer;

[0012] The interlayer dielectric structure is etched to form a contact hole.

[0013] Optionally, the doping weight percentage of the B element is 5% to 9%; the doping weight percentage of the P element is 5% to 9%.

[0014] Optionally, the doping weight ratio of the B element to the P element is 1:1 to 1:1.5.

[0015] Optionally, an angle between a surface of the formed BPSG layer at a corner area of the ESD protection device and a horizontal plane is in a range of 15° to 35°.

[0016] Optionally, the angle between the surface of the formed photoresist layer at the corner area of the ESD protection device and the horizontal plane is in the range of 5° to 10°.

[0017] Optionally, a thickness variation of the formed photoresist layer at a corner area of the ESD protection device compared with a thickness variation of an adjacent area is less than 10%.

[0018] Optionally, the deposition process of the BPSG layer includes plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD).

[0019] Optionally, the temperature range of the reflow process is 850° C. to 950° C., and the holding time is 20 min to 40 min.

[0020] Optionally, the interlayer dielectric structure further includes a silicon oxide layer, and the silicon oxide layer is located below the BPSG layer.

[0021] Optionally, the ESD protection device includes a GGNMOS device and a GCNMOS device.

[0022] The BPSG layer in the semiconductor structure with the ESD protection device prepared in the present application has good fluidity. After the reflow process, the slope of the interlayer dielectric structure at the corner area of the ESD protection device can be effectively reduced, thereby increasing the thickness of the photoresist layer at the corner area of the ESD protection device and reducing the risk of damage to the interlayer dielectric structure during the etching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Shown is a schematic structural diagram of a GGNMOS protection device in the prior art.

[0024] Figure 2 Shown is a process flow diagram of a method for preparing a semiconductor structure with an ESD protection device according to the present application.

[0025] Figure 3 Shown is a schematic structural diagram of the semiconductor structure prepared in this application.

[0026] Figure 4 Shown is a SEM image of the semiconductor structure prepared in this application.

[0027] Component number description

[0028] 100 semiconductor substrate

[0029] 201 ESD Gate Structure

[0030] 300 interlayer dielectric structure

[0031] 400 photoresist layer

[0032] A. Corner area of ESD protection device

[0033] Angle θ1, θ2

[0034] d thickness

[0035] Steps S1 to S5 DETAILED DESCRIPTION

[0036] The following describes the embodiments of the present application through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present application from the disclosure herein. The present application may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present application.

[0037] For example, when describing the embodiments of this application, cross-sectional views of device structures may be partially enlarged to a different scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of protection of this application. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0038] For ease of description, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may be present. As used herein, "between" is inclusive of both endpoints.

[0039] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.

[0040] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present application in a schematic manner. Therefore, the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0041] See Figure 2 This embodiment provides a method for preparing a semiconductor structure having an ESD protection device, comprising the following steps:

[0042] S1: providing a semiconductor substrate;

[0043] S2: forming an ESD protection device, wherein the ESD protection device includes an ESD gate structure located on the semiconductor substrate;

[0044] S3: forming an interlayer dielectric structure covering the semiconductor substrate and the ESD protection device, wherein the interlayer dielectric structure includes a BPSG layer, the BPSG layer is formed by a deposition process and a reflow process, and the weight percentages of the B element and the P element in the BPSG layer are both greater than 4%;

[0045] S4: forming a photoresist layer on the interlayer dielectric structure, and patterning the photoresist layer;

[0046] S5: etching the interlayer dielectric structure to form a contact hole.

[0047] The weight percentages of the B element and the P element in the BPSG layer in this embodiment are both greater than 4%, and the BPSG layer with good fluidity can be prepared. After the reflow process, the slope of the interlayer dielectric structure at the corner area of the ESD protection device can be effectively reduced, thereby increasing the thickness of the photoresist layer at the corner area of the ESD protection device and reducing the risk of damage to the interlayer dielectric structure during the etching process.

[0048] For the specific preparation method, please refer to the following steps:

[0049] First, step S1 is performed to provide a semiconductor substrate 100. The semiconductor substrate 100 can be a silicon substrate, but is not limited thereto. An SOI substrate, etc. can also be used. The specific selection can be made according to needs and is not excessively restricted here.

[0050] Next, step S2 is performed to form an ESD protection device, where the ESD protection device includes an ESD gate structure 201 located on the semiconductor substrate 100 .

[0051] For details, see Figure 3 The figure only illustrates the ESD gate structure 201 located on the semiconductor substrate 100, and does not illustrate the source and drain ends of the ESD protection device. Those skilled in the art can refer to Figure 1 , or forming a doping source terminal and a doping drain terminal in the semiconductor substrate 100 by ion implantation or the like as needed, and Figure 3 The ESD gate structure 201 includes a polysilicon gate and a silicon oxide layer between the polysilicon gate and the semiconductor substrate 100. The ESD protection device formed may include a GGNMOS device and a GCNMOS device, and the specific type of the ESD protection device is not excessively limited here.

[0052] Next, step S3 is performed to form an interlayer dielectric structure 300 covering the semiconductor substrate 100 and the ESD protection device. The interlayer dielectric structure 300 includes a BPSG layer. The BPSG layer is formed by a deposition process and a reflow process, and the weight percentages of the B element and the P element in the BPSG layer are both greater than 4%.

[0053] As an example, the interlayer dielectric structure 300 further includes a silicon oxide layer, and the silicon oxide layer is located below the BPSG layer.

[0054] Specifically, when forming the interlayer dielectric structure 300, a silicon oxide layer can be first formed by a deposition process, and then a BPSG layer can be formed on the silicon oxide layer, so that the silicon oxide layer can serve as an isolation layer between the semiconductor layer and the subsequent metal layer. In order to improve the surface flatness, it is preferred to form the BPSG layer on the silicon oxide layer.

[0055] As an example, the doping weight percentage of the B element may be 5% to 9%; the doping weight percentage of the P element may be 5% to 9%.

[0056] Specifically, to improve the surface flatness of the BPSG layer, in this embodiment, the doping weight percentage of the B element is preferably 5% to 9%, such as 5%, 6%, 7%, 8%, and 9%, and the doping weight percentage of the P element is preferably 5% to 9%, such as 5%, 6%, 7%, 8%, and 9%. The doping weight ratio of the B element to the P element can be 1:1, 1:1.2, and 1:1.5, for example. For example, the doping weight percentages of the B element and the P element can be 6% to 6%, 6% to 8%, and the specific ratio can be selected as needed. In this embodiment, the doping weight percentages of the B element and the P element are both 6%, but this is not limited to this. The doping weight percentage of the P element can also be greater than the doping weight percentage of the B element.

[0057] As an example, the deposition process of the BPSG layer may include plasma enhanced chemical vapor deposition (PECVD) or high-low pressure chemical vapor deposition (LPCVD); the temperature range of the reflow process may be 850°C to 950°C, and the holding time may include 20min to 40min.

[0058] Specifically, the deposition process for the BPSG layer may include plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD), but is not limited thereto. Other CVD deposition methods may also be used. After depositing the BPSG layer, a reflow process is required to flatten the BPSG layer, forming a BPSG layer with good flatness. In this embodiment, the reflow process temperature range is preferably 850°C to 950°C, such as 850°C, 900°C, or 950°C, and the holding time may be 20 minutes, 30 minutes, or 40 minutes, etc., and can be selected based on specific needs.

[0059] As an example, the angle between the surface of the BPSG layer at the corner area of the ESD protection device and the horizontal plane is in a range of 15° to 35°.

[0060] Specifically, in this embodiment, Figure 4 The angle θ1 between the surface of the BPSG layer at the corner region A of the ESD protection device and the horizontal plane is 20°, but this is not limited to this. The angle θ1 between the surface of the BPSG layer and the horizontal plane can also be 15°, 25°, etc., and is not excessively limited here. In this embodiment, because the weight percentages of the B element and the P element in the BPSG layer are both greater than 4%, a smaller angle θ1 can be formed between the corner region A of the ESD protection device and the horizontal plane, thereby forming an inclined surface with a smaller slope.

[0061] Next, step S4 is performed: forming a photoresist layer 400 on the interlayer dielectric structure 300 and patterning the photoresist layer 400 .

[0062] Specifically, the process of forming the photoresist layer 400 is not overly restricted here. In this embodiment, since an inclined surface with a smaller slope is formed at the corner area A of the ESD protection device, the photoresist layer 400 formed on the interlayer dielectric structure 300 can have a smaller thickness variation.

[0063] As an example, the thickness of the formed photoresist layer 400 at the corner area A of the ESD protection device varies by less than 10% compared with the thickness of the adjacent area, such as 8%, 5%, etc., so that a relatively flat photoresist layer 400 can be formed, wherein the angle θ2 between the formed photoresist layer 400 at the corner area A of the ESD protection device and the horizontal plane can range from 5° to 10°, such as 5°, 8°, 10°, etc., and the value of the angle θ2 is smaller than the angle θ1, so that the thickness of the photoresist layer 400 at the corner area A of the ESD protection device can be increased, thereby reducing the risk of damage to the interlayer dielectric structure 300 during the etching process.

[0064] The thickness d of the formed photoresist layer 400 at the corner area A of the ESD protection device may be 0.5 μm to 1.0 μm, such as 0.5 μm, 0.6 μm, 0.8 μm, 1.0 μm, etc.

[0065] Next, step S5 is performed to etch the interlayer dielectric structure 300 to form contact holes (not shown).

[0066] Specifically, the patterned photoresist layer 400 is used as a mask to etch the interlayer dielectric structure 300 to form a contact hole, which facilitates the subsequent formation of a metal contact with the ESD protection device for electrical lead-out. The steps for forming the contact hole and the metal contact are not limited here.

[0067] In summary, the method for preparing a semiconductor structure with an ESD protection device of the present application forms an ESD protection device including an ESD gate structure located on the semiconductor substrate on a semiconductor substrate, and then forms an interlayer dielectric structure covering the semiconductor substrate and the ESD protection device, the interlayer dielectric structure including a BPSG layer formed by a deposition process and a reflow process, and the weight percentages of the B element and the P element in the BPSG layer are both greater than 4%, and then a patterned photoresist layer is formed on the interlayer dielectric structure, and the interlayer dielectric structure is etched to form contact holes. The BPSG layer prepared in the present application has good fluidity, and after the reflow process, the slope of the interlayer dielectric structure at the corner area of the ESD protection device can be effectively reduced, thereby increasing the thickness of the photoresist layer at the corner area of the ESD protection device and reducing the risk of damage to the interlayer dielectric structure during the etching process.

[0068] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this application shall be covered by the claims of this application.

Claims

1. A method for preparing a semiconductor structure having an ESD protection device, characterized in that: The following steps are involved: Providing a semiconductor substrate (100); forming an ESD protection device, the ESD protection device comprising an ESD gate structure (201) located on the semiconductor substrate (100); forming an interlayer dielectric structure (300) covering the semiconductor substrate (100) and the ESD protection device, wherein the interlayer dielectric structure (300) comprises a BPSG layer, the BPSG layer is formed by a deposition process and a reflow process, and the weight percentages of the B element and the P element in the BPSG layer are both greater than 4%; forming a photoresist layer (400) on the interlayer dielectric structure (300), and patterning the photoresist layer (400); The interlayer dielectric structure (300) is etched to form a contact hole.

2. The method for preparing a semiconductor structure having an ESD protection device according to claim 1, wherein: The doping weight percentage of the B element is 5% to 9%; the doping weight percentage of the P element is 5% to 9%.

3. The method for preparing a semiconductor structure having an ESD protection device according to claim 1, wherein: The doping weight ratio of the B element to the P element is 1:1 to 1:1.

5.

4. The method for preparing a semiconductor structure having an ESD protection device according to claim 1, wherein: The angle between the surface of the formed BPSG layer at the corner area of the ESD protection device and the horizontal plane is in the range of 15° to 35°.

5. The method for preparing a semiconductor structure with an ESD protection device according to claim 1, wherein: The angle between the surface of the formed photoresist layer (400) at the corner area of the ESD protection device and the horizontal plane is in the range of 5° to 10°.

6. The method for preparing a semiconductor structure with an ESD protection device according to claim 1, wherein: The thickness of the formed photoresist layer (400) at the corner area of the ESD protection device varies by less than 10% compared with the thickness of the adjacent area.

7. The method for preparing a semiconductor structure having an ESD protection device according to claim 1, wherein: The deposition process of the BPSG layer includes plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD).

8. The method for preparing a semiconductor structure having an ESD protection device according to claim 1, wherein: The temperature range of the reflow process is 850° C. to 950° C., and the holding time is 20 min to 40 min.

9. The method for preparing a semiconductor structure having an ESD protection device according to claim 1, wherein: The interlayer dielectric structure (300) further comprises a silicon oxide layer, and the silicon oxide layer is located below the BPSG layer.

10. The method for preparing a semiconductor structure with an ESD protection device according to claim 1, wherein: The ESD protection devices include GGNMOS devices and GCNMOS devices.

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