Multi-level cache circuit unit structure and manufacturing method for monolithic 3D heterogeneous integration

Abstract

The application relates to a single-chip 3D heterogeneous integrated multi-level cache circuit unit structure and a manufacturing method thereof. The structure comprises four functional layers stacked from bottom to top: an SRAM cache layer, a capacitor-free DRAM layer, a ferroelectric field effect transistor storage layer and a ferroelectric diode layer, and a vertical direct contact hole passing through each layer; the SRAM cache layer takes silicon as a substrate; and the capacitor-free DRAM layer and the ferroelectric field effect transistor storage layer are both free of substrates and are directly arranged on the surface of the functional layer below; a metal interconnection layer is arranged between the ferroelectric diode layer and the ferroelectric field effect transistor storage layer; a conductive plug is filled in the vertical direct contact hole, and the conductive plug is interconnected with the metal interconnection layer and the drain in the SRAM cache layer, the drain in the capacitor-free DRAM layer and the drain in the ferroelectric field effect transistor storage layer. The application solves the problem that the interconnection channel between each level of cache in the existing cache architecture is relatively long, resulting in high delay.

Description

Technical Field

[0001] This invention relates to the field of memory, and in particular to a monolithic 3D heterogeneous integrated multi-level cache circuit unit structure and manufacturing method. Background Technology

[0002] To improve execution efficiency and reduce CPU-memory interaction (which impacts CPU efficiency), modern computers typically integrate a multi-level cache architecture on the CPU, commonly a three-level cache architecture: high-speed SRAM cache, DRAM main memory, and large-capacity secondary storage. With the advancement of Moore's Law, the performance of SRAM in the CPU has improved significantly. However, the charging and discharging speed of DRAM capacitors and the interface bandwidth between DRAM and the processor have improved slowly, leading to a widening performance gap between the two. This, in turn, reduces computer processing speed and increases power consumption.

[0003] Furthermore, with the advent of the artificial intelligence era, the amount of data is constantly increasing, requiring DRAM to be frequently refreshed to store temporary data, which increases power consumption. To reduce DRAM refresh rate and thus power consumption, one approach is to utilize DRAM with a 2TOC structure that offers long retention characteristics; another approach is to use a hybrid main memory structure of DRAM + NVM (non-volatile memory) to handle cold and hot data. Cold data is stored in NVM and does not require frequent refresh, while hot data is stored in DRAM, thereby reducing refresh rate and power consumption. In circuits, using 3D integration technology to sequentially stack high-speed SRAM cache, DRAM main memory, NVM, and large-capacity external storage to form 3D in-memory computing chips or circuits can significantly reduce the wiring distance between different levels of memory, reduce latency, and greatly improve memory access bandwidth, thereby significantly improving the efficiency and performance of near-memory computing or in-memory computing, while reducing overall power consumption.

[0004] Traditional 3D integration methods involve fabricating high-speed SRAM cache and DRAM main memory chips or circuits separately, and then using 3D-SiP, 3D-SiC, or 3D-SoC methods based on TSV technology to form a 3D in-memory computing chip or circuit. The drawback of this method is that, limited by the size of the TSV, the interconnect channels between the cache and main memory sections are on the order of several micrometers or tens of micrometers, thus significantly restricting the efficiency and bandwidth of 3D vertical interconnects, with bandwidth ranging from tens to hundreds of Gb / mm². 2 Furthermore, the need for extreme thinning of the already fabricated cache or main memory chips during manufacturing (from hundreds of micrometers to tens of micrometers) will lead to serious process reliability issues.

[0005] Therefore, this invention is proposed. Summary of the Invention

[0006] The main objective of this invention is to provide a monolithic 3D heterogeneous integrated multi-level cache circuit unit structure and manufacturing method, which solves the problem of high latency caused by long interconnection channels between cache levels in existing cache architectures.

[0007] To achieve the above objectives, the present invention provides the following technical solutions.

[0008] The first aspect of the present invention provides a monolithic 3D heterogeneous integrated multi-level cache circuit unit structure, which includes four functional layers stacked from bottom to top: an SRAM cache layer, a capacitor-free DRAM layer, a ferroelectric field-effect transistor storage layer and a ferroelectric diode layer, and a vertical contact hole passing through the SRAM cache layer, the capacitor-free DRAM layer and the ferroelectric field-effect transistor storage layer; the aperture of the vertical contact hole is 1 to 100 nm.

[0009] The SRAM cache layer uses silicon as a substrate, and the channels in the capacitor-free DRAM layer and the ferroelectric field-effect transistor storage layer are made of low-temperature semiconductor materials. The capacitor-free DRAM layer and the ferroelectric field-effect transistor storage layer have no substrate and are directly disposed on the surface of the functional layer below them. A metal interconnect layer is provided between the ferroelectric diode layer and the ferroelectric field-effect transistor storage layer.

[0010] The vertical contact hole is filled with a conductive plug, which is interconnected with the drain of the metal interconnect layer, the drain of the SRAM cache layer, the drain of the capacitorless DRAM layer, and the drain of the ferroelectric field-effect transistor storage layer.

[0011] This invention uses a silicon substrate only for the SRAM cache layer; the capacitor-free DRAM layer and the ferroelectric field-effect transistor storage layer above it are made of low-temperature semiconductor materials. Therefore, it is easier to form interconnect vias (i.e., vertical contact vias), allowing for the integration of four functional layers at once, formed sequentially, without the need to fabricate each layer separately and then create TSV vias. Furthermore, the vertical contact vias in this 3D multi-level cache circuit unit structure can be made at the nanometer scale, significantly improving the efficiency and bandwidth of 3D vertical interconnects.

[0012] In addition, except for the SRAM cache layer, all other layers of this invention use low-temperature oxide semiconductor materials, which reduces the number of times Si single crystal semiconductors are used and the process cost, reduces the impact of thermal budget on the underlying Si-based devices, and improves the manufacturing yield.

[0013] Meanwhile, the combined use of low-temperature semiconductor materials and single-crystal semiconductor devices fully leverages their respective advantages: low-temperature semiconductor materials have lower costs and can be used to create 2T0C DRAM layers and non-volatile memory layers; SRAM circuits fabricated from single-crystal semiconductors have higher performance.

[0014] Based on this, the structure and materials of each functional layer can be further improved to enhance process reliability, reduce leakage current, and lower power consumption.

[0015] Furthermore, the ferroelectric diode layer includes a lower electrode layer, a ferroelectric or antiferroelectric layer, a low-temperature semiconductor layer and an upper electrode layer stacked from bottom to top, and an upper electrode metal interconnect layer is provided above the ferroelectric diode layer.

[0016] Furthermore, the channel in the capacitor-free DRAM layer, the channel in the ferroelectric field-effect transistor storage layer, and the low-temperature semiconductor layer in the low-temperature semiconductor layer are each independently made of at least one of metal oxide semiconductor, ionic oxide semiconductor, and low-dimensional semiconductor material; the metal oxide semiconductor includes at least one of ZnO and SnO, the ionic oxide semiconductor includes at least one of IGZO, IZO, IO, ITO, and IAZO, and the low-dimensional semiconductor material includes at least one of MoS2, SeIn, WS2, and BP.

[0017] Furthermore, the thickness of the low-temperature semiconductor layer in the low-temperature semiconductor layer is 1 nm to 1 μm.

[0018] Furthermore, the SRAM cache layer comprises, from bottom to top, a silicon substrate and a gate stack structure, wherein the gate stack structure comprises a gate oxide layer, a high-k dielectric layer, and a first metal gate stacked sequentially, and the shallow surfaces of the silicon substrate located on both sides of the gate stack structure are respectively provided with source and drain electrodes.

[0019] Furthermore, the capacitor-free DRAM layer includes: a second metal gate, an insulating layer surrounding the second metal gate, a channel covering the surface of the insulating layer, and a source and a drain located on the surface of the channel; and the capacitor-free DRAM layer is isolated from the SRAM cache layer by an insulating material.

[0020] Furthermore, the ferroelectric field-effect transistor storage layer includes: a third metal gate, a non-volatile storage layer surrounding the third metal gate, a channel covering the surface of the non-volatile storage layer, and a source and a drain located on the surface of the channel; and the ferroelectric field-effect transistor storage layer is isolated from the capacitor-free DRAM layer by an insulating material.

[0021] A second aspect of the present invention provides a method for manufacturing the monolithic 3D heterogeneous integrated multi-level cache circuit unit structure described above, comprising:

[0022] Provide silicon substrate,

[0023] An SRAM cache layer is formed on the silicon substrate;

[0024] A capacitor-free DRAM layer is formed above the SRAM cache layer;

[0025] A ferroelectric field-effect transistor storage layer is formed above the capacitor-free DRAM layer;

[0026] Vertical contact holes are etched through the SRAM cache layer, the capacitor-free DRAM layer, and the ferroelectric field-effect transistor storage layer. These vertical contact holes are connected to the drains in the SRAM cache layer, the capacitor-free DRAM layer, and the ferroelectric field-effect transistor storage layer.

[0027] Fill the vertical contact hole with a conductive plug;

[0028] A metal interconnect layer is formed above the storage layer of the ferroelectric field-effect transistor;

[0029] A ferroelectric diode layer is formed above the metal interconnect layer.

[0030] Furthermore, the method for forming the ferroelectric diode layer includes:

[0031] A lower electrode layer, a ferroelectric or antiferroelectric layer, a low-temperature semiconductor layer, and an upper electrode layer are sequentially formed above the metal interconnect layer; then, patterning is performed to form a diode array.

[0032] Furthermore, an upper electrode metal interconnect layer is formed above the upper electrode layer before the patterning process.

[0033] Compared with the prior art, the present invention achieves the following technical effects:

[0034] (1) A manufacturing method that utilizes low-temperature semiconductor material deposition and vertical interconnection to form nanoscale 3D multi-level cache units improves the yield rate. The low-temperature semiconductor material and silicon substrate complement each other to improve the overall performance of the device.

[0035] (2) The diode layer of the lower electrode / ferroelectric (antiferroelectric) / ultra-thin low-temperature semiconductor / upper electrode structure has the characteristic of adjustable Schottky barrier of semiconductor, has self-rectification effect, does not require a selection tube, and further reduces the cost of hardware.

[0036] (3) Each layer can be manufactured using CMOS manufacturing process, which is simple and easy to implement. Attached Figure Description

[0037] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.

[0038] Figure 1 The structural diagram of the multi-level cache circuit unit of monolithic 3D heterogeneous integration provided by the present invention;

[0039] Figures 2 to 18 The structural diagrams obtained from each step of the manufacturing method provided by the present invention are shown. Detailed Implementation

[0040] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0041] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0042] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0043] This invention provides a monolithic 3D heterogeneous integrated multi-level cache circuit unit structure, such as... Figure 1 As shown, this structure enables monolithic 3D integration. The multi-level cache circuit unit structure includes four functional layers stacked from bottom to top: an SRAM cache layer 1, a capacitor-free DRAM layer 2, a ferroelectric field-effect transistor storage layer 3, and a ferroelectric diode layer 4, as well as vertical contact holes 303 passing through the SRAM cache layer 1, the capacitor-free DRAM layer 2, and the ferroelectric field-effect transistor storage layer 3; the aperture of the vertical contact holes 303 is 1–100 nm.

[0044] Of these, only the SRAM cache layer 1 uses silicon as a substrate (which is why this invention refers to it as "monolithic integration"). The semiconductors in the other functional layers all use low-temperature semiconductor materials. For example, the channels in the capacitorless DRAM layer 2 and the ferroelectric field-effect transistor storage layer 3 use low-temperature semiconductor materials. Figure 1 As shown, neither the capacitor-free DRAM layer 2 nor the ferroelectric field-effect transistor storage layer 3 has a substrate; both are directly disposed on the surface of the functional layer below them. Furthermore, a metal interconnect layer 401 is provided between the ferroelectric diode layer 4 and the ferroelectric field-effect transistor storage layer 3.

[0045] The vertical contact hole 303 is filled with a conductive plug, which is interconnected with the metal interconnect layer, the drain 103 in the SRAM cache layer, the drain 206 in the capacitorless DRAM layer, and the drain 301 in the ferroelectric field-effect transistor storage layer, thus forming a vertical interconnect.

[0046] Because this invention uses a silicon substrate only for the SRAM cache layer 1, while the capacitor-free DRAM layer 2 and the ferroelectric field-effect transistor storage layer 3 above it are made of low-temperature semiconductor materials, it is easier to form interconnect vias (i.e., vertical contact holes). This allows for the integration of four functional layers at once, formed sequentially, without the need to fabricate each layer separately and then create TSV vias. Furthermore, the vertical contact holes in this 3D multi-level cache circuit unit structure can reach the nanometer scale, greatly improving the efficiency and bandwidth of 3D vertical interconnects.

[0047] In addition, all layers of this invention, except for the SRAM cache layer 1, use low-temperature oxide semiconductor materials, which reduces the number of times Si single crystal semiconductors are used and the process cost, reduces the impact of thermal budget on the underlying Si-based devices, and improves the manufacturing yield.

[0048] Meanwhile, the combined use of low-temperature semiconductor materials and single-crystal semiconductor devices fully leverages their respective advantages: low-temperature semiconductor materials have lower costs and can be used to create 2T0C DRAM layers and non-volatile memory layers; SRAM circuits fabricated from single-crystal semiconductors have higher performance.

[0049] It should be noted that, although not described in detail above, the functional layers are isolated by necessary insulating materials and interconnected simply through conductive plugs in vertical contact holes. Other electrodes, such as source electrodes, contained within each functional layer may have their necessary metal interconnections.

[0050] In summary, the multi-level cache circuit unit structure provided by the present invention has the following characteristics: the fastest, smallest, and highest-cost SRAM is used as a cache for DRAM; the DRAM with the next fastest speed, smallest capacity, and lowest cost is used as a cache for ferroelectric field-effect transistors; and the ferroelectric field-effect transistor with the next fastest speed, largest capacity, and lowest cost is used as a cache for the slowest, largest-capacity, and lowest-cost ferroelectric diode.

[0051] Based on this, the structure and materials of each functional layer can be further improved to enhance process reliability, reduce leakage current, and lower power consumption.

[0052] In some implementations, such as Figure 1As shown, the ferroelectric diode layer 4 includes, from bottom to top, a lower electrode layer 402, a ferroelectric layer 403 or an antiferroelectric layer, a low-temperature semiconductor layer 404, and an upper electrode layer 405, stacked together. An upper electrode metal interconnect layer 406 is disposed above the ferroelectric diode layer. The lower electrode layer 402 and the upper electrode layer 405 serve as electrodes to be connected to a power source, and are preferably made of metal materials or doped semiconductor materials with good conductivity. Considering that this invention is more suitable for low-temperature processing, metal materials are preferred, which can be formed by sputtering. Common high-performance metal materials include, but are not limited to, Mo, Ti, or W. The low-temperature semiconductor layer 404 can be made of at least one of metal oxide semiconductors, ionic oxide semiconductors, and low-dimensional semiconductor materials. Metal oxide semiconductors include, but are not limited to, at least one of ZnO and SnO; ionic oxide semiconductors include, but are not limited to, at least one of IGZO, IZO, IO, ITO, and IAZO; and low-dimensional semiconductor materials include, but are not limited to, at least one of MoS2, SeIn, WS2, and BP. The layer between the lower electrode layer 402 and the low-temperature semiconductor layer 404 can be a ferroelectric material layer or an antiferroelectric material layer. The antiferroelectric material can be at least one of the following: PbNb[(ZrSn)Ti]O, or HfO2-based antiferroelectric materials. HfO2-based antiferroelectric materials include at least one of HfZrO, HfAlO, HfSiO, HfLaO, and HfGdO. The ferroelectric material can be at least one of the following: PZT, or HfO2-based ferroelectric materials. HfO2-based ferroelectric materials include at least one of HfAlO, HfSiO, HfLaO, and HfGdO. The metal interconnect layer 406 is preferably made of a metal material such as Mo, Ti, or W.

[0053] In some implementations, such as Figure 1 As shown, the channel 203 in the capacitorless DRAM layer, the channel in the ferroelectric field-effect transistor storage layer 308, and the low-temperature semiconductor layer 404 in the low-temperature semiconductor layer are each independently made of at least one of metal oxide semiconductor, ionic oxide semiconductor, and low-dimensional semiconductor material; the metal oxide semiconductor includes at least one of ZnO and SnO, the ionic oxide semiconductor includes at least one of IGZO, IZO, IO, ITO, and IAZO, and the low-dimensional semiconductor material includes at least one of MoS2, SeIn, WS2, and BP.

[0054] In some implementations, such as Figure 1 As shown, the thickness of the low-temperature semiconductor layer 404 in the low-temperature semiconductor layer 4 is 1 nm to 1 μm.

[0055] In some implementations, such as Figure 1As shown, the SRAM cache layer 1 includes, from bottom to top, a silicon substrate 101 and a gate stack structure. The gate stack structure includes a gate oxide layer 106, a high-k dielectric layer 107, and a first metal gate 108 stacked sequentially. The shallow surfaces of the silicon substrate located on both sides of the gate stack structure are respectively provided with source electrodes 105 and drain electrodes 103. The gate oxide layer 106 can be a conventional gate oxide such as silicon oxide or silicon oxynitride. The high-k dielectric layer 107 can be made of materials such as hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, aluminum oxide, lanthanum oxide, or lanthanum aluminum oxide. The first metal gate 108 can be a metal or alloy of Ti, TiN, Ta, TaN, TiAl, W, Mo, TaC, Al, Pd, Sc, Au, TiPd, Mo, or a multilayer metal stack material.

[0056] In some implementations, such as Figure 1 As shown, the capacitor-free DRAM layer 2 includes: a second metal gate 201, an insulating layer 202 surrounding the second metal gate 201, a channel 203 covering the surface of the insulating layer, and a source 205 and a drain 206 located on the surface of the channel 203; and the capacitor-free DRAM layer 2 is isolated from the SRAM cache layer 1 by an insulating material. The second metal gate 201 can be a metal such as Ti, TiN, Ta, TaN, TiAl, W, Mo, TaC, Al, Pd, Sc, Au, TiPd, Mo, or their alloys or multilayer metal stacks. The insulating layer 202 can be doped or undoped silicon oxide, low-k materials including but not limited to organic low-k materials (e.g., organic polymers containing aryl or polycyclic rings), inorganic low-k materials, etc. The source 205 and drain 206 can be made of metals or other materials.

[0057] In some implementations, such as Figure 1 As shown, the ferroelectric field-effect transistor storage layer 3 includes: a third metal gate 305, a non-volatile storage layer 306 surrounding the third metal gate 305, a channel 308 covering the surface of the non-volatile storage layer 306, and a source 307 and a drain 301 located on the surface of the channel 308; and the ferroelectric field-effect transistor storage layer 3 is isolated from the capacitor-free DRAM layer 2 by an insulating material. The non-volatile storage layer 306 can be made of conventional ferroelectric materials (such as PZT), or it can be made of novel HfO2-based ferroelectric materials (such as HfZrO, HfAlO, HfSiO, HfLaO, HfGdO, etc.). The material types of the third metal gate 305, the source 307, and the drain 301 can be referenced from those of the capacitor-free DRAM layer.

[0058] Taking a ferroelectric diode layer containing a ferroelectric layer as an example, this invention provides an embodiment to illustrate its detailed manufacturing process.

[0059] First, a silicon substrate is provided, on which an SRAM cache layer 1 is fabricated. This functional layer includes the necessary structures for the SRAM memory cells, such as... Figure 1 and 2 As shown. Taking PMOS as an example, shallow trench isolation (STI) 102 is performed, the substrate is N-type doped to form a channel, and the two sides of the shallow surface are P-type doped to form the source and drain. A gate stack structure of gate oxide layer 106, high-k dielectric layer 107 and first metal gate 108 is formed sequentially above the channel. Insulating material is deposited, and the contacts 104 of the source and drain are etched. An insulating layer 109 is covered on top and planarized.

[0060] Next, a capacitor-free DRAM layer is formed. First, a second metal gate 201 is deposited at a low temperature on the insulating layer 109, as follows... Figure 3 As shown, the gate is patterned, as follows: Figure 4 As shown. Then, a gate insulating layer 202 and a low-temperature semiconductor channel 203 are deposited, as shown. Figure 5 As shown; the active region is graphically represented, such as... Figure 6 As shown. The source and drain metal deposition and patterning are as follows. Figure 7 As shown; redeposit isolation medium material, such as Figure 8 As shown. Contact holes 207 and interconnects forming the source and drain of the capacitor-free DRAM layer are covered by an insulating layer 204, as shown. Figure 9 As shown.

[0061] Subsequently, a ferroelectric field-effect transistor storage layer is formed above the insulating layer 204, including: the deposition of a third metal gate 305, such as... Figure 10 As shown; further graphicalize the raster, as... Figure 11 As shown. A ferroelectric non-volatile memory layer 306 and a low-temperature semiconductor channel 308 are deposited, as... Figure 12 As shown. The active region is graphically represented, as follows. Figure 13 As shown. The source and drain metal deposition and patterning are as follows. Figure 14 As shown; redeposit isolation medium material, such as Figure 15 As shown. The contact holes 302 and interconnects forming the source and drain of the ferroelectric field-effect transistor's storage layer are covered by an insulating layer 304, as shown. Figure 16 As shown.

[0062] The next crucial step is the interconnection of the layers, etching vertical contact holes 303 that pass through the SRAM cache layer, the capacitor-free DRAM layer, and the ferroelectric field-effect transistor storage layer, as shown below. Figure 17 As shown, a conductive plug is filled. The vertical contact hole 303 is selected to be connected to the drain in the SRAM cache layer, the drain in the capacitorless DRAM layer, and the drain in the ferroelectric field-effect transistor storage layer.

[0063] Then, a metal interconnect layer 401 is formed above the ferroelectric field-effect transistor storage layer. This metal interconnect layer 401 is interconnected with a vertical contact hole 303.

[0064] Subsequently, a ferroelectric diode layer is formed above the metal interconnect layer 401, including: forming a lower electrode layer 402, a ferroelectric layer 403, a low-temperature semiconductor layer 404, an upper electrode layer 405, and an upper electrode metal interconnect layer 406, as shown below. Figure 18 As shown. Then, a graphical processing is performed to form a diode array, as shown. Figure 1 As shown.

[0065] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A multi-level cache circuit unit structure for monolithic 3D heterogeneous integration, characterized in that, It includes four functional layers stacked from bottom to top: an SRAM cache layer, a capacitor-free DRAM layer, a ferroelectric field-effect transistor storage layer, and a ferroelectric diode layer, as well as vertical contact holes passing through the SRAM cache layer, the capacitor-free DRAM layer, and the ferroelectric field-effect transistor storage layer; the aperture of the vertical contact holes is 1~100nm; The SRAM cache layer uses silicon as a substrate, and the channels in the capacitor-free DRAM layer and the ferroelectric field-effect transistor storage layer are made of low-temperature semiconductor materials. The capacitor-free DRAM layer and the ferroelectric field-effect transistor storage layer have no substrate and are directly disposed on the surface of the functional layer below them. A metal interconnect layer is provided between the ferroelectric diode layer and the ferroelectric field-effect transistor storage layer. The vertical contact hole passing through the SRAM cache layer, the capacitor-free DRAM layer, and the ferroelectric field-effect transistor storage layer is connected to the drain of the SRAM cache layer, the drain of the capacitor-free DRAM layer, and the drain of the ferroelectric field-effect transistor storage layer; the vertical contact hole is filled with a conductive plug, and the conductive plug is interconnected with the metal interconnect layer and the drain of the SRAM cache layer, the drain of the capacitor-free DRAM layer, and the drain of the ferroelectric field-effect transistor storage layer.

2. The multi-level cache circuit unit structure of monolithic 3D heterogeneous integration according to claim 1, characterized in that, The ferroelectric diode layer includes a bottom electrode layer, a ferroelectric or antiferroelectric layer, a low-temperature semiconductor layer and a top electrode layer stacked from bottom to top, and a top electrode metal interconnect layer is provided above the ferroelectric diode layer.

3. The multi-level cache circuit unit structure of monolithic 3D heterogeneous integration according to claim 2, characterized in that, The channel in the capacitor-free DRAM layer, the channel in the ferroelectric field-effect transistor storage layer, and the low-temperature semiconductor layer in the low-temperature semiconductor layer each independently employ at least one of metal oxide semiconductor, ionic oxide semiconductor, and low-dimensional semiconductor material; the metal oxide semiconductor includes at least one of ZnO and SnO, the ionic oxide semiconductor includes at least one of IGZO, IZO, IO, ITO, and IAZO, and the low-dimensional semiconductor material includes at least one of MoS2, SeIn, WS2, and BP.

4. The multi-level cache circuit unit structure of monolithic 3D heterogeneous integration according to claim 2, characterized in that, The thickness of the low-temperature semiconductor layer is 1 nm to 1 μm.

5. The multi-level cache circuit unit structure of monolithic 3D heterogeneous integration according to claim 1, characterized in that, The SRAM cache layer comprises, from bottom to top, a silicon substrate and a gate stack structure. The gate stack structure includes a gate oxide layer, a high-k dielectric layer, and a first metal gate stacked sequentially. The shallow surfaces of the silicon substrate located on both sides of the gate stack structure are respectively provided with source and drain electrodes.

6. The multi-level cache circuit unit structure of monolithic 3D heterogeneous integration according to claim 1, characterized in that, The capacitor-free DRAM layer includes: a second metal gate, an insulating layer surrounding the second metal gate, a channel covering the surface of the insulating layer, and a source and a drain located on the surface of the channel; and the capacitor-free DRAM layer is isolated from the SRAM cache layer by an insulating material.

7. The multi-level cache circuit unit structure of monolithic 3D heterogeneous integration according to claim 1, characterized in that, The ferroelectric field-effect transistor storage layer includes: a third metal gate, a non-volatile storage layer surrounding the third metal gate, a channel covering the surface of the non-volatile storage layer, and a source and a drain located on the surface of the channel; and the ferroelectric field-effect transistor storage layer is isolated from the capacitor-free DRAM layer by an insulating material.

8. A method for manufacturing a monolithic 3D heterogeneous integrated multi-level cache circuit unit structure according to any one of claims 1-7, characterized in that, include: Provide silicon substrate, An SRAM cache layer is formed on the silicon substrate; A capacitor-free DRAM layer is formed above the SRAM cache layer; A ferroelectric field-effect transistor storage layer is formed above the capacitor-free DRAM layer; Vertical contact holes are etched through the SRAM cache layer, the capacitor-free DRAM layer, and the ferroelectric field-effect transistor storage layer. These vertical contact holes are connected to the drains in the SRAM cache layer, the capacitor-free DRAM layer, and the ferroelectric field-effect transistor storage layer. Fill the vertical contact hole with a conductive plug; A metal interconnect layer is formed above the storage layer of the ferroelectric field-effect transistor; A ferroelectric diode layer is formed above the metal interconnect layer.

9. The method for manufacturing the monolithic 3D heterogeneous integrated multi-level cache circuit unit structure according to claim 1, characterized in that, The method for forming the ferroelectric diode layer includes: A lower electrode layer, a ferroelectric or antiferroelectric layer, a low-temperature semiconductor layer, and an upper electrode layer are sequentially formed above the metal interconnect layer; then, patterning is performed to form a diode array.

10. The manufacturing method of the monolithic 3D heterogeneous integrated multi-level cache circuit unit structure according to claim 9, characterized in that, An upper electrode metal interconnect layer is formed above the upper electrode layer before the patterning process.

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