Electrode fabrication methods and light-emitting diodes

Abstract

The disclosure provides an electrode manufacturing method and a light emitting diode, and belongs to the technical field of semiconductor devices. The electrode manufacturing method comprises the following steps: manufacturing a first electrode; manufacturing a DBR layer covering the first electrode; opening a first via hole in communication with the first electrode on the DBR layer; filling a filling material in the first via hole; opening a second via hole in communication with the first electrode on the filling material, an included angle between a side wall of the second via hole and a surface of the first electrode is smaller than an included angle between a side wall of the first via hole and the surface of the first electrode; and manufacturing a second electrode covering the DBR layer and the side wall of the second via hole and connected with the first electrode.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor device technology, and in particular to an electrode fabrication method and a light-emitting diode. Background Technology

[0002] In a light-emitting diode (LED) flip chip, a distributed Bragg reflection (DBR) layer is typically designed between the first electrode (primary electrode) and the second electrode (secondary electrode) to connect the first electrode (primary electrode) in an orderly manner and to enable light to be emitted from the front of the chip.

[0003] Typically, the above-mentioned electrode is fabricated as follows: first, a first electrode is fabricated, then a DBR layer is fabricated, and a via is opened on the DBR layer to communicate with the first electrode, and then a second electrode connected to the first electrode is fabricated. Summary of the Invention

[0004] This disclosure provides an electrode fabrication method and a light-emitting diode (LED), which can avoid the risk of second electrode breakage, reduce chip leakage and moisture penetration problems, thereby improving the yield and lifespan of the LED chip. The technical solution is as follows:

[0005] This disclosure provides a method for fabricating an electrode, the method comprising:

[0006] Fabricate the first electrode;

[0007] Fabricate a DBR layer covering the first electrode;

[0008] A first via is formed on the DBR layer to communicate with the first electrode;

[0009] Fill the first via with filler material;

[0010] A second through hole communicating with the first electrode is formed in the filling material, and the angle between the sidewall of the second through hole and the surface of the first electrode is smaller than the angle between the sidewall of the first through hole and the surface of the first electrode.

[0011] A second electrode is fabricated that covers the sidewall of the DBR layer and the second via and is connected to the first electrode.

[0012] Optionally, the filler material is SiO2 or SiN;

[0013] Alternatively, the filling material is a stack, wherein the top layer of the stack is made of SiO2 or SiN.

[0014] Optionally, the first via is formed by dry etching, and the second via is formed by wet etching.

[0015] Optionally, the step of creating a second through-hole in the filling material that communicates with the first electrode includes:

[0016] A photoresist layer with a set pattern is formed on the DBR layer and the filling material by photolithography, the set pattern corresponding to the shape of the first via; the DBR layer exposed by the photoresist layer is etched with an etchant to form the first via; the photoresist layer is then removed.

[0017] Optionally, the etching solution is a mixed solution of hydrofluoric acid and ammonium fluoride, wherein the volume ratio of hydrofluoric acid to ammonium fluoride is 1:15 to 1:25.

[0018] Optionally, the angle between the sidewall of the first via and the surface of the first electrode ranges from 50 to 80 degrees, and the angle between the sidewall of the second via and the surface of the first electrode ranges from 30 to 60 degrees.

[0019] This disclosure provides an LED, which includes a first electrode, a DBR layer, and a second electrode;

[0020] The DBR layer covers the first electrode, and a first via is formed on the DBR layer that communicates with the first electrode; the first via is filled with a filler material, and the filler material has a second via that communicates with the first electrode; the angle between the sidewall of the second via and the surface of the first electrode is smaller than the angle between the sidewall of the first via and the surface of the first electrode; the second electrode covers the DBR layer and the sidewall of the second via, and is connected to the first electrode.

[0021] Optionally, the filler material is SiO2 or SiN.

[0022] Optionally, the filling material is a stack, and the top layer of the stack is made of SiO2 or SiN.

[0023] Optionally, the angle between the sidewall of the first via and the surface of the first electrode ranges from 50 to 80 degrees, and the angle between the sidewall of the second via and the surface of the first electrode ranges from 30 to 60 degrees.

[0024] This disclosure provides a method for manufacturing an LED, the method comprising:

[0025] Fabrication of epitaxial wafers;

[0026] A first electrode is fabricated on the epitaxial wafer;

[0027] Fabricate a DBR layer covering the first electrode;

[0028] A first via is formed on the DBR layer to communicate with the first electrode;

[0029] Fill the first via with filler material;

[0030] A second through hole communicating with the first electrode is formed in the filling material, and the angle between the sidewall of the second through hole and the surface of the first electrode is smaller than the angle between the sidewall of the first through hole and the surface of the first electrode.

[0031] A second electrode is fabricated that covers the sidewall of the DBR layer and the second via and is connected to the first electrode.

[0032] Optionally, the filler material is SiO2 or SiN;

[0033] Alternatively, the filling material is a stack, wherein the top layer of the stack is made of SiO2 or SiN.

[0034] Optionally, the first via is formed by dry etching, and the second via is formed by wet etching.

[0035] This disclosure provides an LED chip manufactured using the LED manufacturing method described in any of the preceding claims.

[0036] The beneficial effects of the technical solutions provided in this disclosure include:

[0037] In the technical solution provided in this disclosure embodiment, a first via connected to the first electrode is first opened on the DBR layer. Then, a filler material is filled into the first via, and a second via is opened on the filler material. The angle between the sidewall of the second via and the surface of the first electrode is smaller than the angle between the sidewall of the first via and the surface of the first electrode. This makes the slope of the sidewall of the second via gentler than that of the sidewall of the first via. In this way, the second electrode will not break at the sidewall of the second via when it is fabricated. Thus, without increasing the thickness of the second electrode, the risk of breakage of the second electrode is avoided, the problems of chip leakage and moisture penetration are reduced, thereby improving the yield and service life of the LED chip. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a flowchart of an electrode fabrication method provided in an embodiment of this disclosure;

[0040] Figure 2 This is a flowchart of an electrode fabrication method provided in an embodiment of this disclosure;

[0041] Figure 3 This is a schematic diagram of an electrode fabrication process provided in an embodiment of this disclosure;

[0042] Figure 4 This is a schematic diagram of an electrode fabrication process provided in an embodiment of this disclosure;

[0043] Figure 5 This is a schematic diagram of an electrode fabrication process provided in an embodiment of this disclosure;

[0044] Figure 6 This is a schematic diagram of an electrode fabrication process provided in an embodiment of this disclosure;

[0045] Figure 7 This is a schematic diagram of an electrode fabrication process provided in an embodiment of this disclosure;

[0046] Figure 8 This diagram shows the angle of the first etched via.

[0047] Figure 9 This diagram shows the angle of the etched second via.

[0048] Figure 10 This is a schematic diagram of an electrode fabrication process provided in an embodiment of this disclosure;

[0049] Figure 11 This is a schematic diagram of an electrode fabrication process provided in an embodiment of this disclosure;

[0050] Figure 12 This is a schematic diagram of an electrode fabrication process provided in an embodiment of this disclosure;

[0051] Figure 13 This is a schematic diagram of an electrode fabrication process provided in an embodiment of this disclosure;

[0052] Figure 14 This disclosure provides a flowchart of an LED manufacturing method;

[0053] Figure 15 This disclosure provides a flowchart of an LED manufacturing method. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0055] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0056] In related technologies, the angle between the sidewall of the via opened on the DBR layer and the surface of the first electrode is usually between 50 and 80 degrees. Due to the relatively thick DBR, the coverage of the second electrode is poor, which can easily cause the second electrode to break at the sidewall of the second via. As a result, when the LED chip is powered on, some areas break, short circuit and leakage occur, and water vapor can easily penetrate.

[0057] To address these issues, related technologies typically increase the thickness of the second electrode. However, this approach not only wastes materials but also results in a thicker overall LED chip, hindering the miniaturization of LED chips.

[0058] Figure 1 This is a flowchart illustrating an electrode fabrication method provided in an embodiment of this disclosure. See also... Figure 1 The electrode fabrication method includes:

[0059] 101: Fabrication of the first electrode.

[0060] In the embodiments of this disclosure, the LED may include an N electrode and a P electrode. Both the N electrode and the P electrode are made using the electrode fabrication method. For example, the fabricated N electrode includes a first electrode and a second electrode, and the fabricated P electrode also includes a first electrode and a second electrode. That is to say, when manufacturing an LED chip, the electrode fabrication method provided in this disclosure can be used to fabricate either an N electrode or a P electrode.

[0061] 102: Fabricate a DBR layer covering the first electrode.

[0062] 103: A first via is formed on the DBR layer to communicate with the first electrode.

[0063] That is, the first through hole penetrates the entire DBR layer, and the first through hole allows the surface of the first electrode to be exposed.

[0064] 104: Fill the first through hole with filler material.

[0065] 105: A second through hole communicating with the first electrode is formed on the filling material.

[0066] That is, the second through hole penetrates the entire filling material, and the second through hole allows the surface of the first electrode to be exposed.

[0067] Wherein, the angle between the sidewall of the second via and the surface of the first electrode is smaller than the angle between the sidewall of the first via and the surface of the first electrode.

[0068] 106: Fabricate a second electrode that covers the sidewall of the DBR layer and the second via and is connected to the first electrode.

[0069] The second electrode is located on the surface of the DBR layer, the sidewall of the second via, and the surface of the first electrode, thereby achieving electrical connection with the first electrode.

[0070] In the technical solution provided in this disclosure embodiment, a first via connected to the first electrode is first opened on the DBR layer. Then, a filler material is filled into the first via, and a second via is opened on the filler material. The angle between the sidewall of the second via and the surface of the first electrode is smaller than the angle between the sidewall of the first via and the surface of the first electrode. This makes the slope of the sidewall of the second via gentler than that of the sidewall of the first via. In this way, the second electrode will not break at the sidewall of the second via when it is fabricated. Thus, without increasing the thickness of the second electrode, the risk of breakage of the second electrode is avoided, the problems of chip leakage and moisture penetration are reduced, thereby improving the yield and service life of the LED chip.

[0071] The solution provided in this disclosure eliminates the risk of breakage of the second electrode without increasing its thickness.

[0072] Figure 2 This is a flowchart illustrating an electrode fabrication method provided in an embodiment of this disclosure. See also... Figure 2 The electrode fabrication method includes:

[0073] 201: Fabrication of the first electrode.

[0074] The first electrode can be a metal electrode, for example, an electrode made of one of the following materials or an electrode made of an alloy formed of at least two of the following materials:

[0075] Gold (Au), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), chromium (Cr), and titanium (Ti).

[0076] For example, the preparation method of the first electrode is as follows: a photoresist layer with a set pattern is prepared by photolithography, wherein the set pattern in this step corresponds to the shape of the first electrode, such as a circle or a rectangle; a metal material is deposited on the photoresist layer; then the metal material and the photoresist layer are removed sequentially, leaving the metal material in the pattern of the photoresist layer, to obtain the first electrode.

[0077] For example, the thickness range of the first electrode can be... in, It refers to 1000 angstroms.

[0078] Figure 3 This is a schematic diagram of an electrode fabrication process provided in an embodiment of this disclosure. See also... Figure 3 The first electrode 1 is prepared.

[0079] 202: Deposit the DBR layer covering the first electrode.

[0080] For example, the DBR layer is an insulating material layer with reflective function, such as a SiO2 / TiO2 stack.

[0081] For example, the DBR layer can be deposited by vapor deposition.

[0082] Figure 4 This is a schematic diagram of an electrode fabrication process provided in an embodiment of this disclosure. See also... Figure 4 A DBR layer 2 is deposited on the first electrode 1.

[0083] 203: A first via is formed on the DBR layer to communicate with the first electrode.

[0084] In one possible implementation, a first via is formed on the DBR layer using a dry etching process to communicate with the first electrode.

[0085] For example, the first via is formed as follows: a photoresist layer with a defined pattern is fabricated using a photolithography process, wherein the defined pattern in this step corresponds to the shape of the first via, such as a circle or a rectangle; the DBR layer is etched using a dry etching process to form the first via on the DBR layer; and the photoresist layer is removed.

[0086] The sidewall of the first via formed by dry etching has a slope, that is, the opening of the first via is large and the bottom is small.

[0087] In another possible implementation, a wet etching process is used to create a first via in the DBR layer that communicates with the first electrode.

[0088] Both dry and wet etching methods can be used to etch the DBR layer. However, regardless of the etching method used, the angle between the sidewall of the first via and the surface of the first electrode is relatively large, ranging from 50 to 80 degrees. Since dry etching is faster, it is usually used to etch the DBR layer.

[0089] For example, the thickness range of the DBR layer can be...

[0090] Figure 5 This is a schematic diagram of an electrode fabrication process provided in an embodiment of this disclosure. See also... Figure 5 A first via 3 is made on the DBR layer 2.

[0091] 204: Fill the first through hole with filler material.

[0092] For example, the filling material can be filled in the following way: a photoresist layer with a set pattern is made by photolithography, wherein the set pattern in this step corresponds to the shape and position of the first via, such as a circle or a rectangle; the filling material is deposited on the photoresist layer; the filling material and the photoresist layer on the photoresist layer are removed in sequence, leaving the filling material in the first via.

[0093] The filler material can also be filled in the following ways: by vapor deposition of a whole layer of filler material; or by etching the filler material through an etching process, leaving only the filler material located in the first via.

[0094] Optionally, the filler material is SiO2 or SiN;

[0095] Alternatively, the filling material is a stack, wherein the top layer of the stack is made of SiO2 or SiN.

[0096] The top layer refers to the outermost layer of the filling material on the side furthest from the first electrode.

[0097] When used as materials in a multilayer stack, if wet etching is employed, the etching rates from fastest to slowest under the same etching environment are: SiO2, SiN, Al2O3, TiO. Therefore, using SiO2 or SiN as the top layer material in a multilayer stack results in a faster etching rate for the top layer than for the bottom layer. This means that the etching rate of the upper part of the filler material is faster than that of the lower part by the etching solution. Consequently, the slope of the via sidewall is gentler, and the angle between the via sidewall and the surface of the first electrode is smaller.

[0098] In addition, TiO2 is relatively difficult to be etched by etching solution, so TiO2 can also be placed at the bottom layer of the filler material.

[0099] For example, the stacked layer can be a SiO2 / SiN stacked layer, or a SiN / SiO2 stacked layer, or a TiO2 / SiN stacked layer, or a TiO2 / SiO2 / SiN stacked layer, or an Al2O3 / SiO2 stacked layer, etc.

[0100] When the above materials are used as fillers, the top surface of the filler is SiO2 or SiN. During wet etching, the adhesion between the top surface of the filler and the photoresist layer is less than that between the top surface of the DBR (TiO2) and the photoresist layer. There are gaps at the edges of the pattern of the filler and the photoresist layer, and the etching solution can enter through these gaps. This results in a faster etching rate on the upper part of the filler than on the lower part. In addition, the upper filler comes into contact with the etching solution earlier than the lower filler, resulting in faster etching of the upper layer. This results in a gentler slope on the sidewall of the via and a smaller angle between the sidewall of the via and the surface of the first electrode.

[0101] In this embodiment of the disclosure, the top surface of the filler material is flush with the top surface of the DBR layer, so that there is only one slope throughout the entire via.

[0102] Figure 6 This is a schematic diagram of an electrode fabrication process provided in an embodiment of this disclosure. See also... Figure 6 Fill the first through hole 3 with filler material 4.

[0103] 205: A second via is formed on the filler material using a wet etching process, which communicates with the first electrode.

[0104] In this step, the second via is formed by wet etching.

[0105] For example, a photoresist layer with a set pattern is formed on the DBR layer and the filler material by photolithography, the set pattern corresponding to the shape of the second via; the filler material exposed by the photoresist layer is etched with an etchant to form the second via; the photoresist layer is then removed.

[0106] The photoresist layer is formed by photoresist deposition. In this embodiment, the photoresist is a Kehua Ruihong positive photoresist.

[0107] When using this photoresist, a gap exists between the photoresist and the top surface of the filler material, allowing the etching solution to enter from the gap between the top surface of the filler material and the photoresist layer. This achieves the goal of a higher etching rate on the upper layer of the filler material compared to the lower layer. Furthermore, the photoresist has a certain adhesion to the top surface of the filler material, and a greater adhesion to the top surface of the DBR layer (TiO2). This force distribution results in a larger gap in the filler material away from the DBR layer compared to the gap in the filler material near the DBR layer. This ensures that the etching solution can only etch the portion of the top surface of the filler material near the pre-defined pattern on the photoresist layer, preventing the opening of the first via from being too large.

[0108] In this embodiment of the disclosure, the environment is as follows when etching is performed using an etching solution:

[0109] The etching solution is a mixture of hydrofluoric acid and ammonium fluoride, with a volume ratio of 1:15 to 1:25. Etching is performed at room temperature for 10 to 60 minutes.

[0110] For example, the volume ratio of hydrofluoric acid to ammonium fluoride is 1:20.

[0111] For example, the etching time is 30 to 45 minutes.

[0112] Wherein, the angle between the sidewall of the second via and the surface of the first electrode is smaller than the angle between the sidewall of the first via and the surface of the first electrode.

[0113] For example, the angle between the sidewall of the first via and the surface of the first electrode ranges from 50 to 80 degrees. The angle between the sidewall of the second via and the surface of the first electrode ranges from 30 to 60 degrees.

[0114] It is worth noting that the sidewall of the first via (or second sidewall) is usually not a smooth sidewall. Here, the angle between the sidewall of the first via (or second sidewall) and the surface of the first electrode can refer to the angle between the two endpoints of the line connecting the intersection of the vertical plane perpendicular to the surface of the first electrode and the sidewall of the first via (or second sidewall) and the surface of the first electrode.

[0115] Figure 7 This is a schematic diagram of an electrode fabrication process provided in an embodiment of this disclosure. See also... Figure 7 A second through hole 5 is formed on the filling material 4. The angle A between the sidewall of the second through hole 5 and the surface of the first electrode 1 is smaller than the angle B between the sidewall of the first through hole 3 and the surface of the first electrode 1.

[0116] Below are scanned images of the actual product after etching. Figure 8 and Figure 9 Explain the magnitudes of angles A and B. Wherein, Figure 8 and Figure 9 It was obtained by scanning with a focused ion beam (FIB) and a transmission electron microscope (TEM). Figure 8 The diagram shown illustrates the angle of the first etched via, as follows: Figure 8 As shown, the angle between the sidewall of the first via and the surface of the first electrode is 53.3 degrees. Figure 9 The diagram shown illustrates the angle of the etched second via, as follows: Figure 9 As shown, the angle between the sidewall of the second via and the surface of the first electrode is 33.6 degrees. It is evident that angle A is significantly smaller than angle B, indicating a gentler slope on the sidewall of the second via.

[0117] 206: Fabricate a second electrode that covers the sidewall of the DBR layer and the second via and is connected to the first electrode.

[0118] The second electrode can be a metal electrode, for example, an electrode made of one of the following materials or an electrode made of an alloy formed of at least two of the following materials:

[0119] Gold (Au), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), chromium (Cr), and titanium (Ti).

[0120] For example, the second electrode can be prepared by vapor deposition.

[0121] Figure 10 This is a schematic diagram of an electrode fabrication process provided in an embodiment of this disclosure. See also... Figure 10 A second electrode 6, which connects to the first electrode 1, is fabricated on the DBR layer 2 and the filler material 4.

[0122] exist Figure 6 , Figure 7 and Figure 10 In the fabrication process shown, the top surface of the filling material is flush with the top surface of the DBR layer, resulting in fewer steps in the final via structure, which facilitates the subsequent fabrication of the second electrode.

[0123] In other embodiments, the top surface of the filler material may be lower than or higher than the top surface of the DBR layer.

[0124] If thickness is used as the standard, the ratio of the thickness of the filler material to the thickness of the DBR layer can range from 30% to 180%.

[0125] When the ratio of the thickness of the filler material to the thickness of the DBR layer is in the range of 30% to 60%, the filler material can be greatly saved and the time of filler material deposition and etching can be shortened, while still ensuring that the fabrication of the second electrode will not break.

[0126] The following is combined with Figures 11 to 13 An exemplary fabrication process is provided for a filling material thickness to DBR layer thickness ratio of 50%.

[0127] Figure 11 This is a schematic diagram of an electrode fabrication process provided in an embodiment of this disclosure. See also... Figure 11 The first via 3 is filled with filler material 4, and the top surface of filler material 4 is much lower than the top surface of DBR layer 2.

[0128] Figure 12 This is a schematic diagram of an electrode fabrication process provided in an embodiment of this disclosure. See also... Figure 12 A second through hole 5 is formed in the filling material 4. The angle A between the sidewall of the second through hole 5 and the surface of the first electrode 1 is smaller than the angle B between the sidewall of the first through hole 3 and the surface of the first electrode 1. At this time, the top of the second through hole 5 forms a step with the sidewall of the first through hole 1.

[0129] Figure 13 This is a schematic diagram of an electrode fabrication process provided in an embodiment of this disclosure. See also... Figure 13 A second electrode 6, which connects to the first electrode 1, is fabricated on the DBR layer 2 and the filler material 4. The second electrode 6 passes through the aforementioned steps.

[0130] Figure 14 This disclosure provides a flowchart of an LED manufacturing method. See also... Figure 14 The LED manufacturing method includes:

[0131] 301: Fabrication of epitaxial wafers.

[0132] 302: Fabricate a first electrode on the epitaxial wafer.

[0133] 303: Fabricate a DBR layer covering the first electrode.

[0134] 304: A first via is formed on the DBR layer to communicate with the first electrode.

[0135] 305: Fill the first through hole with filler material.

[0136] 306: A second through hole communicating with the first electrode is formed in the filling material.

[0137] Wherein, the angle between the sidewall of the second via and the surface of the first electrode is smaller than the angle between the sidewall of the first via and the surface of the first electrode.

[0138] 307: Fabricate a second electrode that covers the sidewall of the DBR layer and the second via and is connected to the first electrode.

[0139] In the technical solution provided in this disclosure embodiment, a first via connected to the first electrode is first opened on the DBR layer. Then, a filler material is filled into the first via, and a second via is opened on the filler material. The angle between the sidewall of the second via and the surface of the first electrode is smaller than the angle between the sidewall of the first via and the surface of the first electrode. This makes the slope of the sidewall of the second via gentler than that of the sidewall of the first via. In this way, the second electrode will not break at the sidewall of the second via when it is fabricated. Thus, without increasing the thickness of the second electrode, the risk of breakage of the second electrode is avoided, the problems of chip leakage and moisture penetration are reduced, thereby improving the yield and service life of the LED chip.

[0140] Figure 15 This disclosure provides a flowchart of an LED manufacturing method. See also... Figure 15 The LED manufacturing method includes:

[0141] 401: Fabrication of epitaxial wafers.

[0142] For example, fabricating an epitaxial wafer includes: providing a substrate; sequentially depositing an N-type semiconductor layer, an active layer, and a P-type semiconductor layer on the substrate; and etching a groove extending from the P-type semiconductor layer to the surface of the N-type semiconductor layer.

[0143] The substrate can be made of sapphire, such as a patterned sapphire substrate. The N-type semiconductor layer 21 can be made of N-type doped gallium nitride. The active layer can include multiple quantum wells and multiple quantum barriers, which are stacked alternately; the quantum wells can be made of indium gallium nitride, and the quantum barriers can be made of gallium nitride. The P-type semiconductor layer can be made of P-type doped gallium nitride.

[0144] Of course, the above-described epitaxial wafer structure is only one example. In other implementations, the epitaxial wafer may include more layers, such as buffer layers, current spreading layers, electron blocking layers, etc. This disclosure does not limit this.

[0145] 402: Fabricate a first N electrode and a first P electrode on the epitaxial wafer.

[0146] The first P electrode is fabricated on the surface of the P-type semiconductor layer, and the first N electrode is fabricated on the surface of the N-type semiconductor layer in the groove.

[0147] 403: Fabricate a DBR layer covering the first N electrode and the first P electrode.

[0148] In this step, the DBR layer simultaneously covers both the N-electrode and the P-electrode.

[0149] 404: A first N-via and a first P-via are respectively opened on the DBR layer to communicate with the first N electrode and the first P electrode.

[0150] 405: Fill the first N-via and the first P-via with filler material respectively.

[0151] 406: A second N-via communicating with the first N electrode is formed in the filling material inside the first N-via, and a second P-via communicating with the first P electrode is formed in the filling material inside the first P-via.

[0152] 407: Fabricate a second N electrode that covers part of the DBR layer and the second N via and is connected to the first N electrode; fabricate a second P electrode that covers another part of the DBR layer and the second P via and is connected to the first P electrode.

[0153] As described above, this disclosure provides a method for fabricating a flip-chip LED. After fabricating an epitaxial wafer, N-electrodes and P-electrodes are fabricated according to the above method. The fabrication methods for both N-electrodes and P-electrodes can be referred to the foregoing. Figure 1 or Figure 2 The electrode fabrication method described above.

[0154] This disclosure also provides an LED manufactured using the LED manufacturing method described in any of the preceding claims.

[0155] by Figure 10 and Figure 13 For example, the LED includes: a first electrode 1, a DBR layer 2, and a second electrode 6.

[0156] The DBR layer 2 covers the first electrode 1, and a first via 3 communicating with the first electrode 1 is formed on the DBR layer 2; the first via 3 is filled with a filler material 4, and a second via 5 communicating with the first electrode 1 is formed in the filler material 4; the angle between the sidewall of the second via 5 and the surface of the first electrode 1 is smaller than the angle between the sidewall of the first via 3 and the surface of the first electrode 1; the second electrode 6 covers the DBR layer 2 and the sidewall of the second via 5, and is connected to the first electrode 1.

[0157] In addition, the LED also includes an epitaxial wafer, with the first electrode 1, the DBR layer 2 and the second electrode 6 all located on the epitaxial wafer.

[0158] In the technical solution provided in this disclosure embodiment, a first via connected to the first electrode is first opened on the DBR layer. Then, a filler material is filled into the first via, and a second via is opened on the filler material. The angle between the sidewall of the second via and the surface of the first electrode is smaller than the angle between the sidewall of the first via and the surface of the first electrode. This makes the slope of the sidewall of the second via gentler than that of the sidewall of the first via. In this way, the second electrode will not break at the sidewall of the second via when it is fabricated. Thus, without increasing the thickness of the second electrode, the risk of breakage of the second electrode is avoided, the problems of chip leakage and moisture penetration are reduced, thereby improving the yield and service life of the LED chip.

[0159] The above is not intended to limit this disclosure in any way. Although this disclosure has been disclosed above through embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this disclosure. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solution of this disclosure shall still fall within the scope of the technical solution of this disclosure.

Claims

1. A method of making an electrode, characterized by, The electrode manufacturing method comprises: manufacturing a first electrode; manufacturing a DBR layer covering the first electrode; opening a first via hole in the DBR layer and communicating with the first electrode; filling a filling material in the first via hole; opening a second via hole on the filling material and communicating with the first electrode, the included angle between the sidewall of the second via hole and the surface of the first electrode is smaller than the included angle between the sidewall of the first via hole and the surface of the first electrode; manufacturing a second electrode covering the DBR layer and the sidewall of the second via hole and connecting with the first electrode.

2. The electrode production method according to claim 1, wherein The filling material is SiO2 or SiN. Alternatively, the filling material is a stack, and the material of the top layer of the stack is SiO2 or SiN.

3. The electrode production method according to claim 2, wherein The first via hole is formed by dry etching, and the second via hole is formed by wet etching.

4. The electrode production method according to claim 3, wherein The opening of the second via hole on the filling material and communicating with the first electrode comprises: on the DBR layer and the filling material, a photoresist layer with a set pattern is manufactured by a photoetching process, the set pattern corresponds to the shape of the first via hole; the DBR layer exposed by the photoresist layer is etched by an etching solution to form the first via hole; and the photoresist layer is removed.

5. The electrode production method according to claim 4, wherein The etching solution is a mixed solution of hydrofluoric acid and ammonium fluoride, and the volume ratio of hydrofluoric acid to ammonium fluoride is 1:15-1:

25.

6. The electrode production method according to any one of claims 1 to 5, wherein The included angle between the sidewall of the first via hole and the surface of the first electrode is 50-80 degrees, and the included angle between the sidewall of the second via hole and the surface of the first electrode is 30-60 degrees.

7. A light-emitting diode, characterized in that, The light emitting diode comprises a first electrode, a DBR layer and a second electrode; The DBR layer covers the first electrode, and the DBR layer is provided with a first via hole communicating with the first electrode; the first via hole is filled with a filling material, and the filling material is provided with a second via hole communicating with the first electrode; the included angle between the sidewall of the second via hole and the surface of the first electrode is smaller than the included angle between the sidewall of the first via hole and the surface of the first electrode; The second electrode covers the DBR layer and the sidewall of the second via hole and connects with the first electrode.

8. The light emitting diode of claim 7, wherein, The filling material is SiO2 or SiN.

9. The light emitting diode of claim 7, wherein the first and second semiconductor layers are formed of a nitride semiconductor. The filling material is a stack, and the material of the top layer of the stack is SiO2 or SiN.

10. The light emitting diode according to any one of claims 7 to 9, wherein, The included angle between the sidewall of the first via hole and the surface of the first electrode is 50-80 degrees, and the included angle between the sidewall of the second via hole and the surface of the first electrode is 30-60 degrees.

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