semiconductor element

Abstract

A semiconductor device includes a first semiconductor layer; a second semiconductor layer on the first semiconductor layer, the second semiconductor layer including a first dopant having a first conductivity type and a second dopant having a second conductivity type, wherein the first dopant has a dopant concentration, and the first conductivity type is different from the second conductivity type; a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer includes a third dopant, the third dopant includes a dopant concentration, and the dopant concentration of the third dopant is higher than the dopant concentration of the first dopant; and an active region between the first semiconductor layer and the second semiconductor layer; wherein the second semiconductor layer includes a bottom surface facing the active region, the active region includes a top surface facing the second semiconductor layer, and a distance between the bottom surface of the second semiconductor layer and the top surface of the active region is not less than 2 nm.

Description

[0001] This application is a divisional application of a Chinese patent application (Application No. 201811399725.7, Application Date: November 22, 2018, Inventive Title: Semiconductor Element). TECHNICAL FIELD

[0002] The present disclosure relates to a semiconductor element, and in particular, to a semiconductor element comprising a semiconductor layer, and the semiconductor layer comprises two different dopants. BACKGROUND

[0003] Light emitting diodes are widely used in solid state lighting sources. Compared with traditional incandescent bulbs and fluorescent lamps, light emitting diodes have the advantages of low power consumption and long service life, so light emitting diodes have gradually replaced traditional light sources and are applied in various fields, such as traffic signs, backlight modules, street lamp lighting, medical equipment, etc. SUMMARY

[0004] The present disclosure provides a semiconductor element. The semiconductor element comprises a first semiconductor layer; a second semiconductor layer on the first semiconductor layer, the second semiconductor layer comprises a first dopant having a first conductivity type and a second dopant having a second conductivity type, wherein the first dopant has a dopant concentration, and the first conductivity type is different from the second conductivity type; a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer comprises a third dopant, the third dopant comprises a dopant concentration, and the dopant concentration of the third dopant is higher than the dopant concentration of the first dopant; and an active region between the first semiconductor layer and the second semiconductor layer; wherein the second semiconductor layer comprises a bottom surface facing the active region, the active region comprises a top surface facing the second semiconductor layer, and the distance between the bottom surface of the second semiconductor layer and the top surface of the active region is not less than 2 nm.

[0005] The present disclosure also provides a semiconductor element. The semiconductor element comprises a first semiconductor layer; a second semiconductor layer on the first semiconductor layer, the second semiconductor layer comprises a first dopant having a first conductivity type and a second dopant having a second conductivity type, the first conductivity type is different from the second conductivity type, wherein the first dopant has a dopant concentration, and the second dopant has a dopant concentration; and an active region between the first semiconductor layer and the second semiconductor layer; wherein the ratio of the dopant concentration of the first dopant to the dopant concentration of the second dopant of the second semiconductor layer is not less than 10.

[0006] The present application also provides a semiconductor device. The semiconductor device includes a first semiconductor layer; a second semiconductor layer on the first semiconductor layer, the second semiconductor layer including a first dopant having a first conductivity type and a second dopant having a second conductivity type, the first conductivity type being different from the second conductivity type, wherein the first dopant has a first dopant concentration and the second dopant has a second dopant concentration; an active region between the first semiconductor layer and the second semiconductor layer; an aluminum-containing layer between the active region and the first semiconductor layer, wherein the aluminum-containing layer includes a dopant having a dopant concentration; and a stress relief structure between the aluminum-containing layer and the first semiconductor layer, wherein the stress relief structure includes a dopant having a dopant concentration, wherein the dopant concentration of the stress relief structure is higher than the dopant concentration of the aluminum-containing layer, and the dopant concentration of the aluminum-containing layer is higher than the second dopant concentration of the second dopant of the second semiconductor layer.

[0007] The present application also provides a semiconductor device. The semiconductor device includes a first semiconductor layer; a second semiconductor layer on the first semiconductor layer, the second semiconductor layer including a first dopant having a first conductivity type; an active region between the first semiconductor layer and the second semiconductor layer; and a confinement layer between the active region and the second semiconductor layer, wherein the confinement layer includes a dopant having a conductivity type, the conductivity type of the dopant of the confinement layer being different from the first conductivity type.

[0008] The present application also provides a semiconductor device. The semiconductor device includes a first semiconductor layer; a second semiconductor layer on the first semiconductor layer, the second semiconductor layer including a first dopant having a first conductivity type; an active region between the first semiconductor layer and the second semiconductor layer, the active region including a plurality of well layers and a plurality of barrier layers alternately, wherein a barrier layer includes a dopant having a dopant concentration, the conductivity type of the dopant of the barrier layer being different from the first conductivity type; and a confinement layer between the active region and the second semiconductor layer, wherein the confinement layer includes a dopant having a dopant concentration, the dopant of the confinement layer having a conductivity type which is different from the first conductivity type, the dopant concentration of the dopant of the barrier layer being not less than the dopant concentration of the dopant of the confinement layer. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A cross-sectional view of a semiconductor device of a first embodiment of the present application;

[0010] Figure 2 A cross-sectional view of a semiconductor device of a second embodiment of the present application;

[0011] Figure 3 A cross-sectional view of a semiconductor device of a third embodiment of the present application;

[0012] Figure 4 A cross-sectional view of a semiconductor element of a fourth embodiment of the present application;

[0013] Figure 5 A cross-sectional view of a semiconductor element of a fifth embodiment of the present application.

[0014] Explanation of symbols

[0015] 1, 2, 3, 4, 5: Semiconductor element

[0016] 10: Substrate

[0017] 20: First semiconductor layer

[0018] 30: Second semiconductor layer

[0019] 40: Active region

[0020] 50: Third semiconductor layer

[0021] 60: Restrictive layer

[0022] 70: First electrode

[0023] 80: Second electrode

[0024] 90: First aluminum-containing layer

[0025] 100: Electron-blocking structure

[0026] 110: Second aluminum-containing layer

[0027] 120: Stress-relaxing structure

[0028] 401: Top surface

[0029] 301: Bottom surface DETAILED DESCRIPTION

[0030] The following embodiments will explain the concept of the present application with reference to the accompanying drawings, in which like or similar parts are designated by like reference numerals, and in which the configuration or thickness of an element can be exaggerated or reduced in the drawings. It should be noted that elements not depicted in the drawings or described in the specification can be in a form known to those skilled in the art.

[0031] In the present application, if not otherwise specified, the general formula Alx1Gai-x1N represents Al x1 Ga (1-x1) N, where 0≤x1≤1; the general formula Inx2Ga1-x2N represents In x2 Ga 1–x2 N, where 0≤x2≤1; and the general formula Inx3Al1-x3Ga1-x3N represents In x3 Al y1 Ga 1-x3-y1N, where 0≤x3≤1, 0≤y1≤1. Adjusting the content of the element can achieve different purposes, for example, but not limited to, adjusting the energy level or adjusting the main light-emitting wavelength of the light-emitting element when the semiconductor element comprises a light-emitting element.

[0032] In the following embodiments, the terms used to indicate directions, such as "up", "down", "front", "back", "left", and "right", refer only to the directions in the drawings. Therefore, the directional terms are used for illustration, not limitation of the present application.

[0033] The composition and dopant of each layer comprised in the semiconductor element of the present application can be analyzed by any suitable means, such as secondary ion mass spectrometer (SIMS).

[0034] The thickness of each layer comprised in the semiconductor element of the present application can be analyzed by any suitable means, such as transmission electron microscopy (TEM) or scanning electron microscope (SEM) for the depth position of each layer in cooperation with, for example, the SIMS spectrum.

[0035] The semiconductor element of the present application comprises a light-emitting element. The light-emitting element comprises a light-emitting diode or a laser.

[0036] Figure 1 A cross-sectional view of a semiconductor element of a first embodiment of the present application. In the present embodiment, the semiconductor element 1 comprises a substrate 10, a first semiconductor layer 20 on the substrate 10, a second semiconductor layer 30 on the first semiconductor layer 20, an active region 40 between the second semiconductor layer 30 and the first semiconductor layer 20, a third semiconductor layer 50 on the second semiconductor layer 30, and a confinement layer 60 between the active region 40 and the second semiconductor layer 30. The semiconductor element 1 further comprises a first electrode 70 electrically connected to the first semiconductor layer 20, and a second electrode 80 electrically connected to the third semiconductor layer 50.

[0037] The active region 40 comprises a plurality of well layers (not shown) and a plurality of barrier layers (not shown) alternately. Each barrier layer has an energy level. Each well layer has an energy level. In an embodiment, the energy level of one of the barrier layers is not less than the energy level of one of the well layers, and preferably higher than the energy level of one of the well layers. Preferably, the energy level of each of the barrier layers is not less than the energy level of each of the well layers, and preferably higher than the energy level of each of the well layers. The well layers comprise III-V semiconductor material. In the present embodiment, the well layers comprise In a Ga 1-aN, where 0 < a < 1. In another embodiment, the well layer includes Al b Ga 1-b N, where 0 < b < 1, and preferably, 0 < b < 0.4. The barrier layer includes Al c Ga 1-c N, where 0 < c < 1. In one embodiment, 0 < c < 0.6. In another embodiment, the barrier layer includes GaN. The thickness of each barrier layer is greater than the thickness of one of the well layers. Preferably, the thickness of each barrier layer is greater than the thickness of each well layer. Preferably, the thickness of each barrier layer is no greater than 15 nm and no less than 3 nm. The thickness of each well layer is no greater than 5 nm and no less than 1 nm. A single well layer and a single barrier layer adjacent thereto are considered a pair. The number of pairs of well and barrier layers is no less than 4 and preferably no greater than 15. The active region 40 includes a top surface 401 facing the confinement layer 60. In one embodiment, the well layer closest to the confinement layer 60 includes the top surface 401.

[0038] The second semiconductor layer 30 includes a first dopant having a first conductivity type and a second dopant having a second conductivity type. To improve light emission efficiency, the first conductivity type is different from the second conductivity type. In the present embodiment, the first conductivity type is p-type. The first dopant includes, but is not limited to, magnesium (Mg). The second dopant includes, but is not limited to, silicon (Si). The second conductivity type is n-type. The first dopant has a dopant concentration, and the second dopant has a dopant concentration. In the present embodiment, the dopant concentration of the first dopant is greater than the dopant concentration of the second dopant of the second semiconductor layer 30. Preferably, to improve light emission efficiency of the semiconductor element 1, the ratio of the dopant concentration of the first dopant to the dopant concentration of the second dopant of the second semiconductor layer 30 is no less than 10, and preferably, greater than 50, and more preferably, no greater than 200. Preferably, the ratio of the dopant concentration of the first dopant to the dopant concentration of the second dopant of the second semiconductor layer 30 is between 50 and 150 inclusive. In one embodiment, the dopant concentration of the first dopant of the second semiconductor layer 30 is greater than 1 x 1018 / cm3, preferably, greater than 1 x 1019 / cm3, and more preferably, no greater than 1 x 1020 / cm3. In one embodiment, the dopant concentration of the second dopant of the second semiconductor layer 30 is greater than 5 x 1018 / cm3, preferably, greater than 1 x 1019 / cm3, and more preferably, no greater than 5 x 1020 / cm3. 18 / cm 3 , preferably, greater than 1 x 1019 / cm3, and more preferably, no greater than 1 x 1020 / cm3. In one embodiment, the dopant concentration of the second dopant of the second semiconductor layer 30 is greater than 5 x 1018 / cm3, preferably, greater than 1 x 1019 / cm3, and more preferably, no greater than 5 x 1020 / cm3. 19 / cm 3 , preferably, greater than 1 x 1019 / cm3, and more preferably, no greater than 1 x 1020 / cm3. In one embodiment, the dopant concentration of the second dopant of the second semiconductor layer 30 is greater than 5 x 1018 / cm3, preferably, greater than 1 x 1019 / cm3, and more preferably, no greater than 5 x 1020 / cm3. 21 / cm 3 , preferably, greater than 1 x 1019 / cm3, and more preferably, no greater than 1 x 1020 / cm3. In one embodiment, the dopant concentration of the second dopant of the second semiconductor layer 30 is greater than 5 x 1018 / cm3, preferably, greater than 1 x 1019 / cm3, and more preferably, no greater than 5 x 1020 / cm3. 16 / cm 3 , preferably, greater than 1 x 1019 / cm3, and more preferably, no greater than 1 x 1020 / cm3. In one embodiment, the dopant concentration of the second dopant of the second semiconductor layer 30 is greater than 5 x 1018 / cm3, preferably, greater than 1 x 1019 / cm3, and more preferably, no greater than 5 x 1020 / cm3. 17 / cm 3 , preferably, greater than 1 x 1019 / cm3, and more preferably, no greater than 1 x 1020 / cm3. In one embodiment, the dopant concentration of the second dopant of the second semiconductor layer 30 is greater than 5 x 1018 / cm3, preferably, greater than 1 x 1019 / cm3, and more preferably, no greater than 5 x 1020 / cm3. 18 / cm 3In one embodiment, the doping concentration of the second dopant of the second semiconductor layer 30 is not greater than 1 x 1018 / cm3. 18 / cm3. 3 If the doping concentration of the second dopant is greater than 5 x 1018 / cm3 18 / cm3. 3 The forward voltage of the semiconductor element 1 will be high, and the light emitting efficiency and the electrical static discharge (ESD) resistance of the semiconductor element 1 will be poor.

[0039] The second semiconductor layer 30 has an energy level greater than that of one of the well layers. Preferably, the energy level of the second semiconductor layer 30 is greater than that of each of the well layers. The second semiconductor layer 30 comprises In d Al e Ga (1-d-e) N, where 0 < d < 1 and 0 < e < 1. In this embodiment, the second semiconductor layer 30 comprises GaN. In another embodiment, the energy level of the second semiconductor layer 30 is greater than that of one of the barrier layers. Preferably, the energy level of the second semiconductor layer 30 is greater than that of each of the barrier layers. In one embodiment, d = 0 and 0 < e < 0.3. In another embodiment, 0 < d < 0.1 and 0 < e < 0.2. In order to improve the light emitting efficiency, the thickness of the second semiconductor layer 30 is between 5 nanometers (nm) and 40 nm, inclusive.

[0040] In this embodiment, the second semiconductor layer 30 comprises a bottom surface 301 facing the active region 40. In order to improve the light emitting efficiency, the distance between the bottom surface 301 of the second semiconductor layer 30 and the top surface 401 of the active region 40 is not less than 2 nm. That is, the second semiconductor layer 30 having the first dopant and the second dopant of different conductive types is separated from the active region 40, and preferably, from the last well layer in the active region 40. If the distance between the bottom surface 301 of the second semiconductor layer 30 and the top surface 401 of the active region 40 is less than 2 nm, the leakage current of the semiconductor element 1 will increase and the electrical static discharge resistance will be poor. In another embodiment, the distance between the bottom surface 301 of the second semiconductor layer 30 and the top surface 401 of the active region 40 is not greater than 150 nm, and preferably, the distance between the bottom surface 301 of the second semiconductor layer 30 and the top surface 401 of the active region 40 is between 2 nm and 50 nm, inclusive.

[0041] In the present embodiment, the energy level of the confinement layer 60 is higher than that of one of the well layers. Preferably, the energy level of the confinement layer 60 is higher than that of each of the well layers. In one embodiment, the thickness of the confinement layer 60 is smaller than that of one of the barrier layers. Preferably, the thickness of the confinement layer 60 is smaller than that of each of the barrier layers. The thickness of the confinement layer 60 is not smaller than 2 nm, and preferably not larger than 15 nm. The confinement layer 60 includes In f Al g Ga (1-f-g) N, where 0≤f≤l and 0≤g≤l. In another embodiment, the confinement layer 60 includes Al h Ga (1-h) N, where 0≤h≤l. In one embodiment, the material of the confinement layer 60 is the same as that of one of the barrier layers. In the present embodiment, the confinement layer 60 includes GaN. In the present embodiment, the confinement layer 60 is unintentionally doped. That is, the amount of dopant source during the formation of the confinement layer 60 is substantially zero. The dopant source includes silane (SiH4) or bis-cyclopentadienyl magnesium (Cp2Mg). In addition, the dopant in the layer located above and adjacent to the confinement layer 60, i.e., the dopant in the second semiconductor layer 30 in the present embodiment, can diffuse into the confinement layer 60. In the present embodiment, the amount of silicon of the second semiconductor layer 30 diffused into the confinement layer 60 is less than the amount of magnesium diffused into the confinement layer 60. Specifically, the doping concentration of silicon in the confinement layer 60 is not larger than 5xl0 16 / cm 3 , and preferably not larger than lxlO 16 / cm 3 .

[0042] In another embodiment, the confinement layer 60 is intentionally doped with an n-type dopant. In the present embodiment, the n-type dopant of the confinement layer 60 includes silicon. In one embodiment, the doping concentration of the n-type dopant of the confinement layer 60 is larger than 5xl0 16 / cm 3 , and preferably not larger than 5xlO 18 / cm 3 . In one embodiment, the doping concentration of the n-type dopant of the confinement layer 60 is not larger than lxlO 18 / cm 3 . If the doping concentration of the n-type dopant of the confinement layer 60 is larger than 5xl0 18 / cm 3 , the starting voltage of the semiconductor device 1 will be high, and the light emitting efficiency and the static resistance of the semiconductor device 1 will be poor.

[0043] The third semiconductor layer 50 includes a third dopant having a third conductivity type. The third conductivity type is the same as the first conductivity type. In this embodiment, the third conductivity type is p-type. In this embodiment, the third dopant includes, but is not limited to, Mg. The third dopant has a doping concentration that is higher than the doping concentration of the first dopant. The doping concentration of the third dopant in the third semiconductor layer 50 is not less than 1×10 18 / cm 3 , preferably, not less than 1×10 19 / cm 3 , more preferably, between 1×10 19 / cm 3 and 5×10 22 / cm 3 (including the end values). The material of the third semiconductor layer 50 includes III-V group semiconductor materials, such as Al i Ga 1-i N, where 0≤i≤1. In one embodiment, 0 < i < 0.1, and preferably, 0 < i < 0.05. If the third semiconductor layer 50 includes Al, the luminous efficiency of the semiconductor device 1 will be higher. In another embodiment, the third semiconductor layer 50 includes GaN. The thickness of the third semiconductor layer 50 is not greater than 15 nm, and preferably, not less than 3 nm.

[0044] In another embodiment, at least one barrier layer includes an n-type dopant having a doping concentration. The n-type dopant includes, but is not limited to, silicon. The doping concentration of the n-type dopant in the barrier layer is greater than the doping concentration of the second dopant in the second semiconductor layer 30. In another embodiment, the doping concentration of the n-type dopant in the barrier layer is not less than the doping concentration of the dopant in the confinement layer 60, and preferably, the doping concentration of the n-type dopant in the barrier layer is greater than the doping concentration of the dopant in the confinement layer 60. If the doping concentration of the n-type dopant in the barrier layer is less than the doping concentration of the dopant in the confinement layer 60, the turn-on voltage of the semiconductor device 1 will become higher, and the luminous efficiency and antistatic ability of the semiconductor device 1 will become worse. In one embodiment, the doping concentration of the n-type dopant in the barrier layer is not less than 5×10 16 / cm 3 , preferably, greater than 1×10 17 / cm 3 , even more preferably, not greater than 5×10 18 / cm 3 . In one embodiment, the doping concentration of the n-type dopant in the barrier layer is not greater than 1×10 18 / cm 3 . If the doping concentration of the n-type dopant in the barrier layer is greater than 5×10 18 / cm 3 , the luminous efficiency of the semiconductor device 1 will become worse.

[0045] Figure 2 A cross-sectional view of a semiconductor element 2 of a second embodiment of the present application. The semiconductor element 2 of the second embodiment of the present application includes substantially the same structure as the semiconductor element 1 of the first embodiment, and the difference between the two will be described below. In the present embodiment, the semiconductor element 2 further includes a first aluminum-containing layer 90 between the confinement layer 60 and the second semiconductor layer 30. The first aluminum-containing layer 90 has an energy level that is greater than the energy level of the confinement layer 60 and greater than the energy level of the second semiconductor layer 30. In one embodiment, the first aluminum-containing layer 90 includes a group III-V semiconductor material, such as Al j Ga 1-j N, where 0 < j < 1. In one embodiment, 0 < j < 0.3. The first aluminum-containing layer 90 includes a dopant. The dopant of the first aluminum-containing layer 90 includes, but is not limited to, magnesium. Preferably, to increase the light emission efficiency, the doping concentration of the dopant of the first aluminum-containing layer 90 is less than the doping concentration of the first dopant of the second semiconductor layer 30. The doping concentration of the dopant of the first aluminum-containing layer 90 is not less than 1 x 1018 / cm3, preferably not less than 5 x 1018 / cm3, more preferably between 5 x 1018 / cm3and 1 x 1020 / cm3(inclusive). The thickness of the first aluminum-containing layer 90 is between 5 nm and 20 nm (inclusive). If the thickness of the first aluminum-containing layer 90 is greater than 20 nm, the threshold voltage of the semiconductor element 2 will increase. 18 / cm 3 18 / cm 3 18 / cm 3 20 / cm 3

[0046] Figure 3 ​​​​Cross-sectional view of a semiconductor device according to a third embodiment of the present invention. The structure included in the semiconductor device 3 according to the third embodiment of the present invention is substantially the same as the structure included in the semiconductor device 2 according to the second embodiment, and the differences between the two will be described below. In this embodiment, the semiconductor device 3 further includes an electron blocking structure 100 located between the third semiconductor layer 50 and the second semiconductor layer 30. The electron blocking structure 100 includes an energy level that is greater than the energy level of the second semiconductor layer 30. In this embodiment, the electron blocking structure 100 includes a plurality of alternating fourth semiconductor layers (not shown in the figure) and a plurality of fifth semiconductor layers (not shown in the figure), where the energy level of one fourth semiconductor layer is not less than the energy level of one fifth semiconductor layer. In another embodiment, the energy level of one fourth semiconductor layer is greater than the energy level of one fifth semiconductor layer. Preferably, the energy level of each fourth semiconductor layer is greater than the energy level of each fifth semiconductor layer. In this embodiment, the energy level of each fourth semiconductor layer is greater than the energy level of the second semiconductor layer 30. The thickness of one fourth semiconductor layer is between 1.5 nm and 5 nm (including the end values). The thickness of one fifth semiconductor layer is between 1.5 nm and 5 nm (including the end values). The thickness of the electron blocking structure 100 is between 20 nm and 60 nm (including the end values). One of the fourth semiconductor layers includes In k Al m Ga 1-k-m N, where 0 ≤ k ≤ 1, 0 ≤ m ≤ 1, preferably, 0 ≤ k ≤ 0.005, 0 < m ≤ 0.5. One of the fifth semiconductor layers includes In n Al p Ga 1-n-p N, where 0 ≤ n ≤ 1, 0 ≤ p ≤ 1, and preferably, p < m. A single fourth semiconductor layer and the single fifth semiconductor layer adjacent to it are regarded as a pair. The number of pairs of the fourth semiconductor layer and the fifth semiconductor layer is between 5 and 10 (including the end values). In this embodiment, the materials of the plurality of fourth semiconductor layers are substantially the same. The materials of the plurality of fifth semiconductor layers are substantially the same. The plurality of alternating fourth semiconductor layers and the plurality of fifth semiconductor layers further improve the light-emitting efficiency of the semiconductor device 3. In one embodiment, the electron blocking structure 100 has the same dopant as the first doped layer 90. In one embodiment, the doping concentration of the dopant in the electron blocking structure 100 is greater than the doping concentration of the dopant in the first aluminum-containing layer 90. The doping concentration of the dopant in the electron blocking structure 100 is greater than 1×10 18 / cm 3 Preferably, it is greater than 1×10 19 / cm 3 More preferably, it is not greater than 1×10 21 / cm 3 .

[0047] In another embodiment, the electron blocking structure 100 is comprised of a single fourth semiconductor layer having a thickness between 20 nm and 60 nm, inclusive.

[0048] Figure 4 A cross-sectional view of a semiconductor device according to a fourth embodiment of the present application. The semiconductor device 4 according to the fourth embodiment of the present application includes substantially the same structure as the semiconductor device 3 according to the third embodiment, and the difference between the two will be described below. In the present embodiment, the semiconductor device 4 further includes a second aluminum-containing layer 110 between the active region 40 and the first semiconductor layer 20. That is, the first aluminum-containing layer 90 and the second aluminum-containing layer 110 are located on opposite sides of the active region 40. The second aluminum-containing layer 110 has an energy level that is greater than that of one of the barrier layers. Preferably, the energy level of the second aluminum-containing layer 110 is greater than that of each of the barrier layers. In the present embodiment, the energy level of the second aluminum-containing layer 110 is greater than that of the confinement layer 60. The energy level of the second aluminum-containing layer 110 is less than that of the first aluminum-containing layer 90. In one embodiment, when the electron blocking structure 100 includes a plurality of fourth semiconductor layers and a plurality of fifth semiconductor layers that alternate, the energy level of the second aluminum-containing layer 110 is less than that of one of the fourth semiconductor layers. In the present embodiment, the energy level of the second aluminum-containing layer 110 is less than that of each of the fourth semiconductor layers. In one embodiment, the second aluminum-containing layer 110 includes Al q Ga 1-q N, where 0 < q < 1, and preferably, q < j, where the first aluminum-containing layer 90 includes Al j Ga 1- j N. Preferably, 0 < q < 0.05. In one embodiment, the second aluminum-containing layer 110 includes an n-type dopant having a doping concentration. In the present embodiment, the n-type dopant of the second aluminum-containing layer 110 includes silicon. In one embodiment, the doping concentration of the n-type dopant of the second aluminum-containing layer 110 is not less than the doping concentration of the n-type dopant of the confinement layer 60. Preferably, the doping concentration of the n-type dopant of the second aluminum-containing layer 110 is greater than the doping concentration of the n-type dopant of the confinement layer 60. In one embodiment, the doping concentration of the n-type dopant of the second aluminum-containing layer 110 is not less than the doping concentration of the second dopant of the second semiconductor layer 30. Preferably, the doping concentration of the n-type dopant of the second aluminum-containing layer 110 is greater than the doping concentration of the second dopant of the second semiconductor layer 30. In one embodiment, the doping concentration of the n-type dopant of the second aluminum-containing layer 110 is not less than 5 x 1018 / cm3, preferably not less than 1 x 1019 / cm3, and more preferably not less than 5 x 1019 / cm3. 16 / cm 3 , preferably not less than 1 x 1019 / cm3, and more preferably not less than 5 x 1019 / cm3. 17 / cm 3 , preferably not less than 1 x 1019 / cm3, and more preferably not less than 5 x 1019 / cm3. 18 / cm 3In one embodiment, the doping concentration of the n-type dopant in the second aluminum-containing layer 110 is not greater than 1×10 18 / cm 3 .

[0049] Figure 5 FIG. is a cross-sectional view of the semiconductor element 5 according to the fifth embodiment of the present invention. The structure included in the semiconductor element 5 according to the fifth embodiment of the present invention is substantially the same as the structure included in the semiconductor element 4 according to the fourth embodiment, and the differences between the two will be described below. In this embodiment, the semiconductor element 5 further includes a stress relief structure 120 located between the second aluminum-containing layer 110 and the first semiconductor layer 20. The stress relief structure 120 includes a plurality of alternating sixth semiconductor layers (not shown in the figure) and a plurality of seventh semiconductor layers (not shown in the figure), where a single sixth semiconductor layer and the single seventh semiconductor layer adjacent to it are regarded as a pair. The sixth semiconductor layer and the seventh semiconductor layer include III-V group semiconductor materials. The energy level of the sixth semiconductor layer in a pair is greater than that of the seventh semiconductor layer. The sixth semiconductor layer includes In r Al s Ga 1-r-s N, where 0≤r≤1, 0≤s≤1. The seventh semiconductor layer includes In t Ga 1-t N, where 0<t≤1. In one embodiment, the sixth semiconductor layer includes GaN. The number of pairs of the sixth semiconductor layer and the seventh semiconductor layer is not less than 3, and preferably, not more than 40.

[0050] The thickness of one of the sixth semiconductor layers is greater than the thickness of one of the seventh semiconductor layers. Preferably, the thickness of each sixth semiconductor layer is greater than the thickness of each seventh semiconductor layer. In one embodiment, the thickness of one of the sixth semiconductor layers is not less than 5 nm, and preferably, not more than 80 nm. In one embodiment, in order to further reduce the starting voltage of the semiconductor element 5, the thickness of one of the sixth semiconductor layers is between 60 nm and 80 nm (including the end values). The thickness of one of the seventh semiconductor layers is not less than 1 nm, and preferably, not more than 10 nm. In one embodiment, one of the sixth semiconductor layers includes an n-type dopant having a doping concentration. In this embodiment, the n-type dopant in the sixth semiconductor layer includes silicon. In one embodiment, the doping concentration of the n-type dopant in the sixth semiconductor layer is greater than the doping concentration of the n-type dopant in the second aluminum-containing layer 110. In one embodiment, the ratio of the doping concentration of the n-type dopant in the sixth semiconductor layer to the doping concentration of the n-type dopant in the second aluminum-containing layer 110 is not less than 2, and preferably, not more than 10. In one embodiment, the doping concentration of the n-type dopant in the sixth semiconductor layer is not less than 5×10 17 / cm 3 , and preferably, not less than 1×10 18 / cm3 More preferably, the sheet resistance is not greater than 1 x 10 19 / cm 3 In one embodiment, the seventh semiconductor layer is undoped or unintentionally doped.

[0051] In the present invention, the first semiconductor layer 20 of the semiconductor device of any embodiment comprises Al q Ga 1–q N, where 0 < q < 1. Preferably, the first semiconductor layer comprises GaN and an n-type dopant. The first semiconductor layer has a thickness not less than 100 nm, and more preferably not more than 3000 nm. The doping concentration of the n-type dopant in the first semiconductor layer 20 is greater than the doping concentration of the n-type dopant in the sixth semiconductor layer. The doping concentration of the n-type dopant in the first semiconductor layer 20 is not less than 1 x 10 18 / cm 3 , and more preferably not less than 5 x 10 18 / cm 3 , and more preferably not less than 5 x 10 18 / cm 3 to 5 x 10 21 / cm 3 (inclusive). The n-type dopant includes, but is not limited to, silicon.

[0052] In the present invention, the semiconductor device of any embodiment further comprises a buffer layer (not shown) between the substrate 10 and the first semiconductor layer 20, which is to reduce defects and improve the quality of the epitaxial layer grown thereon. In one embodiment, the buffer layer comprises Al i Ga 1–i N, where 0 < i < 1. In one embodiment, the buffer layer comprises GaN. In another embodiment, the buffer layer comprises AlN. The buffer layer can be formed by epitaxy or physical vapor deposition (PVD). Physical vapor deposition includes sputtering or electron beam evaporation.

[0053] In the present invention, the substrate 10 of the semiconductor device of any embodiment has a thickness sufficient to support the layers and structures thereon, for example, not less than 50 μm, and more preferably not more than 300 μm. In one embodiment, the substrate 10 comprises sapphire, which comprises a surface and periodic protrusions formed on the surface. In another embodiment, the substrate 10 comprises a conductive material, which includes (Si), germanium (Ge), copper (Cu), molybdenum (Mo), molybdenum tungsten alloy (MoW), gallium nitride (GaN), zinc oxide (ZnO), or copper tungsten (CuW).

[0054] In the present application, the first electrode 70 and the second electrode 80 of any of the embodiments of the semiconductor element are used to connect with an external power source and conduct a current therebetween. The materials of the first electrode 70 and the second electrode 80 include a transparent conductive material or a metal material. The transparent conductive material includes a transparent conductive oxide, which includes indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (Zn2SnO4, ZTO), gallium doped zinc oxide (GZO), tungsten doped indium oxide (IWO), zinc oxide (ZnO), or indium zinc oxide (IZO). The metal material includes gold (Au), platinum (Pt), germanium gold nickel (GeAuNi), titanium (Ti), beryllium gold (BeAu), germanium gold (GeAu), aluminum (Al), zinc gold (ZnAu), or nickel (Ni).

[0055] In an embodiment, the first electrode 70 and the second electrode 80 are respectively located on opposite sides of the substrate 10. In this embodiment, the substrate 10 includes a conductive material.

[0056] The method of performing epitaxial growth includes, but is not limited to, metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxial (HVPE), or liquid-phase epitaxy (LPE). Preferably, the method of performing epitaxial growth includes MOCVD.

[0057] If the semiconductor element of any of the embodiments includes a light emitting element, the peak wavelength of the light emitted by the light emitting element is in the range of visible light or invisible light, and preferably in the range of blue light or ultraviolet light. Preferably, the peak wavelength is between 250 nm and 570 nm, inclusive, and preferably between 350 nm and 480 nm, inclusive.

[0058] In another embodiment of the present application, the elements or structures in the above-mentioned embodiments can be changed or combined with each other. For example, Figure 1 The semiconductor element 1 shown includes a first electrode 70 and a second electrode 80, as shown in the above-mentioned embodiments. Figure 4 The second aluminum-containing layer 110 shown.

[0059] It is to be noted that the embodiments of the present application are merely used to illustrate the present application, and are not used to limit the scope of the present application. Any modification or change made by any person to the present application without departing from the spirit and scope of the present application. The same or similar components in different embodiments, or the components with the same reference numerals in different embodiments have the same physical or chemical properties. In addition, the above-mentioned embodiments in the present application can be combined or replaced with each other under appropriate circumstances, and are not limited to the specific embodiments described. The connection relationship between the specific components described in one embodiment and other components can also be applied to other embodiments, and all fall within the scope of the claims of the present application.

Claims

1. A semiconductor device, characterized in that, Include: First semiconductor layer; A second semiconductor layer is located on the first semiconductor layer, wherein the second semiconductor layer includes a first dopant having a first conductivity type and a second dopant having a second conductivity type, wherein the first dopant has a doping concentration and the first conductivity type is different from the second conductivity type; An active region is located between the first semiconductor layer and the second semiconductor layer, wherein the active region includes a well layer and a barrier layer, the barrier layer having a third dopant having a doping concentration; A confinement layer is located between the active region and the second semiconductor layer, wherein the confinement layer contains a fourth dopant having a doping concentration of a third conductivity type, the third conductivity type of the fourth dopant being different from the first conductivity type; as well as A first aluminum-containing layer is located between the confinement layer and the second semiconductor layer, wherein the first aluminum-containing layer has an energy level, the confinement layer has an energy level, and the energy level of the first aluminum-containing layer is higher than the energy level of the confinement layer. The doping concentration of the third dopant in the barrier layer is not less than the doping concentration of the fourth dopant in the confinement layer.

2. The semiconductor device of claim 1, further comprising a third semiconductor layer located on the second semiconductor layer, wherein the third semiconductor layer comprises a fifth dopant having a doping concentration higher than that of the first dopant.

3. The semiconductor device of claim 1, wherein the second dopant of the second semiconductor layer has a doping concentration, and the doping concentration of the first dopant of the second semiconductor layer is greater than the doping concentration of the second dopant.

4. The semiconductor device of claim 1, wherein the material of the confinement layer is the same as the material of the barrier layer.

5. The semiconductor device of claim 1, wherein the doping concentration of the fourth dopant in the confinement layer is not greater than 1 × 10⁻⁶. 18 / cm 3 .

6. The semiconductor device of claim 1, wherein the doping concentration of the first dopant in the second semiconductor layer is not less than 1 × 10⁻⁶. 18 / cm 3 .

7. The semiconductor device of claim 1, wherein the second dopant of the second semiconductor layer has a doping concentration of not less than 1 × 10⁻⁶. 17 / cm 3 and not greater than 5×10 18 / cm 3 .

8. The semiconductor device of claim 1, further comprising a second aluminum-containing layer located between the first semiconductor layer and the active region.

9. A semiconductor element, characterized in that, Include: First semiconductor layer; A second semiconductor layer is located on the first semiconductor layer, wherein the second semiconductor layer contains a first dopant having a doping concentration; The active region is located between the first semiconductor layer and the second semiconductor layer; A confinement layer is located between the active region and the second semiconductor layer, wherein the confinement layer contains a second dopant, the second dopant having a doping concentration; and The second aluminum-containing layer is located between the first semiconductor layer and the active region; The second aluminum-containing layer includes a third dopant with a doping concentration that is not less than the doping concentration of the second dopant in the confinement layer.

10. The semiconductor device of claim 9, further comprising a first aluminum-containing layer located between the confinement layer and the second semiconductor layer, wherein the first aluminum-containing layer has an energy level, the confinement layer has an energy level, and the energy level of the first aluminum-containing layer is higher than the energy level of the confinement layer.

11. The semiconductor device of claim 10, wherein the first aluminum-containing layer comprises a fourth dopant having a doping concentration.

12. The semiconductor device of claim 9, wherein the active region comprises a well layer and a barrier layer, wherein the doping concentration of the barrier layer is not less than the doping concentration of the second dopant in the confinement layer.

13. The semiconductor device of claim 9, further comprising an electron blocking structure located on the second semiconductor layer, wherein the electron blocking structure has an energy level, the second semiconductor layer has an energy level, and the energy level of the electron blocking structure is higher than the energy level of the second semiconductor layer.

14. The semiconductor device of claim 11, further comprising an electron blocking structure located on the second semiconductor layer, wherein the electron blocking structure includes a sixth dopant having a doping concentration higher than the doping concentration of the fourth dopant in the first aluminum-containing layer.

15. The semiconductor device of claim 13, wherein the thickness of the electron blocking structure is between 20 nm and 60 nm.

16. The semiconductor element of claim 13, further comprising a third semiconductor layer located on the electron blocking structure.

17. The semiconductor device of claim 16, wherein the third semiconductor layer includes a fifth dopant having a doping concentration higher than that of the first dopant in the second semiconductor layer.

18. The semiconductor device of claim 9, further comprising a stress relief structure located on the first semiconductor layer, wherein the stress relief structure comprises a sixth semiconductor layer and a seventh semiconductor layer, the sixth semiconductor layer comprising an energy level, the seventh semiconductor layer comprising an energy level, the energy level of the sixth semiconductor layer being greater than the energy level of the seventh semiconductor layer.

19. The semiconductor device of claim 18, wherein the stress relief structure comprises alternating plurality of sixth semiconductor layers and plurality of seventh semiconductor layers.

20. A semiconductor element, characterized in that, Include: First semiconductor layer; A second semiconductor layer is located on the first semiconductor layer, wherein the second semiconductor layer contains a first dopant, the first dopant having a doping concentration and a first conductivity type; An active region is located between the first semiconductor layer and the second semiconductor layer, wherein the active region includes at least a well layer and a barrier layer; A confinement layer is located between the active region and the second semiconductor layer, wherein the confinement layer contains a second dopant with a doping concentration of a second conductivity type, the second conductivity type of the second dopant being different from the first conductivity type; A first aluminum-containing layer is located between the confinement layer and the second semiconductor layer; The second aluminum-containing layer is located between the first semiconductor layer and the active region; as well as A stress-relieving structure is located between the second aluminum-containing layer and the first semiconductor layer, wherein the stress-relieving structure includes a sixth semiconductor layer and the thickness of the sixth semiconductor layer is between 60 nm and 80 nm.

21. The semiconductor device of claim 20, wherein the confinement layer has an energy level, and the energy level of the first aluminum-containing layer is higher than the energy level of the confinement layer.

22. The semiconductor device of claim 20, wherein the second aluminum-containing layer comprises a dopant having a doping concentration, and the doping concentration of the dopant in the second aluminum-containing layer is not less than the doping concentration of the second dopant.

23. The semiconductor device of claim 20, wherein the stress relief structure comprises a seventh semiconductor layer; and the thickness of the seventh semiconductor layer is between 1 nm and 10 nm.

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