Column-level readout circuit, column-level successive approximation analog-to-digital converter, and infrared imager

Abstract

The present invention provides a column-level readout circuit, a column-level successive approximation analog-to-digital converter, and an infrared imager, which relate to the field of integrated circuits. Each ADC module is an SAR ADC shared by N columns; for the high M bits, a resistor DAC is used to form a high M-bit resistor voltage buffer, and for the low L bits, a capacitive DAC with bridged capacitors is used; the two groups of capacitive DACs with bridged capacitors are respectively the capacitive DAC with bridged capacitors for odd columns and the capacitive DAC with bridged capacitors for even columns. When the capacitive DAC with bridged capacitors for odd columns samples the pixel voltages transmitted by the odd columns in N columns, the capacitive DAC with bridged capacitors for even columns simultaneously quantizes the pixel voltages that have been sampled by the even columns in N columns, or when the capacitive DAC with bridged capacitors for even columns samples the pixel voltages transmitted by the even columns in N columns, the capacitive DAC with bridged capacitors for odd columns simultaneously quantizes the pixel voltages that have been sampled by the odd columns in N columns. The present invention reduces the area of the DAC array, increases the sampling time, improves the efficiency of quantization conversion, reduces power consumption, and has high practicability.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and particularly to a column-level readout circuit, a column-level successive approximation analog-to-digital converter, and an infrared imager. Background Art

[0002] In the past few years, infrared imaging has been applied in a very wide range of fields, such as biomedicine, space exploration, fire fighting, etc. As the core of the infrared imaging system, the design of infrared focal plane circuits and ADCs in the circuits has attracted more and more attention.

[0003] Traditional infrared focal plane ADCs have pixel-level, column-level, and chip-level ones. Considering the strict speed limitation of single-channel chip-level ADCs and the power consumption limitation of pixel-level ADCs, column-level ADCs make a good trade-off among area, sampling rate, power consumption, and signal-to-noise ratio, and are thus widely adopted at present. Traditional column-level ADCs include single-ramp ADCs, cyclic ADCs, SAR ADCs, and delta-sigma ADCs.

[0004] Single-slope ADCs are widely used because of their simple structure, minimum area, and low power consumption. However, for a single-slope ADC to quantize N bits, it requires 2^N clocks, and the conversion rate is very slow, which is not suitable for use with medium and high frame rates.

[0005] Cyclic ADCs only require N clocks to quantize N bits, are a kind of high-speed ADCs, and occupy a relatively small area. However, the design of cyclic ADCs requires operational amplifiers with high gain, high power consumption, and low offset, and the energy efficiency is not high. The power consumption and design difficulties limit their use.

[0006] Delta-sigma ADCs can achieve high precision and high dynamic range by utilizing the characteristics of oversampling and noise shaping. However, due to the need for oversampling, the conversion speed is slow. To increase the speed, high-order modulators are often used, but this will increase the system complexity, consume more hardware costs and power, and reduce the system stability.

[0007] SAR ADCs require N clocks to convert N bits and are suitable for applications with medium and high frame rates. However, traditional SAR ADCs require a large capacitor array, a comparator, and a SAR logic. For an N-bit SAR ADC, it requires 2 N C0s, where C0 represents the unit capacitance. Therefore, the capacitor array will occupy a very large area, and at the same time, it will also bring difficulties to the layout and arrangement of signal lines, reducing the competitiveness of this structure.

[0008] Therefore, how to reduce the occupied area of the SAR ADC digital-to-analog converter (DAC), improve the quantization conversion efficiency, and reduce the power consumption is an urgent problem to be solved. Summary of the Invention

[0009] In view of the above problems, the present invention is proposed to provide a column-level readout circuit, a column-level successive approximation analog-to-digital converter, and an infrared imager that solve the above problems or partially solve the above problems.

[0010] The first aspect of the embodiment of the present invention provides a column-level readout circuit, which includes: a plurality of ADC modules, a timing control unit, a parallel-to-serial output circuit, and a high-M-bit resistor voltage buffer;

[0011] Each ADC module is a SAR ADC shared by N columns.

[0012] For the DAC of the analog-to-digital converter, if its overall is X bit, let X = M + L, where the high-M-bit resistor DAC is used to form the high-M-bit resistor voltage buffer, and the reference voltage generated by the high-M-bit resistor voltage buffer is shared by all the ADC modules, and the low-L-bit uses a capacitive DAC with bridge capacitors;

[0013] Each of the ADC modules includes: an odd-column selector, an even-column selector, a comparator, a control logic unit, and two sets of bridge-capacitor DACs;

[0014] The two sets of bridge-capacitor DACs are respectively a bridge-capacitor DAC for odd columns and a bridge-capacitor DAC for even columns. When the bridge-capacitor DAC for odd columns samples the pixel voltages transmitted by the odd columns in N columns, the bridge-capacitor DAC for even columns simultaneously quantizes the pixel voltages that have been sampled by the even columns in N columns. Or, when the bridge-capacitor DAC for even columns samples the pixel voltages transmitted by the even columns in N columns, the bridge-capacitor DAC for odd columns simultaneously quantizes the pixel voltages that have been sampled by the odd columns in N columns;

[0015] The odd-column selector selects any odd column in the N columns according to column-level decoding and transmits the pixel voltage of the odd column to the bridge-capacitor DAC for odd columns;

[0016] The even-column selector selects any even column in the N columns according to column-level decoding and transmits the pixel voltage of the even column to the bridge-capacitor DAC for even columns;

[0017] For the bridge-capacitor DAC for odd columns and the bridge-capacitor DAC for even columns, both have:

[0018] The upper plates of each bridging capacitor are connected to each other to form the upper plate of the bridging capacitor DAC. The lower plates of each bridging capacitor receive the pixel voltages of their respective columns through their respective lower plate sampling switches, and the lower plates of each bridging capacitor receive the reference voltage through their respective capacitor control switches.

[0019] Between the upper plates of the bridging capacitor DAC for the odd-numbered columns and the upper plates of the bridging capacitor DAC for the even-numbered columns, they are connected through two sets of odd-even switches, and one of the sets of odd-even switches is connected to the comparator.

[0020] The output terminal of the comparator is respectively connected to the control logic unit and the parallel-to-serial output circuit. The output signal of the comparator is the quantization result of its corresponding ADC module.

[0021] The control logic unit generates an odd control signal for controlling the lower plate sampling switch and the capacitor control switch of each bridging capacitor in the bridging capacitor DAC for the odd-numbered columns according to the output signal of the comparator, and generates an even control signal for controlling the lower plate sampling switch and the capacitor control switch of each bridging capacitor in the bridging capacitor DAC for the even-numbered columns.

[0022] The parallel-to-serial output circuit receives the output signal of the comparator, performs parallel-to-serial conversion of the quantization results of multiple ADC modules, and digitally outputs them outside the chip.

[0023] Optionally, the two sets of odd-even switches include: a first set of odd-even switches and a second set of odd-even switches.

[0024] The first set of odd-even switches includes: a first odd switch and a first even switch.

[0025] The second set of odd-even switches includes: a second odd switch and a second even switch.

[0026] The first end of the first odd switch is connected to the upper plate of the bridging capacitor DAC for the odd-numbered columns. The second end of the first odd switch is connected to the first end of the first even switch and receives the common-mode voltage.

[0027] The second end of the first even switch is connected to the upper plate of the bridging capacitor DAC for the even-numbered columns.

[0028] The first end of the second even switch is connected to the upper plate of the bridging capacitor DAC for the odd-numbered columns. The second end of the second even switch is respectively connected to the first end of the second odd switch and the inverting input terminal of the comparator.

[0029] The second end of the second odd switch is connected to the upper plate of the bridging capacitor DAC for the even-numbered columns.

[0030] Optionally, the non-inverting terminal of the comparator receives the common-mode voltage, and the comparator compares the signal output from the second terminal of the second even switch or the first terminal of the second odd switch with the common-mode voltage to obtain the output signal of the comparator;

[0031] The control logic unit generates the odd control signal and the even control signal according to the output signal of the comparator.

[0032] Optionally, in any time period, if the odd-numbered columns sample the pixel voltages transmitted by any odd-numbered column among the N columns using the bridge-capacitor DAC, then the even-numbered columns use the bridge-capacitor DAC to quantify the pixel voltages that have been sampled in any even-numbered column among the N columns during this time period;

[0033] When the odd-numbered columns sample the pixel voltages transmitted by any odd-numbered column among the N columns using the bridge-capacitor DAC, the first odd switch and the second odd switch are both closed, the first even switch and the second even switch are both open, and the lower-plate sampling switches of each capacitor in the bridge-capacitor DAC for the odd-numbered columns are controlled by the odd control signal to be closed, and the capacitor control switches of each capacitor in the bridge-capacitor DAC for the odd-numbered columns are controlled by the odd control signal to be open.

[0034] Optionally, in any time period, if the odd-numbered columns sample the pixel voltages transmitted by any odd-numbered column among the N columns using the bridge-capacitor DAC, then the even-numbered columns use the bridge-capacitor DAC to quantify the pixel voltages that have been sampled in any even-numbered column among the N columns during this time period;

[0035] When the even-numbered columns use the bridge-capacitor DAC to quantify the pixel voltages that have been sampled in any even-numbered column among the N columns, the first odd switch and the second odd switch are both closed, the first even switch and the second even switch are both open, the lower-plate sampling switches of each capacitor in the bridge-capacitor DAC for the even-numbered columns are controlled by the even control signal to be open, and the capacitor control switches of each capacitor in the bridge-capacitor DAC for the even-numbered columns are controlled by the even control signal to be selectively closed to achieve successive approximation comparison quantization of the reference voltage.

[0036] Optionally, the reference voltage includes: V BOT and V TOP ;

[0037] The capacitor control switches of each capacitor in the bridge-capacitor DAC for the even-numbered columns are controlled by the even control signal to be selectively closed, and the voltage of V TOP is higher than the voltage of V BOT Then the high M-bit resistance voltage range connected to the capacitor control switch connected to V is TOP ​ Connected to the said V BOT The high M bit resistance voltage range of the capacitance control control switch connection is The process of realizing successive approximation comparison and quantization of the reference voltage includes:

[0038] Step S1: Switch all the capacitance control switches to connect to the said V BOT , and perform the selection of the high M bit resistance voltage. Among them, the logic of the even control signal of the control connection to the said V BOT is the same as that of the capacitance control switch connected to the said V TOP ;

[0039] Step S2: Let Q S be the charge stored on all the bridging capacitors in the bridging capacitor DAC at the end of any even-numbered column sampling. C Tot is the total capacitance of all the bridging capacitors in the bridging capacitor DAC for the said even-numbered column. Then there is the following formula:

[0040] Q S = C Tot ×(V CM - V COL [n]

[0041] In the above formula, V CM represents the common mode voltage, and V COL [n] represents the pixel voltage obtained by sampling any even-numbered column;

[0042] When all the lower plates of all the bridging capacitors in the bridging capacitor DAC for the said even-numbered column are selected and connected to the said V BOT through their respective capacitance control switches, let the voltage of the upper plates of all the bridging capacitors in the bridging capacitor DAC for the said even-numbered column at this time be V A . Then there is the following formula:

[0043] Q S = C Tot ×(V A - V BOT )

[0044] V A = V CM + V BOT - V COL [n]

[0045] At this time, there is: One end voltage of the comparator is V CM , and one end voltage is V A . Then the voltage V ε for the comparator to perform comparison is:

[0046] V ε = VCOL [n]-V BOT

[0047] Step S3: When making a judgment, first, the V BOT The voltage value selected through the control switch is If the output signal of the comparator is 1, it means that the pixel voltage V COL [n] is higher, and it is necessary to adjust the capacitor control switch connecting the V BOT to select a higher voltage value

[0048] If the output signal of the comparator is 0, it is necessary to adjust the capacitor control switch connecting the V BOT to select a lower reference voltage to perform successive approximation comparison on the reference voltage and select a voltage segment suitable for quantifying the pixel voltage;

[0049] Step S4: According to the result of the comparator, continuously switch the capacitor control switch connecting the V BOT to select the reference voltages generated by different high M bit resistor voltage buffers for comparison, so as to select the V BOT ;

[0050] Step S5: After the comparison of the high Mbit reference voltage is completed, select a V COL corresponding to the pixel voltage V BOT [n] sampled from any even column. Since the logic of the even control signal of the capacitor control switch connected to the V BOT is the same as that connected to the V TOP , at this time: the V COL corresponding to the pixel voltage V TOP [n] sampled from any even column is also selected;

[0051] After determining a V COL corresponding to the pixel voltage V BOT and a V TOP [n] sampled from any even column, perform successive approximation comparison and quantization on the low L bit capacitor DAC. Connect the highest bit capacitor to V TOP , perform corresponding comparison, and according to the result of the comparator, further determine whether the highest bit capacitor control switch is connected to V TOP or V BOT ;

[0052] Step S6: Repeat step S5 to perform successive approximation quantization on the remaining bit capacitors of the low-L bit capacitive DAC, thereby obtaining the corresponding code value.

[0053] Optionally, the column-level readout circuit further includes: a timing control unit;

[0054] Both groups of the parity switches are controlled by the timing control signal of the timing control unit. The timings of the first odd switch and the second odd switch are the same, and the timings of the first even switch and the second even switch are the same;

[0055] When the timing control signals received by the first odd switch and the second odd switch are at a high level, both the first odd switch and the second odd switch are closed, both the first even switch and the second even switch are open, and the odd column selector selects any odd column among the N columns according to column-level decoding;

[0056] When the timing control signals received by the first even switch and the second even switch are at a high level, both the first even switch and the second even switch are closed, both the first odd switch and the second odd switch are open, and the even column selector selects any even column among the N columns according to column-level decoding.

[0057] Optionally, the time for the odd columns to sample the pixel voltages transmitted by any odd column among the N columns using the bridge capacitive DAC is equal to the time for the even columns to quantize the pixel voltages that have been sampled by any even column among the N columns using the bridge capacitive DAC.

[0058] A second aspect of the embodiments of the present invention provides a column-level successive approximation analog-to-digital converter, which includes the column-level readout circuit according to any one of the first aspect.

[0059] A third aspect of the embodiments of the present invention provides an infrared imager, which includes: a photocurrent detector and the column-level readout circuit according to any one of the first aspect.

[0060] The column-level readout circuit provided by the present invention includes: a plurality of ADC modules, a timing control unit, a parallel-to-serial output circuit, and a high-M bit resistor voltage buffer. Each ADC module is an N-column shared SAR ADC; for the DAC of the analog-to-digital converter, if its overall is X bit, let X = M + L, where the high-M bit uses a resistor DAC to form a high-M bit resistor voltage buffer, and the reference voltage generated by the resistor string voltage reference buffer of the high-M bit is shared by all the ADC modules, while the low-L bit uses a capacitive DAC with a bridge capacitor.

[0061] Each ADC module includes: an odd-column selector, an even-column selector, a comparator, a control logic unit, and two sets of bridge-capacitor DACs; the two sets of bridge-capacitor DACs are the bridge-capacitor DAC for odd columns and the bridge-capacitor DAC for even columns respectively. When the bridge-capacitor DAC for odd columns samples the pixel voltages transmitted by the odd columns in N columns, the bridge-capacitor DAC for even columns simultaneously quantizes the pixel voltages that have been sampled by the even columns in N columns. Or, when the bridge-capacitor DAC for even columns samples the pixel voltages transmitted by the even columns in N columns, the bridge-capacitor DAC for odd columns simultaneously quantizes the pixel voltages that have been sampled by the odd columns in N columns.

[0062] The odd-column selector selects any odd column in N columns according to column-level decoding, and transmits the pixel voltages of this odd column to the bridge-capacitor DAC for odd columns; the even-column selector selects any even column in N columns according to column-level decoding, and transmits the pixel voltages of this even column to the bridge-capacitor DAC for even columns. For the bridge-capacitor DAC for odd columns and the bridge-capacitor DAC for even columns, there are:

[0063] The upper plates of each bridge capacitor are connected to each other to form the upper plate of the bridge-capacitor DAC. The lower plate of each bridge-capacitor DAC receives the pixel voltages of its corresponding column through its respective lower-plate sampling switch, and the lower plate of each bridge-capacitor DAC receives the resistor reference voltage through its respective capacitor control switch.

[0064] Between the upper plate of the bridge-capacitor DAC for odd columns and the upper plate of the bridge-capacitor DAC for even columns, they are connected through two sets of odd-even switches, and one of the odd-even switches is connected to the comparator. The output terminal of the comparator is connected to the control logic unit, and the output signal of the comparator is the quantization result of its corresponding ADC module.

[0065] The control logic unit generates an odd control signal for controlling each capacitor lower-plate sampling switch and capacitor control switch in the bridge-capacitor DAC for odd columns, and an even control signal for controlling each capacitor lower-plate sampling switch and capacitor control switch in the bridge-capacitor DAC for even columns according to the output signal of the comparator. And the parallel-to-serial output circuit receives the output signal of the comparator, performs parallel-to-serial conversion of the quantization results of multiple ADC modules, and outputs them digitally outside the chip.

[0066] The column-level readout circuit proposed in the present invention, through the above structure, uses a resistor DAC to form a high M bit resistor voltage buffer in the high M bit, and the generated reference voltage is shared by multiple ADC modules. The low L bit uses a capacitor DAC with a bridge capacitor, and only the capacitor DAC of the low L bit is retained inside each ADC module, which uses a bridge capacitor DAC. Compared with the pure capacitor array SARADC with the same precision, the column-level readout circuit proposed in the present invention reduces the DAC array area, and due to the use of odd-even capacitor DAC, the sampling time of the pixel voltage is increased in disguise, which indirectly improves the efficiency of quantization conversion, reduces the current demand for pixels to columns, reduces power consumption, and has high practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0068] Figure 1 is a schematic diagram of the overall structure of an analog-to-digital converter in an embodiment of the present invention;

[0069] Figure 2 is a schematic structural diagram of a preferred ADC module in an embodiment of the present invention;

[0070] Figure 3 It is a timing diagram of the odd-even switch sent by the timing control unit in an embodiment of the present invention. DETAILED DESCRIPTION

[0071] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0072] A column-level readout circuit of the present invention is newly designed based on the current traditional SAR ADC structure. The pixel array part is the same as the traditional SAR ADC structure, and the pixel array is integrated and sampled by row selection signals and column selection signals respectively.

[0073] In terms of column-level structure, different from the column-level readout circuit of the traditional SAR ADC, the column-level readout circuit proposed in the present invention includes: multiple ADC modules, a timing control unit, a parallel-to-serial output circuit and a high-M bit resistor voltage buffer.

[0074] Reference Figure 1 , which shows the overall structural schematic diagram of the analog-to-digital converter in the embodiment of the present invention. The part within the virtual box is the column-level readout circuit structure proposed by the present invention, and multiple ADC modules are represented by Module 1, Module 2, …… Module K. The reference voltage generated by the high M-bit resistor voltage buffer is used by Module 1, Module 2, …… Module K. The respective quantization conversion results of Module 1, Module 2, …… Module K are transmitted to the parallel-to-serial output circuit, and the parallel-to-serial output circuit converts the parallel digital signal into a serial digital signal, and finally performs digital output and reads out outside the chip.

[0075] In the column-level readout circuit proposed by the present invention, each ADC module is an N-column shared SAR ADC. That is, each ADC module corresponds to N columns of the pixel array, and all ADC modules together correspond to all columns of the entire pixel array. For example: if the pixel array has a total of 256 columns and N = 16, then each ADC module is a 16-column shared SAR ADC, and a total of 16 ADC modules are required, corresponding to the 256-column pixel array.

[0076] For the DAC of the analog-to-digital converter, if the overall analog-to-digital converter is X bit, it can be set that X = M + L. Among them, the high M-bit uses a resistor DAC to form a high M-bit resistor voltage buffer, and the reference voltage generated by this high M-bit resistor voltage buffer is used by all ADC modules, while the low L-bit uses a capacitive DAC with bridge capacitors.

[0077] Each ADC module includes: an odd-column selector, an even-column selector, a comparator, a control logic unit, and two groups of bridge-capacitor DACs. The two groups of bridge-capacitor DACs are respectively a bridge-capacitor DAC for odd columns and a bridge-capacitor DAC for even columns. When the bridge-capacitor DAC for odd columns samples the pixel voltages transmitted by the odd columns in N columns, the bridge-capacitor DAC for even columns simultaneously quantizes the pixel voltages of the even columns in N columns that have been sampled. Or, when the bridge-capacitor DAC for even columns samples the pixel voltages transmitted by the even columns in N columns, the bridge-capacitor DAC for odd columns simultaneously quantizes the pixel voltages of the odd columns in N columns that have been sampled.

[0078] When the odd-column selector selects any odd column in N columns according to column-level decoding, the pixel voltage of this odd column is transmitted to the bridge-capacitor DAC for odd columns; when the even-column selector selects any even column in N columns according to column-level decoding, the pixel voltage of this even column is transmitted to the bridge-capacitor DAC for even columns.

[0079] For the structures of the bridge-capacitor DAC for odd columns and the bridge-capacitor DAC for even columns, both have:

[0080] The upper plates of each bridging capacitor are interconnected to form the upper plate of the bridging capacitor DAC. The lower plates of each bridging capacitor receive the pixel voltages of their respective corresponding columns through their respective lower plate sampling switches, and the lower plates of each bridging capacitor receive the reference voltage through their respective capacitor control switches.

[0081] Between the upper plates of the bridging capacitor DAC for odd-numbered columns and the upper plates of the bridging capacitor DAC for even-numbered columns, they are connected through two groups of odd-even switches, and one of the groups of odd-even switches is connected to the comparator. The output terminal of the comparator is respectively connected to the control logic unit and the parallel-to-serial output circuit. The output signal of the comparator is the quantization result of its corresponding ADC module.

[0082] The control logic unit generates an odd control signal for controlling the lower plate sampling switches and capacitor control switches of each bridging capacitor in the bridging capacitor DAC for odd-numbered columns, and an even control signal for controlling the lower plate sampling switches and capacitor control switches of each bridging capacitor in the bridging capacitor DAC for even-numbered columns according to the output signal of the comparator. The parallel-to-serial output circuit receives the output signal of the comparator, performs parallel-to-serial conversion of the quantization results of multiple ADC modules, and outputs them digitally outside the chip. That is, the parallel-to-serial output circuit performs parallel-to-serial conversion of the quantization results of multiple ADC modules and outputs them digitally outside the chip.

[0083] For the two groups of odd-even switches, a preferred structure includes: a first group of odd-even switches and a second group of odd-even switches; the first group of odd-even switches includes: a first odd switch and a first even switch; the second group of odd-even switches includes: a second odd switch and a second even switch.

[0084] The first end of the first odd switch is connected to the upper plate of the bridging capacitor DAC for odd-numbered columns, the second end of the first odd switch is connected to the first end of the first even switch and receives the common-mode voltage. The second end of the first even switch is connected to the upper plate of the bridging capacitor DAC for even-numbered columns; the first end of the second even switch is connected to the upper plate of the bridging capacitor DAC for odd-numbered columns, and the second end of the second even switch is respectively connected to the first end of the second odd switch and the inverting input terminal of the comparator. The second end of the second odd switch is connected to the upper plate of the bridging capacitor DAC for even-numbered columns.

[0085] In the embodiment of the present invention, the non-inverting input terminal of the comparator receives the common-mode voltage. The comparator compares the signal output from the second end of the second even switch or the first end of the second odd switch with the common-mode voltage to obtain the output signal of the comparator, that is, to obtain the quantization result of the ADC where the comparator is located. And the control logic unit generates an odd control signal and an even control signal according to the output signal of the comparator.

[0086] In an embodiment of the present invention, the column-level readout circuit further includes: a timing control unit. Both groups of odd-even switches are controlled by the timing control signals of the timing control unit. The timings of the first odd switch and the second odd switch are the same, and the timings of the first even switch and the second even switch are the same.

[0087] When the timing control signals received by the first odd switch and the second odd switch are at a high level, both the first odd switch and the second odd switch are closed, both the first even switch and the second even switch are open, and the odd-column selector selects any odd column among the N columns according to column-level decoding.

[0088] Similarly, when the timing control signals received by the first even switch and the second even switch are at a high level, both the first even switch and the second even switch are closed, both the first odd switch and the second odd switch are open, and the even-column selector selects any even column among the N columns according to column-level decoding.

[0089] In any time period, if the odd columns use the bridge-capacitor DAC to sample the pixel voltages transmitted by any odd column among the N columns, the even columns use the bridge-capacitor DAC to quantize the pixel voltages that have been sampled by any even column among the N columns in this time period. When the odd columns use the bridge-capacitor DAC to sample the pixel voltages transmitted by any odd column among the N columns, both the first odd switch and the second odd switch are closed, both the first even switch and the second even switch are open, and the lower-plate sampling switches of each bridge capacitor in the bridge-capacitor DAC for odd columns are controlled by the odd control signal to be closed, and the capacitor control switches of each bridge capacitor in the bridge-capacitor DAC for odd columns are controlled by the odd control signal to be open.

[0090] In any time period, if the odd columns use the bridge-capacitor DAC to sample the pixel voltages transmitted by any odd column among the N columns, the even columns use the bridge-capacitor DAC to quantize the pixel voltages that have been sampled by any even column among the N columns in this time period. When the even columns use the bridge-capacitor DAC to quantize the pixel voltages that have been sampled by any even column among the N columns, both the first odd switch and the second odd switch are closed, both the first even switch and the second even switch are open, the lower-plate sampling switches of each bridge capacitor in the bridge-capacitor DAC for even columns are controlled by the even control signal to be open, and the capacitor control switches of each bridge capacitor in the bridge-capacitor DAC for even columns are controlled by the even control signal to be selectively closed to achieve successive approximation comparison quantization of the reference voltage.

[0091] It can also be known from the above structure that: the time for the odd columns to sample the pixel voltages transmitted by any odd column among the N columns using the bridge-capacitor DAC is equal to the time for the even columns to quantize the pixel voltages that have been sampled by any even column among the N columns using the bridge-capacitor DAC. In this way, the sampling time of the pixel voltages is extended, indirectly improving the quantization conversion efficiency, reducing the current demand from the pixel to the column, and reducing the power consumption.

[0092] To more clearly explain and illustrate the ADC module, refer to Figure 2 , which shows a schematic structural diagram of a preferred ADC module in an embodiment of the present invention. Figure 2 In [reference], N = 16 is taken as an example, that is, one ADC module is used for 16 columns in parallel. Figure 2 In [reference], CSO<3:1> represents the column-level decoding signal for odd columns, and CSE<3:1> represents the column-level decoding signal for even columns. These two signals are respectively used to gate the switches of the corresponding columns. The 8:1 MUX that receives the CSO<3:1> signal is the odd-column selector, and the 8:1 MUX that receives the CSE<3:1> signal is the even-column selector.

[0093] Through Figure 2 it can be known that the odd-column selector receives the pixel voltages V COL [1], V COL [3], …… V COL

[15] of the odd columns among the 16 columns; the even-column selector receives the pixel voltages V COL [2], V COL [4], …… V COL

[16] of the even columns among the 16 columns. And the pixel voltages V COL [1] to V COL

[16] of the 16 columns are all transmitted from the pixel to the column-level transmission circuit.

[0094] Figure 2 In [reference], V BOT and V TOP respectively represent two reference voltages output by the high M-bit resistor voltage buffer. Figure 2 In [reference], the capacitors C0 to C L in the upper part are the bridging capacitors for odd columns, and the capacitors C0 to C L in the lower part are the bridging capacitors for even columns. The group of O and E on the right represents the first group of odd-even switches, and the group of O and E on the left represents the second group of odd-even switches. O in the first group of odd-even switches represents the first odd switch, and E represents the first even switch; naturally, O in the second group of odd-even switches represents the second odd switch, and E represents the second even switch. V CM represents the common-mode voltage. The control logic represents the control logic unit. The control logic respectively generates an odd DAC control signal (i.e., odd control signal) and an even DAC control signal (i.e., even control signal).

[0095] Figure 2 In [reference], whether it is the bridging capacitor for odd columns or the bridging capacitor for even columns, the lower plates of the C1 to C L capacitors all have three-way switches, and the lower plate of the C0 capacitor has two-way switches. The switch connected to the output end of the 8:1 selector is the lower plate sampling switch of each bridging capacitor, and the one connected to VBOT and V TOP The switches respectively connected to V are the capacitance control switches for each bridging capacitor. Among the bridging capacitors in the odd columns, the capacitance control switch of the C0 capacitor is only connected to V TOP and among the bridging capacitors in the even columns, the capacitance control switch of the C0 capacitor is only connected to V BOT .

[0096] Assume that during a certain period, for the odd columns V COL [3] in the pixel array, the pixel voltages start to be sampled. Naturally, at the same time, for the even columns V COL [2] in the pixel array where the sampling is completed, the pixel voltages start to be quantized.

[0097] For the odd-column bridging capacitor DAC, at this time, the pixel voltages transmitted by V COL [3] are sampled. During this process, the first odd switch O and the second odd switch O are both closed, the lower plate sampling switch of the odd-column bridging capacitor DAC is closed, and the CSO<3:1> column decoding is gated through the odd-column selector 8:1MUX to select the pixel voltages of V COL [3] (the third column in the pixel array) and transmit them to the odd-column bridging capacitor DAC. At this time, the odd-column bridging DAC samples the pixel voltages of V COL [3].

[0098] While sampling the pixel voltages of the odd columns V COL [3], the even columns V COL [2] are quantized. Therefore, the sampling time is equal to the entire quantization time of V COL [2]. Compared with the ADC using a single capacitance DAC, the sampling time is greatly extended.

[0099] For quantizing the even columns V COL [2], it is required that the first even switch E and the second even switch E are both disconnected, the lower plate sampling switches of each bridging capacitor in the even-column bridging capacitor DAC are all disconnected, and the even-column selector 8:1MUX does not make a selection. Under the above conditions, the capacitance control switches of each bridging capacitor in the even-column bridging capacitor DAC are selectively closed under the control of the even control signal to implement the process of successive approximation comparison quantization of the reference voltage. This process includes:

[0100] Step S1: Switch all the capacitance control switches to connect to the V BOT to select the high M bit resistance voltage. Among them, the logic of the even control signal for the capacitance control switch connected to the V BOT is the same as that for the capacitance control switch connected to the V TOP ;

[0101] Step S2: Let QS At the end of sampling for any even-numbered column, the even-numbered column uses the charge stored on all the bridging capacitors in the bridging capacitor DAC, C Tot is the total capacitance of all the bridging capacitors in the bridging capacitor DAC for the even-numbered column, then there is the following formula:

[0102] Q S = C Tot × (V CM - V COL [n]

[0103] In the above formula, V CM represents the common-mode voltage, and V COL [n] represents the pixel voltage obtained by sampling any even-numbered column;

[0104] When all the lower plates of all the bridging capacitors in the bridging capacitor DAC for the even-numbered column are all selected and connected to the V BOT through their respective capacitance control switches, let the voltage of the upper plates of all the bridging capacitors in the bridging capacitor DAC for the even-numbered column at this time be V A , then there is the following formula:

[0105] Q S = C Tot × (V A - V BOT )

[0106] V A = V CM + V BOT - V COL [n]

[0107] At this time, there is: one end voltage of the comparator is V CM , and one end voltage is V A , then the voltage V ε for the comparator to make a comparison is:

[0108] V ε = V COL [n] - V BOT

[0109] Step S3: When making a judgment, first, the voltage value selected by the V BOT through the control switch is If the output signal of the comparator is 1, it means that the pixel voltage V COL [n] obtained by sampling any even-numbered column is higher than , and it is necessary to adjust the capacitance control switch connected to the V BOT to select a higher voltage value

[0110] If the output signal of the comparator is 0, it is necessary to adjust the capacitance control switch connected to the V BOT to select a lower reference voltage for successive approximation comparison of the reference voltage to select a voltage segment suitable for quantifying the pixel voltage;

[0111] Step S4: According to the result of the comparator, continuously switch the capacitance control switch connected to the V BOT to select the reference voltages generated by different high M bit resistor voltage buffers for comparison to select a V BOT suitable for the quantified pixel voltage;

[0112] Step S5: After the comparison of the reference voltage of the high Mbit is completed, select a V COL corresponding to the pixel voltage V BOT [n] sampled from any even column. Since the logic of the even control signal of the capacitance control switch connected to the V BOT is the same as that connected to the V TOP , at this time: the V COL corresponding to the pixel voltage V TOP [n] sampled from any even column is also selected;

[0113] After determining a V COL corresponding to the pixel voltage V BOT [n] sampled from any even column and a V TOP , perform successive approximation comparison quantization of the low L bit capacitance DAC. The method for performing successive approximation comparison quantization of the low L bit capacitance DAC includes:

[0114] First connect the highest bit capacitor to V TOP , then perform the corresponding comparison, and then according to the output result of the comparator, further determine whether the highest bit capacitance control switch is connected to V TOP or V BOT .

[0115] Step S6: Repeat Step S5 to perform step-by-step approximation quantization on the remaining bit capacitors of the low L bit capacitance DAC to obtain the corresponding code value.

[0116] For the timing of the odd-even switch sent by the timing control unit, reference can be made to Figure 3In the timing diagram shown, O represents the timing of the first and second odd switches, and E represents the timing of the first and second even switches. At this time, [1] to

[16] represent the odd or even columns selected by the CSO<3:1> and CSE<3:1> column decoding. The entire process from [1] to

[16] is the multi-column parallel readout process, because other ADC modules (such as ADCs with 17 to 32 columns, ADCs with 33 to 48 columns, etc.) also use the same method and timing.

[0117] Based on the above-mentioned column-level readout circuit, an embodiment of the present invention further provides a column-level successive approximation type analog-to-digital converter, and the column-level successive approximation type analog-to-digital converter includes any of the above-mentioned column-level readout circuits.

[0118] Based on the above-mentioned column-level readout circuit, an embodiment of the present invention further provides an infrared imager, which includes: a photocurrent detector and any of the above-mentioned column-level readout circuits.

[0119] Through the above embodiments, the column-level readout circuit of the present invention uses a resistor DAC to form a high M bit resistor voltage buffer, and the generated reference voltage is shared by multiple ADC modules. The low L bit uses a capacitor DAC with a bridge capacitor, and each ADC module only retains a low L bit capacitor DAC inside, which uses a bridge capacitor DAC. Compared with the pure capacitor array SARADC with the same precision, the column-level readout circuit proposed in the present invention reduces the capacitor array area, and due to the use of odd-even capacitor DAC, the sampling time of the pixel voltage is increased in disguise, which indirectly improves the efficiency of quantization conversion, reduces the current demand for pixels to columns, reduces power consumption, and has high practicality.

[0120] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0121] The embodiments of the present invention have been described above in conjunction with the accompanying drawings. However, the present invention is not limited to the above specific embodiments. The above specific embodiments are merely illustrative rather than restrictive. Under the inspiration of the present invention, those of ordinary skill in the art can also make many forms without departing from the spirit of the present invention and the scope protected by the claims. All of these are within the protection scope of the present invention.

Claims

1. A column-level readout circuit, characterized in that, The column-level readout circuit includes: a plurality of ADC modules, a timing control unit, a parallel-to-serial output circuit, and a high-M-bit resistor voltage buffer; Each ADC module is a SAR ADC shared by N columns; For the DAC of the analog-to-digital converter, if its overall is X bit, let X = M + L, where the high-M-bit part uses a resistor DAC to form the high-M-bit resistor voltage buffer, and the reference voltage generated by the high-M-bit resistor voltage buffer is shared by all the ADC modules, and the low-L-bit part uses a capacitor DAC with bridged capacitors; Each of the ADC modules includes: an odd-column selector, an even-column selector, a comparator, a control logic unit, and two sets of bridged-capacitor DACs; The two sets of bridged-capacitor DACs are respectively a bridged-capacitor DAC for odd columns and a bridged-capacitor DAC for even columns. When the bridged-capacitor DAC for odd columns samples the pixel voltages transmitted by the odd columns among the N columns, the bridged-capacitor DAC for even columns simultaneously quantizes the pixel voltages that have been sampled by the even columns among the N columns. Or, when the bridged-capacitor DAC for even columns samples the pixel voltages transmitted by the even columns among the N columns, the bridged-capacitor DAC for odd columns simultaneously quantizes the pixel voltages that have been sampled by the odd columns among the N columns; The odd-column selector selects any one of the odd columns among the N columns according to column-level decoding, and transmits the pixel voltages of the odd column to the bridged-capacitor DAC for odd columns; The even-column selector selects any one of the even columns among the N columns according to column-level decoding, and transmits the pixel voltages of the even column to the bridged-capacitor DAC for even columns; For the bridged-capacitor DAC for odd columns and the bridged-capacitor DAC for even columns, there are: The upper plates of each bridged capacitor are connected to each other to form the upper plate of the bridged-capacitor DAC. The lower plate of each bridged capacitor receives the pixel voltages of its corresponding column through its respective lower-plate sampling switch, and the lower plate of each bridged capacitor receives the reference voltage through its respective capacitor control switch; Between the upper plates of the bridged-capacitor DAC for odd columns and the upper plates of the bridged-capacitor DAC for even columns, they are connected through two sets of odd-even switches, and are connected to the comparator through one of the sets of odd-even switches; The output terminal of the comparator is respectively connected to the control logic unit and the parallel-to-serial output circuit, and the output signal of the comparator is the quantization result of its corresponding ADC module; The control logic unit generates an odd control signal for controlling each lower-plate sampling switch and capacitor control switch of the bridged-capacitor DAC for odd columns according to the output signal of the comparator, and generates an even control signal for controlling each lower-plate sampling switch and capacitor control switch of the bridged-capacitor DAC for even columns; The parallel-to-serial output circuit receives the output signal of the comparator, performs parallel-to-serial conversion on the quantization results of the multiple ADC modules, and digitally outputs them outside the chip.

2. The column-level readout circuit according to claim 1, wherein The two sets of odd-even switches include: a first set of odd-even switches and a second set of odd-even switches; The first set of odd-even switches includes: a first odd switch and a first even switch; The second set of odd-even switches includes: a second odd switch and a second even switch; A first end of the first odd switch is connected to an upper plate of the bridge capacitor DAC of the odd-numbered columns, and a second end of the first odd switch is connected to a first end of the first even switch and receives a common-mode voltage; A second end of the first even switch is connected to an upper plate of the bridge capacitor DAC of the even-numbered columns; A first end of the second even switch is connected to an upper plate of the bridge capacitor DAC of the odd-numbered columns, and a second end of the second even switch is respectively connected to a first end of the second odd switch and an inverting end of the comparator; A second end of the second odd switch is connected to an upper plate of the bridge capacitor DAC of the even-numbered columns.

3. The column-level readout circuit according to claim 2, wherein A non-inverting end of the comparator receives the common-mode voltage, and the comparator compares a signal output from a second end of the second even switch or a first end of the second odd switch with the common-mode voltage to obtain an output signal of the comparator; The control logic unit generates the odd control signal and the even control signal according to the output signal of the comparator.

4. The column-level readout circuit according to claim 2, wherein In any time period, if the bridge capacitor DAC of the odd-numbered columns samples pixel voltages transmitted in any odd-numbered column among N columns, then the bridge capacitor DAC of the even-numbered columns quantizes the pixel voltages that have been sampled in any even-numbered column among N columns in this time period; When the bridge capacitor DAC of the odd-numbered columns samples pixel voltages transmitted in any odd-numbered column among N columns, the first odd switch and the second odd switch are both closed, the first even switch and the second even switch are both open, a lower plate sampling switch of each capacitor in the bridge capacitor DAC of the odd-numbered columns is controlled by the odd control signal to be closed, and a capacitor control switch of each capacitor in the bridge capacitor DAC of the odd-numbered columns is controlled by the odd control signal to be open.

5. The column-level readout circuit according to claim 4, characterized in that, In any time period, if the bridge capacitor DAC of the odd-numbered columns samples pixel voltages transmitted in any odd-numbered column among N columns, then the bridge capacitor DAC of the even-numbered columns quantizes the pixel voltages that have been sampled in any even-numbered column among N columns in this time period; When the bridge capacitor DAC of the even-numbered columns quantizes the pixel voltages that have been sampled in any even-numbered column among N columns, the first odd switch and the second odd switch are both closed, the first even switch and the second even switch are both open, a lower plate sampling switch of each capacitor in the bridge capacitor DAC of the even-numbered columns is controlled by the even control signal to be open, and a capacitor control switch of each capacitor in the bridge capacitor DAC of the even-numbered columns is controlled by the even control signal to be selectively closed to realize successive approximation comparison quantization of the reference voltage.

6. The column-level readout circuit according to claim 5, wherein The reference voltage includes: V BOT and V TOP ; The capacitive control switches of each capacitor in the even-numbered column bridge capacitor DAC are selectively closed under the control of the even control signal, and the voltage of the V TOP is higher than the voltage of the V BOT by Then it is connected to the V TOP The high M-bit resistance voltage range connected to the capacitive control switch is Connected to the V BOT The high M-bit resistance voltage range connected to the capacitive control switch is The process of realizing successive approximation comparison and quantization of the reference voltage includes: Step S1: Switch all the capacitance control switches to connect to the V BOT , and perform the selection of the high M bit resistance voltage. Among them, the logic of the even control signal of the capacitance control switch connected to the V BOT is the same as that of the capacitance control switch connected to the V TOP . Step S2: Let Q S be, at the end of sampling of any even-numbered column, the charge stored on all bridging capacitors in the bridging-capacitor DAC for the even-numbered column, and C Tot be the total capacitance of all bridging capacitors in the bridging-capacitor DAC for the even-numbered column. Then, there is the following formula: Q S = C Tot × (V CM - V COL [n]) In the above formula, V CM represents the common-mode voltage, and V COL [n] represents the pixel voltage obtained by sampling any even-numbered column; When the lower plates of all the bridging capacitors in the bridging capacitor DAC for the even-numbered columns are all selected and connected to the V through their respective capacitance control switches BOT At this time, assume that the voltage of the upper plates of all the bridging capacitors in the bridging capacitor DAC for the even-numbered columns is V A , then there is the following formula: Q S = C Tot × (V A - V BOT ) V A = V CM + V BOT - V COL [n] At this time, there is: the voltage at one end of the comparator is V CM , the voltage at one end is V A , then the voltage V ε for the comparator to compare is: V ε = V COL [n] - V BOT Step S3: When making a judgment, first, the V BOT voltage value selected by the control switch is If the output signal of the comparator is 1, it means that the pixel voltage V COL [n] sampled from any even column is higher than and it is necessary to adjust the capacitor control switch connected to the V BOT to select a higher voltage value If the output signal of the comparator is 0, it is necessary to adjust the capacitance control switch connected to the V BOT to select a lower reference voltage for successive approximation comparison of the reference voltage to select a voltage segment suitable for quantifying the pixel voltage; Step S4: According to the result of the comparator, continuously switch the capacitive control switch connecting the V BOT to select the reference voltages generated by different high M-bit resistor voltage buffers for comparison, so as to select the V BOT suitable for the pixel voltage to be quantized; Step S5: After the comparison of the reference voltage of the high Mbit is completed, a pixel voltage V COL [n] corresponding to any even column sampling is selected BOT . Since the logic of the even control signal of the capacitance control switch connected to the V BOT is the same as that connected to the V TOP , at this time: the pixel voltage V COL [n] corresponding to any even column sampling is also selected TOP ; After determining a pixel voltage V COL [n] corresponding to any even-numbered column sampling, a V BOT and a V TOP are obtained. Then, successive approximation comparison quantization of the low L-bit capacitive DAC is performed. The highest-bit capacitor is connected to V TOP , and corresponding comparison is carried out. According to the result of the comparator, it is further determined whether the control switch of the highest-bit capacitor is connected to V TOP or V BOT ; Step S6: Repeat step S5 to perform successive approximation quantization on the remaining bit capacitors of the low-L bit capacitor DAC, and then obtain corresponding code values.

7. The column-level readout circuit according to claim 2, wherein The column-level readout circuit further includes: a timing control unit; Both groups of the odd-even switches are controlled by the timing control signals of the timing control unit. The timings of the first odd switch and the second odd switch are the same, and the timings of the first even switch and the second even switch are the same; When the timing control signals received by the first odd switch and the second odd switch are at high level, both the first odd switch and the second odd switch are closed, both the first even switch and the second even switch are open, and the odd column selector selects any odd column among the N columns according to column-level decoding; When the timing control signals received by the first even switch and the second even switch are at high level, both the first even switch and the second even switch are closed, both the first odd switch and the second odd switch are open, and the even column selector selects any even column among the N columns according to column-level decoding.

8. The column-level readout circuit according to claim 1, characterized in that, The time for the odd columns to sample the pixel voltages transmitted by any odd column among the N columns using the bridge capacitor DAC is equal to the time for the even columns to quantize the pixel voltages that have been sampled by the bridge capacitor DAC for any even column among the N columns.

9. A column-level successive approximation analog-to-digital converter, characterized in that, The column-level successive approximation analog-to-digital converter includes the column-level readout circuit according to any one of claims 1-8.

10. An infrared imager, characterized in that, The infrared imager includes: a photocurrent detector and the column-level readout circuit according to any one of claims 1-8.

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