Three-dimensional memory and methods of making the same, memory systems

Abstract

Embodiments of the present application provide a three-dimensional memory and a manufacturing method thereof, and a memory system. The three-dimensional memory includes: a semiconductor layer; a stack structure located at one side of the semiconductor layer; a channel structure penetrating through the stack structure in a direction perpendicular to the semiconductor layer, and in the same plane perpendicular to the semiconductor layer, a cross-sectional dimension of the channel structure at a surface of the stack structure away from the semiconductor layer is greater than a cross-sectional dimension of the channel structure at a surface of the stack structure close to the semiconductor layer; and a gate line slit structure penetrating through the stack structure in a direction perpendicular to the semiconductor layer and extending in a direction parallel to the semiconductor layer, in a plane perpendicular to the extending direction, a cross-sectional dimension of at least part of the gate line slit structure at the surface of the stack structure away from the semiconductor layer is less than a cross-sectional dimension of the gate line slit structure at the surface of the stack structure close to the semiconductor layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and more particularly, to a three-dimensional memory and a preparation method thereof, and a memory system. BACKGROUND

[0002] In order to improve the unit storage density of the three-dimensional memory, the number of stacked layers in the three-dimensional memory (for example, 3D NAND memory) is gradually increased. However, the increase in the number of stacked layers brings challenges to the formation of the channel structure and the gate line gap structure by using a deep hole etching process, and affects the performance of the three-dimensional memory. SUMMARY

[0003] The present application provides a three-dimensional memory and a preparation method thereof, and a memory system, which can at least partially solve the above problems in the related art or other problems in the field.

[0004] Some embodiments of the present application provide a three-dimensional memory, comprising: a semiconductor layer; a stacked structure located at one side of the semiconductor layer; a channel structure penetrating through the stacked structure in a direction perpendicular to the semiconductor layer, and in the same plane perpendicular to the semiconductor layer, a cross-sectional size of the channel structure at a surface of the semiconductor layer away from the stacked structure is greater than a cross-sectional size of the channel structure at a surface of the stacked structure close to the semiconductor layer; and a gate line gap structure penetrating through the stacked structure in a direction perpendicular to the semiconductor layer and extending in a direction parallel to the semiconductor layer, a cross-sectional size of at least part of the gate line gap structure at the surface of the semiconductor layer away from the stacked structure is less than a cross-sectional size of the gate line gap structure at the surface of the semiconductor layer close to the stacked structure.

[0005] In some embodiments, along a first direction, a cross-sectional size of at least part of the gate line gap structure in the first direction gradually decreases, the first direction being a direction perpendicular to the semiconductor layer and away from the semiconductor layer.

[0006] In some embodiments, the gate line gap structure comprises a first part and a second part in contact with each other, the second part being located at a side of the first part away from the semiconductor layer, the first part penetrating through the stacked structure, wherein along the first direction, a cross-sectional size of the first part in the first direction gradually decreases, and a cross-sectional size of the second part in the first direction gradually increases.

[0007] In some embodiments, at the surface of the stacked structure close to the semiconductor layer, a distance between the channel structure and the gate line gap structure is 50 nm to 150 nm.

[0008] In some embodiments, a first distance is provided between the channel structure and the gate slot structure at the surface of the stacked structure away from the semiconductor layer, and a second distance is provided between the channel structure and the gate slot structure at the surface of the stacked structure close to the semiconductor layer, wherein the difference between the first distance and the second distance is less than 100 nm.

[0009] In some embodiments, the cross-sectional dimensions of the channel structure gradually increase along the first direction.

[0010] In some embodiments, the channel structure includes at least two sub-channel structures, and the cross-sectional dimensions of each sub-channel structure gradually increase along the first direction.

[0011] In some embodiments, the three-dimensional memory further includes: a selection stack structure located on the side of the stack structure away from the semiconductor layer; and a selection channel structure extending through the selection stack structure, including an insulating layer and a selection channel layer from the outside to the inside, wherein the insulating layer and the selection channel layer are in contact, and the selection channel layer is connected to the channel structure.

[0012] In some embodiments, the three-dimensional memory further includes: a stop layer located on the side of the select stack structure away from the semiconductor layer, wherein the select channel structure extends through the stop layer; and conductive contacts located on the side of the stop layer away from the select stack structure and in contact with the select channel structure and the stop layer.

[0013] In some embodiments, the gate slot structure extends through the stack structure, the select stack structure, and the stop layer. The three-dimensional memory also includes an isolation portion extending through the select stack structure and the stop layer, and located on both sides of the portion of the gate slot structure that extends through the select stack structure and the stop layer.

[0014] In some embodiments, the three-dimensional memory further includes: an interconnect layer located on the side of the conductive contacts away from the semiconductor layer; and a peripheral circuit semiconductor structure connected to the interconnect layer on the side away from the semiconductor layer.

[0015] In some embodiments, the grid gap structure includes an insulating material layer and a conductive material layer from the outside in.

[0016] Other embodiments of this application provide a memory system comprising: at least one three-dimensional memory as described in the embodiments above; and a memory controller coupled to the three-dimensional memory for controlling the three-dimensional memory.

[0017] Some embodiments of this application provide a method for fabricating a three-dimensional memory, the method comprising: forming a channel structure through the stacked structure from a first side of the stacked structure; and forming a gate wire slot through the stacked structure from a second side of the stacked structure opposite to the first side.

[0018] In some embodiments, after forming the channel structure through the stacked structure, the fabrication method further includes: forming a first insulating layer on a first side; forming a first opening through the first insulating layer from the side of the first insulating layer away from the stacked structure; and filling the first opening with a first material to form a first stop layer, wherein the first material and the material of the stacked structure have different etching selectivity ratios.

[0019] In some embodiments, prior to forming the first insulating layer, the fabrication method further includes: forming a selective stack structure on a first side; and forming a selective channel structure through the selective stack structure, wherein the selective channel structure includes an insulating layer and a selective channel layer from the outside to the inside, the insulating layer and the selective channel layer being in contact, and the selective channel layer being connected to the channel structure.

[0020] In some embodiments, before forming the selection channel structure through the selection stack structure, the fabrication method further includes: forming a second stop layer on the side of the selection stack structure away from the stack structure; and forming a conductive contact through the first insulating layer to the selection channel structure and the second stop layer on the side of the second stop layer away from the selection stack structure.

[0021] In some implementations, the conductive contacts and the first stop layer are formed in the same process.

[0022] In some embodiments, the fabrication method further includes: forming an initial isolation portion that penetrates the second stop layer and the selected stack structure; wherein forming a gate wire slot through the stack structure includes: forming a gate wire slot through the initial isolation portion to divide the initial isolation portion into isolation portions located on both sides of the gate wire slot.

[0023] In some embodiments, the stacked structure includes a plurality of gate dielectric layers and a plurality of gate sacrificial layers stacked alternately. After forming the gate line gap, the fabrication method further includes: removing the first material in the first opening through the gate line gap and replacing the plurality of gate sacrificial layers with a plurality of gate layers; and sequentially forming an insulating material layer and a conductive material layer in the gate line gap.

[0024] According to at least one embodiment of this application, the three-dimensional memory and its fabrication method, and memory system provided by this application, by making the cross-sectional dimension of at least a portion of the gate line slot structure in the stacked structure away from the semiconductor layer surface smaller than its cross-sectional dimension in the stacked structure near the semiconductor layer surface, can reduce the distance between the channel structure and the gate line slot structure near the semiconductor layer. This helps to reduce the bending risk of the gate layer near the semiconductor layer in the stacked structure and ensures the structural and electrical performance of the gate layer. Furthermore, while ensuring the performance of the gate layer near the semiconductor layer in the stacked structure, the overall distance between the channel structure and the gate line slot structure can be reduced, thereby making the three-dimensional memory structure more compact and improving the unit storage density of the three-dimensional memory. Attached Figure Description

[0025] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0026] Figure 1 This is a cross-sectional schematic diagram of a three-dimensional memory according to an exemplary embodiment of this application;

[0027] Figure 2 This is a cross-sectional schematic diagram of a three-dimensional memory according to another exemplary embodiment of this application;

[0028] Figure 3 This is a flowchart of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application;

[0029] Figures 4A to 4K This is a cross-sectional schematic diagram of the fabrication process of a three-dimensional memory according to an exemplary embodiment of this application.

[0030] Figure 5 This is a system block diagram of a memory system according to an exemplary embodiment of this application; and

[0031] Figure 6A and Figure 6B This is a schematic diagram of a memory system according to an exemplary embodiment of this application. Detailed Implementation

[0032] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first part discussed herein may also be referred to as the second part, and the first subchannel structure may also be referred to as the second substructure, and vice versa.

[0034] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0035] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0036] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0037] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0038] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0039] This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0040] Figure 1 This is a schematic cross-sectional view of a three-dimensional memory 100 according to an exemplary embodiment of this application. For example, Figure 1 The illustrated three-dimensional memory 100 may be a part of a complete three-dimensional memory (not shown). It should be noted that, in the following figures, the x-axis, y-axis, and z-axis illustrate the spatial relationships of the components. For example, the semiconductor layer 112 extends laterally in the x and y directions, the positive z-direction is perpendicular to and away from the semiconductor layer 112, and the negative z-direction is perpendicular to and close to the semiconductor layer 112. The same concepts will be used throughout this application to describe spatial relationships.

[0041] like Figure 1 As shown, the three-dimensional memory 100 includes a semiconductor layer 112, a stacked structure 120, a channel structure 130, and a gate gap structure 140. The stacked structure 120 is located on one side of the semiconductor layer 112. For example, the stacked structure 120 may include a plurality of first gate dielectric layers (e.g., first gate dielectric layer 121) and a plurality of gate layers (e.g., gate layer 122) alternately stacked in the z-direction. The channel structure 130 extends through the stacked structure 120. In the same plane perpendicular to the semiconductor layer 112 (i.e., the yz plane), the cross-sectional dimension (e.g., diameter d1) of the channel structure 130 at the surface of the stacked structure 120 away from the semiconductor layer 112 is larger than the cross-sectional dimension (e.g., diameter d2') of the channel structure 130 at the surface of the stacked structure 120 close to the semiconductor layer 112.

[0042] The gate slot structure 140 extends through the stacked structure 120 in the z-direction and, for example, in the x-direction. For example, the gate slot structure 140 is a trench structure extending in the x-direction. In the same plane perpendicular to the x-direction (i.e., the yz plane), the cross-sectional dimension (e.g., trench width w1) of the gate slot structure 140 at the surface of the stacked structure 120 away from the semiconductor layer 112 is larger than the cross-sectional dimension (e.g., trench width w2) of the gate slot structure 140 in the z-direction at the surface of the stacked structure 120 near the semiconductor layer 112.

[0043] In this embodiment, the inventors discovered that as the number of stacked layers in the stacked structure 120 gradually increases, the ratio (e.g., d2' / d1) between the cross-sectional dimension (e.g., diameter d2') of the channel structure 130 near the surface of the semiconductor layer 112 and the cross-sectional dimension (e.g., diameter d1) of the channel structure 130 away from the surface of the semiconductor layer 112 gradually decreases. That is, the difference (e.g., d1-d2') between the cross-sectional dimension (e.g., diameter d1) of the channel structure 130 away from the surface of the semiconductor layer 112 and the cross-sectional dimension (e.g., diameter d2') of the channel structure 130 near the surface of the semiconductor layer 112 gradually increases. In other words, the top dimension (e.g., diameter d1) of the channel structure 130 is larger than the bottom dimension (e.g., diameter d2'). Similarly, the top dimension (e.g., slot width w1) of the gate slot structure 140 is larger than the bottom dimension (e.g., slot width w2), resulting in an increased distance between the channel structure 130 and the gate slot structure 140 near the surface of the semiconductor layer 112 in the stacked structure 120. This also makes the gate layer (e.g., gate layer 122) near the semiconductor layer 112 larger in the y-direction, increasing the risk of bending of the gate layer (e.g., gate layer 122) near the semiconductor layer 112. Furthermore, to reduce the bending risk of the gate layer (e.g., gate layer 122) near the semiconductor layer 112, it is necessary to increase the thickness of the gate layer in the stacked structure, for example. However, under the design requirements of the total thickness of the stacked structure, the number of gate layers and the first gate dielectric layer in the stacked structure is reduced, which is not conducive to improving the storage density of the three-dimensional memory.

[0044] Figure 2 This is a cross-sectional schematic diagram of a three-dimensional memory 200 according to another exemplary embodiment of this application. For example, Figure 2 The three-dimensional memory 200 shown may be a part of a complete three-dimensional memory (not shown). The various structures in the three-dimensional memory 200 provided in this embodiment will be described in detail below.

[0045] like Figure 2 As shown, the three-dimensional memory 200 includes a semiconductor layer 212, a stacked structure 220, a channel structure 230, and a gate line gap structure 240.

[0046] The semiconductor layer 212 may extend laterally in both the x and y directions. In some embodiments, the material of the semiconductor layer 212 may include at least one of silicon (e.g., monocrystalline silicon c-Si, polycrystalline silicon p-Si, amorphous silicon α-Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), or any other suitable semiconductor material. For example, the material of the semiconductor layer 212 may be polycrystalline silicon.

[0047] The stacked structure 220 is located on one side of the semiconductor layer 212. In some embodiments, the stacked structure 220 may include a plurality of alternately stacked first gate dielectric layers (e.g., first gate dielectric layer 221) and a plurality of gate layers (e.g., gate layer 222). For example, each of the plurality of first gate dielectric layers and each of the plurality of gate layers may extend laterally in the x and y directions. The material of the first gate dielectric layer may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any other suitable dielectric material, and the material of the gate layer may include, but is not limited to, metals (e.g., tungsten, cobalt, copper, aluminum), polysilicon, silicides, or any other suitable conductive material. For example, the material of the first gate dielectric layer may be silicon oxide, and the material of the gate layer may be tungsten. Generally, the more stacked first gate dielectric layers and gate layers there are, the higher the integration of the memory cell, i.e., the greater the unit storage density.

[0048] The channel structure 230 extends through the stacked structure 220 in the z-direction and, for example, into the semiconductor layer 212. For example, the channel structure 230 may be a columnar structure. In the same plane perpendicular to the semiconductor layer 212 (i.e., the yz plane), the cross-sectional dimension (e.g., diameter d1) of the channel structure 230 at the surface of the stacked structure 220 away from the semiconductor layer 212 is larger than the cross-sectional dimension (e.g., diameter d2') of the channel structure 230 at the surface of the stacked structure 220 near the semiconductor layer 212. In some examples, the channel structure 230 may include two sub-channel structures 231 and 232 stacked in the z-direction. Each sub-channel structure 231 and 232 may be a columnar structure. Along the positive z-direction, the cross-sectional dimension of the sub-channel structure 231 gradually increases in the z-direction; for example, along the positive z-direction, the diameter of the sub-channel structure 231 increases from d2' to d1'. Similarly, along the positive z-direction, the cross-sectional dimension of the sub-channel structure 232 gradually increases in the z-direction; for example, along the positive z-direction, the diameter of the sub-channel structure 232 increases from d2 to d1. In other examples, the channel structure 230 does not include the sub-channel structure. For example, along the positive z-direction, the cross-sectional dimension (e.g., diameter) of the channel structure gradually increases in the z-direction (not shown).

[0049] It should be noted that the channel structure or sub-channel structure has a cross-sectional dimension that gradually increases along the positive z-direction, and outliers in the cross-sectional dimension caused by protrusions or depressions on the outer surface of the channel structure or sub-channel structure should be excluded. Furthermore, the channel structure may include a greater number (e.g., more than 2) of sub-channel structures, each connected to each other in the z-direction, and each sub-channel structure having a gradually increasing cross-sectional dimension in the z-direction.

[0050] The gate slot structure 240 passes through (e.g., through) the stacked structure 220 in the z-direction and, for example, through the semiconductor layer 212. For example, the gate slot structure 240 may be a trench structure extending along the x-direction. In some examples, the gate slot structure 240 may include a first portion 241 and a second portion 242 that are in contact with each other, wherein the second portion 242 will be described in detail below. In this example, the first portion 241 of the gate slot structure 240 may pass through (e.g., through) the stacked structure 220, and in the same plane perpendicular to the x-direction (i.e., the yz plane), the cross-sectional dimension (e.g., trench width w1) of the first portion 241 on the stacked structure 220 away from the surface of the semiconductor layer 212 is smaller than the cross-sectional dimension (e.g., trench width w2) of the first portion 241 on the stacked structure 220 near the surface of the semiconductor layer 212. In other examples, the gate slot structure does not include a second portion (not shown). The gate slot structure traverses the stacked structure in the z-direction, for example, residing in the first gate dielectric layer of the stacked structure 220 furthest from the semiconductor layer 212, penetrating the stacked structure 220, or extending into other structures on the side of the stacked structure 220 furthest from the semiconductor layer 212. In this example, in the same plane perpendicular to the x-direction (i.e., the yz plane), the cross-sectional dimension of the gate slot structure in the stacked structure 220 furthest from the surface of the semiconductor layer 212 is smaller than its cross-sectional dimension in the stacked structure 220 near the surface of the semiconductor layer 212.

[0051] According to the three-dimensional memory provided by this embodiment, since the cross-sectional dimension of the channel structure in the stacked structure away from the semiconductor layer surface is larger than its cross-sectional dimension in the stacked structure near the semiconductor layer surface, by making the cross-sectional dimension of at least a portion of the gate slot structure in the stacked structure away from the semiconductor layer surface smaller than its cross-sectional dimension in the stacked structure near the semiconductor layer surface, the distance between the channel structure and the gate slot structure near the semiconductor layer can be reduced. This helps to reduce the bending risk of the gate layer near the semiconductor layer in the stacked structure and ensures the structural and electrical performance of the gate layer. Furthermore, while ensuring the performance of the gate layer near the semiconductor layer in the stacked structure, the overall distance between the channel structure and the gate slot structure can be reduced, thereby making the structure of the three-dimensional memory more compact and improving the unit storage density of the three-dimensional memory.

[0052] In some implementations, such as Figure 2As shown, when the gate slot structure 240 includes a first portion 241 and a second portion 242, the cross-sectional dimension of the first portion 241 gradually decreases along the positive z-direction. For example, the slot width of the first portion 241 decreases from w2 to w1 along the positive z-direction. In other embodiments, when the gate slot structure does not include a second portion (not shown), the cross-sectional dimension of the gate slot structure gradually decreases along the positive z-direction. By making at least a portion of the gate slot structure have a gradually decreasing cross-sectional dimension along the positive z-direction, for example, in conjunction with a channel structure or sub-channel structure having a gradually increasing cross-sectional dimension along the positive z-direction, the distance between the channel structure and the gate slot structure in the z-direction is made more uniform, which helps to reduce the bending risk of the individual gate layers arranged in the z-direction in the stacked structure.

[0053] In some implementations, reference continues. Figure 2 In the stacked structure 220, a first distance L1 is maintained between the channel structure 230 and the gate line slot structure 240 at the surface of the stacked structure 220 away from the semiconductor layer 212, and a second distance L2 is maintained between the channel structure 230 and the gate line slot structure 240 at the surface of the stacked structure 220 near the semiconductor layer 212. The difference between the first distance L1 and the second distance L2 is less than 100 nm. In this case, the distance between the channel structure 230 and the gate line slot structure 240 is relatively uniform both near and away from the semiconductor layer 212, which helps to reduce the bending risk of the gate layer near the semiconductor layer in the stacked structure. In other embodiments, the second distance L2 between the channel structure 230 and the gate line slot structure 240 is 50 nm to 150 nm. In this case, the bending risk of the gate layer near the semiconductor layer in the stacked structure is smaller, which helps to ensure the structural and electrical performance of the gate layer.

[0054] In some implementations, reference continues. Figure 2 The three-dimensional memory 200 may further include a select stack structure 250 and a select channel structure 254. The select stack structure 250 may be located on the side of the stack structure 220 away from the semiconductor layer 212. Exemplarily, the select stack structure 250 covers the surface of the stack structure 220 away from the semiconductor layer 212 and the end face of the channel structure 230. The select stack structure 250 may include a second gate dielectric layer 251 and a select gate layer 252. It should be noted that the number of pairs of second gate dielectric layers and select gate layers is not limited. Figure 2As shown in the diagram, the number of pairs of second gate dielectric layers and select gate layers can be three to five. The material of the second gate dielectric layer can be, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any other suitable dielectric material, and the material of the select gate layer can be, but is not limited to, metals (e.g., tungsten, cobalt, copper, aluminum), polysilicon, silicides, or any other suitable conductive material. For example, the material of the second gate dielectric layer can be silicon oxide, and the material of the select gate layer can be polysilicon (e.g., doped polysilicon).

[0055] In some embodiments, the selected channel structure 254 may extend through the selected stack structure 250. For example, the selected channel structure 254 may be a columnar structure. The selected channel structure 254 may include an insulating layer 255 and a selected channel layer 256 disposed from the outside to the inside, for example, the selected channel layer 256 may be a columnar structure. The insulating layer 255 and the selected channel layer 256 are in contact, for example, the insulating layer 255 surrounds the outside of the selected channel layer 256. The material of the insulating layer 255 may include, but is not limited to, silicon oxide, silicon nitride, and silicon oxide, or any suitable insulating material. For example, the material of the insulating layer 255 may be silicon oxide. The material of the selected channel layer 256 may include, but is not limited to, amorphous silicon, polycrystalline silicon, or monocrystalline silicon, or any suitable semiconductor material. For example, the material of the selected channel layer 256 may be polycrystalline silicon. In some embodiments, unlike the selected channel structure 254, the channel structure 230 may include a functional layer 233 and a channel layer 234 disposed sequentially from the outside to the inside. Functional layer 233 may include a barrier layer, a charge trapping layer, and a tunneling layer disposed sequentially from the outside in. The materials of the barrier layer, charge trapping layer, and tunneling layer may include, but are not limited to, silicon oxide, silicon nitride, and silicon oxide, respectively. Channel layer 234 is located inside functional layer 233 (e.g., tunneling layer). The material of the channel layer may include, but is not limited to, amorphous silicon, polycrystalline silicon, or monocrystalline silicon, or any suitable semiconductor material. For example, the material of channel layer 234 may be polycrystalline silicon. For example, channel layer 234 extends into semiconductor layer 212, and electrical connection is achieved through direct contact between channel layer 234 and semiconductor layer 212. Furthermore, channel layer 256 may be electrically connected to its corresponding channel structure (e.g., channel layer 234 in channel structure 230). For example, channel layer 256 may be electrically connected to a channel layer in its corresponding channel structure through a channel plug. Since the select transistor corresponding to the select channel structure 254 does not need to use the charge trapping layer to capture charge to realize data storage, by making the insulating layer 255 and the select channel layer 256 in the select channel structure 254 in direct contact, even if the select channel structure 254 does not include the charge trapping layer, the change in the threshold voltage of the select transistor caused by the charge trapping layer can be addressed.

[0056] In some implementations, reference continues. Figure 2As mentioned above, the gate gap structure 240 may include a second portion 242. The first portion 241 and the second portion 242 are in contact with each other in the z-direction. The second portion 242 is located on the side of the first portion 241 away from the semiconductor layer 212. For example, both the first portion 241 and the second portion 242 can be trench structures extending along the x-direction. Along the positive z-direction, the cross-sectional size of the second portion 242 gradually increases in the z-direction. For example, along the positive z-direction, the trench width of the second portion 242 increases from w3 to w4. In this embodiment, since the cross-sectional size changes of the first portion 241 and the second portion 242 in the z-direction have opposite trends, the first portion 241 and the second portion 242 can be etched and formed along the positive z-direction and the negative z-direction, respectively. In this way, the intermediate structure corresponding to the second portion 242 can serve as a stop layer for etching the first portion 241, thereby helping to ensure the etching process and the morphology of the first portion 241 during its formation.

[0057] In some implementations, reference continues. Figure 2 The gate slot structure 240 may include an insulating material layer 243 and a conductive material layer 244 disposed from the outside in. For example, the central portions of the first portion 241 and the second portion 242 are both conductive material layers 244, with the insulating material layer 243 surrounding the outer periphery of the conductive material layer 244. The material of the insulating material layer 243 may include, but is not limited to, silicon oxide, silicon nitride, and silicon oxide, or any suitable insulating material. The material of the conductive material layer 244 may include, but is not limited to, metals (e.g., tungsten, cobalt, copper, aluminum), polysilicon, silicides, or any other suitable conductive material. For example, the material of the insulating material layer 243 may be silicon oxide. The material of the conductive material layer 244 may be polysilicon. When the gate slot structure 240 includes two materials (e.g., silicon oxide and polysilicon), it helps to adjust the structural stress of the gate slot structure 240, thereby achieving stress balance in the three-dimensional memory 200. In other embodiments, the gate slot structure may include only an insulating material (e.g., silicon oxide), which is not limited in this application.

[0058] In some implementations, reference continues. Figure 2The three-dimensional memory 200 may further include a stop layer 253 and conductive contacts 262. The stop layer 253 is located on the side of the select stack structure 250 away from the semiconductor layer 212, and a select channel structure 254 extends through the stop layer 253. For example, the end face of the select channel structure 254 away from the semiconductor layer 212 may be flush with the surface of the stop layer 253 away from the semiconductor layer 212. The conductive contacts 262 may be located on the side of the stop layer 253 away from the select stack structure 250 and contact the select channel structure 254 and the stop layer 253. For example, the end face of the conductive contact 262 contacts the end face of the select channel structure 254, and the end face size of the conductive contact 262 may be larger than the end face size of the select channel structure 254 (not shown), so that the end face of the conductive contact 262 also contacts the stop layer 253. Furthermore, in some examples, the 3D memory 200 may also include a first insulating layer 261, which may be located on the side of the selected stack structure 250 away from the semiconductor layer 212. For example, the first insulating layer 261 may cover the surface of the selected stack structure 250 away from the semiconductor layer 212 and the end face of the selected channel structure 254 away from the semiconductor layer 212. Exemplarily, the material of the stop layer 253 and the material of the first insulating layer 261 may have different etching selectivity ratios. For example, the material of the stop layer 253 may include, but is not limited to, silicon nitride, and the material of the first insulating layer 261 may include, but is not limited to, silicon oxide. In this embodiment, the conductive contact 262 may be formed by etching the first insulating layer 261 along the negative z-direction. The stop layer 253 facilitates the etching process during the formation of the conductive contact 262 and also reduces the risk of damage to the selected channel structure 254.

[0059] In some implementations, reference continues. Figure 2 The three-dimensional memory 200 may further include an isolation portion 257. The isolation portion 257 may extend through the selective stack structure 250 and the stop layer 253, and the isolation portion 257 may be located on both sides of the portion of the gate slot structure 240 that extends through the selective stack structure 250 and the stop layer 253. For example, the isolation portion 257 may include a first sub-isolation portion 2571 and a second sub-isolation portion 2572. The first sub-isolation portion 2571 and the second sub-isolation portion 2572 may be located on both sides of the gate slot structure 240 in the y-direction. For example, the isolation portion 257 may extend in the x-direction, and its extension length may be approximately the same as the extension length of the gate slot structure 240 in the x-direction. For example, the material of the isolation portion 257 may have a different etching selectivity than the material of the stop layer 253. This is used to isolate the etching material (e.g., etching solution) from the stop layer 253 during the "gate replacement" process using the gate gap when the interior of the gate gap structure 240 is not filled with material, thereby reducing the risk of the stop layer 253 being replaced or even preventing the stop layer from being damaged.

[0060] It should be noted that in some embodiments, the three-dimensional memory 200 may not include a selected stacking structure and a selected channel structure. That is, the first insulating layer 261 in the three-dimensional memory 200 may cover the surface of the stacking structure 220 away from the semiconductor layer 212 and the end face of the channel structure 230 away from the semiconductor layer 212. This is not a limitation.

[0061] In some embodiments, the three-dimensional memory 200 may further include an interconnect layer 263 and a peripheral circuit semiconductor structure 270. The interconnect layer 263 may be located on the side of the conductive contacts 262 away from the semiconductor layer 212. Exemplarily, the interconnect layer 263 may include a plurality of interconnect structures (e.g., interconnect structure 265) extending laterally in the x and y directions and a plurality of via structures (e.g., via structure 264) extending in the z direction. The materials of the interconnect structures and via structures may include, but are not limited to, metals (e.g., tungsten, cobalt, copper, aluminum), polysilicon, silicides, or any other suitable conductive material. The peripheral circuit semiconductor structure 270 may be connected to the interconnect layer 263 on the side away from the semiconductor layer 212. For example, the peripheral circuit semiconductor structure 270 may include peripheral circuitry for controlling the memory cells corresponding to the channel structure to implement various operations. For example, peripheral circuitry may include one or more of the following: page buffer / sensor amplifier, decoder (e.g., row decoder or column decoder), word line driver, input / output (I / O) circuitry, charge pump, voltage source or voltage generator, current or voltage reference, or any active or passive device (e.g., transistor, diode, resistor, or capacitor) of the circuitry.

[0062] Although embodiments of the present application describe exemplary structures of three-dimensional memories, it will be understood that one or more features may be omitted, substituted, or added from the structure of the three-dimensional memory. For example, various well regions may be formed in the semiconductor layer 212 as needed. Furthermore, the materials of the layers described are merely exemplary.

[0063] Some embodiments of this application also provide a method for fabricating a three-dimensional memory. Figure 3 This is a flowchart of a method 300 for fabricating a three-dimensional memory according to an exemplary embodiment of this application. For example, Figure 3 The fabrication method 300 of the three-dimensional memory shown (hereinafter referred to as fabrication method 300) can be used to fabricate... Figure 2 The three-dimensional memory 200 is shown.

[0064] like Figure 3 As shown, the preparation method 300 includes steps S310 and S320.

[0065] S310, a channel structure is formed from the first side of the stacked structure, which runs through the stacked structure.

[0066] S320, a gate line slot is formed from the second side of the stacked structure opposite to the first side, passing through the stacked structure.

[0067] According to the fabrication method of the three-dimensional memory provided in this embodiment, by forming a channel structure from a first side of the stacked structure and a gate line slot from a second side of the stacked structure opposite to the first side, the distance between the channel structure and the gate line slot structure can be reduced. This helps to reduce the bending risk of the gate layer in the stacked structure and ensures the structural and electrical performance of the gate layer. Furthermore, while ensuring the performance of the gate layer in the stacked structure, the overall distance between the channel structure and the gate line slot structure can be reduced, resulting in a compact structure of the fabricated three-dimensional memory and improving the unit storage density of the three-dimensional memory.

[0068] Figures 4A to 4K This is a cross-sectional schematic diagram of the fabrication process of a three-dimensional memory according to an exemplary embodiment of this application. For example, according to... Figure 3 The preparation method 300 shown can form Figures 4A to 4K The intermediate structure of the three-dimensional memory is shown below. (Followed by...) Figures 4A to 4K Steps S310 and S320 described above are illustrated by way of example. For the sake of brevity, the same content as above will not be repeated here.

[0069] S310

[0070] Figure 4A The intermediate structure 400a of the three-dimensional memory after executing step S310 is shown. (Example) Figure 4A As shown, in some embodiments, during and before step S310, the stacked structure 420 may include a plurality of alternately stacked first gate dielectric layers (e.g., first gate dielectric layer 421) and a plurality of gate sacrificial layers (e.g., gate sacrificial layer 423). For example, each of the plurality of first gate dielectric layers and each of the plurality of gate sacrificial layers may extend laterally in both the x and y directions. The material of the gate sacrificial layer may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any other suitable dielectric material, and the material of the gate sacrificial layer and the material of the first gate dielectric layer may have different etching selectivity ratios. For example, the material of the first gate dielectric layer may be silicon oxide, and the material of the gate sacrificial layer may be silicon nitride.

[0071] In some embodiments, the stacked structure 420 may be formed on one side of the substrate 411. For example, the substrate 411 is used to provide mechanical support. The material of the substrate 411 may include, but is not limited to, silicon (e.g., single-crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. For example, the substrate 411 may be a silicon substrate.

[0072] In some embodiments, before forming the stacked structure 420 on one side of the substrate 411, the fabrication method 300 may further include forming a silicon oxide layer 413 and a polysilicon layer 414 on one side of the substrate 411 (e.g., the surface of the substrate 411). In other words, the silicon oxide layer 413 and the polysilicon layer 414 may be formed between the substrate 411 and the stacked structure 420, for example, as stop layers in subsequent processes to control the etching process, as will be described in detail below.

[0073] In some embodiments, the channel structure 430 may include multiple sub-channel structures (e.g., sub-channel structures 431 and 432). For example, step S310 may include the following sub-steps: First, a first sub-stacking structure 424 is formed on one side of the substrate 411 (e.g., the surface of the polysilicon layer 414). Then, a first sub-channel hole (corresponding to the outer contour of the first sub-channel structure 431) is formed from a first side of the first sub-stacking structure 424 (e.g., the side away from the substrate 411) through the first sub-stacking structure 424 and extending into the substrate 411, and a sacrificial material is filled within the first sub-channel hole. For example, the first sub-channel hole may be formed by etching along the negative z-direction from the surface of the first sub-stacking structure 424 away from the substrate 411 using an etching process. Then, a second sub-stacking structure 425 is formed covering the surface of the first sub-stacking structure 424 away from the substrate 411 and the end face of the first sub-channel hole 431 away from the substrate 411. Next, a second sub-channel hole (corresponding to the outer contour of the second sub-channel structure 432) is formed through the second sub-stacking structure 425 from a first side (e.g., the side away from the substrate 411), wherein the second sub-channel hole can be at least partially aligned with the first sub-channel hole. Similarly, for example, the second sub-channel hole can be formed by etching along the negative z-direction from the surface of the second sub-stacking structure 425 away from the substrate 411 using an etching process. The sacrificial material within the first sub-channel hole is then removed via the second sub-channel hole, such that the first and second sub-channel holes communicate with each other to form a channel hole. Finally, a functional layer 433 and a channel layer 434 are sequentially formed within the channel hole to form the channel structure 430.

[0074] Although embodiments of this application describe an exemplary method of fabricating a channel structure 430 comprising two sub-channel structures 431 and 432, it will be understood that a greater number of sub-channel structures may be formed using similar methods.

[0075] In other embodiments, the channel structure (not shown) may not include multiple sub-channel structures. For example, step S310 may include the following sub-steps: First, a stacked structure 420 is formed on one side of the substrate 411 (e.g., the surface of the polysilicon layer 414). Then, a channel hole is formed from a first side of the stacked structure 420 (e.g., the side away from the substrate 411) through the stacked structure 420 and extending into the substrate 411. For example, the channel hole may be formed by etching from the surface of the stacked structure 420 away from the substrate 411 along the negative z-direction using an etching process. Then, a functional layer and a channel layer are sequentially formed within the channel hole to form the channel structure.

[0076] It should be noted that during the process of etching channel holes or sub-channel holes from the first side of the stacked structure or sub-stacked structure to form the channel structure or sub-channel structure, the cross-sectional size of the channel structure or sub-channel structure in the z direction gradually decreases along the etching direction (i.e., the negative z direction).

[0077] In some implementations, reference continues. Figure 4A After forming the channel structure 430, the fabrication method 300 may further include: forming a selective stacking structure 450 on a first side of the stacked structure 420, and forming a selective channel structure 454 through the selective stacking structure 450. Exemplarily, after forming the selective stacking structure 450, an etching process may be used to etch along the negative z-direction from the side of the selective stacking structure 450 away from the substrate 411 to form a selective channel hole (corresponding to the outer contour of the selective channel structure 454), wherein the selective channel hole may be at least partially aligned with the channel structure 430. An insulating layer 455 is then formed on the sidewall of the selective channel hole. Next, a selective channel layer 456 is formed within the selective channel hole where the insulating layer 455 is formed to form the selective channel structure 454. This causes the insulating layer 455 and the selective channel layer 456 to be in contact, and the selective channel layer 456 (e.g., the end face of the selective channel layer 456 near the channel structure 430) is connected to the channel structure 430. For example, between forming the selective stack structure 450 and forming the selective channel structure 454, the fabrication method 300 may further include forming a second stop layer 453 on the side of the selective stack structure 450 away from the stack structure 420, such that the selective channel structure 454 can penetrate the second stop layer 453. For example, the second stop layer 453 can be used to control the etching process during the subsequent formation of conductive contacts, as will be described in detail below.

[0078] In some embodiments, the preparation method 300 may further include forming an initial isolation portion and its corresponding isolation portion. Figure 4B The intermediate structure 400b of the three-dimensional memory is shown after the second opening corresponding to the initial isolation section is formed. Figure 4CAn intermediate structure 400c of the three-dimensional memory after the initial isolation section is formed is shown. The method for forming the isolation section corresponding to the initial isolation section will be described in detail below.

[0079] like Figure 4B As shown, an etching process can be used to form a second opening 458 penetrating the second stop layer 453 and the selected stack structure 450 from the side of the second stop layer 453 away from the stack structure 420. For example, the second opening 458 can extend in the x-direction and has a length in the x-direction approximately the same as the subsequently formed gate line slot. Further, as Figure 4C As shown, thin film deposition processes can be used for... Figure 4B The second opening 458 shown is filled to form an initial isolation portion 457', which extends through the second stop layer 453 and the selective stack structure 450. The material of the initial isolation portion 457' may have a different etching selectivity than the material of the second stop layer 453; for example, the material of the second stop layer 453 may be silicon nitride, and the material of the initial isolation portion 457' may be silicon oxide.

[0080] In some embodiments, the preparation method 300 may further include forming a first insulating layer and conductive contacts. Figure 4C The intermediate structure 400c shown also includes a first insulating layer 461. Additionally, Figure 4D The intermediate structure 400d of the three-dimensional memory after the formation of conductive contacts and the first stop layer is shown.

[0081] Continue to refer to Figure 4C For example, a first insulating layer 461 can be formed on a first side of the stacked structure 420 (e.g., the surface of the second stop layer 453) using a thin-film deposition process. The material of the first insulating layer 461 can have a different etching selectivity than the material of the second stop layer 453; for example, the material of the first insulating layer 461 can be silicon oxide, and the material of the second stop layer 453 can be silicon nitride. Further, as... Figure 4D As shown, for example, an etching process can be used to form an opening corresponding to the conductive contact 462 in the first insulating layer 461 (the opening corresponds to the outer contour of the conductive contact 462). This opening can be at least partially aligned with the selective channel structure 454, and the cross-sectional dimension of the opening in the z-direction can be larger than the cross-sectional dimension of the selective channel structure 454 in the z-direction (not shown), so that the end face of the opening approximately rests on the surface of the second stop layer 453. This facilitates control of the etching process for forming the opening corresponding to the conductive contact 462, reducing the risk of damage to the selective channel structure 454 or the selective stack structure 450. Further, for example, a thin-film deposition process can be used to fill the opening with conductive material to form the conductive contact 462.

[0082] In some embodiments, the preparation method 300 may further include forming a first stop layer. Figure 4D The intermediate structure 400d shown also includes a first stop layer 445. (Continue to refer to...) Figure 4D For example, an etching process can be used to form a first opening (corresponding to the outer contour of the first stop layer 445) penetrating the first insulating layer 461 from the side of the first insulating layer 461 away from the stacked structure 420. For example, the first opening can extend in the x-direction and has a length approximately the same in the x-direction as the subsequently formed gate line slot. Further, a thin-film deposition process can be used to fill the first opening with a first material to form the first stop layer 445. The first material and the material of the stacked structure 420 (e.g., silicon oxide and silicon nitride) have different etching selectivity ratios. For example, the first material can include metallic conductive materials such as tungsten, cobalt, copper, and aluminum. The first stop layer 445 can be used to control the etching process during the subsequent formation of the gate line slot, as described in detail below. It should be noted that during the etching of the first opening from the side of the first insulating layer 461 away from the stacked structure 420, the cross-sectional dimension (e.g., the width in the y-direction) of the first opening gradually decreases along the etching direction (i.e., the negative z-direction).

[0083] It should be noted that when the preparation method 300 includes forming an initial isolation portion 457', the initial isolation portion 457' and the first stop layer 445 can be substantially aligned in the z direction, and the cross-sectional dimension of the initial isolation portion 457' in the z direction (e.g., the width in the y direction) can be greater than the cross-sectional dimension of the first stop layer 445 in the z direction (e.g., the width in the y direction), such that both sides of the portion of the first stop layer 445 extending to the initial isolation portion 457' are surrounded by the initial isolation portion 457'.

[0084] In some embodiments, the formation of the conductive contact 462 and the first stop layer 445 described above can be performed in the same process. For example, the same mask can be used to etch the opening corresponding to the conductive contact 462 and the first opening corresponding to the first stop layer 445 in the same step, and the same thin film deposition process can be used to fill the opening corresponding to the conductive contact 462 and the first opening corresponding to the first stop layer 445, so that the materials filling the opening and the first opening are the same. This preparation method helps to simplify the process flow. It should be noted that during the etching process of the opening corresponding to the conductive contact 462 and the first opening corresponding to the first stop layer 445, the second stop layer 453 can make the opening stop approximately at its surface, while the initial isolation portion 457' does not provide the function of making the first opening stop approximately at its surface. Therefore, during the same etching process of the opening and the first opening, the first opening will extend into the initial isolation portion 457', thereby making the first stop layer 445 extend into the initial isolation portion 457'.

[0085] In other embodiments, where the fabrication method 300 does not include forming the selective stack structure 450 and the second stop layer 453 (not shown), for example, a first insulating layer 461 may be formed on a first side of the stack structure 420 (e.g., the surface of the stack structure 420 away from the substrate 411) using a thin film deposition process, and a first opening is formed through the first insulating layer 461 from the side of the first insulating layer 461 away from the stack structure 420, and the extension distance of the first opening in the z-direction is controlled, for example, by controlling the timing of the etching process.

[0086] In some embodiments, the fabrication method 300 may further include forming an interconnect layer and a semiconductor structure for connecting peripheral circuits. Figure 4E An intermediate structure 400e of a three-dimensional memory is shown after the formation of interconnect layers and the semiconductor structure connecting the peripheral circuitry. (See diagram below.) Figure 4E As shown, an interconnect layer 463 can be formed on the side of the conductive contact 462 and the first insulating layer 461 away from the stacked structure 420 using any process known in the art. Further, a peripheral circuit semiconductor structure 470 can be connected to the interconnect layer 463 on the side away from the stacked structure 420 using any process known in the art, thereby enabling signal transmission between the peripheral circuit semiconductor structure 470 and, for example, the channel structure 430. For example, a bonding process can be used to physically connect the peripheral circuit semiconductor structure 470 to the interconnect layer 463. It should be noted that "bonding" can include any suitable bonding technique such as hybrid bonding, anodic bonding, fused bonding, transfer bonding, adhesive bonding, and eutectic bonding.

[0087] In some embodiments, the fabrication method 300 may further include removing the substrate, a portion of the functional layer of the channel structure, and forming a semiconductor layer. Figure 4F The intermediate structure 400f of the three-dimensional memory after the substrate has been removed is shown. Figure 4G The intermediate structure 400g of the three-dimensional memory after removing some functional layers of the channel structure is shown. Figure 4H The intermediate structure 400h of the three-dimensional memory forming the semiconductor layer is shown.

[0088] like Figure 4F As shown, it can be Figure 4E The intermediate structure 400e shown is flipped 180° before subsequent steps are performed. For example, an etching process is used to remove... Figure 4E The substrate 411 shown exposes a channel structure 430 extending into the substrate 411, such as a functional layer 433 on the outer layer of the channel structure 430. For example, in the case where the fabrication method 300 includes forming a silicon oxide layer 413, the silicon oxide layer 413 can serve as an etch stop layer for removing the substrate 411, thereby facilitating control of the etching process for removing the substrate 411. Further, asFigure 4G As shown, etching can be used to remove... Figure 4F The partial functional layer 433 shown exposes the channel layer 434. For example, the partial functional layer 433 may be the portion of the functional layer 433 located outside the polysilicon layer 414 and the stacked structure 420. For example, in the case where the fabrication method 300 includes forming the polysilicon layer 414, the polysilicon layer 414 can serve as an etch stop layer for removing the partial functional layer 433, thereby facilitating control of the etch process for removing the partial functional layer 433. Further, as... Figure 4H As shown, a semiconductor material layer 415 can be formed on the second side of the stacked structure 420 (e.g., the surface of the polycrystalline silicon layer 414) using a thin-film deposition process. The second side of the stacked structure 420 may be opposite to the first side of the stacked structure 420 in the z-direction. The semiconductor material layer 415 may cover the channel layer 434, thereby achieving electrical connection between the semiconductor material layer 415 and the channel layer 434. The material of the semiconductor material layer 415 may include, but is not limited to, silicon (e.g., monocrystalline silicon c-Si, polycrystalline silicon p-Si, amorphous silicon α-Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), or any other suitable semiconductor material. For example, the semiconductor material layer 415 may be fabricated using polycrystalline silicon, so that there is no obvious interface between the semiconductor material layer 415 and the polycrystalline silicon layer 414. The polycrystalline silicon layer 414 and the semiconductor material layer 415 together constitute the semiconductor layer 412. In other examples, where the preparation method 300 does not include forming a polysilicon layer 414, the reformed semiconductor material layer 415 is the semiconductor layer 412.

[0089] S320

[0090] Figure 4H The intermediate structure 400h shown also includes the gate line gap 446 formed after performing step S320. For example... Figure 4H As shown, for example, an etching process can be used to form a gate line slot 446 through the stacked structure 420 from the second side of the stacked structure 420. For example, the gate line slot 446 can be a trench extending in the x-direction. It should be noted that the gate line slot 446 formed by etching from the second side of the stacked structure gradually decreases in cross-sectional dimensions (e.g., slot width) in the z-direction along the etching direction (i.e., the positive z-direction).

[0091] In some implementations, reference continues. Figure 4HIn the case where fabrication method 300 includes forming a first stop layer 445, the gate line slot 446 and the first stop layer 445 can be approximately aligned in the z-direction. Furthermore, since the first material constituting the first stop layer 445 (e.g., tungsten) and the materials of the stacked structure 420 (e.g., silicon oxide and silicon nitride) have different etching selectivity ratios, the gate line slot 446 can be made to stop approximately on the surface of the first stop layer 445, thereby facilitating control of the etching process for forming the gate line slot 446. It is understood that... Figure 4H The distance shown in the diagram where the gate line slot 446 extends into the first stop layer 445 is merely an example. In reality, under the influence of the first stop layer 445, the gate line slot 446 may remain on the surface of the first stop layer 445, or it may have a smaller extension distance within the first stop layer 445.

[0092] In some embodiments, as mentioned above, the preparation method 300 may further include forming an initial isolation portion 457' (see reference). Figure 4G (Corresponding isolation section 457.) See also: Figure 4H For example, the initial isolation portion 457', the first stop layer 445, and the gate line slot 446 may be generally aligned with each other in the z-direction. During the formation of the gate line slot 446, the gate line slot 446 may pass through the initial isolation portion 457', dividing the initial isolation portion 457' into a first sub-isolation portion 4571 and a second sub-isolation portion 4572. The portion of the gate line slot 446 extending in the z-direction into the initial isolation portion 457' is surrounded on both sides by the divided first sub-isolation portion 4571 and second sub-isolation portion 4572, respectively.

[0093] In some embodiments, the fabrication method 300 further includes "gate replacement" and forming a gate line gap structure. Figure 4I The intermediate structure 400i of the three-dimensional memory after the first stopping layer is removed is shown. Figure 4J An intermediate structure 400j of a three-dimensional memory is shown after replacing multiple gate sacrificial layers with multiple gate layers. Figure 4K The three-dimensional memory 400k is shown after the formation of the gate line slot structure.

[0094] like Figure 4I As shown, for example, an etching process can be used to remove the gate line gaps 446. Figure 4H The first stop layer 445 shown in the figure exposes the first opening corresponding to the first stop layer 445. In this embodiment, the gate gap 446' may also include a re-exposed first opening. Further, as Figure 4J As shown, for example, an etching process can be used to etch the gate line through the gap 446'. Figure 4H The plurality of gate sacrificial layers (e.g., gate sacrificial layer 423) shown are replaced with a plurality of gate layers (e.g., gate layer 422).

[0095] It should be noted that continued reference is necessary. Figure 4J Since the isolation portions 457 (i.e., the first sub-isolation portion 4571 and the second sub-isolation portion 4572) are located on both sides of the gate line slot 446' located on the portion of the selective stack structure 450 and the second stop layer 453, and the material of the isolation portion 457 can have a different etching selectivity ratio than the material of the second stop layer 453, the isolation portion 457 is removed via the gate line slot 446' using an etching material (e.g., an etching solution). Figure 4H During the process of creating multiple gate sacrificial layers (e.g., gate sacrificial layer 423) as shown, the risk of etch material damaging the selected stack structure 450 and the second stop layer 453 can be reduced.

[0096] In some implementations, such as Figure 4K As shown, for example, thin film deposition processes can be used in... Figure 4J An insulating material layer 443 is formed on the inner wall of the gate line slot 446' shown, and a conductive material layer 444 is formed within the gate line slot 446' where the insulating material layer 443 is formed, thereby forming a gate line slot structure 440. In another embodiment, for example, a thin film deposition process can be used in... Figure 4J The grid line gap 446' shown is completely filled with insulating material, but this application does not impose any limitations.

[0097] Some embodiments of this application also provide a memory system. Figure 5 This is a block diagram of a system 10 having a memory system 12 according to an embodiment of this application.

[0098] System 10 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 12 located therein). Figure 5 As shown, system 10 may include a host 18 and a memory system 12, the memory system 12 having one or more three-dimensional memories 14 and a memory controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the three-dimensional memories 14.

[0099] The three-dimensional memory 14 may be the three-dimensional memory described in any embodiment of this application, for example, Figure 2 The illustrated three-dimensional memory 200. According to some embodiments, a storage controller 16 is coupled to the three-dimensional memory 14 and a host 18, and is configured to control the three-dimensional memory 14. The storage controller 16 manages data stored in the three-dimensional memory 14 and communicates with the host 18. In some embodiments, the storage controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the storage controller 16 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc. The storage controller 16 can be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The storage controller 16 may also be configured to manage various functions related to data stored in or to be stored in the 3D memory 14, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the storage controller 16 is further configured to process error correction codes (ECCs) related to data read from or written to the 3D memory 14. The storage controller 16 may also perform any other appropriate functions, such as formatting the 3D memory 14. The storage controller 16 may communicate with external devices (e.g., host 18) according to specific communication protocols. For example, the storage controller 16 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0100] The storage controller 16 and one or more three-dimensional memories 14 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 12 can be implemented and packaged into different types of end electronic products. Figure 6A In one example shown, the storage controller 16 and a single 3D memory 14 may be integrated into the memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a connection between the memory card 22 and a host computer (e.g., Figure 5 The host 18) is coupled to the memory card connector 24. In such a way... Figure 6B In another example shown, the storage controller 16 and multiple 3D memories 14 may be integrated into the SSD 26. The SSD 26 may further include a connection between the SSD 26 and a host (e.g., Figure 5 The SSD connector 28 is coupled to the host 18. In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than that of the memory card 22.

[0101] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A three-dimensional memory, characterized in that, include: Semiconductor layer; A stacked structure is located on one side of the semiconductor layer; A channel structure extends through the stacked structure in a direction perpendicular to the semiconductor layer, and in the same plane perpendicular to the semiconductor layer, the cross-sectional dimension of the channel structure at the surface of the stacked structure away from the semiconductor layer is larger than its cross-sectional dimension at the surface of the stacked structure close to the semiconductor layer; as well as A gate line slot structure extends through the stacked structure in a direction perpendicular to the semiconductor layer and in a direction parallel to the semiconductor layer. In the same plane perpendicular to the extension direction, at least a portion of the gate line slot structure has a smaller cross-sectional dimension at the surface of the stacked structure away from the semiconductor layer than its cross-sectional dimension at the surface of the stacked structure near the semiconductor layer.

2. The three-dimensional memory according to claim 1, wherein, Along a first direction, the cross-sectional dimension of the at least part of the gate line slot structure gradually decreases in the first direction, which is perpendicular to the semiconductor layer and away from the semiconductor layer.

3. The three-dimensional memory according to claim 2, wherein, The gate line gap structure includes a first part and a second part that are in contact with each other, the second part being located on the side of the first part away from the semiconductor layer, and the first part passing through the stacked structure. Along the first direction, the cross-sectional dimension of the first part gradually decreases in the first direction, while the cross-sectional dimension of the second part gradually increases in the first direction.

4. The three-dimensional memory according to claim 2, wherein, In the stacked structure near the surface of the semiconductor layer, the distance between the channel structure and the gate gap structure is 50 nm to 150 nm.

5. The three-dimensional memory according to claim 2, wherein at the surface of the stacked structure away from the semiconductor layer, there is a first distance between the channel structure and the gate line slot structure, and at the surface of the stacked structure close to the semiconductor layer, there is a second distance between the channel structure and the gate line slot structure, wherein the difference between the first distance and the second distance is less than 100 nm.

6. The three-dimensional memory according to any one of claims 2 to 5, wherein, Along the first direction, the cross-sectional dimensions of the channel structure gradually increase in the first direction.

7. The three-dimensional memory according to any one of claims 2 to 5, wherein, The channel structure includes at least two sub-channel structures, and along the first direction, the cross-sectional dimension of each sub-channel structure gradually increases in the first direction.

8. The three-dimensional memory according to any one of claims 1 to 5, wherein, Also includes: Select a stacked structure located on the side of the stacked structure furthest from the semiconductor layer; as well as Selective channel structure, extending through the selective stack structure, includes an insulating layer and a selective channel layer from the outside in, wherein the insulating layer and the selective channel layer are in contact, and the selective channel layer is connected to the channel structure.

9. The three-dimensional memory according to claim 8, wherein, Also includes: A stop layer is located on the side of the selected stack structure away from the semiconductor layer, wherein the selected channel structure extends through the stop layer; as well as A conductive contact is located on the side of the stop layer away from the select stack structure and is in contact with the select channel structure and the stop layer.

10. The three-dimensional memory according to claim 9, wherein, The gate wire slot structure extends through the stacked structure, the selected stacked structure, and the stop layer; the three-dimensional memory further includes: An isolation section extends through the select stack structure and the stop layer, and is located on both sides of the portion of the gate slot structure that extends through the select stack structure and the stop layer.

11. The three-dimensional memory according to claim 9, wherein, Also includes: An interconnect layer is located on the side of the conductive contact away from the semiconductor layer; as well as The peripheral circuit semiconductor structure is connected to the interconnect layer on the side away from the semiconductor layer.

12. The three-dimensional memory according to any one of claims 1 to 5, wherein, The grid line slot structure includes an insulating material layer and a conductive material layer from the outside in.

13. A memory system, including: At least one three-dimensional memory as described in any one of claims 1 to 12; as well as A storage controller, coupled to the three-dimensional memory, is used to control the three-dimensional memory.

14. A method for fabricating a three-dimensional memory, characterized in that, include: A channel structure is formed from the first side of the stacked structure, penetrating the stacked structure; A semiconductor layer is formed, the semiconductor layer being located on a second side of the stacked structure, the second side being disposed opposite to the first side; as well as A gate wire slot is formed from the second side of the stacked structure, passing through the stacked structure; Specifically, in the same plane perpendicular to the semiconductor layer, the cross-sectional dimension of the channel structure at the surface of the stacked structure away from the semiconductor layer is larger than its cross-sectional dimension at the surface of the stacked structure near the semiconductor layer, and the cross-sectional dimension of the gate gap at the surface of the stacked structure away from the semiconductor layer is smaller than its cross-sectional dimension at the surface of the stacked structure near the semiconductor layer.

15. The preparation method according to claim 14, wherein, After forming a channel structure that runs through the stacked structure, the fabrication method further includes: A first insulating layer is formed on the first side; A first opening is formed through the first insulating layer from the side of the first insulating layer away from the stacked structure; and A first material is filled into the first opening to form a first stop layer, wherein the first material and the material of the stacked structure have different etching selectivity ratios.

16. The preparation method according to claim 15, wherein, Before forming the first insulating layer, the preparation method further includes: A selective stacking structure is formed on the first side; and A selection channel structure is formed that runs through the selection stack structure, wherein the selection channel structure includes an insulating layer and a selection channel layer from the outside to the inside, the insulating layer and the selection channel layer are in contact, and the selection channel layer is connected to the channel structure.

17. The preparation method according to claim 16, wherein, Before forming the selective channel structure that runs through the selective stack structure, the fabrication method further includes: A second stop layer is formed on the side of the selected stack structure away from the stack structure; and On the side of the second stop layer away from the selected stack structure, a conductive contact is formed that extends through the first insulating layer to the selected channel structure and the second stop layer.

18. The preparation method according to claim 17, wherein, The conductive contact and the first stop layer are formed in the same process.

19. The preparation method according to claim 17, wherein, The preparation method further includes: An initial isolation section is formed that extends through the second stop layer and the selected stack structure; The formation of the gate wire gaps through the stacked structure includes: A grid line slot is formed through the initial isolation portion to divide the initial isolation portion into isolation portions located on both sides of the grid line slot.

20. The fabrication method according to claim 15 or 19, wherein the stacked structure comprises alternatingly stacked plurality of gate dielectric layers and plurality of gate sacrificial layers, and after forming the gate line gap, the fabrication method further comprises: The first material within the first opening is removed via the gate line gap, and the plurality of gate sacrificial layers are replaced with a plurality of gate layers; as well as An insulating material layer and a conductive material layer are sequentially formed in the gaps of the grid lines.

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