A room temperature multiferroic semiconductor storage and computing device

Abstract

The present invention belongs to the field of multiferroic storage technology, and specifically relates to a room-temperature multiferroic semiconductor storage and computing integrated device. The present invention utilizes multiferroic semiconductor materials and field effect transistor logic, and both the computing and storage functions are based on single-phase multiferroic semiconductor materials under the application conditions of achieving high speed, low power consumption, low cost and normal operation at room temperature. The room-temperature multiferroic semiconductor storage and computing integrated device of the present invention realizes the switching function of the multiferroic semiconductor operator by: applying a gate voltage to form a connecting channel; at the same time, the ferromagnetic polarization is controlled by the gate voltage to realize the non-volatile magnetic storage function of the multiferroic semiconductor, thereby fundamentally solving the "storage wall" problem between storage and computing.

Description

Technical Field

[0001] The present invention belongs to the technical field of multiferroic storage, and in particular relates to a room temperature multiferroic semiconductor storage and computing integrated device. Background Art

[0002] With the rapid development of artificial intelligence, big data, and deep learning technologies, very high requirements are placed on information storage and computing capabilities, requiring computer architecture and systems to have the characteristics of high speed, low power consumption, and small size.

[0003] At present, modern computers use the von Neumann architecture that separates information processing and storage, and the storage is divided into multiple levels, including volatile storage, non-volatile storage, etc. Volatile storage is fast, at the order of 10 nanoseconds, while non-volatile storage is slow, at the order of 10 microseconds, but the speed of the computing unit CPU is less than 1 nanosecond. The memory speed is much lower than the speed of the operator, resulting in the "storage wall" problem, which has become an important bottleneck affecting computer performance. About 40% of the power consumption is consumed in the round-trip transmission of data, which greatly reduces the collaborative efficiency of computing and storage. Therefore, the development of high-speed, high-density, low-power, non-volatile room-temperature storage devices that match the speed of the computing unit CPU has become a focus and challenge of industry research.

[0004] The arithmetic unit obtains instructions and data to be processed through the memory, and transmits them to the memory after logical operations and outputs them to the outside. However, since the memory and the arithmetic unit are two independent units, the arithmetic unit needs to transmit the processed data to the memory after each command execution. Such repeated execution of commands makes the operation efficiency low and the unit computing power insufficient, which greatly affects the further development of computers and hinders the development of artificial intelligence technology and big data processing technology.

[0005] Current non-volatile memories include hard disks, flash memory, phase change memory, resistive random access memory, etc. Most of them have certain limitations. For example, flash memory has a write and erase speed limited by the tunneling of electrons to the floating gate, and its operating speed is 10 microseconds; and although the phase change memory can reach a speed of 20-100 nanoseconds, it has the problem of high energy consumption. Therefore, it is impossible to meet the needs of high speed and low power consumption at the same time, and it is impossible to truly solve the problem of the storage wall between the memory and the operator; it is urgent to develop a new type of room temperature storage and computing device to solve the von Neumann bottleneck, improve efficiency and reduce power consumption. Summary of the invention

[0006] In view of the above-mentioned problems and shortcomings, and to solve the storage wall problem and the problem that existing memories cannot simultaneously meet the requirements of high speed and low power consumption, the present invention provides a room-temperature multiferroic semiconductor storage and computing integrated device, which is based on halide multiferroic and implemented using field effect transistor logic.

[0007] The object of the present invention is achieved through the following technical solutions:

[0008] A room temperature multiferroic semiconductor storage and computing integrated device comprises a multiferroic semiconductor film, an insulating layer, a source electrode, a drain electrode and a gate electrode, and operates at room temperature.

[0009] The multiferroic semiconductor film is a transition metal halide or sulfide MX n , where M is chromium Cr, iron Fe, nickel Ni, cobalt Co or manganese Mn, X is iodine I, bromine Br, chlorine Cl or sulfur S, and n = 1, 2, 3. Multiferroic semiconductor films have ferroelectricity and ferromagnetism, and their ferroelectric and ferromagnetic polarization directions can be changed by voltage.

[0010] The source and gate are arranged on the multiferroic semiconductor film, an insulating layer is arranged between the gate and the multiferroic semiconductor film, the gate and the multiferroic semiconductor film, the source and the drain are isolated from each other by the insulating layer, a conductive channel located in the multiferroic semiconductor film exists between the source and the gate, and the source, the drain and the multiferroic semiconductor film are in ohmic contact.

[0011] The gate voltage is V GS The threshold voltage of the multiferroic semiconductor film is V T , the magnetic control threshold voltage of the multiferroic semiconductor film is V M , drain voltage V DS and gate voltage V GS Less than the breakdown voltage of the multiferroic semiconductor.

[0012] Furthermore, after a positive voltage is applied to the multiferroic semiconductor film by the gate, a conductive channel is formed in the multiferroic semiconductor film, connecting the source and the drain. At this time, the multiferroic semiconductor storage-computing integrated device is in the on state, which is represented by 1. When no voltage is applied to the multiferroic semiconductor film, the multiferroic semiconductor film does not form a conductive channel, the source and the drain are disconnected, and the multiferroic semiconductor storage-computing integrated device is in the off state, which is represented by 0. By changing the gate voltage to control the source and drain currents, the conductive channel is controlled to be on and off, thereby realizing logical operations.

[0013] Furthermore, after a positive voltage is applied to the multiferroic semiconductor film by the gate, the multiferroic semiconductor film is magnetized, the gate voltage drops to 0, and the multiferroic semiconductor device still has residual electric polarization and residual magnetization, the electric polarization direction is upward, the magnetization direction is upward, and the information is stored, which is represented as "1". When the gate voltage is negative, the multiferroic semiconductor film is in a disconnected state, the upward residual electric polarization of the multiferroic semiconductor film weakens until it flips downward, and demagnetization occurs, the magnetization of the multiferroic semiconductor device weakens, and the gate voltage is gradually reduced to 0. At this time, the residual electric polarization of the multiferroic semiconductor device is downward, the residual magnetization is weakened, and the information is erased, which is represented as "0".

[0014] Furthermore, to read the stored information, a small current is applied to the multiferroic semiconductor film through the source and drain. When the magnetization is upward, the resistance is high, and the information is stored, which is represented by "1". When the magnetization is weak, the resistance is low, and the information is erased, which is represented by "0".

[0015] Furthermore, when the magnetic control threshold voltage V M >Threshold voltage V for multiferroic semiconductor to conduct electricity T hour:

[0016] If V GS <V T , and V GS <V M , the multiferroic semiconductor device is in the cut-off state.

[0017] If V GS ≥V T , and V GS <V M , the multiferroic semiconductor device is in the on state and can only realize the computing function.

[0018] If V GS ≥V T , and V GS ≥V M , the multiferroic semiconductor is in the on state, realizing the computing and storage functions at the same time, that is, realizing storage and computing integration.

[0019] Furthermore, when the threshold voltage V T >Magnetic control threshold voltage V M hour:

[0020] If V GS <V T , and V GS <V M , the multiferroic semiconductor device is in the cut-off state.

[0021] If V GS ≥V M , and V GS <V T , the multiferroic semiconductor device is in the on state and can only realize the storage function, realizing a non-volatile magnetic memory.

[0022] If V GS ≥V T , and V GS ≥V M , the multiferroic semiconductor is in the on state, realizing both computing and non-volatile storage functions, achieving storage and computing integration.

[0023] Furthermore, when the gate voltage V TWhen the gate voltage is positive and reaches the polarization saturation voltage, the electric polarization and magnetic polarization of the multiferroic semiconductor are both upward, and the gate voltage is gradually reduced to 0. At this time, the multiferroic semiconductor device has residual electric polarization and residual magnetization, the electric polarization direction is upward, the magnetization direction is upward, and the information is stored, which is represented as "1". When the gate voltage is negative and reaches the polarization saturation voltage, the upward residual electric polarization of the multiferroic semiconductor is weakened until it flips downward, and the residual magnetization direction and intensity occur accordingly. The gate voltage is gradually reduced to 0. At this time, the residual electric polarization of the multiferroic semiconductor device is downward, the residual magnetization is weakened or downward, and the information is erased, which is represented as "0".

[0024] Furthermore, the gate, source and drain are gold Au, silver Ag, copper Cu, aluminum Al, chromium Cr, platinum Pt, palladium Pd, p-type doped silicon substrate, n-type doped silicon substrate and / or graphene.

[0025] Furthermore, the insulating layer is SiO2, TiO2, ZnO, HfO2, Al2O3, GeO2 or hBN.

[0026] In summary, the present invention uses field effect transistor logic on multiferroic semiconductor materials to provide a multiferroic semiconductor storage and computing integrated device that works at room temperature under the application conditions of achieving high speed, low power consumption, low cost and normal operation at room temperature; both the computing and storage functions are based on single-phase multiferroic semiconductor materials. By applying a gate voltage, a connecting channel is formed to realize the switching function of the multiferroic semiconductor operator; at the same time, the ferromagnetic polarization is controlled by the gate voltage to realize the non-volatile magnetic storage function of the multiferroic semiconductor, thereby fundamentally solving the "storage wall" problem between storage and computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a schematic diagram of the cross-sectional structure of the multiferroic semiconductor storage and computing integrated device in Example 1.

[0028] Figure 2 This is a schematic diagram of the cross-sectional structure of the multiferroic semiconductor storage and computing integrated device in Example 2.

[0029] Figure 3 This is a schematic diagram of the three-dimensional structure of the multiferroic semiconductor storage and computing integrated device in Example 3.

[0030] Figure 4 This is a reflection magnetic circular dichroism (RMCD) characterization diagram of Example 1.

[0031] Description of the drawings: multiferroic semiconductor film-10, source-20, drain-30, insulating layer-40, substrate-50, bottom electrode-60, top electrode-70. DETAILED DESCRIPTION

[0032] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. This embodiment is implemented on the premise of the technical solution of the present invention, and a detailed implementation method and a specific operation process are given, but the protection scope of the present invention is not limited to the following embodiments. In the accompanying drawings, for the sake of clear display, the thickness of the layers and regions is exaggerated, and the size ratio relationship between the various parts in the diagram does not reflect the actual size relationship. In the following examples, in order to describe more clearly, the polarization direction is given by way of example, but it should be understood that the polarization direction of the multiferroic semiconductor storage and computing device is not limited to the direction given in the diagram.

[0033] Example 1

[0034] The cross-sectional structure diagram of the multiferroic semiconductor storage-computing integrated device provided in this embodiment is as follows: Figure 1 As shown, it mainly includes a multiferroic semiconductor film 10 , a source 20 , a drain 30 , an insulating layer 40 and a substrate 50 .

[0035] The multiferroic semiconductor film 10 is an n-type semiconductor; the substrate 50 is a doped conductive silicon substrate, which serves as a gate. The gate 50 is isolated from the multiferroic semiconductor film 10, the source 20, and the drain 30 by an insulating layer 40. The source 20, the drain 30 and the multiferroic semiconductor film 10 are in ohmic contact. In this embodiment, the multiferroic semiconductor film 10, the source 20, the drain 30, the insulating layer 40 and the gate 50 can simultaneously realize logical operations and data storage, thereby realizing storage and computing integration.

[0036] When a certain positive voltage is applied to the multiferroic semiconductor film 10 by the gate 50, a conductive channel is formed in the multiferroic semiconductor film 10, connecting the source 20 and the drain 30. At this time, the multiferroic semiconductor storage-computing integrated device is in the on state, which is represented by "1". When no voltage is applied to the multiferroic semiconductor film 10, the multiferroic semiconductor film 10 does not form a conductive channel, the source 20 and the drain 30 are disconnected, and the multiferroic semiconductor storage-computing integrated device is in the off state, which is represented by "0". The source-drain current can be controlled by changing the gate voltage, thereby controlling the "on" and "off" of the conductive channel to achieve logical operations.

[0037] At the same time, when a certain positive voltage is applied to the multiferroic semiconductor film 10 by the gate 50, the multiferroic semiconductor film 10 is magnetized, the gate voltage drops to 0, and the multiferroic semiconductor device still has residual electric polarization and residual magnetization, the electric polarization direction is upward, the magnetization direction is "up", and information is stored, which is represented as "1". When the gate 50 voltage is negative, the multiferroic semiconductor film 10 is in a disconnected state, the upward residual electric polarization of the multiferroic semiconductor film 10 is weakened until it flips downward, and demagnetization occurs, the magnetization of the multiferroic semiconductor device is weakened, and the gate voltage is gradually reduced to 0. At this time, the residual electric polarization of the multiferroic semiconductor device is downward, the residual magnetization is weakened, and the information is erased, which is represented as "0".

[0038] Furthermore, to read the stored information, a small current is applied to the multiferroic semiconductor film 10 through the source 20 and the drain 30, and the resistance of the multiferroic semiconductor film 10 is measured. When the magnetization is upward, the resistance is in a high resistance state, and the information is in a storage state, which is represented as "1". When the magnetization is weak, the resistance is in a low resistance state, and the information is in an erased state, which is represented as "0".

[0039] It should be noted that, for the multiferroic semiconductor storage-computing integrated device based on this architecture, applying voltage to the source and drain will not change the magnetization direction of the multiferroic semiconductor film 10.

[0040] The multiferroic semiconductor film 10 includes but is not limited to transition metal halides, sulfides (MX n , wherein M is one of chromium Cr, iron Fe, nickel Ni, cobalt Co, and manganese Mn, X is one of iodine I, bromine Br, chlorine Cl, and sulfur S, and n=1, 2, 3).

[0041] The drain electrode 30 and the source electrode 20 are disposed on both sides of the multiferroic semiconductor thin film 10 and separated by the multiferroic semiconductor thin film 10 .

[0042] Optionally, an insulating layer or barrier layer is provided between the gate 50 and the multiferroic semiconductor film 10. The insulating layer or barrier layer includes but is not limited to at least one of silicon dioxide SiO2, germanium dioxide GeO2, aluminum oxide Al2O3, hexagonal boron nitride hBN, and hafnium oxide HfO2.

[0043] The above-mentioned room-temperature multiferroic semiconductor storage and computing integrated device can simultaneously realize the storage function of a non-volatile memory and the switching function of an operator in a single multiferroic semiconductor.

[0044] Example 2

[0045] The cross-sectional structure diagram of the multiferroic semiconductor storage-computing integrated device provided in this embodiment is as follows: Figure 2 As shown, it includes a multiferroic semiconductor film 10 , a source electrode 20 , a drain electrode 30 , an insulating layer 40 , a substrate 50 , a bottom electrode 60 and a top electrode 70 .

[0046] The multiferroic semiconductor film 10 is an n-type semiconductor; the substrate 50 is a doped conductive silicon substrate, which serves as a gate. The gate 50 is isolated from the multiferroic semiconductor film 10, the source 20, and the drain 30 by an insulating layer 40. The source 20, the drain 30, the bottom electrode 60, the top electrode 70 are in ohmic contact with the multiferroic semiconductor film 10. In this example, the multiferroic semiconductor film 10, the source 20, the drain 30, the insulating layer 40, the gate 50, the bottom electrode 60, and the top electrode 70 can simultaneously realize logical operations and data storage, thereby realizing storage and computing integration.

[0047] When a certain positive voltage is applied to the multiferroic semiconductor film 10 by the gate 50, a conductive channel is formed in the multiferroic semiconductor film 10, connecting the source 20 and the drain 30. At this time, the multiferroic semiconductor storage-computing integrated device is in the on state, represented as "1"; when no voltage is applied to the multiferroic semiconductor film 10, the multiferroic semiconductor film 10 does not form a conductive channel, the source 20 and the drain 30 are disconnected, and the multiferroic semiconductor storage-computing integrated device is in the off state, represented as "0". The source-drain current can be controlled by changing the gate voltage, thereby controlling the "on" and "off" of the conductive channel to achieve logical operations.

[0048] At the same time, when a certain positive voltage is applied to the multiferroic semiconductor film 10 by the gate 50, the multiferroic semiconductor film 10 is magnetized, the gate voltage drops to 0, and the multiferroic semiconductor device still has residual electric polarization and residual magnetization, the electric polarization direction is upward, the magnetization direction is "up", and information is stored, which is represented as "1". When the gate 50 voltage is negative, the multiferroic semiconductor film 10 is in a disconnected state, the upward residual electric polarization of the multiferroic semiconductor film 10 is weakened until it flips downward, and demagnetization occurs, the magnetization of the multiferroic semiconductor device is weakened, and the gate voltage is gradually reduced to 0. At this time, the residual electric polarization of the multiferroic semiconductor device is downward, the residual magnetization is weakened, and the information is erased, which is represented as "0".

[0049] Furthermore, to read the stored information, a small voltage is applied to the multiferroic semiconductor film 10 through the bottom electrode 60 and the top electrode 70, and the tunneling current of the multiferroic semiconductor film 10 is measured. When the magnetization is upward, the tunneling current is large, which is a high current state, and the information is in the storage state, which is represented by "1". In the weak magnetization state, the tunneling current is small, which is a low current state, and the information is in the erased state, which is represented by "0".

[0050] It should be noted that, for the multiferroic semiconductor storage-computing integrated device based on this architecture, applying voltage to the source, drain, bottom electrode and top electrode will not change the magnetization direction of the multiferroic semiconductor film 10.

[0051] The multiferroic semiconductor film 10 includes but is not limited to transition metal halides, sulfides (MX n , wherein M is one of chromium Cr, iron Fe, nickel Ni, cobalt Co, and manganese Mn, X is one of iodine I, bromine Br, chlorine Cl, and sulfur S, and n=1, 2, 3).

[0052] The drain electrode 30 , the source electrode 20 , the bottom electrode 60 and the top electrode 70 are disposed on both sides of the multiferroic semiconductor thin film 10 and separated by the multiferroic semiconductor thin film 10 .

[0053] Optionally, an insulating layer or barrier layer is provided between the gate 50 and the multiferroic semiconductor film 10. The insulating layer or barrier layer includes but is not limited to at least one of silicon dioxide SiO2, germanium dioxide GeO2, aluminum oxide Al2O3, hexagonal boron nitride hBN, and hafnium oxide HfO2.

[0054] The above-mentioned room-temperature multiferroic semiconductor storage and computing integrated device can simultaneously realize the storage function of a non-volatile memory and the switching function of an operator in a single multiferroic semiconductor.

[0055] Example 3

[0056] The three-dimensional structure diagram of the multiferroic semiconductor storage and computing integrated device provided in this embodiment is as follows Figure 3 As shown, it includes a multiferroic semiconductor film 10 , a source electrode 20 , a drain electrode 30 , an insulating layer 40 , a substrate 50 , an upper electrode 60 and a lower electrode 70 .

[0057] The multiferroic semiconductor film 10 is an n-type semiconductor; the substrate 50 is a doped conductive silicon substrate, which serves as a gate. The gate 50 is isolated from the multiferroic semiconductor film 10, the source 20, the drain 30, the upper electrode 60, and the lower electrode 70 by the insulating layer 40. The source 20, the drain 30, the upper electrode 60, the lower electrode 70 are in ohmic contact with the multiferroic semiconductor film 10. In this embodiment, the multiferroic semiconductor film 10, the source 20, the drain 30, the insulating layer 40, the gate 50, the upper electrode 60, and the lower electrode 70 can simultaneously realize logical operations and data storage, thereby realizing storage and calculation integration.

[0058] When a certain positive voltage is applied to the multiferroic semiconductor film 10 by the gate 50, a conductive channel is formed in the multiferroic semiconductor film 10, connecting the source 20 and the drain 30. At this time, the multiferroic semiconductor storage-computing integrated device is in the on state, represented as "1"; when no voltage is applied to the multiferroic semiconductor film 10, the multiferroic semiconductor film 10 does not form a conductive channel, the source 20 and the drain 30 are disconnected, and the multiferroic semiconductor storage-computing integrated device is in the off state, represented as "0". The source-drain current can be controlled by changing the gate voltage, thereby controlling the "on" and "off" of the conductive channel to achieve logical operations.

[0059] At the same time, when a certain positive voltage is applied to the multiferroic semiconductor film 10 by the gate 50, the multiferroic semiconductor film 10 is magnetized, the gate voltage drops to 0, and the multiferroic semiconductor device still has residual electric polarization and residual magnetization, the electric polarization direction is upward, the magnetization direction is "up", and information is stored, which is represented as "1". When the gate 50 voltage is negative, the multiferroic semiconductor film 10 is in a disconnected state, the upward residual electric polarization of the multiferroic semiconductor film 10 is weakened until it flips downward, and demagnetization occurs, the magnetization of the multiferroic semiconductor device is weakened, and the gate voltage is gradually reduced to 0. At this time, the residual electric polarization of the multiferroic semiconductor device is downward, the residual magnetization is downward or weakened, and the information is erased, which is represented as "0".

[0060] Furthermore, to read the stored information, a small current is applied to the multiferroic semiconductor film 10 through the upper electrode 60 and the lower electrode 70, and the resistance of the multiferroic semiconductor film 10 is measured. When the magnetization is upward, the resistance is in a high resistance state, and the information is in a storage state, which is represented as "1". When the magnetization is weak, the resistance is in a low resistance state, and the information is in an erased state, which is represented as "0".

[0061] Furthermore, the reading of the stored information is achieved by reading the Hall voltage between the upper electrode 60 and the lower electrode 70. A small current is applied to the multiferroic semiconductor film 10 through the source 20 and the drain 30 to test the Hall voltage between the upper electrode 60 and the lower electrode 70. When the current is positive and the magnetization direction is upward, the Hall voltage between the electrode 60 and the lower electrode 70 is positive, and the information is in the storage state, which is represented as "1". When the current is positive and the magnetization direction is downward, the Hall voltage between the electrode 60 and the lower electrode 70 is negative, and the information is in the erased state, which is represented as "0".

[0062] Furthermore, multiferroic semiconductor devices based on this architecture can realize polymorphic storage:

[0063] When a certain positive voltage is applied to the multiferroic semiconductor film 10 by the gate 50, the upward polarization is saturated, the multiferroic semiconductor film 10 is polarized upward, the magnetization is upward, the gate voltage drops to 0, and the multiferroic semiconductor device still has residual polarization and residual magnetization, the polarization direction is upward, the magnetization direction is "up", and the information is stored, which is represented as "1";

[0064] When the gate 50 voltage is negative, the downward electric polarization is saturated. At this time, the multiferroic semiconductor film 10 is in an off state. The electric polarization of the multiferroic semiconductor film 10 is downward, and the magnetization is also downward. The gate voltage is gradually reduced to 0. At this time, the residual electric polarization of the multiferroic semiconductor device is downward, and the residual magnetization is downward. The information is erased and represented as "0".

[0065] When the gate 50 voltage is negative and less than the coercive field, the upward electric polarization is weakened but still upward. At this time, the multiferroic semiconductor film 10 is in an off state, the electric polarization of the multiferroic semiconductor film 10 is upward, and the magnetization is downward. The gate voltage is gradually reduced to 0. At this time, the residual electric polarization of the multiferroic semiconductor device is upward, and the residual magnetization is downward, and information is stored, which is represented by "2";

[0066] When the gate 50 voltage changes from negative to positive and is less than the coercive field, the downward polarization weakens but remains downward, and the multiferroic semiconductor film 10 is polarized upward and magnetized upward. The gate voltage is gradually reduced to 0. At this time, the residual polarization of the multiferroic semiconductor device is downward and the residual magnetization is upward, and information is stored, which is represented by "3".

[0067] The storage information can be read by simultaneously measuring the resistance of the source 20 and the drain 30 and the Hall voltage between the upper electrode 60 and the lower electrode 70 .

[0068] It should be noted that, for the multiferroic semiconductor storage-computing integrated device based on this architecture, applying voltage to the source, drain, upper electrode and lower electrode will not change the magnetization direction of the multiferroic semiconductor film 10.

[0069] The multiferroic semiconductor film 10 includes but is not limited to transition metal halides, sulfides (MX n , wherein M is one of chromium Cr, iron Fe, nickel Ni, cobalt Co, and manganese Mn, X is one of iodine I, bromine Br, chlorine Cl, and sulfur S, and n=1, 2, 3).

[0070] The drain electrode 30 , the source electrode 20 , the upper electrode 60 and the lower electrode 70 are disposed on both sides of the multiferroic semiconductor thin film 10 and separated by the multiferroic semiconductor thin film 10 .

[0071] Optionally, an insulating layer or barrier layer is provided between the gate 50 and the multiferroic semiconductor film 10. The insulating layer or barrier layer includes but is not limited to at least one of silicon dioxide SiO2, germanium dioxide GeO2, aluminum oxide Al2O3, hexagonal boron nitride hBN, and hafnium oxide HfO2.

[0072] The room temperature multiferroic semiconductor storage and computing integrated device provided in the above embodiment 1 can simultaneously realize the storage function of the non-volatile memory and the switching function of the operator in a single multiferroic semiconductor. Figure 4 As shown in the figure, the electric field achieves the regulation of the magnetic domains of the multiferroic semiconductor under zero magnetic field. It includes the 10 magnetic domain with magnetization upward and the 20 magnetic domain with magnetization downward. The arrow pointing upward indicates that the magnetization direction of the magnetic domain is upward, and the arrow pointing downward indicates that the magnetization direction of the magnetic domain is downward. When no voltage is applied, the 10 magnetic domain and the 20 magnetic domain are similar in size, opposite in direction, and do not show magnetization; when the voltage reaches V=15V, the 10 magnetic domain expands and magnetizes upward. By changing the voltage to regulate the magnetic domains of the multiferroic semiconductor, the storage function is realized.

[0073] It can be seen from the above embodiments that the present invention uses room temperature multiferroic semiconductor materials and field effect transistor logic to design a room temperature multiferroic semiconductor storage and computing integrated device under the application conditions of achieving high speed, low power consumption, low cost and stable operation at room temperature. By applying a gate voltage, a connecting channel is formed to realize the logic operation function of the multiferroic semiconductor operator; at the same time, the magnetization polarization is controlled by the gate voltage to realize the storage function of the multiferroic semiconductor memory and thus solve the "storage wall" problem between the memory and the operator.

Claims

1. A room temperature multiferroic semiconductor storage and computing integrated device, characterized in that: It includes a multiferroic semiconductor film, an insulating layer, a source electrode, a drain electrode and a gate electrode; The multiferroic semiconductor film is a transition metal halide or sulfide MX n , where M is chromium Cr, iron Fe, nickel Ni, cobalt Co or manganese Mn, X is iodine I, bromine Br, chlorine Cl or sulfur S, and n = 1, 2, 3; multiferroic semiconductor films have ferroelectricity and ferromagnetism, and their ferroelectric and ferromagnetic polarization directions can be changed by voltage; The source electrode and the gate electrode are arranged on the multiferroic semiconductor film, an insulating layer is arranged between the gate electrode and the multiferroic semiconductor film, the gate electrode and the multiferroic semiconductor film, the source electrode and the drain electrode are isolated from each other by the insulating layer, a conductive channel located in the multiferroic semiconductor film exists between the source electrode and the gate electrode, and the source electrode, the drain electrode and the multiferroic semiconductor film are in ohmic contact; The gate voltage is V GS The threshold voltage of the multiferroic semiconductor film is V T , the magnetic control threshold voltage of the multiferroic semiconductor film is V M , drain voltage V DS and gate voltage V GS Less than the breakdown voltage of the multiferroic semiconductor.

2. The room temperature multiferroic semiconductor storage and computing integrated device according to claim 1, characterized in that: When the magnetic control threshold voltage V M >Threshold voltage V for multiferroic semiconductor to conduct electricity T hour: If V GS <V T , and V GS <V M , the multiferroic semiconductor device is in the cut-off state; If V GS ≥V T , and V GS <V M , the multiferroic semiconductor device is in the on state and can only realize the computing function; If V GS ≥V T , and V GS ≥V M , the multiferroic semiconductor is in the on state, realizing the computing and storage functions at the same time, that is, realizing storage and computing integration.

3. The room temperature multiferroic semiconductor storage and computing integrated device according to claim 1, characterized in that: When the multiferroic semiconductor is powered, the threshold voltage V T >Magnetic control threshold voltage V M hour: If V GS <V T , and V GS <V M , the multiferroic semiconductor device is in the cut-off state; If V GS ≥V M , and V GS <V T , the multiferroic semiconductor device is in the on state and can only realize the storage function, realizing non-volatile magnetic memory; If V GS ≥V T , and V GS ≥V M , the multiferroic semiconductor is in the on state, realizing both computing and non-volatile storage functions, achieving storage and computing integration.

4. The room temperature multiferroic semiconductor storage and computing integrated device according to claim 1, characterized in that: When the gate voltage V T After it is positive and reaches the polarization saturation voltage, the electric polarization and magnetic polarization of the multiferroic semiconductor are both upward, and the gate voltage is gradually reduced until it reaches 0. At this time, the multiferroic semiconductor device has residual electric polarization and residual magnetization, the electric polarization direction is upward, the magnetization direction is upward, and the information is stored, which is represented by 1; When the applied gate voltage is negative and reaches the polarization saturation voltage, the upward residual electric polarization of the multiferroic semiconductor weakens until it flips downward, and the residual magnetization direction and intensity change accordingly. The gate voltage is gradually reduced to 0. At this time, the residual electric polarization of the multiferroic semiconductor device is downward, the residual magnetization is weakened or downward, and the information is erased, which is expressed as 0.

5. The room temperature multiferroic semiconductor storage and computing integrated device as claimed in claim 1, characterized in that: The insulating layer is SiO2, TiO2, ZnO, HfO2, Al2O3, GeO2 or hBN.

6. The room temperature multiferroic semiconductor storage and computing integrated device according to claim 1, characterized in that: The gate, source and drain are gold Au, silver Ag, copper Cu, aluminum Al, chromium Cr, platinum Pt, palladium Pd, p-type doped silicon substrate, n-type doped silicon substrate and / or graphene.

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