Drive circuit fault positioning device and air conditioning system

Abstract

The application discloses a drive circuit fault positioning device and an air conditioning system. The drive circuit fault positioning device comprises a main control chip connected with drive chips and capable of positioning abnormal switching tubes. The number of detection pins of the main control chip is less than the number of the drive chips, and at least one detection pin is connected with multiple drive chips. Compared with the prior art, the application can realize accurate positioning of multiple fault points by using less interfaces.

Description

Technical Field

[0001] This invention relates to air conditioning systems, and in particular to a drive circuit fault location device and an air conditioning system. Background Technology

[0002] IGBTs are high-frequency switching devices with high current density inside the chip. When an overcurrent or short-circuit fault occurs, the current flowing through the device exceeds the rated value, which can easily cause the junction temperature of the device die to become too high, leading to device damage. Therefore, as a crucial component of optical storage systems, the protection circuit of IGBTs is extremely important.

[0003] Generally, the driver chip of a power switch has a built-in fault feedback signal, which is returned to the fault judgment (TZ) port of the main control chip. Multiple fault feedback signals are returned to one TZ port, which makes it impossible to locate the fault after a fault occurs. In other cases, multiple fault feedback signals are returned to multiple corresponding TZ ports, resulting in insufficient TZ ports.

[0004] Therefore, how to design a drive circuit fault location device and air conditioning system that can achieve accurate fault location using fewer interfaces is a technical problem that the industry urgently needs to solve. Summary of the Invention

[0005] To address the problem that existing technologies cannot achieve accurate fault location with a limited number of interfaces, this invention proposes a drive circuit fault location device and an air conditioning system.

[0006] The technical solution of the present invention is to propose a drive circuit fault location device. The drive circuit includes multiple interconnected switching transistors and a drive chip that is matched and configured to control the on / off state of each switching transistor. The fault location device includes a main control chip connected to the drive chip. The number of detection pins of the main control chip is less than the number of drive chips, and at least one detection pin is connected to multiple drive chips. The main control chip can locate the abnormal switching transistor according to the level of the detection pin.

[0007] Furthermore, the driving circuit adopts a three-phase full-bridge circuit and includes switching transistors S1 and S2 for forming the first bridge arm, switching transistors S3 and S4 for forming the second bridge arm, switching transistors S5 and S6 for forming the third bridge arm, and a first driving chip matched with the switching transistor S1, a second driving chip matched with the switching transistor S2, a third driving chip matched with the switching transistor S3, a fourth driving chip matched with the switching transistor S4, a fifth driving chip matched with the switching transistor S5, and a sixth driving chip matched with the switching transistor S6.

[0008] Furthermore, the driver chip includes a first detection pin, a second detection pin, a third detection pin, and a fourth detection pin. The first detection pin is connected to the second driver chip, the fourth driver chip, and the sixth driver chip, respectively. The second detection pin is connected to the first driver chip and the second driver chip, respectively. The third detection pin is connected to the third driver chip and the fourth driver chip, respectively. The fourth detection pin is connected to the fifth driver chip and the sixth driver chip, respectively.

[0009] Furthermore, when the first detection pin and the second detection pin are at a low level, the main control chip determines that the switching transistor S2 is abnormal;

[0010] When the first detection pin is at a low level and the second detection pin is at a high level, the main control chip determines that the switching transistor S1 is abnormal.

[0011] When the first detection pin and the third detection pin are at a low level, the main control chip determines that the switching transistor S4 is abnormal;

[0012] When the first detection pin is at a low level and the third detection pin is at a high level, the main control chip determines that the switching transistor S3 is abnormal.

[0013] When the first detection pin and the fourth detection pin are at a low level, the main control chip determines that the switching transistor S6 is abnormal;

[0014] When the first detection pin is at a low level and the fourth detection pin is at a high level, the main control chip determines that the switching transistor S5 is abnormal.

[0015] Furthermore, the driver chip includes a first detection pin, a second detection pin, a third detection pin, and a fourth detection pin. The first detection pin is connected to the first driver chip and the fourth driver chip, the second detection pin is connected to the second driver chip and the fifth driver chip, the third detection pin is connected to the first driver chip, the second driver chip, and the third driver chip, and the fourth detection pin is connected to the sixth driver chip.

[0016] Furthermore, when the first detection pin and the third detection pin are at a low level, and the second detection pin is at a high level, the main control chip determines that the switching transistor S1 is abnormal;

[0017] When the first detection pin is at a low level, and the second detection pin and the third detection pin are at a high level, the main control chip determines that the switching transistor S4 is abnormal.

[0018] When the first detection pin is at a high level, and the second detection pin and the third detection pin are at a low level, the main control chip determines that the switching transistor S2 is abnormal.

[0019] When the first detection pin and the third detection pin are at a high level, and the second detection pin is at a low level, the main control chip determines that the switching transistor S5 is abnormal.

[0020] When the first detection pin and the second detection pin are at a high level, and the third detection pin is at a low level, the main control chip determines that the switching transistor S3 is abnormal.

[0021] When the fourth detection pin is at a low level, the main control chip determines that the switching transistor S6 is abnormal.

[0022] Furthermore, the driving circuit adopts a T-type three-level topology, which includes switching transistors S1, S2, and S3 for forming the first bridge arm, switching transistors S4, S5, and S6 for forming the second bridge arm, and switching transistors S7, S8, and S9 for forming the third bridge arm, as well as a first driving chip matched with the switching transistor S1, a second driving chip matched with the switching transistor S2, a third driving chip matched with the switching transistor S3, a fourth driving chip matched with the switching transistor S4, a fifth driving chip matched with the switching transistor S5, a sixth driving chip matched with the switching transistor S6, a seventh driving chip matched with the switching transistor S7, an eighth driving chip matched with the switching transistor S8, and a ninth driving chip matched with the switching transistor S9.

[0023] Furthermore, the driver chip includes a first detection pin, a second detection pin, a third detection pin, a fourth detection pin, and a fifth detection pin. The first detection pin is connected to the first driver chip, the fourth driver chip, and the seventh driver chip, respectively. The second detection pin is connected to the second driver chip, the fifth driver chip, and the eighth driver chip, respectively. The third detection pin is connected to the first driver chip, the second driver chip, and the third driver chip, respectively. The fourth detection pin is connected to the fourth driver chip, the fifth driver chip, and the sixth driver chip, respectively. The fifth detection pin is connected to the ninth driver chip.

[0024] Furthermore, when the first detection pin and the third detection pin are at a low level, and the second detection pin and the fourth detection pin are at a high level, the main control chip determines that the switching transistor S1 is abnormal;

[0025] When the first detection pin and the fourth detection pin are at a low level, and the second detection pin and the third detection pin are at a high level, the main control chip determines that the switching transistor S4 is abnormal.

[0026] When the first detection pin is low, and the second, third, and fourth detection pins are all high, the main control chip determines that the switching transistor S7 is abnormal.

[0027] When the first detection pin and the fourth detection pin are at a high level, and the second detection pin and the third detection pin are at a low level, the main control chip determines that the switching transistor S2 is abnormal.

[0028] When the first detection pin and the third detection pin are at a high level, and the second detection pin and the fourth detection pin are at a low level, the main control chip determines that the switching transistor S5 is abnormal.

[0029] When the first detection pin, the third detection pin, and the fourth detection pin are all at a high level, and the second detection pin is at a low level, the main control chip determines that the switching transistor S8 is abnormal.

[0030] When the first detection pin and the second detection pin are at a high level, and the third detection pin is at a low level, the main control chip determines that the switching transistor S3 is abnormal.

[0031] When the first detection pin and the second detection pin are at a high level, and the fourth detection pin is at a low level, the main control chip determines that the switching transistor S6 is abnormal.

[0032] When the fifth detection pin is at a low level, the main control chip determines that the switching transistor S9 is abnormal.

[0033] The present invention also proposes an air conditioning system having the above-mentioned drive circuit fault location device.

[0034] Compared with the prior art, the present invention has at least the following beneficial effects:

[0035] This invention adjusts the detection pins of the main control chip, enabling the accurate location of multiple fault points using fewer detection pins, i.e. fewer hardware interfaces, thus saving time and manpower for troubleshooting. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a connection diagram of a drive circuit fault location device according to an embodiment of the present invention;

[0038] Figure 2 for Figure 1 A schematic diagram of the judgment logic of the main control chip in the embodiment;

[0039] Figure 3 This is a connection diagram of the drive circuit fault location device according to another embodiment of the present invention;

[0040] Figure 4 for Figure 3 A diagram showing the relationship between the switching transistor and the detection pin in the embodiment;

[0041] Figure 5 for Figure 2 A schematic diagram of the judgment logic of the main control chip in the embodiment;

[0042] Figure 6 This is a diagram showing the relationship between the switching transistor and the detection pin in another embodiment of the present invention;

[0043] Figure 7 This is a connection diagram of the drive circuit fault location device according to another embodiment of the present invention;

[0044] Figure 8 for Figure 7 A diagram showing the relationship between the switching transistor and the detection pin in the embodiment. Detailed Implementation

[0045] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0046] Therefore, a feature pointed out in this specification is used to describe one feature of one embodiment of the invention, and does not imply that every embodiment of the invention must have the described feature. Furthermore, it should be noted that this specification describes many features. Although certain features may be combined to illustrate possible system designs, these features may also be used in other combinations not explicitly stated. Therefore, unless otherwise stated, the described combinations are not intended to be limiting.

[0047] The principles and structure of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0048] In typical driver circuits, the driver chip for the switching transistor has a built-in fault feedback signal. Traditional methods for troubleshooting switching transistor faults often involve: 1) connecting multiple fault feedback signals to a single hardware interface. While this method can determine if the driver circuit is faulty, it cannot accurately pinpoint the fault location; or 2) connecting one fault feedback signal to one hardware interface. While this method can accurately locate the fault location, it wastes a significant number of hardware interfaces. The present invention aims to precisely locate the fault point of the switching transistor by using fewer hardware interfaces and adjusting the connection method of these interfaces.

[0049] The driving circuit proposed in this invention includes multiple interconnected switching transistors and a driving chip matched to each switching transistor. Each driving chip can control the on / off state of the switching transistor connected to it, thereby realizing the control of the driving circuit. At the same time, each driving chip also has a fault detection function. When an overcurrent fault occurs in a switching transistor, the corresponding driving chip will send a low-level fault feedback signal, thereby determining that the switching transistor connected to it is abnormal.

[0050] The fault location device proposed in this invention includes a main control chip connected to a driver chip. The main control chip has multiple hardware interfaces, each of which is configured with a detection pin. The number of detection pins is less than the number of driver chips. In this invention, by allocating the connection methods between the detection pins and the driver chip, and then based on the voltage level on each detection pin, the abnormal switching transistor in the driver circuit can be accurately determined. Compared with the traditional method where one driver chip is connected to one detection pin, this method saves hardware interfaces of the main control chip and conserves resources.

[0051] Please see Figure 1 In one embodiment of the present invention, the driving circuit adopts a three-phase full-bridge circuit, which includes switching transistors S1 and S2 for forming the first bridge arm, switching transistors S3 and S4 for forming the second bridge arm, switching transistors S5 and S6 for forming the third bridge arm, and a first driving chip matched with the switching transistor S1. Figure 1 The S1 driver chip and the second driver chip matched with the switching transistor S2 are also mentioned. Figure 1 The S2 driver chip and the third driver chip matched with the switching transistor S3 (in the middle) Figure 1 The S3 driver chip in the middle), and the fourth driver chip matched with the switching transistor S4 ( Figure 1 The S4 driver chip in the middle), and the fifth driver chip matched with the switching transistor S5 ( Figure 1 The S5 driver chip), and the sixth driver chip matched with the switching transistor S6. Figure 1 (S6 driver chip in the middle). Each switching transistor has a corresponding driver chip, and when one of the switching transistors has an overcurrent fault, the corresponding driver chip can send a low-level fault feedback signal for subsequent detection pin detection and fault judgment.

[0052] In this embodiment, the present invention has four detection pins, each corresponding to a hardware interface. Compared with the traditional connection method, the present invention saves at least two hardware interfaces. Specifically, the driver chip includes a first detection pin, a second detection pin, a third detection pin, and a fourth detection pin. The first detection pin is connected to the second, third, and fourth driver chips, the second detection pin is connected to the first and second driver chips, the third detection pin is connected to the third and fourth driver chips, and the fourth detection pin is connected to the fifth and sixth driver chips.

[0053] Each detection pin can combine the fault feedback signals from the connected driver chip and output a corresponding level signal. The way each detection pin combines signals is consistent with an AND gate; it outputs a low-level signal upon receiving any low-level signal. Therefore, this invention, through the above connection method, can accurately locate the abnormality of six switching transistors. For example, when both the first and second detection pins are low, since the first detection pin is low, it can be determined that an abnormality has occurred in switching transistors S2, S4, and S6. Since the second detection pin is low, it can be further determined that switching transistors S1 and S2 are abnormal. Combining these two findings, the abnormality can be located in switching transistor S2.

[0054] Based on the above logic, the truth table for determining the abnormality of the switching transistor in this embodiment can be determined as follows:

[0055] TZ1 TZ2 TZ3 TZ4 Fault switch coding Case 1 1 0 1 1 S1 Case 2 0 0 1 1 S2 Case 3 1 1 0 1 S3 Case 4 0 1 0 1 S4 Case 5 1 1 1 0 S5 Case 6 0 1 1 0 S6

[0056] TZ1 represents the first detection pin, TZ2 represents the second detection pin, TZ3 represents the third detection pin, and TZ4 represents the fourth detection pin. 1 represents a high level and 0 represents a low level. It can be seen that the level of the detection pin is different for different switching transistors. Therefore, the specific abnormal switching transistor can be located by the level status of each detection pin.

[0057] Please see Figure 2 In this case, the judgment logic of the main control chip of the present invention is as follows:

[0058] When the first detection pin and the second detection pin are at a low level, the main control chip determines that the switch S2 is abnormal;

[0059] When the first detection pin is low and the second detection pin is high, the main control chip determines that the switching transistor S1 is abnormal.

[0060] When the first detection pin and the third detection pin are at a low level, the main control chip determines that the switching transistor S4 is abnormal;

[0061] When the first detection pin is low and the third detection pin is high, the main control chip determines that the switching transistor S3 is abnormal.

[0062] When the first detection pin and the fourth detection pin are at a low level, the main control chip determines that the switching transistor S6 is abnormal;

[0063] When the first detection pin is low and the fourth detection pin is high, the main control chip determines that the switching transistor S5 is abnormal.

[0064] In this invention, regardless of which switching transistor malfunctions, the fault will be indicated by an indicator light, and the drive circuit will be stopped for user maintenance. Figure 2 (The overcurrent in the above judgment logic, i.e., the exception)

[0065] Please see Figure 3 In addition to the driving circuit, the present invention also proposes another embodiment, in which the driving chip also has four detection pins, namely a first detection pin, a second detection pin, a third detection pin, and a fourth detection pin. The first detection pin is connected to the first driving chip and the fourth driving chip, the second detection pin is connected to the third driving chip and the fifth driving chip, the third detection pin is connected to the first driving chip, the second driving chip, and the third driving chip, and the fourth detection pin is connected to the sixth driving chip.

[0066] Please see Figure 4 By simplifying the above correspondence between detection pins and switching transistors, we can obtain a relationship diagram between detection pins and switching transistors. Based on this diagram, the truth table for detecting switching transistor malfunctions can be easily derived.

[0067] TZ1 TZ2 TZ3 TZ4 Fault switch coding Case 1 0 1 0 1 S1 Case 2 0 1 1 1 S4 Case 3 1 0 0 1 S2 Case 4 1 0 1 1 S5 Case 5 1 1 0 1 S3 Case 6 1 1 1 0 S6

[0068] TZ1 represents the first detection pin, TZ2 represents the second detection pin, TZ3 represents the third detection pin, and TZ4 represents the fourth detection pin. 1 represents a high level and 0 represents a low level. It can be seen that the level of the detection pin is different for different switching transistors. Therefore, the specific abnormal switching transistor can be located by the level status of each detection pin.

[0069] Please see Figure 5 According to this truth table, the judgment logic of the main control chip of this invention is as follows:

[0070] When the first detection pin and the third detection pin are at a low level, and the second detection pin is at a high level, the main control chip determines that the switching transistor S1 is abnormal.

[0071] When the first detection pin is low and the second and third detection pins are high, the main control chip determines that the switching transistor S4 is abnormal.

[0072] When the first detection pin is high and the second and third detection pins are low, the main control chip determines that the switching transistor S2 is abnormal.

[0073] When the first detection pin and the third detection pin are at a high level, and the second detection pin is at a low level, the main control chip determines that the switching transistor S5 is abnormal.

[0074] When the first detection pin and the second detection pin are at a high level, and the third detection pin is at a low level, the main control chip determines that the switching transistor S3 is abnormal.

[0075] When the fourth detection pin is low, the main control chip determines that the switching transistor S6 is abnormal.

[0076] Here, since the fourth detection pin is connected separately to the switching transistor S6, the abnormal state of the switching transistor S6 can be determined by its own voltage level, without needing to combine the states of the first, second, and third detection pins for judgment. Similar to the previous embodiment, as long as any abnormality is detected in any switching transistor, this invention will report a fault and shut down the drive circuit to facilitate user maintenance.

[0077] Furthermore, the present invention can also be applied to the driving circuit of a T-type three-level topology. In this topology, the driving circuit includes switching transistors S1, S2, and S3 for forming the first bridge arm, switching transistors S4, S5, and S6 for forming the second bridge arm, and switching transistors S7, S8, and S9 for forming the third bridge arm. It also includes a first driving chip matched with switching transistor S1, a second driving chip matched with switching transistor S2, a third driving chip matched with switching transistor S3, a fourth driving chip matched with switching transistor S4, a fifth driving chip matched with switching transistor S5, a sixth driving chip matched with switching transistor S6, a seventh driving chip matched with switching transistor S7, an eighth driving chip matched with switching transistor S8, and a ninth driving chip matched with switching transistor S9.

[0078] Please see Figure 6In this topology, the driver chip of the present invention is provided with five detection pins, namely the first detection pin, the second detection pin, the third detection pin, the fourth detection pin, and the fifth detection pin. The first detection pin is connected to the first driver chip, the fourth driver chip, and the seventh driver chip, respectively. The second detection pin is connected to the second driver chip, the fifth driver chip, and the eighth driver chip, respectively. The third detection pin is connected to the first driver chip, the second driver chip, and the third driver chip, respectively. The fourth detection pin is connected to the fourth driver chip, the fifth driver chip, and the sixth driver chip, respectively. The fifth detection pin is connected to the ninth driver chip.

[0079] pass Figure 6 The relationship diagram shown allows for easy determination of the truth table for switching transistor malfunction in this embodiment:

[0080] TZ1 TZ2 TZ3 TZ4 TZ5 Fault switch coding Case 1 0 1 0 1 1 S1 Case 2 0 1 1 0 1 S4 Case 3 0 1 1 1 1 S7 Case 4 1 0 0 1 1 S2 Case 5 1 0 1 0 1 S5 Case 6 1 0 1 1 1 S8 Case 7 1 1 0 1 1 S3 Case 8 1 1 1 0 1 S6 Situation 9 1 1 1 1 0 S9

[0081] TZ1 represents the first detection pin, TZ2 represents the second detection pin, TZ3 represents the third detection pin, TZ4 represents the fourth detection pin, and TZ5 represents the fifth detection pin. 1 represents a high level and 0 represents a low level. It can be seen that the level of the detection pin is different for different switching transistors. Therefore, the specific abnormal switching transistor can be located by the level status of each detection pin.

[0082] In this embodiment, the judgment logic of the main control chip of the present invention is as follows:

[0083] When the first detection pin and the third detection pin are at a low level, and the second detection pin and the fourth detection pin are at a high level, the main control chip determines that the switching transistor S1 is abnormal.

[0084] When the first detection pin and the fourth detection pin are at a low level, and the second detection pin and the third detection pin are at a high level, the main control chip determines that the switching transistor S4 is abnormal.

[0085] When the first detection pin is low and the second, third, and fourth detection pins are all high, the main control chip determines that the switching transistor S7 is abnormal.

[0086] When the first detection pin and the fourth detection pin are at a high level, and the second detection pin and the third detection pin are at a low level, the main control chip determines that the switching transistor S2 is abnormal.

[0087] When the first detection pin and the third detection pin are at a high level, and the second detection pin and the fourth detection pin are at a low level, the main control chip determines that the switching transistor S5 is abnormal.

[0088] When the first detection pin, the third detection pin, and the fourth detection pin are all at a high level, and the second detection pin is at a low level, the main control chip determines that the switching transistor S8 is abnormal.

[0089] When the first detection pin and the second detection pin are at a high level, and the third detection pin is at a low level, the main control chip determines that the switching transistor S3 is abnormal.

[0090] When the first detection pin and the second detection pin are at a high level, and the fourth detection pin is at a low level, the main control chip determines that the switching transistor S6 is abnormal.

[0091] When the fifth detection pin is low, the main control chip determines that the switching transistor S9 is abnormal.

[0092] Here, since the fifth detection pin is connected separately to the switching transistor S9, the abnormal state of the switching transistor S9 can be determined by its own voltage level, without needing to consider the states of the first, second, third, and fourth detection pins. Similar to the previous embodiment, this invention will report a fault and shut down the drive circuit as soon as any abnormality is detected in the switching transistor, facilitating user maintenance.

[0093] Furthermore, this invention can also be applied to a type I three-level main circuit topology; please refer to [link / reference]. Figure 7 In this topology, the driving circuit includes switching transistors S1, S2, S3, and S4 for forming the first bridge arm; switching transistors S5, S6, S7, and S8 for forming the second bridge arm; and switching transistors S9, S10, S11, and S12 for forming the third bridge arm. It also includes a first driving chip matched with switching transistor S1; a second driving chip matched with switching transistor S2; a third driving chip matched with switching transistor S3; a fourth driving chip matched with switching transistor S4; a fifth driving chip matched with switching transistor S5; a sixth driving chip matched with switching transistor S6; a seventh driving chip matched with switching transistor S7; an eighth driving chip matched with switching transistor S8; a ninth driving chip matched with switching transistor S9; a tenth driving chip matched with switching transistor S10; an eleventh driving chip matched with switching transistor S11; and a twelfth driving chip matched with switching transistor S12.

[0094] Please see Figure 8In this topology, the driver chip of the present invention is provided with two detection pins, namely a first detection pin, a second detection pin, a third detection pin, a fourth detection pin, a fifth detection pin, and a sixth detection pin. The first detection pin is connected to the first driver chip, the fourth driver chip, the seventh driver chip, and the tenth driver chip, respectively. The second detection pin is connected to the second driver chip, the fifth driver chip, the eighth driver chip, and the eleventh driver chip, respectively. The third detection pin is connected to the first driver chip, the second driver chip, and the third driver chip, respectively. The fourth detection pin is connected to the fourth driver chip, the fifth driver chip, and the sixth driver chip, respectively. The fifth detection pin is connected to the seventh driver chip, the eighth driver chip, and the ninth driver chip, respectively. The sixth detection pin is connected to the twelfth driver chip.

[0095] pass Figure 8 The relationship diagram shown allows for easy determination of the truth table for switching transistor malfunction in this embodiment:

[0096]

[0097]

[0098] TZ1 represents the first detection pin, TZ2 represents the second detection pin, TZ3 represents the third detection pin, TZ4 represents the fourth detection pin, TZ5 represents the fifth detection pin, and TZ6 represents the sixth detection pin. 1 represents a high level and 0 represents a low level. It can be seen that the level of the detection pin is different for different switching transistors. Therefore, the specific abnormal switching transistor can be located by the level status of each detection pin.

[0099] In this embodiment, the judgment logic of the main control chip of the present invention is as follows:

[0100] When the first and third detection pins are low, and the second, fourth, and fifth detection pins are high, the main control chip determines that the switching transistor S1 is abnormal.

[0101] When the first and fourth detection pins are low, and the second, third, and fifth detection pins are high, the main control chip determines that the switching transistor S4 is abnormal.

[0102] When the first and fifth detection pins are low, and the second, third, and fourth detection pins are high, the main control chip determines that the switching transistor S7 is abnormal.

[0103] When the first detection pin is low and the second, third, fourth, and fifth detection pins are high, the main control chip determines that the switching transistor S10 is abnormal.

[0104] When the second and third detection pins are low, and the first, fourth, and fifth detection pins are high, the main control chip determines that the switching transistor S2 is abnormal.

[0105] When the second and fourth detection pins are low, and the first, third, and fifth detection pins are high, the main control chip determines that the switching transistor S5 is abnormal.

[0106] When the second and fifth detection pins are low, and the first, third, and fourth detection pins are high, the main control chip determines that the switching transistor S8 is abnormal.

[0107] When the second detection pin is low and the first, third, fourth, and fifth detection pins are high, the main control chip determines that the switching transistor S11 is abnormal.

[0108] When the third detection pin is low and the first and second detection pins are high, the main control chip determines that the switching transistor S3 is abnormal.

[0109] When the fourth detection pin is low and the first and second detection pins are high, the main control chip determines that the switching transistor S6 is abnormal.

[0110] When the fifth detection pin is low and the first and second detection pins are high, the main control chip determines that the switching transistor S9 is abnormal.

[0111] When the sixth detection pin is low, the main control chip determines that the switching transistor S12 is abnormal.

[0112] In this embodiment, since the third detection pin is only connected to switching transistors S1, S2, and S3, the abnormal state of switching transistor S3 can be determined simply by combining the states of the first and second detection pins. Similarly, switching transistor S6 can be determined based on the states of the first, second, and fourth detection pins, and switching transistor S9 can be determined based on the states of the first, second, and fifth detection pins. For switching transistor S12, since it is only connected to the sixth detection pin, the abnormal state of switching transistor S12 can be determined solely by the state of the sixth detection pin. Similar to the previous embodiment, this invention will report a fault and shut down the drive circuit as soon as any abnormality is detected in any switching transistor, facilitating user maintenance.

[0113] In the above embodiments, the present invention provides application diagrams of three-phase full-bridge circuit, T-type three-level main circuit topology, and I-type three-level main circuit topology. However, the actual application of the present invention does not precede the above embodiments. It can be well adapted to any number of switching transistor topology circuits. As long as the judgment logic is consistent with the present invention, it should be within the protection scope of the present invention.

[0114] The present invention also proposes an air conditioning system having the above-mentioned drive circuit fault location device.

[0115] Compared with existing technologies, this invention adjusts the detection pins of the main control chip, which can use fewer detection pins, i.e. fewer hardware interfaces, to accurately locate multiple fault points, saving time and manpower for troubleshooting.

[0116] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A drive circuit fault location device, wherein the drive circuit includes a plurality of interconnected switching transistors and a drive chip that is matched and configured to control the on / off state of each switching transistor, characterized in that, The fault location device includes a main control chip connected to the driver chip. The number of detection pins of the main control chip is less than the number of driver chips, and at least one of the detection pins is connected to multiple driver chips. The main control chip can locate the abnormal switching transistor based on the level of the detection pin. The driving circuit adopts a three-phase full-bridge circuit and includes switching transistors S1 and S2 for forming the first bridge arm, switching transistors S3 and S4 for forming the second bridge arm, switching transistors S5 and S6 for forming the third bridge arm, and a first driving chip matched with the switching transistor S1, a second driving chip matched with the switching transistor S2, a third driving chip matched with the switching transistor S3, a fourth driving chip matched with the switching transistor S4, a fifth driving chip matched with the switching transistor S5, and a sixth driving chip matched with the switching transistor S6. The main control chip includes a first detection pin, a second detection pin, a third detection pin, and a fourth detection pin. The first detection pin is connected to the second driver chip, the fourth driver chip, and the sixth driver chip, respectively. The second detection pin is connected to the first driver chip and the second driver chip, respectively. The third detection pin is connected to the third driver chip and the fourth driver chip, respectively. The fourth detection pin is connected to the fifth driver chip and the sixth driver chip, respectively.

2. The drive circuit fault location device according to claim 1, characterized in that, When the first detection pin and the second detection pin are at a low level, the main control chip determines that the switching transistor S2 is abnormal; When the first detection pin is at a low level and the second detection pin is at a high level, the main control chip determines that the switching transistor S1 is abnormal. When the first detection pin and the third detection pin are at a low level, the main control chip determines that the switching transistor S4 is abnormal; When the first detection pin is at a low level and the third detection pin is at a high level, the main control chip determines that the switching transistor S3 is abnormal. When the first detection pin and the fourth detection pin are at a low level, the main control chip determines that the switching transistor S6 is abnormal; When the first detection pin is at a low level and the fourth detection pin is at a high level, the main control chip determines that the switching transistor S5 is abnormal.

3. A drive circuit fault location device, wherein the drive circuit includes a plurality of interconnected switching transistors and a drive chip that is matched and configured to control the on / off state of each switching transistor, characterized in that, The fault location device includes a main control chip connected to the driver chip. The number of detection pins of the main control chip is less than the number of driver chips, and at least one of the detection pins is connected to multiple driver chips. The main control chip can locate the abnormal switching transistor based on the level of the detection pin. The driving circuit adopts a three-phase full-bridge circuit and includes switching transistors S1 and S2 for forming the first bridge arm, switching transistors S3 and S4 for forming the second bridge arm, switching transistors S5 and S6 for forming the third bridge arm, and a first driving chip matched with the switching transistor S1, a second driving chip matched with the switching transistor S2, a third driving chip matched with the switching transistor S3, a fourth driving chip matched with the switching transistor S4, a fifth driving chip matched with the switching transistor S5, and a sixth driving chip matched with the switching transistor S6. The main control chip includes a first detection pin, a second detection pin, a third detection pin, and a fourth detection pin. The first detection pin is connected to the first driver chip and the fourth driver chip, the second detection pin is connected to the second driver chip and the fifth driver chip, the third detection pin is connected to the first driver chip, the second driver chip, and the third driver chip, and the fourth detection pin is connected to the sixth driver chip.

4. The drive circuit fault location device according to claim 3, characterized in that, When the first detection pin and the third detection pin are at a low level, and the second detection pin is at a high level, the main control chip determines that the switching transistor S1 is abnormal. When the first detection pin is low, and the second detection pin and the third detection pin are... When the signal is high, the main control chip determines that the switching transistor S4 is abnormal; When the first detection pin is at a high level, and the second detection pin and the third detection pin are at a low level, the main control chip determines that the switching transistor S2 is abnormal. When the first detection pin and the third detection pin are at a high level, and the second detection pin is at a low level, the main control chip determines that the switching transistor S5 is abnormal. When the first detection pin and the second detection pin are at a high level, and the third detection pin is at a low level, the main control chip determines that the switching transistor S3 is abnormal. When the fourth detection pin is at a low level, the main control chip determines that the switching transistor S6 is abnormal.

5. A drive circuit fault location device, wherein the drive circuit includes a plurality of interconnected switching transistors and a drive chip that is matched and configured to control the on / off state of each switching transistor, characterized in that, The fault location device includes a main control chip connected to the driver chip. The number of detection pins of the main control chip is less than the number of driver chips, and at least one of the detection pins is connected to multiple driver chips. The main control chip can locate the abnormal switching transistor based on the level of the detection pin. The driving circuit adopts a T-type three-level topology, which includes switching transistors S1, S2, and S3 for forming the first bridge arm, switching transistors S4, S5, and S6 for forming the second bridge arm, and switching transistors S7, S8, and S9 for forming the third bridge arm. It also includes a first driving chip matched with the switching transistor S1, a second driving chip matched with the switching transistor S2, a third driving chip matched with the switching transistor S3, a fourth driving chip matched with the switching transistor S4, a fifth driving chip matched with the switching transistor S5, a sixth driving chip matched with the switching transistor S6, a seventh driving chip matched with the switching transistor S7, an eighth driving chip matched with the switching transistor S8, and a ninth driving chip matched with the switching transistor S9. The main control chip includes a first detection pin, a second detection pin, a third detection pin, a fourth detection pin, and a fifth detection pin. The first detection pin is connected to the first driver chip, the fourth driver chip, and the seventh driver chip, respectively. The second detection pin is connected to the second driver chip, the fifth driver chip, and the eighth driver chip, respectively. The third detection pin is connected to the first driver chip, the second driver chip, and the third driver chip, respectively. The fourth detection pin is connected to the fourth driver chip, the fifth driver chip, and the sixth driver chip, respectively. The fifth detection pin is connected to the ninth driver chip.

6. The drive circuit fault location device according to claim 5, characterized in that, When the first detection pin and the third detection pin are at a low level, and the second detection pin and the fourth detection pin are at a high level, the main control chip determines that the switching transistor S1 is abnormal. When the first detection pin and the fourth detection pin are low, and the second detection pin and When the third detection pin is at a high level, the main control chip determines that the switching transistor S4 is abnormal; When the first detection pin is low, and the second, third, and fourth detection pins are all high, the main control chip determines that the switching transistor S7 is abnormal. When the first detection pin and the fourth detection pin are at a high level, and the second detection pin and the third detection pin are at a low level, the main control chip determines that the switching transistor S2 is abnormal. When the first detection pin and the third detection pin are at a high level, and the second detection pin and the fourth detection pin are at a low level, the main control chip determines that the switching transistor S5 is abnormal. When the first detection pin, the third detection pin, and the fourth detection pin are all at a high level, and the second detection pin is at a low level, the main control chip determines that the switching transistor S8 is abnormal. When the first detection pin and the second detection pin are at a high level, and the third detection pin is at a low level, the main control chip determines that the switching transistor S3 is abnormal. When the first detection pin and the second detection pin are at a high level, and the fourth detection pin is at a low level, the main control chip determines that the switching transistor S6 is abnormal. When the fifth detection pin is at a low level, the main control chip determines that the switching transistor S9 is abnormal.

7. An air conditioning system, characterized in that, The air conditioning system has a drive circuit fault location device as described in any one of claims 1 to 6.

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