Configurable algorithm design method and device, electronic equipment and readable storage medium

Abstract

The application relates to the technical field of algorithm design, and provides an algorithm design method, device, electronic equipment and computer readable storage medium, which comprises the following steps: obtaining an algorithm configuration request parameter, wherein the algorithm configuration request parameter carries an application code mark; determining a target application program corresponding to the algorithm configuration request parameter from a preset algorithm platform according to the application code mark; obtaining an operator list corresponding to the target application program from a preset memory mapping table according to the target application program, wherein the operator list carries stage execution sequence information used for representing an execution sequence of the operators; determining a corresponding executor combination according to the stage execution sequence information; and performing processing on the operator list based on the executor combination to obtain an algorithm execution result. Through the above technical scheme, the coupling of each module in algorithm design can be reduced, and the efficiency of algorithm development and design can be improved.

Description

Technical Field

[0001] The embodiments of this application relate to, but are not limited to, the field of algorithm design technology, and in particular to a configurable algorithm design method, apparatus, electronic device, and computer-readable storage medium. Background Technology

[0002] In the financial industry, there are often multiple working systems. With existing technologies, a single algorithm solution is frequently applied to multiple working system scenarios. To avoid redundant development, an algorithm middle platform is usually built to provide services in a tenantized manner. Currently, the middle platform solutions in the industry generally develop corresponding processing logic for business needs and control functional modules through simple development configurations. This results in strong coupling, low development efficiency, and an inability to meet the large-scale configuration needs of algorithm projects for multiple scenarios. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] To address the problems mentioned in the background section, embodiments of this application provide a configurable algorithm design method, apparatus, electronic device, and computer-readable storage medium, reducing the coupling between various modules in algorithm design and improving the efficiency of algorithm development and design.

[0005] In a first aspect, embodiments of this application provide a configurable algorithm design method, the method comprising:

[0006] Obtain algorithm configuration request parameters, wherein the algorithm configuration request parameters carry an application encoding tag;

[0007] The corresponding target application is determined from the preset algorithm platform based on the application encoding mark;

[0008] The target application retrieves a corresponding list of operators from a preset memory mapping table, wherein the list of operators carries stage execution order information that characterizes the execution order of operators;

[0009] The corresponding executor combination is determined based on the stage execution sequence information;

[0010] The algorithm execution result is obtained by performing the operation on the operator list based on the executor combination.

[0011] According to some embodiments of this application, the algorithm platform includes multiple target applications, each target application carrying application scenario attribute information, and the step of determining the corresponding target application from the preset algorithm platform based on the application encoding tag includes:

[0012] The application encoding mark is matched with the application scenario attribute information to obtain the application matching result;

[0013] The corresponding target application is selected from the algorithm platform based on the application matching result.

[0014] According to some embodiments of this application, the target application carries application scenario attribute information, the memory mapping table carries application execution marker information, and the step of obtaining the corresponding operator list from the preset memory mapping table according to the target application includes:

[0015] The application scenario attribute information and the application execution marker information are subjected to a second matching process to obtain the algorithm execution matching result;

[0016] The corresponding list of operators is selected from the memory mapping table based on the matching results obtained from the algorithm.

[0017] According to some embodiments of this application, determining the corresponding executor combination based on the stage execution sequence information includes:

[0018] The execution order information of the stages is split to obtain multiple stage execution parameters;

[0019] Multiple executors are selected from the algorithm platform based on the multiple stage execution parameters;

[0020] The actuator combination is obtained by combining multiple actuators.

[0021] According to some embodiments of this application, the operator list includes multiple stage operators, and the step of performing execution processing on the operator list based on the executor combination to obtain the algorithm execution result includes:

[0022] Execution information is determined by combining multiple stage operators with the executor;

[0023] The executor combination executes multiple stage operators sequentially according to the execution information to obtain the algorithm execution result.

[0024] According to some embodiments of this application, after performing execution processing on the operator list based on the executor combination to obtain the algorithm execution result, the method further includes:

[0025] The algorithm execution results are analyzed and processed to obtain algorithm execution effect information;

[0026] The operator list in the memory mapping table is adjusted based on the algorithm execution effect information to enable hot data refresh of the operator list in the memory mapping table.

[0027] According to some embodiments of this application, after performing execution processing on the operator list based on the executor combination to obtain the algorithm execution result, the method further includes:

[0028] Obtain the new algorithm configuration request parameters;

[0029] The new algorithm configuration request parameters are compared with the previous algorithm configuration request parameters to obtain the new algorithm configuration information;

[0030] The newly added stage operator is obtained from the memory mapping table based on the newly added algorithm configuration information;

[0031] The newly added stage operator is added to the previous operator list to form a new operator list;

[0032] The algorithm is re-executed on the list of operators to obtain a new result.

[0033] Secondly, embodiments of this application also provide a content recommendation device, the device comprising:

[0034] The first processing module is used to obtain algorithm configuration request parameters, wherein the algorithm configuration request parameters carry an application encoding tag;

[0035] The second processing module is used to determine the corresponding target application from the preset algorithm platform based on the application encoding mark;

[0036] The third processing module is used to obtain the corresponding operator list from a preset memory mapping table according to the target application, wherein the operator list carries stage execution order information for characterizing the execution order of operators;

[0037] The fourth processing module is used to determine the corresponding executor combination based on the stage execution sequence information;

[0038] The fifth processing module is used to perform execution processing on the operator list based on the executor combination to obtain the algorithm execution result.

[0039] Thirdly, embodiments of this application also provide an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the configurable algorithm design method described in the first aspect above.

[0040] Fourthly, embodiments of this application also provide a computer-readable storage medium storing computer-executable instructions for executing the configurable algorithm design method described in the first aspect above.

[0041] The configurable algorithm design method according to the embodiments provided in this application has at least the following beneficial effects: In the configurable algorithm design process, firstly, algorithm configuration request parameters are obtained, wherein the algorithm configuration request parameters carry application encoding tags; then, the corresponding target application is determined from a preset algorithm platform based on the application encoding tags; then, the corresponding operator list is obtained from a preset memory mapping table based on the target application, wherein the operator list carries stage execution order information used to characterize the execution order of operators; then, the corresponding executor combination is determined based on the stage execution order information; finally, the operator list is executed based on the executor combination to obtain the algorithm execution result. Through the above technical solution, the coupling of various modules in algorithm design is reduced, and the efficiency of algorithm development and design is improved. Attached Figure Description

[0042] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0043] Figure 1 This is a flowchart of a configurable algorithm design method provided in one embodiment of this application;

[0044] Figure 2 This is a flowchart illustrating the determination of a target application in a configurable algorithm design method provided in one embodiment of this application;

[0045] Figure 3 This is a flowchart illustrating the process of obtaining an operator list in a configurable algorithm design method provided in one embodiment of this application;

[0046] Figure 4 This is a flowchart illustrating the determination of executor combinations in a configurable algorithm design method provided in one embodiment of this application;

[0047] Figure 5 This is a flowchart illustrating the execution processing of an operator list in a configurable algorithm design method provided in one embodiment of this application;

[0048] Figure 6 This is a flowchart of a configurable algorithm design method provided in another embodiment of this application;

[0049] Figure 7 This is a flowchart of a configurable algorithm design method provided in another embodiment of this application;

[0050] Figure 8 This is a schematic diagram of a configurable algorithm design apparatus provided in one embodiment of this application;

[0051] Figure 9 This is a schematic diagram of an electronic device provided in one embodiment of this application. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0053] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0054] It should be noted that, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0055] In the financial industry, there are often multiple working systems. With existing technologies, a single algorithm solution is frequently applied to multiple working system scenarios. To avoid redundant development, an algorithm middle platform is usually built to provide services in a tenantized manner. Currently, the middle platform solutions in the industry generally develop corresponding processing logic for business needs and control functional modules through simple development configurations. This results in strong coupling, low development efficiency, and an inability to meet the large-scale configuration needs of algorithm projects for multiple scenarios.

[0056] A single algorithm solution is often used in multiple scenarios. To avoid redundant development, an algorithm platform is typically built to provide services in a tenantized manner. However, the basic data of multiple scenarios are generally different, and there are personalized requirements. Therefore, it is necessary to configure the algorithm to meet the needs of each business. During the development and iteration process of algorithm-related projects, there will be an iterative optimization process of "debug parameters - effect evaluation - re-debug parameters". In order to facilitate configuration changes and debugging and reduce the impact on business, it is best to modularize the algorithm and build a complete service through configuration component orchestration. In this way, each debugging only requires changing the configuration of the corresponding component, resulting in low coupling and good system stability. Finally, the algorithm configuration and the algorithm component itself should ideally provide hot refresh functionality to improve the efficiency of development iteration.

[0057] A robust algorithm platform needs to modularize and configurable algorithms, providing hot-refresh functionality, and flexibly orchestrate to serve multiple scenarios. Existing industry-standard platform solutions typically develop corresponding processing logic for each business requirement, controlling functional modules through simple on / off configurations. This not only results in strong coupling and low development efficiency but also fails to meet the extensive configuration needs of algorithm projects across multiple scenarios. Furthermore, as project requirements increase and complexity rises, it becomes difficult to maintain. The configurable algorithm design method proposed in this application addresses these issues, improving development efficiency, system flexibility, and stability.

[0058] This application provides a configurable algorithm design method, apparatus, electronic device, and computer-readable storage medium. In the configurable algorithm design process, firstly, algorithm configuration request parameters are obtained, wherein the algorithm configuration request parameters carry application encoding markers; then, the corresponding target application is determined from a preset algorithm platform based on the application encoding markers; next, the corresponding operator list is obtained from a preset memory mapping table based on the target application, wherein the operator list carries stage execution order information used to characterize the execution order of operators; then, the corresponding executor combination is determined based on the stage execution order information; finally, the operator list is executed based on the executor combination to obtain the algorithm execution result. Through the above technical solution, the coupling between various modules in algorithm design is reduced, and the efficiency of algorithm development and design is improved.

[0059] The configurable algorithm design method provided in this application relates to the field of algorithm design technology. This configurable algorithm design method can be applied to a terminal, a server, or software running on either a terminal or a server. In some embodiments, the terminal can be a smartphone, tablet, laptop, desktop computer, etc.; the server can be configured as an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms; the software can be an application implementing the configurable algorithm design method, but is not limited to the above forms.

[0060] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0061] It should be noted that in all specific embodiments of this application, when processing data related to user identity or characteristics, such as user information, user behavior data, user historical data, and user location information, user permission or consent is obtained first. Furthermore, the collection, use, and processing of this data comply with relevant laws, regulations, and standards of the relevant countries and regions. In addition, when embodiments of this application require access to sensitive personal information of users, separate permission or consent from the user is obtained through pop-ups or redirects to confirmation pages. Only after obtaining the user's separate permission or consent is the necessary user-related data for the proper functioning of the embodiments of this application obtained.

[0062] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0063] like Figure 1 As shown, Figure 1This is a flowchart of a configurable algorithm design method provided in one embodiment of this application. The configurable algorithm design method includes, but is not limited to, steps S100 to S500.

[0064] Step S100: Obtain algorithm configuration request parameters, wherein the algorithm configuration request parameters carry an application encoding tag;

[0065] Step S200: Determine the corresponding target application from the preset algorithm platform according to the application encoding mark;

[0066] Step S300: Obtain the corresponding operator list from the preset memory mapping table according to the target application, wherein the operator list carries stage execution order information used to characterize the execution order of operators;

[0067] Step S400: Determine the corresponding executor combination based on the stage execution sequence information;

[0068] Step S500: Perform execution processing on the operator list based on the executor combination to obtain the algorithm execution result.

[0069] It should be noted that in the configurable algorithm design process, the algorithm configuration request parameters are first obtained, which carry application encoding markers. Next, the corresponding target application is determined from a pre-defined algorithm platform based on the application encoding markers. Then, the corresponding operator list is obtained from a pre-defined memory mapping table based on the target application, where the operator list carries stage execution order information used to characterize the operator execution order. Next, the corresponding executor combination is determined based on the stage execution order information. Finally, the operator list is executed based on the executor combination to obtain the algorithm execution result. This technical solution reduces the coupling between various modules in the algorithm design and improves the efficiency of algorithm development and design.

[0070] It's important to note that the term "middle platform" is generally used in large enterprises. It typically refers to building a flexible and rapidly adaptable architecture to quickly fulfill front-end requirements, avoid redundant development, and improve work efficiency. As part of a platform-based organization, the middle platform is an organizational module between front-end requirement units and back-end resource departments. These modules are often what are traditionally called cost centers in organizations. They are responsible for integrating back-end resources into the "middleware" needed by the front-end, making them readily available for use. Middle platforms are divided into three categories: business middle platforms, data middle platforms, and organizational middle platforms. Business middle platforms are mostly traditional cost centers that integrate back-end resources into the "middleware" needed by the front-end, making them readily available for use. The "business middle platform" is also known as the "tangible middle platform" because it has a physical department. The data middle platform, which should be called the "datafication of the business middle platform," allows resources and capabilities to be highly shared, forming a data aggregation and enabling intelligent decision-making based on algorithms to support the operation of both the business and organizational middle platforms. The organizational middle platform is a team composed of business partners dispatched to the front end from departments such as finance, human resources, and strategy. The "organizational middle platform" is also known as the "intangible middle platform" because it lacks a physical department and permeates every business unit. For the algorithm middle platform, for multiple business needs, the algorithms all aim to achieve three goals: classification, regression, and clustering. In the process of building algorithms, only the algorithm interface needs to be developed. After defining the fields, training, optimization, and deployment can be quickly implemented. The algorithm code is universal, minimizing development effort. The algorithm middle platform provides visualized intelligent algorithm management functions through the task center module. Users can deploy algorithm services, configure algorithm logic, control algorithm start and stop, view algorithm running status, and monitor the utilization rates of various hardware components corresponding to the algorithm services through a visual interface.

[0071] It is worth noting that the algorithm configuration request parameter carries an application encoding tag, which corresponds to a target application and is unique; for example, if the target application has a tag 1, and the application encoding tag carried by the algorithm configuration request parameter is 1, then the algorithm configuration request parameter corresponds to the target application.

[0072] Understandably, the algorithm platform contains multiple target applications. The corresponding target application can be selected from the algorithm platform by using the application encoding tag carried in the algorithm configuration request parameters. Each target application corresponds to an operator list in the memory mapping table. The operator list carries stage execution order information to characterize the execution order of the operators. The corresponding executor combination can be determined by using the stage execution order information. Finally, the operator list is executed based on the executor combination to obtain the algorithm execution result.

[0073] It should be noted that a target application refers to a computer program designed to perform one or more specific tasks. It runs in user mode, can interact with the user, and has a visual user interface. Target applications are usually divided into two parts: a graphical user interface and an engine, which is different from the concept of application software. Application software refers to the purpose of use and can be a single program or a collection of other subordinate components.

[0074] It's important to note that a memory-mapped table maps a file to a block of memory. Similar to virtual memory, a memory-mapped table reserves a region of address space and allocates physical storage to this region. The physical storage for a memory-mapped file comes from a file that already exists on disk, and the file must be mapped before any operations can be performed on it. When using a memory-mapped table to process files stored on disk, I / O operations on the file are eliminated, making it particularly useful when handling large files.

[0075] It should be noted that an algorithm solution has multiple stages, such as preprocessing, business processing, and postprocessing. Therefore, operators are grouped by stage, and each stage consists of one or more operators. The stages are executed serially in the configured order.

[0076] In some embodiments, such as Figure 2 As shown, the algorithm platform includes multiple target applications, each of which carries application scenario attribute information. The above step S200 may include, but is not limited to, steps S210 to S220.

[0077] Step S210: Perform a first matching process between the application encoding mark and the application scenario attribute information to obtain the application matching result;

[0078] Step S220: Select the corresponding target application from the algorithm platform based on the application matching results.

[0079] It should be noted that the algorithm platform includes multiple target applications, each carrying application scenario attribute information. In the process of determining the corresponding target application, the application encoding mark is first matched with the application scenario attribute information to obtain the application matching result; then, the corresponding target application is selected from the algorithm platform based on the application matching result.

[0080] It is worth noting that in the process of performing the first matching process between the application encoding mark and the application scenario attribute information, the application encoding mark and the application scenario attribute information are compared and matched to obtain the matching result. For example, the application encoding mark is 3, and each target application carries application scenario attribute information. The application scenario attribute information can be marked starting from 1. In the process of matching and comparing the application encoding mark 3 with a number of application scenario attribute information, the target application whose application scenario attribute information is also 3 will be selected.

[0081] In some embodiments, such as Figure 3 As shown, the target application carries application scenario attribute information, and the memory mapping table carries application execution marker information. The above step S300 may include, but is not limited to, steps S310 to S320.

[0082] Step S310: Perform a second matching process on the application scenario attribute information and the application execution marker information to obtain the algorithm execution matching result;

[0083] Step S320: Select the corresponding operator list from the memory mapping table based on the matching result of the algorithm execution.

[0084] It should be noted that the target application carries application scenario attribute information, and the memory mapping table carries application execution marker information. During the selection of the operator list, the application scenario attribute information and the application execution marker information are subjected to a second matching process to obtain the algorithm execution matching result. Then, the corresponding operator list is selected from the memory mapping table based on the algorithm execution matching result.

[0085] It is worth noting that the target application carries application scenario attribute information, and the memory-mapped table carries application execution marker information. Therefore, performing a second matching process on the application scenario attribute information and the application execution marker information yields the algorithm execution matching result. Then, based on the algorithm execution matching result, the corresponding operator list is selected from the memory-mapped table. For example, if the target application carries an application scenario attribute of 2, and the memory-mapped table carries application execution marker information (which is a number starting from 1), the second matching process will select the operator list with the application execution marker information of 2 from the memory-mapped table. Furthermore, the corresponding operator list can be selected from the memory-mapped table based on the algorithm execution matching result.

[0086] It's important to clarify that a memory-mapped table maps a file to a block of memory. Similar to virtual memory, a memory-mapped table reserves a region of address space and allocates physical storage to this region. The physical storage for a memory-mapped file comes from a file that already exists on disk, and the file must be mapped before any operations can be performed on it. When processing files stored on disk using memory-mapped tables, I / O operations on the file are eliminated, making memory-mapped tables particularly useful when handling large files.

[0087] It should be noted that an algorithm solution has multiple stages, such as preprocessing, business processing, and postprocessing. Therefore, operators are grouped by stage, and each stage consists of one or more operators. The stages are executed serially in the configured order.

[0088] In some embodiments, such as Figure 4 As shown, step S400 may include, but is not limited to, steps S410, S420 and S430.

[0089] Step S410: The stage execution sequence information is split to obtain multiple stage execution parameters;

[0090] Step S420: Select multiple executors from the algorithm platform based on the execution parameters of multiple stages;

[0091] Step S430: Perform simultaneous processing on multiple actuators to obtain an actuator combination.

[0092] It should be noted that in the process of determining the executor combination, the execution order information of each stage is first split to obtain multiple stage execution parameters; then, multiple executors are selected from the algorithm platform based on the multiple stage execution parameters; finally, the multiple executors are combined to obtain the executor combination.

[0093] It is worth noting that the operator list carries stage execution order information to characterize the execution order of operators. By splitting the stage execution order information, multiple stage execution parameters can be obtained. Based on the multiple stage execution parameters, multiple executors corresponding to each stage execution parameter are selected from the algorithm platform. Each stage execution parameter corresponds to an executor. Finally, the selected multiple executors are combined to obtain the executor combination.

[0094] It should be noted that each executor can execute the operators of the corresponding stage. An algorithm scheme has multiple stages, such as preprocessing, business processing, postprocessing, etc. Therefore, the operators are grouped by stage, and each stage is composed of one or more operators. The stages are executed serially in the configured order.

[0095] It is worth noting that there are multiple executors in the algorithm platform. Based on the execution parameters of multiple stages, multiple corresponding executors can be selected from the algorithm platform. Finally, the multiple executors are processed in conjunction to obtain the executor combination. The executor combination can perform operation processing on the operator list in sequence.

[0096] In some embodiments, such as Figure 5 As shown, the operator list includes multiple stage operators, and the above step S500 may include, but is not limited to, steps S510 and S520.

[0097] Step S510: Determine execution information based on the combination of multiple stage operators and executors;

[0098] Step S520: The executor combines multiple stage operators to perform sequential execution processing based on the execution information, thereby obtaining the algorithm execution result.

[0099] It should be noted that the operator list includes multiple stage operators. During the execution of the algorithm, the execution information is first determined by combining multiple stage operators with the executor. Then, the executor combines the multiple stage operators in sequence according to the execution information to obtain the algorithm execution result.

[0100] It is worth noting that the execution information can be determined by combining multiple stage operators and executors. The executor combination includes multiple executors arranged in sequence, and each executor is arranged according to the order of execution. Therefore, the execution information can be determined by combining multiple stage operators and executors. Then, the multiple stage operators can be executed sequentially according to the execution information by combining the executors to obtain the algorithm execution result.

[0101] In some embodiments, such as Figure 6 As shown, after performing the above step S500, steps S610 and S620 may also be performed.

[0102] Step S610: Analyze and process the algorithm execution results to obtain algorithm execution effect information;

[0103] Step S620: Adjust the corresponding operator list in the memory mapping table according to the algorithm execution effect information so that the operator list in the memory mapping table can be hot refreshed.

[0104] It should be noted that after the algorithm execution result is obtained by performing the operation on the operator list based on the executor combination, the algorithm execution result can be analyzed to obtain the algorithm execution effect information. Then, the corresponding operator list in the memory mapping table is adjusted according to the algorithm execution effect information so that the operator list in the memory mapping table can be hot refreshed.

[0105] It's worth noting that cached data typically exists in key-value pairs, with the key containing the data itself and the keyword containing a descriptive name. The cache's capacity determines its maximum number of data entries. When the capacity is full, adding new data triggers a cleanup process: clearing out some of the existing data to make room for the new data. There are many cleanup strategies (determining when and how to clean up data), which determine the different types of caches. Hot data refresh records the number of times each stored data is used. Each call checks if the cache size exceeds its capacity; if so, cleanup begins, starting with the least frequently used data until the cache size is within its capacity.

[0106] It is understandable that analyzing the algorithm execution results means analyzing the algorithm's execution effect to obtain information about the algorithm's execution effect; finally, based on the algorithm execution effect information, the relevant execution parameters of the corresponding operator list in the memory mapping table are modified and adjusted so that better execution results can be obtained in the subsequent execution of related operators.

[0107] In some embodiments, such as Figure 7 As shown, after step S500, there may be steps S710, S720, S730, S740 and S750.

[0108] Step S710: Obtain new algorithm configuration request parameters;

[0109] Step S720: Compare the new algorithm configuration request parameters with the previous algorithm configuration request parameters to obtain the new algorithm configuration information;

[0110] Step S730: Obtain the newly added stage operator from the memory mapping table according to the newly added algorithm configuration information;

[0111] Step S740: Add the newly added stage operator to the previous operator list to form a new operator list;

[0112] Step S750: Re-process the operator list to obtain a new algorithm execution result.

[0113] It should be noted that after obtaining the algorithm execution result, new algorithm configuration request parameters can be obtained. Then, the new algorithm configuration request parameters are compared with the previous algorithm configuration request parameters to obtain the new algorithm configuration information. Next, the new stage operators are obtained from the memory mapping table based on the new algorithm configuration information. Then, the new stage operators are added to the previous operator list to form a new operator list. Finally, the operator list is re-executed to obtain the new algorithm execution result.

[0114] It is worth noting that by comparing the new algorithm configuration request parameters with the previous algorithm configuration request parameters, the new algorithm configuration information can be obtained. Based on the new algorithm configuration information, the new stage operators can be retrieved from the memory-mapped table without having to re-extract and load the entire operator list, making the algorithm configuration simpler and faster.

[0115] It is worth noting that this application proposes a configurable algorithm design method. This method modularizes algorithm classes, orchestrates them through configuration, provides suitable methods for instantiating operators, and groups operators by stage, providing execution methods within each stage, offering flexibility and scalability. At the configuration level, scenarios are abstracted into application configurations, with each application having a corresponding algorithm orchestration configuration file. This allows for personalized configurations for each algorithm class, resulting in a clear hierarchy, ease of maintenance, and the ability to meet the needs of numerous configurations and parameters in algorithm projects across multiple scenarios. Furthermore, configuration files are stored in a configuration center, and operators can be reinitialized through constructors, thus possessing hot-refresh capabilities. This meets the need for rapid feedback and parameter tuning during algorithm project development iterations, improving development efficiency. Additionally, multiple algorithm configurations can be defined within the same scenario to achieve testing, canary releases, and other functionalities. The system's modules exhibit low coupling, strong scalability, and excellent stability.

[0116] In addition, such as Figure 8 As shown, one embodiment of this application also provides a configurable algorithm design apparatus 10, comprising:

[0117] The first processing module 100 is used to obtain algorithm configuration request parameters, wherein the algorithm configuration request parameters carry application encoding tags;

[0118] The second processing module 200 is used to determine the corresponding target application from the preset algorithm platform according to the application encoding mark;

[0119] The third processing module 300 is used to obtain the corresponding operator list from the preset memory mapping table according to the target application, wherein the operator list carries stage execution order information used to characterize the execution order of operators;

[0120] The fourth processing module 400 is used to determine the corresponding executor combination based on the stage execution sequence information;

[0121] The fifth processing module 500 is used to perform execution processing on the operator list based on the executor combination to obtain the algorithm execution result.

[0122] The specific implementation of the configurable algorithm design device 10 is basically the same as the specific implementation of the configurable algorithm design method described above, and will not be repeated here.

[0123] In addition, such as Figure 9 As shown, one embodiment of this application also provides an electronic device 700, which includes: a memory 720, a processor 710, and a computer program stored on the memory 720 and executable on the processor 710.

[0124] The processor 710 and memory 720 can be connected via a bus or other means.

[0125] The non-transient software program and instructions required to implement the configurable algorithm design method of the above embodiments are stored in memory 720. When executed by processor 710, the configurable algorithm design method of each of the above embodiments is executed, for example, the above-described methods are executed. Figure 1 Method steps S100 to S500 Figure 2 Method steps S210 to S220, Figure 3 Method steps S310 to S320 in the text Figure 4 Method steps S410 to S430, Figure 5 Method steps S510 to S520 in the text Figure 6 Method steps S610 to S620 and Figure 7 Method steps S710 to S750.

[0126] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0127] Furthermore, one embodiment of this application also provides a computer-readable storage medium storing computer-executable instructions that are executed by a processor 710 or a controller, for example, by a processor 710 in the above-described device embodiment. These instructions cause the processor 710 to execute the configurable algorithm design method described above, for example, to perform the above-described [specific method / method]. Figure 1 Method steps S100 to S500 Figure 2 Method steps S210 to S220, Figure 3 Method steps S310 to S320 in the text Figure 4 Method steps S410 to S430, Figure 5 Method steps S510 to S520 in the text Figure 6 Method steps S610 to S620 and Figure 7 Method steps S710 to S750.

[0128] The above embodiments can be used in combination, and modules with the same name in different embodiments may be the same or different.

[0129] The foregoing has described specific embodiments of this application; other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims may be performed in a different order than those shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily have to follow the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0130] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of apparatus, devices, and computer-readable storage media are basically similar to the method embodiments, so the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0131] The apparatus, device, computer-readable storage medium and method provided in the embodiments of this application are corresponding. Therefore, the apparatus, device and non-volatile computer storage medium also have similar beneficial technical effects as the corresponding method. Since the beneficial technical effects of the method have been described in detail above, the beneficial technical effects of the corresponding apparatus, device and computer storage medium will not be described again here.

[0132] In the 1990s, improvements to a technology could be clearly distinguished as either hardware improvements (e.g., improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the methodology). However, with technological advancements, many methodological improvements today can be considered direct improvements to the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved methodology into the hardware circuit. Therefore, it cannot be said that a methodological improvement cannot be implemented using hardware physical modules. For example, a Programmable Logic Device (PLD) (such as a Field Programmable Gate Array (FPGA)) is such an integrated circuit whose logic function is determined by the user programming the device. Designers can program and "integrate" a digital system onto a PLD themselves, without needing chip manufacturers to design and manufacture dedicated integrated circuit chips. Furthermore, nowadays, instead of manually manufacturing integrated circuit chips, this programming is mostly implemented using "logic compiler" software. Similar to the software compiler used in program development, the original code before compilation must be written in a specific programming language, called a Hardware Description Language (HDL). There are many HDLs, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, and RHDL (Ruby Hardware Description Language). Currently, the most commonly used are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should understand that by simply performing some logic programming on the method flow using one of these hardware description languages ​​and programming it into an integrated circuit, the hardware circuit implementing the logical method flow can be easily obtained.

[0133] The controller can be implemented in any suitable manner. For example, it can take the form of a microprocessor or processor and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicon Labs C8051F320. A memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art will also recognize that, in addition to implementing the controller in purely computer-readable program code form, the same functionality can be achieved by logically programming the method steps to make the controller take the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, such a controller can be considered a hardware component, and the means included therein for implementing various functions can also be considered as structures within the hardware component. Alternatively, the means for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0134] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0135] For ease of description, the above apparatus is described by dividing it into various functional units. Of course, in implementing the embodiments of this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0136] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, embodiments of this application can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of this application can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0137] This specification is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0138] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0139] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0140] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0141] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0142] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0143] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0144] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the existence of A alone, A and B simultaneously, or B alone. A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of singular or plural items. For example, at least one of a, b, and c can represent: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, and c can be single or multiple.

[0145] The embodiments of this application can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. The embodiments of this application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In a distributed computing environment, program modules can reside in local and remote computer storage media, including storage devices.

[0146] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0147] The above description is merely an embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of this application should be included within the scope of the claims of this application.

Claims

1. A configurable algorithm design method, characterized in that, The method includes: Obtain algorithm configuration request parameters, wherein the algorithm configuration request parameters carry an application encoding tag; The corresponding target application is determined from the preset algorithm platform based on the application encoding mark; The target application retrieves a corresponding list of operators from a preset memory mapping table, wherein the list of operators carries stage execution order information that characterizes the execution order of operators; The corresponding executor combination is determined based on the stage execution sequence information; The operator list is processed based on the executor combination to obtain the algorithm execution result; Obtain new algorithm configuration request parameters; compare the new algorithm configuration request parameters with the previous algorithm configuration request parameters to obtain new algorithm configuration information; obtain new stage operators from the memory mapping table based on the new algorithm configuration information; add the new stage operators to the previous operator list to form a new operator list; The algorithm platform includes multiple target applications, each carrying application scenario attribute information. The step of determining the corresponding target application from the preset algorithm platform based on the application encoding marker includes: The application encoding mark is matched with the application scenario attribute information to obtain the application matching result; The corresponding target application is selected from the algorithm platform based on the application matching result; The target application carries application scenario attribute information, and the memory mapping table carries application execution marker information. The step of obtaining the corresponding operator list from the preset memory mapping table based on the target application includes: The application scenario attribute information and the application execution marker information are subjected to a second matching process to obtain the algorithm execution matching result; The corresponding list of operators is selected from the memory mapping table based on the matching results obtained from the algorithm.

2. The configurable algorithm design method according to claim 1, characterized in that, The step of determining the corresponding executor combination based on the stage execution sequence information includes: The execution order information of the stages is split to obtain multiple stage execution parameters; Multiple executors are selected from the algorithm platform based on the multiple stage execution parameters; The actuator combination is obtained by combining multiple actuators.

3. The configurable algorithm design method according to claim 1, characterized in that, The operator list includes multiple stage operators. The process of performing execution processing on the operator list based on the executor combination to obtain the algorithm execution result includes: Execution information is determined by combining multiple stage operators with the executor; The executor combination executes multiple stage operators sequentially according to the execution information to obtain the algorithm execution result.

4. The configurable algorithm design method according to claim 1, characterized in that, After performing the algorithm execution result by executing the operator list based on the executor combination, the method further includes: The algorithm execution results are analyzed and processed to obtain algorithm execution effect information; The operator list in the memory mapping table is adjusted based on the algorithm execution effect information to enable hot data refresh of the operator list in the memory mapping table.

5. The configurable algorithm design method according to claim 1, characterized in that, After adding the newly added stage operator to the previous operator list to form a new operator list, the method further includes: The algorithm is re-executed on the list of operators to obtain a new result.

6. A configurable algorithm design device, characterized in that, The device includes: The first processing module is used to obtain algorithm configuration request parameters, wherein the algorithm configuration request parameters carry an application encoding tag; The second processing module is used to determine the corresponding target application from the preset algorithm platform based on the application encoding mark; The third processing module is used to obtain the corresponding operator list from a preset memory mapping table according to the target application, wherein the operator list carries stage execution order information for characterizing the execution order of operators; The fourth processing module is used to determine the corresponding executor combination based on the stage execution sequence information; The fifth processing module is used to perform execution processing on the operator list based on the executor combination to obtain the algorithm execution result; Obtain new algorithm configuration request parameters; compare the new algorithm configuration request parameters with the previous algorithm configuration request parameters to obtain new algorithm configuration information; obtain new stage operators from the memory mapping table based on the new algorithm configuration information; add the new stage operators to the previous operator list to form a new operator list; The algorithm platform includes multiple target applications, each carrying application scenario attribute information. The step of determining the corresponding target application from the preset algorithm platform based on the application encoding marker includes: The application encoding mark is matched with the application scenario attribute information to obtain the application matching result; The corresponding target application is selected from the algorithm platform based on the application matching result; The target application carries application scenario attribute information, and the memory mapping table carries application execution marker information. The step of obtaining the corresponding operator list from the preset memory mapping table based on the target application includes: The application scenario attribute information and the application execution marker information are subjected to a second matching process to obtain the algorithm execution matching result; The corresponding list of operators is selected from the memory mapping table based on the matching results obtained from the algorithm.

7. An electronic device, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, when the processor executes the computer program, it implements the configurable algorithm design method as described in any one of claims 1 to 5.

8. A computer-readable storage medium storing computer-executable instructions, characterized in that, The computer-executable instructions are used to execute the configurable algorithm design method according to any one of claims 1 to 5.

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