Information processing device

Abstract

Embodiments of the present invention relate to a technology for controlling a non-volatile memory. An information processing device is provided that is capable of recovering an incomplete write to a storage system that has terminated abnormally or restarted unintentionally. According to the embodiment, the information processing device includes a non-volatile memory and a CPU. The CPU stores first data in the non-volatile memory, sends a first write request associated with the first data to the storage system for the first time, and stores first management data including information corresponding to the first write request in the non-volatile memory. In response to receiving a first response to the first write request sent for the first time, the CPU appends information indicating that the first response has been received to the management data.

Description

[0001] This application is based on and claims the benefit of priority from Japanese Patent Application No. 2021-144701 (filing date: September 6, 2021). The entire contents of this basic application are incorporated herein by reference. Technical Field

[0002] Embodiments of the present invention relate to a technology for controlling a nonvolatile memory. Background Art

[0003] In recent years, storage systems equipped with nonvolatile memory have become widely popular. As one such storage system, solid-state drives (SSDs) equipped with NAND flash memory are known. SSDs are used as main memory in various computing devices.

[0004] For example, when receiving a write request from the host, the storage system writes the user data received from the host in conjunction with the write request into the nonvolatile memory and returns a response to the host.

[0005] Alternatively, the storage system may write the user data in a specific data unit to the non-volatile memory after the total amount of user data requested to be written by multiple write requests received from the host reaches a specific data unit, and return responses corresponding to each of the multiple write requests to the host. For example, the specific data unit is the amount of data that can be written to the non-volatile memory in a single data write operation. Specifically, the storage system may employ a mechanism that does not immediately execute the write operation corresponding to a single received write request, but instead executes the write operation corresponding to the multiple write requests after the total amount of user data requested to be written by the multiple write requests reaches a specific data unit. This mechanism is hereinafter referred to as Delayed Write Completion.

[0006] In delayed write completion, for example, user data of a specific data unit (e.g., a write unit) including a plurality of user data corresponding to a plurality of write requests is written to the non-volatile memory, thereby enabling efficient use of the storage area of ​​the non-volatile memory. However, in delayed write completion, writing and responding to each write request can be delayed before accepting the plurality of write requests corresponding to the user data of the write unit.

[0007] However, in the storage system, a storage area (ie, a buffer) is sometimes provided for temporarily storing user data requested to be written from the host. In this case, the user data is transferred from the buffer to the nonvolatile memory and written into the nonvolatile memory.

[0008] Storage systems may also include a power-loss protection (PLP) function. The PLP function uses the energy from the charge stored in the storage system's power storage device to write user data stored in the buffer and not yet written to the non-volatile memory to the non-volatile memory if power to the storage system from an external power source is cut off. The PLP function allows the storage system to write user data stored in the buffer, requested by the host, to the non-volatile memory even in situations such as an unauthorized power outage.

[0009] On the other hand, storage systems may not have a buffer capable of protecting stored data using the PLP function. In this case, if the storage system abnormally terminates or is unintentionally restarted between the time the host accepts a write request and the time the user data associated with the write request is written to non-volatile memory, the write process corresponding to the accepted write request cannot be completed. Furthermore, if a write is performed based on delayed write completion, the storage system may not be able to complete the write process corresponding to multiple accepted write requests. Summary of the Invention

[0010] An embodiment of the present invention provides an information processing apparatus capable of recovering incomplete writing to a storage system that has terminated abnormally or restarted unintentionally.

[0011] According to an embodiment, an information processing device is connectable to a storage system. The information processing device includes a non-volatile memory and a processor. The processor stores first data in the non-volatile memory. The processor sends a first write request associated with the first data to the storage system for the first time. The processor stores first management data including information corresponding to the first write request in the non-volatile memory. In response to receiving a first response to the first write request sent for the first time from the storage system, the processor appends information indicating that the first response to the first write request sent for the first time has been received to the first management data. After receiving the first response, the processor deletes the first data and the first management data from the non-volatile memory in response to receiving a second response to the first write request sent for the first time from the storage system. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a block diagram showing a configuration example of an information processing system including an information processing device (host) and a storage system according to an embodiment.

[0013] Figure 2 This is a diagram showing a configuration example of a lock data list used in the information processing device of this embodiment.

[0014] Figure 3 It means in Figure 1 A diagram showing an example structure of a logical-physical address translation table used in a storage system.

[0015] Figure 4 It means in Figure 1 A diagram showing an example structure of a write management table used in a storage system.

[0016] Figure 5 Yes Figure 1 A block diagram of an example of a bind action in an information processing system.

[0017] Figure 6 Yes Figure 1 A block diagram of an example of a write operation in an information processing system.

[0018] Figure 7 It means in Figure 6 FIG. 1 is a diagram of a first example of a locked data list after being updated in a write operation.

[0019] Figure 8 It means in Figure 6 FIG2 is a diagram of a second example of the locked data list after being updated in the write operation of .

[0020] Figure 9 Yes Figure 6 Block diagram of an example of subsequent write operations.

[0021] Figure 10 It means in Figure 9 FIG. 1 is a diagram showing an example of a locked data list after being updated in a write action.

[0022] Figure 11 Yes Figure 1 A block diagram of an example of a shutdown action in an information processing system.

[0023] Figure 12 Yes Figure 11 Block diagram of an example of subsequent closing actions.

[0024] Figure 13 Yes Figure 1 A block diagram of an example of an unbinding action in an information processing system.

[0025] Figure 14 Yes Figure 1 A block diagram of an example of a recovery action in an information processing system.

[0026] Figure 15 Yes Figure 14 Block diagram of an example of subsequent recovery actions.

[0027] Figure 16 Yes Figure 15 Block diagram of an example of subsequent recovery actions.

[0028] Figure 17 This is a flowchart showing an example of the procedure of the binding process executed in the information processing apparatus according to this embodiment.

[0029] Figure 18 It means in Figure 1 A flowchart of an example of steps of a binding process performed in a storage system.

[0030] Figure 19 This is a flowchart showing an example of the procedure of a write request process executed in the information processing apparatus according to this embodiment.

[0031] Figure 20 It means in Figure 1 Flowchart of an example of steps of a write control process performed in a storage system.

[0032] Figure 21 This is a flowchart showing an example of the procedure of the response reception process executed in the information processing device according to this embodiment.

[0033] Figure 22 This is a flowchart showing an example of the procedure of the unbinding process executed in the information processing device according to this embodiment.

[0034] Figure 23 It means in Figure 1 A flowchart of an example of the steps of an unbinding process performed in a storage system.

[0035] Figure 24 This is a flowchart showing an example of the procedure of the shutdown process executed in the information processing apparatus according to this embodiment.

[0036] Figure 25 It means in Figure 1 A flowchart of an example of the steps of a shutdown process performed in a storage system.

[0037] Figure 26 This is a flowchart showing an example of the steps of the startup process executed in the information processing apparatus according to this embodiment.

[0038] Figure 27 This is a flowchart showing an example of the procedure of the recovery write request process executed in the information processing apparatus according to this embodiment.

[0039] Figure 28 It means in Figure 1 A flowchart of an example of steps of a startup process performed in a storage system.

[0040] Figure 29 This is a flowchart showing an example of the procedure of a recovery write request process executed by the information processing device according to this embodiment when a flash command (flash command) is used.

[0041] Figure 30 It means in Figure 1 A flowchart of an example of the steps of a write control process executed in a storage system using a flash memory command. DETAILED DESCRIPTION

[0042] Hereinafter, embodiments will be described with reference to the drawings.

[0043] First, refer to Figure 1 The configuration of an information processing system 1 including an information processing device according to an embodiment will be described. The information processing system 1 includes an information processing device 2 and a storage system 3 .

[0044] The information processing device 2 may be a storage server that stores a large amount of diverse data in the storage system 3 or a personal computer. Hereinafter, the information processing device 2 is also referred to as a host 2.

[0045] The storage system 3 is a semiconductor memory device configured to write data to a nonvolatile memory such as a NAND flash memory and read data from the nonvolatile memory. The storage system is also called a storage device. The storage system is implemented as a solid-state drive (SSD), for example.

[0046] The storage system 3 can be used as a storage for the host 2. The storage system 3 can be built into the host 2 or connected to the host 2 via a cable or a network.

[0047] The interface for connecting the host 2 and the storage system 3 complies with standards such as PCI Express (PCIe) (registered trademark), Ethernet (registered trademark), Fibre Channel, and NVM Express (NVMe) (registered trademark).

[0048] The following describes respective configuration examples of the host 2 and the storage system 3.

[0049] (Configuration example of host 2)

[0050] The host 2 includes, for example, a CPU 21 , a random access memory (RAM) 22 , a memory interface (memory I / F) 23 , and a nonvolatile random access memory (NVRAM) 24 . The CPU 21 , RAM 22 , memory I / F 23 , and NVRAM 24 may be connected via a bus 20 .

[0051] The CPU 21 is, for example, at least one processor and controls the operations of various components within the host computer 2 .

[0052] RAM 22 is a volatile memory. RAM 22 is implemented as, for example, dynamic random access memory (DRAM) or static random access memory (SRAM). The storage area of ​​RAM 22 is allocated to, for example, an operating system (OS) 221, a driver 222, and various application programs. Hereinafter, application programs are also referred to as applications.

[0053] The memory I / F 23 functions as a control circuit for controlling communication between the host 2 and the storage system 3. The memory I / F 23 sends various commands to the host 2, such as input / output (I / O) commands and various control commands. I / O commands include, for example, write commands and read commands. Control commands include, for example, flash (flush) commands, virtual PLP drive mode transfer commands, virtual PLP drive mode release commands, recovery mode transfer commands, and recovery mode release commands. The virtual PLP drive mode transfer command is also referred to as a first mode transfer command. The virtual PLP drive mode release command is also referred to as a first mode release command. The recovery mode transfer command is also referred to as a second mode transfer command. The recovery mode release command is also referred to as a second mode release command.

[0054] The flash memory command is a command for writing user data that has not been written into the NAND flash memory 5 of the storage system 3 from the host 2 or a storage area within the storage system 3 into the NAND flash memory 5 of the storage system 3 .

[0055] The first mode transition command is used to transition the storage system 3 from the normal drive mode to the virtual power-off protection drive mode (virtual PLP drive mode). The first mode transition command, for example, includes identification information (host ID) of the host 2 that issued the first mode transition command. The host ID is information that allows the storage system 3 to uniquely identify a host. For example, the host identifier specified in the NVMe standard is used as the host ID.

[0056] In the storage system 3, either the normal drive mode or the virtual PLP drive mode is set to the first operation mode. The host 2 provides a virtual power-off protection function (virtual PLP function) to the storage system 3 that has been switched to the virtual PLP drive mode (i.e., the storage system 3 whose first operation mode is the virtual PLP drive mode). The virtual PLP function uses data stored in the NVRAM 24 to recover user data written to the storage system 3 (more specifically, the NAND flash memory 5) that could not be completed due to abnormal termination caused by the host 2, abnormal power failure of the storage system 3, or unintentional restart of the storage system 3.

[0057] Hereinafter, a storage system 3 that has been switched to the virtual PLP drive mode by the host 2 in response to the first mode switch command is also referred to as a storage system 3 operating in the virtual PLP drive mode with respect to the host 2. Furthermore, the host 2 does not provide the virtual PLP function to a storage system 3 that has not been switched to the virtual PLP drive mode (i.e., a storage system 3 whose first operating mode is the normal drive mode).

[0058] The first mode release command is a command for causing the storage system 3 to shift from the virtual PLP drive mode to the normal drive mode.

[0059] The second mode transition command is a command for transitioning the storage system 3 from the normal write mode to the recovery write mode. In the storage system 3, either the normal write mode or the recovery write mode is set as the second operation mode. In the storage system 3 that has transitioned to the recovery write mode (i.e., the storage system 3 whose second operation mode is the recovery write mode), it is guaranteed that the write processing corresponding to the write command received from the host 2 is executed in the order in which the write commands were received. In addition, in the storage system 3 that has not transitioned to the recovery write mode (i.e., the storage system 3 whose second operation mode is the normal write mode), it may not be guaranteed that the write processing corresponding to the write command received from the host 2 is executed in the order in which the write commands were received.

[0060] The second mode release command is a command for causing the storage system 3 to shift from the recovery write mode to the normal write mode.

[0061] NVRAM 24 is a nonvolatile memory. Examples of NVRAM 24 include MRAM (Magnetoresistive Random Access Memory), PRAM (Phase Change Random Access Memory), ReRAM (Resistive Random Access Memory), and FeRAM (Ferroelectric Random Access Memory). The storage area of ​​NVRAM 24 is allocated to store various data used for processing by the host 2, a buffer area serving as a data buffer 242, an area for a submission queue (SQ) 243, an area for a completion queue (CQ) 244, and an area for storing a pointer list 246.

[0062] The data buffer 242 is a storage area for temporarily storing user data to be written to the NAND flash memory 5 of the storage system 3 .

[0063] The commit queue 243 is a queue for storing commands in order to send the commands from the host 2 to the storage system 3 .

[0064] The completion queue 244 is a queue for storing responses (completions) in order to return responses (completions) from the storage system 3 to the host 2. The storage system 3 can respond with multiple completions for one write command.

[0065] Furthermore, the host 2 may also implement additional submission queues 243 and completion queues 244 for each type of command, such as management commands, read commands, and input / output commands such as write commands, for each storage system 3. Furthermore, the host 2 may implement multiple submission queues 243 and completion queues 244 for input / output commands for each storage system 3. In this embodiment, the submission queues 243 and completion queues 244 are implemented in the NVRAM 24, but submission queues 243 and completion queues 244 other than those for write commands may also be implemented in the RAM 22.

[0066] The pointer list 246 is a list of pointers indicating the locations of user data associated with a write command or a read command on the data buffer 242. In this embodiment, the pointer list 246 is stored in the NVRAM 24, but the pointer list 246 may also be stored in the RAM 22.

[0067] Various data used in the processing of the host 2 include, for example, a virtual PLP drive ID 241 and a locked data list 245 .

[0068] The virtual PLP drive ID 241 indicates the identification information (drive ID) of the storage system 3 that the host 2 has switched to the virtual PLP drive mode. The drive ID is information that allows the host 2 to uniquely identify a single storage system 3. Furthermore, if the host 2 switches multiple storage systems 3 to the virtual PLP drive mode, the NVRAM 24 stores multiple virtual PLP drive IDs 241 corresponding to the multiple storage systems 3.

[0069] The lock data list 245 is data used to manage the processing status of write commands issued from the host 2 to the storage system 3. One lock data list 245 corresponds to, for example, one storage system 3. More specifically, one lock data list 245 is associated with, for example, the virtual PLP drive ID 241 of the corresponding storage system 3.

[0070] Alternatively, multiple lock data lists 245 corresponding to multiple storage systems 3 may be stored in the NVRAM 24. In this case, each of the multiple lock data lists 245 is associated with the virtual PLP drive ID 241 of a corresponding storage system 3. In other words, the host 2 can use the virtual PLP drive ID 241 of a storage system 3 to identify the lock data list 245 to be used for that storage system 3.

[0071] Figure 2 The following shows an example structure of the lock data list 245 used by the host 2. The lock data list 245 may include one or more entries corresponding to one or more write commands sent from the host 2 to the storage system 3. Each entry includes, for example, an SQ entry information field, a completion order field, a data area management information field, and a completion status field.

[0072] The SQ Entry Information field contains information representing the corresponding write instruction (SQ Entry Information). The SQ Entry Information includes information such as the instruction type, content, and parameters required for execution. Specifically, the SQ Entry Information field includes, for example, the instruction opcode, data pointer, instruction ID, namespace ID, LBA (Logical Block Address), and data length.

[0073] The instruction opcode is a code indicating the type of the corresponding instruction (here, a write instruction). As the instruction opcode, for example, an Opcode determined by the NVMe standard is used.

[0074] The data pointer is information indicating the location where user data to be written according to the corresponding write instruction is stored in the host 2. As a data pointer, for example, a physical region page (PRP: Physical RegionPage) entry or its list, or a scatter gather list (SGL: Scatter Gather List) specified by the NVMe standard is used. When PRP is used in a case where the amount of data is large, a pointer to the list of PRP entries is saved in the SQ entry information field. When SGL is used, only the first segment of the SGL is saved in the SQ entry information field. In addition, the list of PRP entries and the second and subsequent segments of the SGL are saved in the pointer list 246.

[0075] The command ID is identification information of the corresponding write command.

[0076] The namespace ID is information identifying the namespace in which the corresponding write instruction should be executed. Multiple logical address spaces (LBA spaces) may exist for host 2 to access storage system 3. Each logical address space is sometimes referred to as a namespace. One of the multiple namespaces can be identified by the namespace ID.

[0077] The LBA is the LBA specified by the corresponding write command and indicates the beginning LBA of the LBA range into which the user data should be written according to the write command.

[0078] The data length is the data length specified by the corresponding write instruction. This data length indicates the length of the user data to be written according to the write instruction. Therefore, by specifying the LBA and data length with the write instruction, the LBA range of the user data to be written according to the write instruction can be determined.

[0079] The Completion Order field indicates the order in which the first completion for the corresponding write command was received. Each of the one or more completions received by the host 2 is assigned a sequence number in the order in which they were received. The Completion Order field indicates the sequence number assigned to the first completion for the corresponding write command.

[0080] The data area management information field indicates information that can identify the storage area (e.g., page) within the NVRAM 24 that stores user data to be written according to the corresponding write command. For example, this information can be used to lock or unlock the identified storage area in the NVRAM 24 using the functions of the OS 221.

[0081] The completion status field indicates whether the first completion for the corresponding write instruction has been received. In addition, the completion status field can be omitted to store a sequence number in the completion order field to indicate that the first completion for the corresponding write instruction has been received.

[0082] In the following description of the lock data list 245, the value indicated in the SQ entry information field is also referred to simply as SQ entry information. The same applies to the values ​​indicated in the other fields of the lock data list 245 and the values ​​indicated in the fields of other tables.

[0083] return Figure 1 Here, the program executed by the CPU 21 is described.

[0084] The CPU 21 executes various programs loaded from the NVRAM 24 to the RAM 22, for example. The programs executed by the CPU 21 include an OS 221, a driver 222, and various applications.

[0085] The OS 221 is a program for controlling basic operations of various components within the host computer 2. The CPU 21 executing the OS 221 controls, for example, input and output, file management, memory management, and communication.

[0086] The driver 222 is a program for controlling devices connected to the host 2. For example, the CPU 21 executing the driver 222 sends a command or data to the storage system 3 via the memory I / F 23. The CPU 21 executing the driver 222 receives a response or data to the command from the storage system 3 via the memory I / F 23.

[0087] The CPU 21 functions as, for example, a command issuing unit 211, a write management unit 212, and a recovery control unit 213 by executing the driver 222. Figures 5 to 16 Specific operations of the command issuing unit 211 , the write management unit 212 , and the recovery control unit 213 : The command issuing unit 211 , the write management unit 212 , and the recovery control unit 213 may be implemented by dedicated hardware in the host 2 .

[0088] (Configuration Example of Storage System 3)

[0089] The storage system 3 includes, for example, a controller 4, a NAND flash memory 5, and a DRAM 6. The controller 4 can be implemented as a system-on-a-chip (SoC) circuit. The controller 4 can also have an internal SRAM. Alternatively, the DRAM 6 can be built into the controller 4.

[0090] The DRAM 6 is a volatile memory. In a RAM such as the DRAM 6, for example, a storage area for firmware (FW) 61, a cache area for a logical-physical address conversion table 62, and a storage area for a write management table 63 are provided.

[0091] The FW 61 is a program for controlling the operation of the controller 4. The FW 61 is loaded into the DRAM 6 from the NAND flash memory 5, for example.

[0092] The logical-physical address conversion table 62 manages mappings between each logical address and each physical address of the NAND flash memory 5 .

[0093] The write management table 63 manages information related to received write commands.

[0094] The NAND flash memory 5 includes multiple blocks. Each block includes multiple pages. A block serves as the minimum unit for data erase operations. Blocks are sometimes referred to as "erase blocks" or "physical blocks." Each page includes multiple memory cells connected to a single word line. A page functions as a unit for data write and read operations. Furthermore, a word line can also function as a unit for data write and read operations.

[0095] The number of program / erase cycles (P / E cycles) for each block has an upper limit, called the maximum P / E cycle number. A single P / E cycle for a block includes both an erase operation (erasing all memory cells in the block) and a program operation (programming) to write data to each page of the block.

[0096] For example, user data and management data can be written to the NAND flash memory 5. User data is data to be written to the NAND flash memory 5 in association with a write command received from the host 2. Management data is data used to manage the operation of the storage system 3. For example, the management data includes a virtual PLP host ID 51, first mode information 52, and a command log 53.

[0097] The virtual PLP host ID 51 indicates the host ID of the host 2 that shifts the storage system 3 to the virtual PLP drive mode. The virtual PLP host ID 51 is stored in the NAND flash memory 5 while the storage system 3 operates in the virtual PLP drive mode.

[0098] The first mode information 52 indicates whether the first operation mode of the storage system 3 is the normal drive mode or the virtual PLP drive mode. When the storage system 3 transitions from the normal drive mode to the virtual PLP drive mode, the first mode information 52 is updated to indicate the virtual PLP drive mode. Furthermore, when the storage system 3 transitions from the virtual PLP drive mode to the normal drive mode, the first mode information 52 is updated to indicate the normal drive mode.

[0099] The command log 53 shows the command IDs of the commands whose corresponding processing has been completed. The command log 53 is used for debugging the storage system 3. The controller 4 stores the command IDs in the command log 53 so that the order in which the processing corresponding to the commands is completed can be managed.

[0100] The controller 4 functions as a memory controller configured to control the NAND flash memory 5 .

[0101] The controller 4 can also function as a flash translation layer (FTL) configured to perform data management and block management of the NAND flash memory 5. The data management performed by the FTL includes: (1) management of mapping information indicating the correspondence between each logical address and each physical address of the NAND flash memory 5, and (2) processing for hiding the difference between page-based read / write operations and block-based erase operations. Block management includes management of bad blocks, wear leveling, and garbage collection.

[0102] The logical address is used by the host 2 to specify the address of the storage system 3. The logical address is, for example, a logical block address (LBA). The following mainly illustrates the case where LBA is used as the logical address.

[0103] The management of the mapping between each LBA and each physical address is performed using the logical-physical address translation table 62. The controller 4 uses the logical-physical address translation table 62 to manage the mapping between each LBA and each physical address in a specific management size unit. The physical address corresponding to a certain LBA represents the physical storage location in the NAND flash memory 5 where the data of the LBA is written. The controller 4 uses the logical-physical address translation table 62 to manage the multiple storage areas formed by logically dividing the storage area of ​​the NAND flash memory 5. These multiple storage areas correspond to multiple LBAs respectively. That is, these multiple storage areas are each determined by one LBA. The logical-physical address translation table 62 can also be loaded from the NAND flash memory 5 to the DRAM 6 when the power of the storage system 3 is turned on.

[0104] Data writing to one page can be performed only once in each P / E cycle. Therefore, instead of writing the updated data corresponding to a certain LBA to the physical storage location of the previous data corresponding to the LBA, the controller 4b writes it to another physical storage location. Then, the controller 4 updates the logical-physical address translation table 62 by associating the LBA with the other physical storage location, thereby invalidating the previous data. The data referenced from the logical-physical address translation table 62 (i.e., data associated with the LBA) is called valid data. In addition, data that is not associated with any LBA is called invalid data. Valid data is data that may be read from the host 2 later. Invalid data is data that has no possibility of being read from the host 2.

[0105] The controller 4 may also include a host interface (host I / F) 11, a CPU 12, a NAND interface (NAND I / F) 13, a DRAM interface (DRAM I / F) 14, and a timer 15. The host I / F 11, CPU 12, NAND I / F 13, DRAM I / F 14, and timer 15 may also be connected via a bus 10.

[0106] The host I / F 11 functions as a circuit for receiving various commands, such as I / O commands and various control commands, from the host 2 , and also functions as a circuit for transmitting responses or data to the host 2 .

[0107] The NAND I / F 13 electrically connects the controller 4 and the NAND flash memory 5. The NAND I / F 13 complies with interface standards such as Toggle DDR and OpenNAND Flash Interface (ONFI).

[0108] The NAND I / F 13 functions as a NAND control circuit configured to control the NAND flash memory 5. The NAND I / F 13 may be connected to a plurality of memory chips within the NAND flash memory 5 via a plurality of channels (Ch). By driving the plurality of memory chips in parallel, the access bandwidth to the entire NAND flash memory 5 can be increased.

[0109] The DRAM I / F 14 functions as a DRAM control circuit configured to control access to the DRAM 6 .

[0110] The timer 15 measures time and can provide the measured time to each unit in the controller 4 .

[0111] The CPU 12 is a processor configured to control the host I / F 11, NAND I / F 13, DRAM I / F 14, and timer 15. The CPU 12 performs various processes by executing FW 61 loaded from the NAND flash memory 5 to the DRAM 6. FW 61 is a control program including a set of commands for causing the CPU 12 to execute various processes. The CPU 12 can perform command processing, etc., for processing various commands from the host 2. The operation of the CPU 12 is controlled by FW 61 executed by the CPU 12.

[0112] The functions of each unit in the controller 4 may be implemented by dedicated hardware in the controller 4 or by the CPU 12 executing the FW 61 .

[0113] The CPU 12 functions as, for example, a command receiving unit 121, a mode control unit 122, and a write control unit 123. The CPU 12 functions as each of these units by, for example, executing FW61. Figures 5 to 16 Described later.

[0114] Next, refer to Figure 3 as well as Figure 4 , two tables used in storage system 3 are explained.

[0115] Figure 3The following shows an example of the structure of the logical-physical address translation table 62. The logical-physical address translation table 62 manages the mapping between each LBA and each physical address of the NAND flash memory 5. The controller 4 can use the logical-physical address translation table 62 to convert LBAs to physical addresses. The controller 4 can also use the logical-physical address translation table 62 to convert physical addresses to LBAs.

[0116] exist Figure 3 In the example shown, physical address "X" is mapped to LBA "0", physical address "Y" is mapped to LBA "1", and physical address "Z" is mapped to LBA "2".

[0117] Figure 4 : shows an example of the structure of the write management table 63. The write management table 63 may include one or more entries corresponding to one or more write commands. Each entry includes, for example, a command ID field, an LBA field, a data length field, and a data pointer field.

[0118] The command ID field indicates the command ID of the corresponding write command.

[0119] The LBA field indicates the LBA specified by the corresponding write command. This LBA indicates the beginning LBA of the LBA range into which user data should be written according to the write command.

[0120] The data length field indicates the data length specified by the corresponding write instruction. The data length indicates the length of the user data to be written according to the write instruction. Therefore, using the LBA and data length specified by the write instruction, the LBA range to which the user data should be written according to the write instruction can be determined.

[0121] The data pointer field indicates the data pointer specified by the corresponding write command. This data pointer indicates the location within the host 2 where the user data to be written to the NAND flash memory 5 according to the write command is stored. In other words, the controller 4 transfers the user data from the storage location within the host 2 indicated by the data pointer to the storage system 3.

[0122] Next, refer to Figures 5 to 16 , several examples of actions performed in the information processing system 1 are described.

[0123] Figure 5 2 is a block diagram showing an example of a binding operation in the information processing system 1. The binding operation is an operation for performing initial settings so that the storage system 3 connected to the host 2 operates in the virtual PLP drive mode.

[0124] Specifically, first, the command issuing unit 211 of the host 2 sends a first mode transfer command ( Figure 5(1) in FIG. 1 ). The first mode transition instruction can include the host ID of the host 2. In addition, the host 2 can also notify the storage system 3 of the host ID separately from sending the first mode transition instruction.

[0125] In the storage system 3, the command receiving unit 121 receives the first mode transfer command. The command receiving unit 121 sends the received first mode transfer command to the mode control unit 122 ( Figure 5 (2) in the text).

[0126] The mode control unit 122 checks whether the host ID included in the first mode transition command is stored as the virtual PLP host ID 51 in the NAND flash memory 5 ( Figure 5 (3) in the text).

[0127] When the host ID is not stored in the NAND flash memory 5, the mode control unit 122 causes the storage system 3 to transition to the virtual PLP drive mode and updates the first mode information 52 to indicate the virtual PLP drive mode ( Figure 5 Then, the mode control unit 122 writes the host ID included in the first mode transfer instruction into the NAND flash memory 5. As a result, the host ID of the host 2 that causes the storage system 3 to transfer to the virtual PLP drive mode is registered in the NAND flash memory 5 as the virtual PLP host ID 51 ( Figure 5 (5) in the figure). Furthermore, the mode control unit 122 sends a response indicating that the transition to the virtual PLP drive mode is completed and the drive ID of the storage system 3 to the instruction issuing unit 211 via the instruction receiving unit 121 and the completion queue 244 ( Figure 5 (6) in the ).

[0128] The command issuing unit 211 of the host 2 receives the response sent by the storage system 3. The command issuing unit 211 saves the drive ID included in the received response in the NVRAM 24 ( Figure 5 (7) in the example). As a result, the drive ID of the storage system 3 in which the host 2 has switched to the virtual PLP drive mode is registered in the NVRAM 24 as the virtual PLP drive ID 241. In addition, the instruction issuing unit 211 sends the received response to the write management unit 212 ( Figure 5 Based on the response indicating that the transition to the virtual PLP drive mode is complete, the write management unit 212 generates a lock data list 245 associated with the virtual PLP drive ID 241 and stores it in the NVRAM 24 ( Figure 5 (9) in the text).

[0129] Furthermore, if a host ID different from the host ID included in the first mode transition command is already stored in the NAND flash memory 5 as the virtual PLP host ID 51, the storage system 3 operates in the virtual PLP drive mode with respect to the other host having the host ID. In this case, the mode control unit 122 does not convert the received first mode transition command into the virtual PLP drive mode. The mode control unit 122 returns an error notification indicating that the mode transition to the virtual PLP drive mode has not been completed to the command issuing unit 211 via the command receiving unit 121 and the completion queue 244. Figure 5 (10) in the ).

[0130] Through the above binding operation, if storage system 3 is not operating in virtual PLP drive mode with respect to other hosts, host 2 can cause storage system 3 to transition to virtual PLP drive mode. Furthermore, in storage system 3, host 2's host ID and first mode information 52 indicating that storage system 3 is operating in virtual PLP drive mode are stored in NAND flash memory 5. Furthermore, host 2 stores storage system 3's drive ID and lock data list 245 associated with the drive ID in NVRAM 24. In this way, host 2 and storage system 3 can perform initial settings for operating storage system 3 in virtual PLP drive mode.

[0131] (Write action)

[0132] Next, refer to Figures 6 to 10 , an example of a write operation in the information processing system 1 will be described. The write operation is an operation for sending a write command from the host 2 to the storage system 3 and writing the user data associated with the write command into the NAND flash memory 5. For example, the write operation is described in Figure 5 The binding action is then performed.

[0133] Here, the commit queue 243 and the completion queue 244 provided in the NVRAM 24 of the host 2 are described. The host 2 sends a command to the storage system 3 via the commit queue 243. The storage system 3 returns a completion of the command to the host 2 via the completion queue 244.

[0134] Submission queue 243 includes multiple slots for storing commands issued by host 2 to storage system 3. The position (i.e., slot) within submission queue 243 where host 2 should store a command is indicated by the SQ Tail pointer. The position within submission queue 243 where storage system 3 should fetch a command is indicated by the SQ Head pointer.

[0135] Completion queue 244 includes multiple slots for storing responses to commands from storage system 3. The location within completion queue 244 where storage system 3 should store a response is indicated by the CQ Tail pointer. The location within completion queue 244 where host 2 should retrieve a response is indicated by the CQ Head pointer.

[0136] The following describes a specific example of a write operation in the host 2 and the storage system 3. Figures 6 to 10 In the illustrated example, for easier understanding of the description, the case where only write instructions are written to the submission queue 243 is illustrated.

[0137] Figure 6 This is a block diagram illustrating an example of a write operation in information processing system 1. This diagram illustrates a case where the command issuing unit 211 and the write management unit 212 of host 2 receive a write request to write user data 71 to NAND flash memory 5. This write request is, for example, a write request from an application executed by CPU 21.

[0138] First, in the host 2, the write management unit 212 uses the function of the application or OS 221 to lock the user data 71 ( Figure 6 (1) in the preceding text. More specifically, the write management unit 212 uses a function of the OS 221 to lock the storage area (e.g., page) storing the user data 71. This prevents the storage area storing the user data 71 from being unintentionally released or paged out. Alternatively, the user data 71 can be stored in the RAM 22 using an application or a function of the OS 221. When the user data 71 is stored in the RAM 22, the write management unit 212 copies the user data 71 from the RAM 22 to the NVRAM 24.

[0139] The command issuing unit 211 issues a write command for writing the user data 71. That is, the command issuing unit 211 generates SQ entry information corresponding to the write command for writing the user data 71. The command issuing unit 211 sends the generated SQ entry information to the write management unit 212 ( Figure 6 (2) in the text).

[0140] The write management unit 212 uses the SQ entry information sent by the command issuing unit 211 to create an entry in the locked data list 245. The created entry includes, for example, the SQ entry information corresponding to the issued write command and data area management information. The data area management information is information that can identify the storage area in the data buffer 242 that stores the user data 71. The write management unit 212 adds the created entry to the locked data list 245 ( Figure 6 (3) in the text).

[0141] Figure 7 Indicates Figure 6 This is an example of the lock data list 245 in which an entry is added in the operation (3) in FIG. The lock data list 245 includes the added entry 81 .

[0142] exist Figure 7 In the example shown, entry 81 includes SQ entry information "sqentry_info1" corresponding to the issued write command and data region management information "region_info1" indicating the storage region within data buffer 242 storing user data 71 associated with the write command. Entry 81 also does not include the completion order or completion status.

[0143] return Figure 6 Next, the instruction issuing unit 211 saves the issued write instruction (SQ entry information) in the commit queue 243 ( Figure 6 (4) in the figure). The action of saving the instruction to the submission queue 243 will be described in more detail. First, the instruction issuing unit 211 writes the instruction (here, a write instruction) to the slot indicated by the SQ Tail pointer in the submission queue 243. The instruction issuing unit 211 adds 1 to the SQ Tail pointer. In addition, when the value obtained by adding 1 to the SQ Tail pointer reaches the number of slots in the submission queue 243 (i.e., the queue size), the instruction issuing unit 211 sets the SQ Tail pointer to 0. Then, the instruction issuing unit 211 writes the updated value of the SQ Tail pointer to the SQ Tail doorbell register of the storage system 3. In this way, the action of saving the instruction to the submission queue 243 includes the action of writing the instruction to the submission queue 243 and the action of updating the SQ Tail pointer.

[0144] When the SQ Tail doorbell register is updated, the command reception unit 121 of the storage system 3 receives the update and obtains a write command from the commit queue 243 ( Figure 6 Then, the command receiving unit 121 sends the acquired write command to the write control unit 123 ( Figure 6(6) in the table). Here, the action of obtaining an instruction from the submission queue 243 is described in more detail. First, when there is a difference between the SQ Head pointer and the SQ Tail pointer, the instruction receiving unit 121 extracts an instruction (here, a write instruction) from the slot indicated by the SQ Head pointer in the submission queue 243. The instruction receiving unit 121 increments the SQ Head pointer by 1. Furthermore, when the value obtained by adding 1 to the SQ Head pointer reaches the number of slots in the submission queue 243, the instruction receiving unit 121 sets the SQ Head pointer to 0. Thus, the action of obtaining an instruction from the submission queue 243 includes the action of obtaining an instruction from the submission queue 243 and the action of updating the SQ Head pointer.

[0145] Next, the write control unit 123 uses the write command sent by the command receiving unit 121 to update the write management table 63 ( Figure 6 (7) in ). Specifically, the write control unit 123 appends an entry including the instruction ID, LBA, data length, and data pointer specified by the write instruction to the write management table 63. In addition, after confirming that the LBA specified by the write instruction is valid, or that data can be written to the LBA, and that the data pointer is valid, the write control unit 123 appends the corresponding entry to the write management table 63. The data pointer is considered valid when, for example, the data pointer does not indicate an inaccessible area within the host 2, but indicates an area commensurate with the data length. Then, the write control unit 123 notifies the instruction receiving unit 121 that the update of the write management table 63 based on the write instruction has been completed ( Figure 6 (8) in the ).

[0146] The command receiving unit 121 stores the first completion (indicating normal completion) of the write command in the completion queue 244 ( Figure 6 (9) in). This first completion includes the instruction ID of the write instruction. The action of saving the completion in the completion queue 244 is described in more detail. First, the instruction acceptance unit 121 writes the completion in the slot indicated by the CQ Tail pointer in the completion queue 244. The instruction acceptance unit 121 adds 1 to the CQ Tail pointer. In addition, when the value obtained by adding 1 to the CQ Tail pointer reaches the number of slots in the completion queue 244, the instruction acceptance unit 121 sets the CQTail pointer to 0. The instruction acceptance unit 121 issues an interrupt. By issuing an interrupt, the instruction acceptance unit 121 notifies the host 2 that a new completion to be processed is in the completion queue 244. In this way, the action of saving the completion in the completion queue 244 includes: the action of writing the completion in the completion queue 244, the action for updating the CQ Tail pointer, and the action of issuing an interrupt.

[0147] Furthermore, when the write command acquired from the commit queue 243 is an unexecutable command, the command accepting unit 121 may store a completion indicating an error completion as the first completion in the completion queue 244 .

[0148] Next, the command issuing unit 211 of the host 2 obtains the first completion ( Figure 6 Then, the instruction issuing unit 211 sends the first completion ( Figure 6 (11) in). Here, the action of obtaining completion from the completion queue 244 is described in more detail. First, the instruction issuing unit 211 takes out the completion from the slot indicated by the CQ Head pointer in the completion queue 244 according to the interrupt issued by the instruction receiving unit 121 of the storage system 3. The instruction issuing unit 211 adds 1 to the CQ Head pointer. In addition, when the value obtained by adding 1 to the CQ Head pointer reaches the number of slots in the completion queue 244, the instruction issuing unit 211 sets the CQ Head pointer to 0. The instruction issuing unit 211 writes the updated CQ Head pointer to the CQ Head doorbell register of the storage system 3. Then, the instruction issuing unit 211 clears the interrupt received from the storage system 3. As described above, the operation of obtaining completion from the completion queue 244 includes the action of taking out the completion from the completion queue 244, the action for updating the CQ Head pointer, and the action of clearing the interrupt.

[0149] When the first completion indicates normal completion, the write management unit 212 receives the first completion from the command issuing unit 211 and updates the entry corresponding to the received first completion in the lock data list 245 ( Figure 6 (12) in ). Specifically, the write management unit 212 assigns a sequence number indicating the order in which the completion is received to the first completion received. For example, the write management unit 212 assigns a sequence number that increases by 1 each time the first completion for the write instruction is received from the storage system 3 via the completion queue 244. In addition, the write management unit 212 obtains the instruction ID included in the first completion received. The write management unit 212 determines the entry that includes the SQ entry information corresponding to the obtained instruction ID in the lock data list 245. Then, the write management unit 212 appends the assigned sequence number (i.e., information indicating the order in which the completion is received) and information indicating that the first completion has been received to the determined entry.

[0150] When the first completion is a completion indicating an error completion, the write management unit 212 releases the lock of the user data 71 in the data buffer 242 corresponding to the received first completion ( Figure 6Then, the write management unit 212 deletes the entry corresponding to the first completion received from the lock data list 245 ( Figure 6 (14) in). More specifically, the write management unit 212 obtains the instruction ID included in the first completion received. The write management unit 212 determines the entry including the SQ entry information corresponding to the obtained instruction ID in the lock data list 245. The write management unit 212 uses the data area management information in the determined entry to unlock the user data 71. In addition, when the write management unit 212 creates a list of PRP entries and the second and subsequent segments of SGL, it also releases the area where their pointer lists 246 are stored. Then, the write management unit 212 deletes the specified entry from the lock data list 245 (that is, deletes it from NVRAM24). In addition, the unlocked user data 71 is deleted from the data buffer 242. Specifically, other data can be stored in the storage area in the data buffer 242 where the unlocked user data 71 is stored.

[0151] Figure 8 Indicates Figure 6 This is an example of the locked data list 245 after the entry is updated in the action (12) in FIG. The locked data list 245 includes the updated entry 81.

[0152] exist Figure 8 In the example shown, entry 81 has a completion sequence "cseq1" indicating the order in which the first completion was received, and a completion status "completed" indicating that the first completion has been received. In other words, entry 81 uses the completion sequence "cseq1" to indicate that the first completion has been received.

[0153] When the update of the lock data list 245 is completed, the write management unit 212 returns a write completion response in the case of normal completion of the first completion in response to the write request generated by the application or OS 221, and returns an error response in the case of error completion.

[0154] As described above, there are cases where the application or OS 221 stores the user data 71 in the RAM 22, and the write management unit 212 copies the user data 71 from the RAM 22 to the NVRAM 24. In this case, the application or OS 221 can release the area in the RAM 22 storing the user data 71 upon receiving the first completion indicating an error termination, and use it for other purposes. The write management unit 212 can also release the NVRAM 24 storing the user data 71.

[0155] Figure 9 Yes Figure 6This block diagram illustrates an example of a subsequent write operation. This example illustrates a case where the total amount of user data 71 requested to be written by the storage system 3 through multiple write commands received from the host 2 reaches a specific data unit. The specific data unit is, for example, the amount of data that can be written to the NAND flash memory 5 in a single data write operation (i.e., a write unit).

[0156] In the storage system 3, after the total amount of user data 71 requested to be written by multiple write commands received from the host 2 reaches a specific data unit, the command reception unit 121 and the write control unit 123 write the specific data unit of user data 71 to the NAND flash memory 5 and return a second completion corresponding to each of the multiple write commands to the host 2. Specifically, the command reception unit 121 and the write control unit 123 do not immediately execute the write operation corresponding to a single received write command. Instead, they operate using a mechanism (Delayed Write Completion) in which the write operations corresponding to the multiple write commands are executed after the total amount of user data 71 requested to be written by the multiple write commands reaches a specific data unit.

[0157] Specifically, the write control unit 123 transfers the user data 71 of the write unit from the data buffer 242 to the NAND flash memory 5, and writes the transferred user data 71 of the write unit into the NAND flash memory 5 (programming). Figure 9 Then, when there is a write command that allows the corresponding user data 71 to be read from the NAND flash memory 5, the write control unit 123 notifies the command receiving unit 121 of the completion of the processing corresponding to the write command ( Figure 9 (2) in the above). The write control unit 123 notifies the instruction receiving unit 121 of the completion of the processing corresponding to the plurality of write instructions corresponding to the user data 71 of the write unit. The write control unit 123 deletes the entries corresponding to the plurality of write instructions from the write management table 63 ( Figure 9 In addition, the write control unit 123 adds the instruction ID of each of the plurality of write instructions to the instruction log 53 ( Figure 9 (4) in the text).

[0158] Each time the command receiving unit 121 receives a notification from the write control unit 123, it transmits a second completion message ( ) to the host 2 indicating that the processing corresponding to the corresponding write command has been completed. Figure 9 More specifically, the command receiving unit 121 stores the second completion of the corresponding write command in the completion queue 244 according to the notification from the write control unit 123. The notification from the write control unit 123 includes, for example, the command ID of the completed write command.

[0159] Furthermore, when an error occurs in processing corresponding to a write command, the command reception unit 121 transmits a completion indicating the error as a second completion to the host 2 .

[0160] Next, the command issuing unit 211 of the host 2 obtains the second completion ( Figure 9 Then, the instruction issuing unit 211 sends the obtained second completion ( Figure 9 (7) in the text).

[0161] The write management unit 212 receives the second completion from the instruction issuing unit 211 and unlocks the user data 71 in the data buffer 242 corresponding to the received second completion ( Figure 9 Then, the write management unit 212 deletes the entry corresponding to the second completion received from the lock data list 245 ( Figure 9 (9) in ). More specifically, the write management unit 212 obtains the instruction ID included in the second completion received. The write management unit 212 determines the entry including the SQ entry information corresponding to the obtained instruction ID in the lock data list 245. The write management unit 212 uses the data area management information in the determined entry to unlock the user data 71 whose writing has been completed. In addition, when the write management unit 212 creates a list of PRP entries and the second and subsequent segments of SGL, it also releases the area where their pointer lists 246 are stored. Then, the write management unit 212 deletes the determined entry from the lock data list 245 (that is, deletes it from NVRAM24). In addition, the unlocked user data 71 is deleted from the data buffer 242. Specifically, other data can be stored in the storage area in the data buffer 242 that stores the unlocked user data 71.

[0162] Furthermore, if the second completion indicates an error, the host 2 (specifically, the write management unit 212) deems the storage system 3 to be faulty. The write management unit 212 suspends processing for the storage system 3 and performs exception handling for the information processing system 1. For example, the write management unit 212 deletes all data associated with the storage system 3. This deleted data includes the user data 71 in the data buffer 242 corresponding to the storage system 3 and the lock data list 245 corresponding to the storage system 3. Furthermore, the write management unit 212 stops sending write commands to at least the faulty storage system 3. Furthermore, the write management unit 212 responds to all write requests from applications or the OS 221 with errors.

[0163] Figure 10 Indicates Figure 9This is an example of the locked data list 245 whose entry is deleted in the action of (9) in FIG. The locked data list 245 includes the entry 81 corresponding to the second completion received.

[0164] exist Figure 10 In the example shown, entry 81 includes SQ entry information "sqentry_info1," completion sequence "cseq1," data region management information "region_info1," and completion status "completed." In other words, entry 81 indicates that the first completion has been received. Entry 81 is deleted upon receipt of a second completion from storage system 3 for the corresponding write command (i.e., the write command corresponding to SQ entry information "sqentry_info1").

[0165] Furthermore, a write command (SQ entry information) stored in the commit queue 243 is cleared, for example, upon receipt of the first completion for the write command. Therefore, the SQ entry information corresponding to the write command is stored in the entry of the lock data list 245. In this case, the write command (SQ entry information) stored in the commit queue 243 of the NVRAM 24 may also be stored in the RAM 22.

[0166] In addition, the write instruction stored in the submission queue 243 may not be cleared before receiving the second completion for the write instruction.

[0167] In the entry 245, instead of the SQ entry information, the entry indicating the submission queue 243 is stored.

[0168] In addition, the write instructions stored in the submission queue 243 are used as SQ entry information. Furthermore, since the write instructions are not cleared from the submission queue 243, the SQ Head pointer is not updated, and the submission queue 243 is prone to becoming full, potentially preventing the issuance of other instructions such as read instructions. Therefore, the submission queue 243 is preferably set up as a dedicated submission queue for issuing write instructions.

[0169] Through the above-described write operation, while the storage system 3 writes user data using Delayed Write Completion based on a write command received from the host 2 , the host 2 can manage the status of the process corresponding to the issued write command using the locked data list 245 .

[0170] Specifically, when host 2 sends a write command to storage system 3, it appends an entry corresponding to the write command to locked data list 245. The appended entry does not, for example, include a completion order or completion status. Therefore, host 2 can manage the situation where it has not received the first or second completion for the corresponding write command using the appended entry. In other words, host 2 can manage the situation where it has not received the first completion by issuing (sending) the corresponding write command to storage system 3 using the appended entry.

[0171] When the storage system 3 accepts a write command from the host 2 and adds the corresponding entry to the write management table 63, it returns the first completion for the write command to the host 2. Based on the first completion received from the storage system 3, the host 2 updates the corresponding entry in the lock data list 245. The updated entry includes, for example, the completion order and completion status. Therefore, the host 2 can manage, through the updated entry, the situation where the first completion for the corresponding write command has been received but the second completion has not been received. In other words, the host 2 can manage, through the updated entry, the situation where the storage system 3 has accepted the corresponding write command.

[0172] Furthermore, when the storage system 3 completes writing the user data corresponding to the write command using Delayed Write Completion, it returns a second completion for the write command to the host 2. Based on the second completion received from the storage system 3, the host 2 deletes the corresponding entry in the locked data list 245. Thus, by deleting the entry, the host 2 can terminate management related to the corresponding write command.

[0173] Furthermore, the write control unit 123 of the storage system 3 may also write padding (padding) of the user data band corresponding to the accepted write command to the NAND flash memory 5 when the time elapsed from the acceptance of the write command exceeds a threshold. Here, writing padding of the user data band refers to writing data in a write unit consisting of user data and padding data. This threshold is based on, for example, the upper limit of the time expected by the host 2 until the second completion of the write command is obtained. The time elapsed from the acceptance of the write command is measured, for example, using the timer 15. More specifically, the write control unit 123 transfers the user data corresponding to the accepted write command from the data buffer 242 of the host 2 to the NAND flash memory 5 when the time elapsed from the acceptance of the write command exceeds the threshold. The write control unit 123 then writes the transferred padding of the user data band to the NAND flash memory 5. Thus, the command acceptance unit 121 can notify the second completion of the write command within the time expected by the host 2.

[0174] (Close action)

[0175] Next, refer to Figure 11 and Figure 12 An example of a shutdown operation in the information processing system 1 will be described. The shutdown operation is an operation for terminating the operation of the storage system 3 after writing of user data corresponding to all write commands sent from the host 2 to the storage system 3 is completed.

[0176] Figure 11 This is a block diagram illustrating an example of a shutdown operation in information processing system 1. This example illustrates a case where a flash memory command is used to complete the writing of user data 71 corresponding to all write commands sent from host 2 to storage system 3. Furthermore, for ease of explanation, it is assumed that host 2 has already received the first completion for all write commands sent from host 2 to storage system 3 and has not yet received the second completion for at least one write command.

[0177] First, in the host 2, the write management unit 212 stops accepting new I / O requests from applications, etc. Then, the write management unit 212 requests the command issuing unit 211 to issue a flash memory command ( Figure 11 (1) in the command issuing unit 211 issues a flash memory command according to the request of the write management unit 212 and saves it in the submission queue 243 ( Figure 11 (2) in the text).

[0178] Next, in the storage system 3, the command receiving unit 121 obtains the flash memory command ( Figure 11 (3) in the above). The command receiving unit 121 sends the obtained flash memory command to the write control unit 123 ( Figure 11 (4) in the text).

[0179] The write control unit 123 uses the write management table 63 to determine whether there is user data 71 ( ) to be written to the NAND flash memory 5 based on the flash memory command received from the command reception unit 121. Figure 11 Specifically, if there is at least one entry in the write management table 63, the write control unit 123 determines that there is user data 71 to be written to the NAND flash memory 5. If there is no entry in the write management table 63, the write control unit 123 determines that there is no user data 71 to be written to the NAND flash memory 5.

[0180] When there is user data 71 to be written into the NAND flash memory 5, the write control unit 123 transfers the user data 71 from the data buffer 242 to the NAND flash memory 5, and writes the transferred user data 71 into the NAND flash memory 5 with padding ( Figure 11Then, the write control unit 123 notifies the instruction receiving unit 121 of the completion of the processing corresponding to the write instruction that can read the corresponding user data 71 from the NAND flash memory 5 ( Figure 11 (7) in the above). The write control unit 123 notifies the instruction receiving unit 121 of the completion of the processing corresponding to one or more write instructions corresponding to the written user data 71. The write control unit 123 deletes the entries corresponding to one or more write instructions from the write management table 63 ( Figure 11 In addition, the write control unit 123 adds the instruction ID of each of the one or more write instructions to the instruction log 53 ( Figure 11 (9) in the text).

[0181] Then, each time the command receiving unit 121 receives a notification from the write control unit 123, it stores a second completion indicating that the processing corresponding to the corresponding write command is completed in the completion queue 244 ( Figure 11 (10) in the ).

[0182] In this way, in the storage system 3, the writing of the user data 71 corresponding to all the write commands sent from the host 2 to the storage system 3 is completed according to the flash memory command. Thus, a second completion is returned to the host 2 for all the write commands.

[0183] Later in host 2 Figure 11 The actions and references in (11) to (14) Figure 9 The operations (6) to (9) of the aforementioned write operation are the same. By receiving the second completion for all write commands sent from the host 2 to the storage system 3, all entries in the lock data list 245 are deleted. That is, the lock data list 245 becomes a hole. Based on the fact that all entries in the lock data list 245 are deleted, the write management unit 212 determines that the writing of the user data 71 corresponding to all write commands sent from the host 2 to the storage system 3 has been completed. Then, the write management unit 212 notifies the command issuing unit 211 that the writing of the user data 71 corresponding to all write commands has been completed ( Figure 11 (15) in the text).

[0184] Figure 12 express Figure 11 Example of subsequent closing actions.

[0185] When notified that the writing of the user data 71 corresponding to all the write commands has been completed, the command issuing unit 211 sends a close command ( Figure 12 (1) in the .

[0186] In the storage system 3, the command receiving unit 121 receives the shutdown command from the host 2. The command receiving unit 121 sends the received shutdown command to the mode control unit 122 ( Figure 12 (2) in the text).

[0187] The mode control unit 122 changes the operation mode of the storage system 3 from the virtual PLP drive mode to the normal drive mode according to the shutdown command received from the command receiving unit 121. Then, the mode control unit 122 updates the first mode information 52 in the NAND flash memory 5 to indicate the normal drive mode ( Figure 12 In addition, the mode control unit 122 deletes the virtual PLP host ID 51 of the host 2 stored in the NAND flash memory 5 according to the shutdown command ( Figure 12 (4) in the text).

[0188] After that, the command receiving unit 121 notifies the command issuing unit 211 of the host 2 that the shutdown is completed ( Figure 12 (5) in the text).

[0189] After receiving the notification, the instruction issuing unit 211 deletes the virtual PLP drive ID 241 of the storage system 3 stored in the NVRAM 24 ( Figure 12 Then, the instruction issuing unit 211 deletes the submission queue 243, the completion queue 244, and the lock data list 245 stored in the NVRAM 24 ( Figure 12 (7) in FIG. 2 ). The instruction issuing unit 211 releases, for example, the storage area in the NVRAM 24 that stores the virtual PLP drive ID 241 and the lock data list 245 .

[0190] Through the above shutdown operation, host 2 can shift storage system 3 to normal drive mode after completing the writing of user data corresponding to all write commands sent from host 2 to storage system 3. Furthermore, the data used to operate storage system 3 in virtual PLP drive mode (more specifically, virtual PLP drive ID 241, lock data list 245, and virtual PLP host ID 51) can be deleted. Therefore, the operation of storage system 3 can be terminated normally according to the shutdown command.

[0191] (Start action)

[0192] Next, the startup action in the information processing system 1 is described. The startup action may include an unbinding action and a recovery action for recovering the storage system 3 when the storage system 3 is started after an abnormal termination, or when it is restarted unintentionally, or when the host 2 is started after an abnormal termination. Here, the abnormal termination of the storage system 3 means that the storage system 3 terminates the action before completing the writing of user data corresponding to all write instructions received by the storage system 3. In addition, the unintentional restart of the storage system 3 means that the storage system 3 restarts without completing the above-mentioned shutdown action. The abnormal termination of the host 2 means that the host 2 terminates the action before the storage system 3 completes the writing of user data corresponding to all write instructions issued by the host 2 to the storage system 3.

[0193] The unbinding operation is, for example, an operation for forcibly returning the storage system 3 from the virtual PLP drive mode to the normal drive mode when no user data has been written to the storage system 3 due to an abnormal termination or unintentional restart of the storage system 3. The recovery operation is an operation for recovering user data written to the storage system 3 due to an abnormal termination or unintentional restart of the storage system 3 using data stored in the NVRAM 24. Specific examples of each of the unbinding operation and the recovery operation are described below.

[0194] (Unbinding action)

[0195] Figure 13 This is a block diagram illustrating an example of an unbinding operation in information processing system 1. Here, it is assumed that storage system 3, operating in virtual PLP drive mode, terminates abnormally or restarts unintentionally immediately before this startup. In this case, storage system 3 continues to operate in virtual PLP drive mode after this startup. Furthermore, it is assumed that no user data written to storage system 3 could not be completed due to the abnormal termination or unintentional restart of storage system 3. In other words, it is assumed that the entry indicating the receipt of the first completion is not included in locked data list 245.

[0196] First, the restoration control unit 213 of the host 2 determines whether the drive ID of the storage system 3 connected to the host 2 matches the virtual PLP drive ID 241 stored in the NVRAM 24 ( Figure 13 (1) in the .

[0197] If the drive ID of storage system 3 differs from the virtual PLP drive ID 241 in NVRAM 24, it is inferred that storage system 3 is operating in virtual PLP drive mode for a host different from host 2. Therefore, host 2 does not access storage system 3 until storage system 3 returns to normal drive mode. For example, storage system 3 returns to normal drive mode from virtual PLP drive mode by performing an unbinding operation between itself and the other host based on an operation by the operator of host 2.

[0198] In addition, if the NVRAM 24 of the host 2 fails and needs to be replaced, and all data stored in the NVRAM 24 is lost, or if another host fails and cannot be repaired and the storage system 3 is connected to the host 2, the virtual PLP drive ID 241 will not match the drive ID of the storage system 3. In this case, for example, based on the operation of the operator of the host 2, the host 2 can also issue a first mode release command to the storage system 3, temporarily restore the storage system 3 to the normal mode, and then follow the reference Figure 5 The steps described cause the storage system 3 to transition to the virtual PLP drive mode.

[0199] When the drive ID of the storage system 3 matches the virtual PLP drive ID 241 in the NVRAM 24, that is, when the drive ID of the storage system 3 is stored in the NVRAM 24, the recovery control unit 213 determines whether the lock data list in the NVRAM 24 is correct.

[0200] 245 includes an entry indicating the receipt of the first completion (Figure

[0201] 13 (2)). The lock data list 245 is a virtual PLP drive of the storage system 3.

[0202] ID241 creates an associated locked data list.

[0203] The entry indicating the receipt of the first completion is, for example, an entry including a completion order and a completion status indicating the receipt of the first completion. If the locked data list 245 does not include an entry indicating the receipt of the first completion, the recovery control unit 213 determines that no user data has been written to the storage system 3 due to an abnormal termination or unintentional restart of the host 2 or storage system 3. If the locked data list 245 includes an entry indicating the receipt of the first completion, the recovery control unit 213 determines that no user data has been written to the storage system 3 due to an abnormal termination or unintentional restart of the storage system 3, despite a normal response to a write request from the application or OS 221.

[0204] As mentioned above, in Figure 13 In the example shown, it is assumed that the lock data list 245 does not include an entry indicating that the first completion has been received. In this case, the recovery control unit 213 deletes the data before the abnormal end associated with the storage system 3 from the NVRAM 24. The deleted data includes the write instruction (SQ entry information) stored in the submission queue 243, the completion stored in the completion queue 244, the lock data list 245, the pointer list 246, and the user data 71 remaining on the data buffer 242. The recovery control unit 213 recreates these data after the recovery process is completed, thereby enabling the storage system 3 to be used in the virtual PLP drive mode. The recovery control unit 213 requests the instruction issuing unit 211 to issue the first mode release instruction ( Figure 13 Then, the restoration control unit 213 deletes the virtual PLP drive ID 241 of the storage system 3 stored in the NVRAM 24 ( Figure 13 (4) in the text).

[0205] The instruction issuing unit 211 sends the first mode release instruction to the storage system 3 ( Figure 13 (5) in the text).

[0206] In the storage system 3 after startup (or restart), the mode control unit 122 determines whether the host ID of the host 2 connected to the storage system 3 is consistent with the virtual PLP host ID 51 stored in the NAND flash memory 5 ( Figure 13 In addition, the mode control unit 122 uses the first mode information 52 stored in the NAND flash memory 5 to determine whether the storage system 3 is set to the normal drive mode or the virtual PLP drive mode ( Figure 13 (7) in ). As mentioned above, in Figure 13 In the example shown, it is assumed that the storage system 3 is set to the virtual PLP drive mode.

[0207] If the host ID of host 2 is different from the virtual PLP host ID 51 in NAND flash memory 5, it is estimated that storage system 3 is operating in the virtual PLP drive mode for a host different from host 2. In this case, command reception unit 121 waits for a first mode release command from another host, for example.

[0208] When the host ID of the host 2 matches the virtual PLP host ID 51 in the NAND flash memory 5, the command accepting unit 121 receives the first mode release command from the host 2. The command accepting unit 121 sends the received first mode release command to the mode control unit 122 ( Figure 13 (8) in the ).

[0209] The mode control unit 122 changes the storage system 3 from the virtual PLP drive mode to the normal drive mode according to the first mode release command received from the command receiving unit 121. Then, the mode control unit 122 updates the first mode information 52 in the NAND flash memory 5 to indicate the normal drive mode ( Figure 13 In addition, the mode control unit 122 deletes the virtual PLP host ID 51 of the host 2 stored in the NAND flash memory 5 according to the first mode release instruction ( Figure 13 (10) in the ).

[0210] Through the above unbinding action, if the storage system 3 operating in the virtual PLP drive mode ends abnormally before it is about to start up, or if the storage system 3 operating in the virtual PLP drive mode is connected to a different host 2, or if the host 2 loses the data stored in NVRAM 24 for making the storage system 3 operate in the virtual PLP drive mode (more specifically, the virtual PLP drive ID 241 and the lock data list 245), the host 2 can forcibly return the storage system 3 from the virtual PLP drive mode to the normal drive mode. The storage system 3 that has been transferred to the normal drive mode can operate in the virtual PLP drive mode relative to the host 2 again through the binding action with the host 2. Alternatively, the storage system 3 that has been transferred to the normal drive mode can also operate in the virtual PLP drive mode relative to the other host through the binding action between the host 2 and the host. In addition, the unbinding action can also be performed at any timing not limited to the startup of the storage system 3.

[0211] (Resume action)

[0212] Figure 14 This is a block diagram illustrating an example of a recovery operation in information processing system 1. Here, it is assumed that storage system 3, operating in virtual PLP drive mode, terminates abnormally or restarts unintentionally immediately before the current startup. In this case, storage system 3 continues to operate in virtual PLP drive mode after the current startup. Furthermore, it is assumed that user data written to storage system 3 cannot be completed due to the abnormal termination or unintentional restart of storage system 3. In other words, it is assumed that an entry indicating the receipt of the first completion is included in locked data list 245.

[0213] First, the restoration control unit 213 of the host 2 determines whether the drive ID of the storage system 3 connected to the host 2 matches the virtual PLP drive ID 241 stored in the NVRAM 24 ( Figure 14 (1) in the .

[0214] If the drive ID of the storage system 3 is different from the virtual PLP drive ID 241 in the NVRAM 24, it is estimated that the storage system 3 is operating in the virtual PLP drive mode for a host different from the host 2. Therefore, the host 2 does not access the storage system 3 until the storage system 3 returns to the normal drive mode. In the storage system 3, for example, a recovery operation is performed with the other host.

[0215] When the drive ID of the storage system 3 matches the virtual PLP drive ID 241 in the NVRAM 24, the recovery control unit 213 determines whether the lock data list 245 in the NVRAM 24 includes an entry indicating that the first completion has been received. Figure 14 (2) in the text).

[0216] As mentioned above, in Figure 14 In the example shown, it is assumed that an entry indicating that the first completion has been received is included in the lock data list 245. In this case, the recovery control unit 213 requests the instruction issuing unit 211 to issue the second mode transition instruction ( Figure 14 (3) in FIG. 2 ). In addition, the recovery control unit 213 recreates the submission queue 243 and the completion queue 244 in the NVRAM 24 .

[0217] The instruction issuing unit 211 sends the second mode transition instruction to the storage system 3 ( ) via the newly generated commit queue 243 or the commit queue dedicated to management instructions according to the request of the recovery control unit 213. Figure 14 (4) in the text).

[0218] In the started storage system 3, the mode control unit 122 determines whether the host ID of the host 2 connected to the storage system 3 matches the virtual PLP host ID 51 stored in the NAND flash memory 5 ( Figure 14 In addition, the mode control unit 122 refers to the first mode information 52 stored in the NAND flash memory 5 to determine whether the storage system 3 is set to the normal drive mode or the virtual PLP drive mode ( Figure 14 (6) in ). As mentioned above, in Figure 14 In the example shown, it is assumed that the storage system 3 is set to the virtual PLP drive mode.

[0219] If the host ID of the host 2 is different from the virtual PLP host ID 51 in the NAND flash memory 5 , the storage system 3 deems that the host 2 is operating abnormally, and therefore notifies the host 2 that the second mode transition command has an error.

[0220] When the host ID of the host 2 matches the virtual PLP host ID 51 in the NAND flash memory 5, the command receiving unit 121 sends the received second mode transition command to the mode control unit 122 ( Figure 14 (7) in the text).

[0221] The mode control unit 122 causes the storage system 3 to transition from the normal write mode to the recovery write mode based on the second mode transition command received from the command accepting unit 121. The command accepting unit 121 notifies the host 2 that the second mode transition command has been completed normally and the storage system 3 has transitioned to the recovery write mode. Figure 14 (8) in the ).

[0222] Figure 15 express Figure 14 An example of subsequent recovery actions. Figure 15 In the recovery operation shown, the host 2 re-requests the storage system 3 that has shifted to the recovery write mode to write user data that could not be completed due to abnormal termination or unintended restart.

[0223] Specifically, the recovery control unit 213 of the host 2 specifies n entries ( n entries each indicating that the first completion has been received) in the lock data list 245 associated with the virtual PLP drive ID 241 of the storage system 3. Figure 15 (1) in ). n is an integer greater than or equal to 1.

[0224] The restoration control unit 213 uses the completion order included in each of the determined n entries to select one of the n entries in ascending order of completion order. Hereinafter, the selected entry is also referred to as the target entry. Figure 15 In the subsequent operations shown, n entries are used as target entries one by one in ascending order of completion.

[0225] The restoration control unit 213 uses the data area management information included in the target entry to lock the user data 71 in the corresponding data buffer 242 ( Figure 15 Then, the recovery control unit 213 uses the SQ entry information included in the target entry to request the instruction issuing unit 211 to issue the corresponding write instruction ( Figure 15 (3) in the text).

[0226] Furthermore, if an entry indicating that the first completion has not been received exists in the lock data list 245, the recovery control unit 213 deletes the entry. An entry indicating that the first completion has not been received is, for example, an entry that does not include a completion order or a completion status. Since the recovery control unit 213 has not received the first completion, it determines that the write command corresponding to the entry has not been accepted by the storage system 3. Furthermore, since the first completion has not been received, the application, etc., that requested the write of the user data corresponding to the entry, is not notified of the completion of the write. Therefore, there is no need to resend the write command corresponding to the entry indicating that the first completion has not been received to the storage system 3. Therefore, the recovery control unit 213 deletes the entry indicating that the first completion has not been received from the lock data list 245.

[0227] The command issuing unit 211 stores the write command corresponding to the SQ entry information in the target entry in the commit queue 243 in response to the request for issuing the write command from the recovery control unit 213 ( Figure 15 (4) in the text).

[0228] Then, the restoration control unit 213 deletes the completion order and completion status in the object entry ( Figure 15 (5) in FIG. 3 ). Thus, the target entry indicates that the corresponding write command has been issued (sent) to the storage system 3 but the first completion has not been received.

[0229] Later Figure 15 The actions and references from (6) to (10) in Figure 6 The operations (5) to (9) of the aforementioned write operation are the same. That is, the command reception unit 121 and the write control unit 123 of the storage system 3 update the write management table 63 based on the write command received from the commit queue 243 and save the first completion in the completion queue 244.

[0230] Then, the command issuing unit 211 of the host 2 obtains the first completion ( Figure 15 (11) in the command issuing unit 211 sends the obtained first completion ( Figure 15 (12) in the text).

[0231] The restoration control unit 213 receives the first completion from the instruction issuing unit 211, and updates the entry corresponding to the received first completion in the lock data list 245 ( Figure 15 Specifically, the write management unit 212 adds a sequence number indicating the order in which the completions were received and information indicating that the first completion has been received to the entry corresponding to the first completion received.

[0232] Through the above Figure 15 In the recovery action shown, the host 2 can use the n entries in the lock data list 245 that each indicate the receipt of the first completion to resend write commands requesting the writing of the corresponding user data to the storage system 3 in ascending order of completion. Therefore, the transmission of write commands that were not completed due to abnormal termination or unintentional restart of the storage system 3 can be reproduced taking into account the order in which they were received by the storage system 3.

[0233] Since the storage system 3 operates in the recovery write mode, the write control unit 123 of the storage system 3 ensures that corresponding user data is written in the order in which the write commands are received.

[0234] Figure 16 express Figure 15 Examples of subsequent recovery actions.

[0235] After sending all n write commands corresponding to n object entries to the storage system 3, the recovery control unit 213 of the host 2 requests the command issuing unit 211 to issue a flash memory command ( Figure 16 (1) in the command issuing unit 211 issues a flash memory command according to the request of the recovery control unit 213 and saves it in the submission queue 243 ( Figure 16 (2) in the text).

[0236] Later Figure 16 The actions and references from (3) to (10) in Figure 11 The above-described shutdown operation is similar to the operations (3) to (10). That is, the command receiving unit 121 and the write control unit 123 of the storage system 3 complete the writing of the user data 71 corresponding to all write commands sent from the host 2 to the storage system 3 based on the flash memory commands obtained from the commit queue 243, and save the second completion in the completion queue 244.

[0237] Next, the command issuing unit 211 of the host 2 obtains the second completion ( Figure 16 Then, the instruction issuing unit 211 sends the obtained second completion ( Figure 16 (12) in the text).

[0238] The restoration control unit 213 receives the second completion from the instruction issuing unit 211, and unlocks the user data 71 in the data buffer 242 corresponding to the received second completion ( Figure 16 Then, the recovery control unit 213 deletes the entry corresponding to the second completion received from the lock data list 245 ( Figure 16 (14) in the ).

[0239] By receiving the second completion for all write commands sent from the host 2 to the storage system 3, all entries in the locked data list 245 are deleted. That is, the locked data list 245 becomes a hole. Based on the fact that all entries in the locked data list 245 have been deleted, the recovery control unit 213 determines that the writing of the user data 71 corresponding to all write commands sent from the host 2 to the storage system 3 has been completed. Then, the recovery control unit 213 notifies the command issuing unit 211 that the writing of the user data corresponding to all write commands has been completed ( Figure 16 (15) in the text).

[0240] The instruction issuing unit 211 sends the second mode release instruction ( Figure 16 (16) in the ).

[0241] The command accepting unit 121 of the storage system 3 receives the second mode release command from the host 2. The command accepting unit 121 sends the received second mode release command to the write control unit 123 ( Figure 16 (17) in the text).

[0242] The write control unit 123 shifts the storage system 3 from the recovery write mode to the normal write mode in response to the second mode release command.

[0243] Through the above recovery action, the writing of user data that could not be completed due to abnormal termination or unintentional restart of the storage system 3 can be completed. That is, the host 2 can use the lock data list 245 that manages the processing status of the issued write command to recover the unfinished write to the storage system 3 that terminated abnormally or restarted unintentionally. Then, the host 2 can start accepting new I / O requests from the application. The new I / O request is a new data read request or data write request for the storage system 3. That is, the host 2 can newly issue a read instruction or a write instruction corresponding to the accepted new I / O request to the storage system 3. In addition, not only in the storage system 3, but also in the case of abnormal termination or unintentional restart of the host 2, the lock data list 245 is stored non-volatilely, so the same recovery action can be performed.

[0244] In addition, with reference Figure 9Similarly to the aforementioned write operation, the write control unit 123 may also fill and write the user data band corresponding to the accepted write command to the NAND flash memory 5 when the time elapsed from the acceptance of the write command exceeds a threshold. In this case, the host 2 can receive the second completion within the expected time, so the recovery control unit 213 and the command issuing unit 211 do not need to send the flash memory command to the storage system 3.

[0245] Alternatively, the recovery control unit 213 and the command issuing unit 211 may send a second mode release command to the storage system 3 upon receiving the first completion for all write commands sent from the host 2 to the storage system 3. Specifically, upon receiving the first completion for all sent write commands, the recovery control unit 213 can determine that the writing of user data that could not be completed due to an abnormal termination or unintended restart of the storage system 3 has been recovered. In this case, based on the receipt of the first completion for all sent write commands, the recovery control unit 213 and the command issuing unit 211 send the second mode release command to the storage system 3 via the submission queue 243 and begin accepting new I / O requests from applications.

[0246] Next, refer to Figures 17 to 30 The flowchart of FIG. 1 illustrates the order of processing executed in the host 2 and the storage system 3.

[0247] (Binding process in host 2)

[0248] Figure 17 This is a flowchart showing an example of the steps of the binding process executed by the CPU 21 of the host 2. The binding process is a process for performing initial settings so that the storage system 3 connected to the host 2 operates in the virtual PLP drive mode. The CPU 21 executes the binding process when the storage system 3 is connected to the host 2, for example.

[0249] First, the CPU 21 sends a first mode transition command to the storage system 3 (step S101). The first mode transition command is a command for causing the storage system 3 to transition to the virtual PLP drive mode. The first mode transition command includes a host ID.

[0250] Then, the CPU 21 receives a response to the first mode transition instruction from the storage system 3 (step S102). The received response includes information indicating whether the storage system 3 has transitioned to the virtual PLP drive mode. Furthermore, the received response may include the drive ID of the storage system 3. Based on the received response, the CPU 21 determines whether the storage system 3 has transitioned to the virtual PLP drive mode (step S103).

[0251] If the storage system 3 has not transitioned to the virtual PLP drive mode (No in step S103), the CPU 21 terminates the binding process. For example, if the storage system 3 transitions to the virtual PLP drive mode through the binding process performed by a host different from the host 2, the storage system 3 returns a response to the host 2 indicating that the transition to the virtual PLP drive mode has not been made in response to the first mode transition command from the host 2. In this case, the CPU 21 terminates the binding process.

[0252] When the storage system 3 is switched to the virtual PLP drive mode (Yes in step S103), the CPU 21 stores the drive ID of the storage system 3 in the NVRAM 24 as the virtual PLP drive ID 241 (step S104). For example, the CPU 21 stores the drive ID included in the response received from the storage system 3 in the NVRAM 24. Alternatively, the CPU 21 may store the drive ID obtained during the connection process and authentication process with the storage system 3 in the NVRAM 24. Then, the CPU 21 generates a lock data list 245 associated with the drive ID of the storage system 3, stores it in the NVRAM 24 (step S105), and ends the binding process.

[0253] Through the above binding process, the CPU 21 can perform initial settings to enable the storage system 3 connected to the host 2 to operate in the virtual PLP drive mode. Specifically, when the storage system 3 transitions to the virtual PLP drive mode according to the first mode transition instruction, the CPU 21 can save the virtual PLP drive ID 241 and the lock data list 245 corresponding to the storage system 3 in the NVRAM 24.

[0254] (Binding Processing in Storage System 3)

[0255] Figure 18 3 is a flowchart showing an example of the procedure of the binding process executed by the CPU 12 of the storage system 3. The CPU 12 executes the binding process in response to receipt of the first mode transition instruction from the host 2.

[0256] First, the CPU 12 obtains the host ID included in the first mode transition command received from the host 2 (step S201). The host ID included in the first mode transition command is referred to as a first host ID.

[0257] The CPU 12 determines whether a host ID different from the first host ID is already registered in the storage system 3 (step S202). Specifically, the CPU 12 determines whether a host ID different from the first host ID is stored in the NAND flash memory 5 as the virtual PLP host ID 51. If a host ID different from the first host ID is stored in the NAND flash memory 5, the CPU 12 determines that a host ID different from the first host ID is already registered in the storage system 3. Alternatively, if no host ID is stored in the NAND flash memory 5, or if the first host ID is stored in the NAND flash memory 5, the CPU 12 determines that a host ID different from the first host ID is not registered in the storage system 3.

[0258] If a host ID different from the first host ID is already registered in the storage system 3, the CPU 12 notifies the host 2 of an error (step S203), and terminates the binding process. Specifically, since the storage system 3 is already operating in virtual PLP drive mode for another host with the registered host ID, the CPU 12 notifies the host 2 that the mode has been transitioned to virtual PLP drive mode in response to the failed first mode transition command.

[0259] If a host ID different from the first host ID is not registered in the storage system 3, the CPU 12 stores the first host ID in the NAND flash memory 5 (step S204). The CPU 12 causes the storage system 3 to transition from normal drive mode to virtual PLP drive mode (step S205). Specifically, the CPU 12 rewrites the first mode information 52 in the NAND flash memory 5 indicating normal drive mode with the first mode information 52 indicating virtual PLP drive mode. The CPU 12 then sends a response to the host 2 including information indicating that the transition to virtual PLP drive mode (mode transition completed) has been completed (step S206). The response may also include the drive ID of the storage system 3.

[0260] Through the above binding process, when the storage system 3 receives the first mode transition command from the host 2, it can transition from the normal drive mode to the virtual PLP drive mode if it is not operating in the virtual PLP drive mode with respect to other hosts.

[0261] (Processing for writing user data to the storage system 3 in the host 2)

[0262] Figure 19 This is a flowchart showing an example of the steps of the write request process executed by the CPU 21 of the host 2. The write request process is a process for the host 2 to request the storage system 3 to write user data. The CPU 21 refers to Figure 17The binding process described above causes the storage system 3 to transition to the virtual PLP drive mode and then executes the write request process.

[0263] First, the CPU 21 stores the user data to be written to the NAND flash memory 5 in the data buffer 242 (step S301). Alternatively, if the user data to be written to the NAND flash memory 5 is already stored in the RAM 22, the CPU 21 may copy the user data to the data buffer 242. The CPU 21 then locks the user data stored in the data buffer 242 (step S302). More specifically, the CPU 21 uses the functions of the executed OS 221 to lock the state of the storage area (e.g., page) storing the user data used by the driver 222. This prevents the storage area storing the user data from being unintentionally released.

[0264] The CPU 21 issues a write command (hereinafter referred to as a first write command) for writing the user data stored in the data buffer 242 into the NAND flash memory 5 (step S303 ).

[0265] Next, the CPU 21 adds an entry corresponding to the first write instruction to the locked data list 245 (step S304). The added entry includes, for example, SQ entry information corresponding to the first write instruction and data area management information. The SQ entry information corresponding to the first write instruction is information indicating the first write instruction. More specifically, the SQ entry information corresponding to the first write instruction is information stored in the commit queue 243 in order for the storage system 3 to execute processing corresponding to the first write instruction. Furthermore, the data area management information corresponding to the first write instruction is information that identifies the storage area within the data buffer 242 that stores the user data corresponding to the first write instruction.

[0266] Then, the CPU 21 saves the first write instruction (ie, the SQ entry information indicating the first write instruction) in the commit queue 243 (step S305 ).

[0267] Alternatively, after saving the first write command in the commit queue 243 in step S305, the CPU 21 may execute step S304 of adding an entry corresponding to the first write command to the locked data list 245. Alternatively, the CPU 21 may execute step S304 and step S305 in parallel.

[0268] Through the above write request processing, the CPU 21 can request the storage system 3 to write the user data stored in the data buffer 242. In addition, the CPU 21 can use the lock data list 245 to manage information related to the write request to the storage system 3 (that is, information related to the issued write command).

[0269] (Processing for Writing User Data in Storage System 3)

[0270] Figure 20 This is a flowchart illustrating an example of the steps of a write control process executed by the CPU 12 of the storage system 3. The write control process receives a write command from the host 2 and controls the writing of user data corresponding to the received write command. For ease of explanation, the example illustrates a case where the CPU 12 receives only write commands from the host 2's submit queue 243.

[0271] First, the CPU 12 obtains a write command (hereinafter referred to as the second write command) from the submission queue 243 (step S401). The CPU 12 updates the write management table 63 based on the second write command (step S402). Specifically, the CPU 12 obtains, for example, the command ID, LBA, data length, and data pointer from the second write command. The CPU 12 adds an entry representing the obtained command ID, LBA, data length, and data pointer to the write management table 63.

[0272] Then, the CPU 12 saves the first completion for the second write command in the completion queue 244 (step S403 ). The first completion for the second write command includes the command ID of the second write command.

[0273] Next, the CPU 12 determines whether the total amount of unwritten user data stored in the data buffer 242 of the host 2 has reached the write unit (step S404 ). The CPU 12 uses the write management table 63 to obtain the total amount of unwritten user data stored in the data buffer 242 .

[0274] If the total amount of unwritten user data stored in the data buffer 242 has not reached the write unit (step S404, No), the CPU 12 returns to step S401. That is, the CPU 12 continues to execute the process for accepting a new write command.

[0275] When the total amount of unwritten user data stored in the data buffer 242 reaches the write unit (step S404, YES), the CPU 12 transfers the user data of the write unit from the data buffer 242 of the host 2 to the NAND flash memory 5 of the storage system 3 (step S405). The CPU 12 writes the transferred user data into the NAND flash memory 5 (step S406).

[0276] Next, the CPU 12 determines whether there is a write command capable of reading the corresponding user data from the NAND flash memory 5 (step S407). If there is no write command capable of reading the corresponding user data (step S407, No), the CPU 12 returns to step S407. In other words, since the host 2 cannot be notified of the second completion indicating that the writing of the user data corresponding to the write command has been completed, the CPU 12 returns to step S407.

[0277] If there is a write instruction that can read the corresponding user data (Yes in step S407), the CPU 12 saves the second completion for the write instruction in the completion queue 244 (step S408). Hereinafter, the write instruction that can read the corresponding user data is referred to as the target write instruction. The second completion for the target write instruction includes the instruction ID of the target write instruction. Then, the CPU 12 updates the write management table 63 (step S409). Specifically, the CPU 12 deletes the entry corresponding to the target write instruction from the write management table 63. In addition, the CPU 12 updates the instruction log 53 by adding the instruction ID of the target write instruction (step S410).

[0278] Next, the CPU 12 determines whether a second completion has been stored in the completion queue 244 for all write commands corresponding to the user data of the write unit written in step S406 (step S411). If a second completion has not been stored in the completion queue 244 for at least one write command corresponding to the user data of the write unit (step S411, No), the CPU 12 returns to step S407.

[0279] On the other hand, if the second completion is stored in the completion queue 244 for all write commands corresponding to the user data in the write unit (step S411: Yes), the CPU 12 returns to step S401. That is, the CPU 12 continues to accept new write commands from the host 2 and control the writing of user data corresponding to the accepted write commands.

[0280] Through the above write control processing, the CPU 12 can accept write commands from the host 2 and control the writing of user data corresponding to the accepted write commands. Specifically, when the CPU 12 accepts a write command from the host 2, it returns a first completion signal to the host 2. Furthermore, when the CPU 12 stores a write unit of user data in the data buffer 242, it writes the user data of that write unit to the NAND flash memory 5. The CPU 12 then returns a second completion signal to the host 2 for the write command corresponding to the user data that has already been written.

[0281] Therefore, the CPU 12 can notify the host 2 of the processing status of the write command by returning the first completion and the second completion to the host 2. In addition, the CPU 12 can efficiently use the storage area of ​​the NAND flash memory 5 by writing based on Delayed Write Completion.

[0282] Furthermore, the CPU 12 can also write the user data band corresponding to the accepted write command to the NAND flash memory 5, not only when the total amount of unwritten user data stored in the data buffer 242 of the host 2 reaches the write unit in step S404, but also when the time elapsed from the acceptance of the write command exceeds a threshold. Specifically, the CPU 12 transfers the user data corresponding to the accepted write command from the data buffer 242 of the host 2 to the NAND flash memory 5 when the time elapsed from the acceptance of the write command exceeds the threshold. The CPU 12 then writes the transferred user data band to the NAND flash memory 5. Thus, the CPU 12 can notify the host 2 of the second completion of the write command within the time expected by the host 2.

[0283] (Processing in Host 2 Based on Response from Storage System 3)

[0284] Figure 21 This is a flowchart showing an example of the steps of the response reception process executed by the CPU 21 of the host 2. The response reception process is based on the response (completion) received from the storage system 3. The CPU 21 executes the response reception process in response to receiving an interrupt issued by the storage system 3.

[0285] First, the CPU 21 obtains a completion from the completion queue 244 (step S501). The CPU 21 obtains the command ID included in the obtained completion (step S502). Then, the CPU 21 identifies the entry corresponding to the obtained command ID in the lock data list 245 (step S503).

[0286] CPU 21 uses the determined entry to determine whether the received completion is the first completion (step S504). Specifically, if no value is set as the completion status in the determined entry, CPU 21 determines that the received completion is the first completion. Alternatively, if a value indicating that the first completion has been received is set as the completion status in the determined entry, CPU 21 determines that the received completion is the second completion.

[0287] If the received completion is the first completion (step S504, yes), CPU21 adds 1 to the variable Cseq used when assigning sequence numbers to completions (i.e., increments it) (step S505). Then, CPU21 uses variable Cseq to update the determined entry (step S506) and ends the response reception process. Specifically, CPU21 appends (sets) the sequence number represented by variable Cseq as the completion order within the determined entry. Thus, the received completion is assigned the sequence number represented by variable Cseq. In addition, CPU21 appends a value indicating that the first completion has been received as the completion status within the determined entry.

[0288] If the received completion is the second completion (step S504, No), the CPU 21 unlocks the user data in the data buffer 242 associated with the obtained command ID (step S507). After the lock on the data buffer 242 is unlocked, the application or OS 221 deletes the user data 71. The CPU 21 can, for example, use the data management area information in the identified entry to determine the user data in the data buffer 242 that should be unlocked. When the lock on the user data is unlocked, the user data is deleted. That is, the storage area in the data buffer 242 (i.e., the storage area in the NVRAM 24) storing the user data is released. Then, the CPU 21 deletes the identified entry from the locked data list 245 (step S508) and ends the response reception process.

[0289] Through the above response reception processing, CPU 21 can perform different processing depending on whether the received completion is the first completion or the second completion for the corresponding write instruction. Specifically, if the received completion is the first completion, CPU 21 appends the sequence number Cseq assigned to the completion and information indicating that the first completion has been received to the entry in the corresponding lock data list 245. Alternatively, if the received completion is the second completion, CPU 21 deletes the corresponding user data (i.e., the user data that has been written) and the corresponding entry in the lock data list 245 from NVRAM 24.

[0290] Next, we will refer to Figure 22 and Figure 23 The unbinding process is described below. The unbinding process is used to forcibly switch the storage system 3 from the virtual PLP drive mode to the normal drive mode. Here, it is assumed that the storage system 3 is operating in the virtual PLP drive mode with respect to the host 2. In the storage system 3 operating in the virtual PLP drive mode, the host ID of the host 2 and the first mode information 52 indicating the virtual PLP drive mode are stored in the NAND flash memory 5.

[0291] (Unbinding process in host 2)

[0292] Figure 22 This is a flowchart showing an example of the steps of the unbinding process executed by the CPU 21 of the host 2. The CPU 21 can execute the unbinding process when the host 2 or the storage system 3 is restarted after abnormal termination, or when the storage system 3 is restarted unintentionally.

[0293] First, the CPU 21 sends a first mode release command to the storage system 3 (step S601). The first mode release command is a command requesting a transition from the virtual PLP drive mode to the normal drive mode. Then, the CPU 21 deletes the virtual PLP drive ID 241 from the NVRAM 24 (step S602). Alternatively, the CPU 21 may delete the virtual PLP drive ID 241 from the NVRAM 24 upon receiving a response from the storage system 3 indicating that the transition to the normal drive mode has been completed.

[0294] Through the above-described unbinding process, the CPU 21 can shift the storage system 3 operating in the virtual PLP drive mode to the normal drive mode.

[0295] (Unbinding Processing in Storage System 3)

[0296] Figure 23 3 is a flowchart showing an example of the procedure of the unbinding process executed by the CPU 12 of the storage system 3. The CPU 12 executes the unbinding process in response to receipt of the first mode release command from the host 2.

[0297] Based on the first mode release command received from the host 2, the CPU 12 causes the storage system 3 to transition from the virtual PLP drive mode to the normal drive mode (step S701). More specifically, the CPU 12 updates the first mode information 52 stored in the NAND flash memory 5 to indicate the normal drive mode. The CPU 12 then deletes the virtual PLP host ID 51 from the NAND flash memory 5 (step S702).

[0298] Through the above-described unbinding process, the CPU 12 can shift the storage system 3 from the virtual PLP drive mode to the normal drive mode based on the first mode release command received from the host 2 .

[0299] Next, refer to Figure 24 as well as Figure 25 , the shutdown process when the operation of the storage system 3 ends normally is explained.

[0300] (Shutdown process in host 2)

[0301] Figure 242 is a flowchart showing an example of the procedure of the shutdown process executed by the CPU 21 of the host 2. The CPU 21 executes the shutdown process before requesting the storage system 3 to terminate the operation.

[0302] First, the CPU 21 saves the flash instruction in the commit queue 243 (step S801 ).

[0303] Next, the CPU 21 executes the response receiving process (step S802). Figure 21 Then, the CPU 21 uses the lock data list 245 to determine whether a second completion has been received for all the issued write commands (step S803). If the lock data list 245 does not include any entry, the CPU 21 determines that a second completion has been received for all the issued write commands. If the lock data list 245 includes at least one entry, the CPU 21 determines that at least one of the issued write commands has not received a second completion.

[0304] If the second completion has not been received for at least one of the issued write commands (step S803 , No), the CPU 21 returns to step S802 . That is, the CPU 21 continues processing for receiving the completion for the issued write command from the storage system 3 .

[0305] When receiving the second completion for all the issued write commands (step S803, YES), the CPU 21 deletes the virtual PLP drive ID 241 and the lock data list 245 from the NVRAM 24 (step S804). Then, the CPU 21 sends a close command to the storage system 3 (step S805).

[0306] Through the above shutdown process, the CPU 21 can send a shutdown command to the storage system 3 after receiving the second completion of all write commands issued to the storage system 3. In other words, the CPU 21 can control the storage system 3 so that it does not terminate its operation (i.e., does not terminate abnormally) until the writing of user data corresponding to all write commands is completed.

[0307] (Close Processing in Storage System 3)

[0308] Figure 25 This is a flowchart showing an example of the procedure of the shutdown process executed by the CPU 12 of the storage system 3. The CPU 12 executes the shutdown process in response to a request from the host 2 (more specifically, a flash command, a shutdown instruction, etc.).

[0309] First, the CPU 12 obtains a flash memory command from the commit queue 243 (step S901). Based on the obtained flash memory command, the CPU 12 transfers the unwritten user data corresponding to the received write command from the data buffer 242 of the host 2 to the NAND flash memory 5 of the storage system 3 (step S902). The CPU 12 fills the transferred user data into the NAND flash memory 5 (step S903).

[0310] The subsequent steps S904 to S908 and reference Figure 20 The steps S407 to S411 of the above-described write control process are the same. That is, the CPU 12 performs a process for storing the second completion of all write commands corresponding to the written user data in the completion queue 244 .

[0311] Then, when the second completion of all write instructions corresponding to the written user data is saved in the completion queue 244 (Yes in step S908), the CPU 12 receives a shutdown command from the host 2 (step S909). Based on the shutdown command, the CPU 12 causes the storage system 3 to transition from the virtual PLP drive mode to the normal drive mode (step S910). More specifically, the CPU 12 updates the first mode information 52 stored in the NAND flash memory 5 to indicate the normal drive mode. In addition, the CPU 12 deletes the virtual PLP host ID 51 stored in the NAND flash memory 5 (step S911). Then, the CPU 12 ends the operation of the storage system 3 (step S912).

[0312] Through the above shutdown process, the CPU 12 can complete the writing of user data corresponding to all write commands issued to the storage system 3 according to the flash memory commands received from the host 2. Then, the CPU 12 can terminate the operation of the storage system 3 after saving the second completion of all these write commands in the completion queue 244. In other words, the CPU 12 can control the storage system 3 so that the operation of the storage system 3 does not terminate (i.e., does not terminate abnormally) until the writing of user data corresponding to all write commands is completed.

[0313] Furthermore, as described above, the CPU 12 may also fill and write the user data band corresponding to the accepted write command to the NAND flash memory 5 when the time elapsed from the acceptance of the write command exceeds the threshold. In this case, the CPU 12 notifies the host 2 of the second completion of the write command within the time expected by the host 2, so the CPU 21 of the host 2 may not perform the step of saving the flash memory command to the submission queue 243 during the shutdown process (equivalent to the step of Figure 24 Step S801).

[0314] Next, refer to Figures 26 to 28The startup process is a process for determining whether the storage system 3 has been unable to complete writing of user data due to abnormal termination or unintentional restart immediately before the current startup, and for resuming the writing of the unable user data.

[0315] (Startup processing in host 2)

[0316] Figure 26 This is a flowchart showing an example of the steps of the startup process executed by the CPU 21 of the host 2. When the storage system 3 is started up and connected to the host 2, the CPU 21 executes the startup process.

[0317] The CPU 21 determines whether the virtual PLP drive ID 241 is stored in the NVRAM 24 (step S1001 ). For example, if the storage system 3 terminates abnormally immediately before startup or if the storage system 3 is restarted unintentionally, the virtual PLP drive ID 241 may be stored in the NVRAM 24 .

[0318] If the virtual PLP drive ID 241 is not stored in the NVRAM 24 (No in step S1001), the CPU 21 creates a submission queue 243 and a completion queue 244 in the NVRAM 24 (step S1002). That is, the CPU 21 allocates storage areas within the NVRAM 24 as the submission queue 243 and the completion queue 244. Then, the CPU 21 begins accepting new I / O requests from the application (step S1003), and the startup process ends.

[0319] If the virtual PLP drive ID 241 is stored in the NVRAM 24 (Yes in step S1001), the CPU 21 obtains the drive ID of the storage system 3 connected to the host 2 (step S1004). The CPU 21 determines whether the obtained drive ID matches the virtual PLP drive ID 241 stored in the NVRAM 24 (step S1005).

[0320] If the obtained drive ID is different from the virtual PLP drive ID 241 stored in NVRAM 24 (No in step S1005), CPU 21 ends the startup process. That is, the connected storage system 3 is different from the storage system that operates in the virtual PLP drive mode with respect to the host 2, so CPU 21 ends the startup process. In addition, the host 2 and the storage system 3 can also refer to Figure 17 as well as Figure 18 In this case, the storage system 3 can be made to operate in the virtual PLP drive mode again with respect to the host 2 .

[0321] When the acquired drive ID matches the virtual PLP drive ID 241 stored in the NVRAM 24 (step S1005 , YES), the CPU 21 determines whether there is an entry indicating that the first completion has been received in the lock data list 245 associated with the acquired drive ID (step S1006 ).

[0322] If there is no entry in the lock data list 245 indicating that the first completion has been received (step S1006 , No), the CPU 21 creates the commit queue 243 and the completion queue 244 in the NVRAM 24 (step S1002 ). The CPU 21 then begins accepting new I / O requests from the application (step S1003 ), and terminates the startup process.

[0323] When there is an entry in the lock data list 245 indicating that the first completion has been received (yes in step S1006), CPU21 creates a submission queue 243 and a completion queue 244 for NVRAM24 (step S1007). CPU21 sends a second mode transfer instruction to the storage system 3 (step S1008). The second mode transfer instruction is an instruction for transferring the storage system 3 from the normal write mode to the recovery write mode. Then, CPU21 executes the recovery write request processing (step S1009). The recovery write request processing is a processing for requesting the storage system 3 to write the following user data, which is user data corresponding to one or more entries in the lock data list 245 indicating that the first completion has been received. In more detail, in the recovery write request processing, the write instructions corresponding to one or more entries in the lock data list 245 indicating that the first completion has been received are saved in the submission queue 243. For the specific steps of the recovery write request processing, refer to Figure 27 Described later.

[0324] Next, the CPU 21 executes a response receiving process (step S1010). In the response receiving process, a process corresponding to the first completion or the second completion of the write instruction received from the storage system 3 is performed. Figure 21 As described.

[0325] Then, the CPU 21 determines whether or not a second completion has been received for all the issued write commands (step S1011). The issued write commands are all the write commands issued in the recovery write request process of step S1009.

[0326] If the second completion has not been received for at least one of all the issued write commands (step S1011 , No), the CPU 21 returns to step S1010 . That is, the CPU 21 continues processing for receiving the completion for the issued write command from the storage system 3 .

[0327] If the second completion is received for all issued write commands (step S1011, yes), the CPU 21 sends a second mode release command to the storage system 3 (step S1012). The second mode release command is used to switch the storage system from recovery write mode to normal write mode. The CPU 21 then begins accepting new I / O requests from the application (step S1013), completing the startup process.

[0328] Through the above startup process, the CPU 21 can again request the storage system 3 to write user data that was not completed due to abnormal termination of the storage system 3 immediately before the current startup or due to an unintended restart of the storage system 3. More specifically, the CPU 21 issues a write command based on the entry in the locked data list 245 indicating the completion of the first write, and stores the command in the commit queue 243. Thus, the CPU 21 can request the storage system 3 to write user data.

[0329] Alternatively, in step S1011, instead of determining whether a second completion has been received for all issued write commands, CPU 21 may determine whether a first completion has been received for all issued write commands. If CPU 21 receives a first completion for all issued write commands, it can determine that the writing of user data, which was unable to be completed due to an abnormal termination or unintended restart of storage system 3 immediately prior to this startup, has been resumed. In this case, based on the receipt of the first completion for all issued write commands, CPU 21 sends a second mode release command to storage system 3 and begins accepting new I / O requests from applications.

[0330] Figure 27 This is a flowchart showing an example of the steps of the recovery write request process executed by the CPU 21 of the host 2. The recovery write request process is equivalent to referring to Figure 26 The startup process is step S1009.

[0331] First, the CPU 21 retrieves n entries from the lock data list 245, in ascending order of completion, each indicating that the first completion has been received (step S1101). n is an integer greater than or equal to 1. The CPU 21 then sets a variable i to 1 (step S1102). The variable i is used to identify one of the n entries in ascending order of completion. Hereinafter, the i-th entry among the n entries in ascending order of completion will be referred to as the i-th entry.

[0332] The CPU 21 uses the data area management information of the i-th entry to lock the user data in the corresponding data buffer 242 (step S1103). More specifically, the CPU 21 uses the data area management information of the i-th entry to identify the storage area in the data buffer 242 where the user data is stored. The CPU 21 then uses the function of the executed OS 221 to lock the identified storage area.

[0333] Next, the CPU 21 issues a write command based on the information in the SQ entry of the i-th entry (hereinafter referred to as the i-th write command) (step S1104). The CPU 21 saves the i-th write command to the submission queue 243 (step S1105). The CPU 21 deletes the values ​​set as the completion order and completion status in the i-th entry (step S1106). In other words, after issuing the corresponding write command, the CPU 21 updates the i-th entry to indicate that the first completion has not yet been received. Then, the CPU 21 increments the variable i by 1 (step S1107).

[0334] Next, the CPU 21 determines whether the variable i is less than or equal to n (step S1108). If the variable i is less than or equal to n (yes in step S1108), the CPU 21 returns to step S1103. In other words, the CPU 21 also performs processing for sending a write command based on another entry indicating that the first completion has been received to the storage system 3.

[0335] When the variable i exceeds n (NO in step S1108 ), the CPU 21 ends the recovery write request process.

[0336] Through the above-described recovery write request processing, CPU 21 can request storage system 3 to write user data that could not be completed due to abnormal termination or unintended restart of storage system 3 immediately before the current startup. Specifically, CPU 21 can use locked data list 245 to send write commands corresponding to n entries indicating that the first completion has been received to storage system 3 via commit queue 243.

[0337] (Startup Processing in Storage System 3)

[0338] Figure 28 1 is a flowchart showing an example of the steps of the startup process executed by the CPU 12 of the storage system 3. When the storage system 3 is started up and a connection with the host 2 is established, the CPU 12 executes the startup process.

[0339] First, the CPU 12 notifies the host 2 of the drive ID (step S1201). The drive ID may be notified to the host 2 during the process of establishing a connection between the storage system 3 and the host.

[0340] Next, the CPU 12 obtains the first mode information 52 stored in the NAND flash memory 5 (step S1202). The first mode information 52 indicates whether the storage system 3 is in normal drive mode or virtual PLP drive mode. The CPU 12 determines whether the obtained first mode information 52 indicates the virtual PLP drive mode (step S1203).

[0341] If the acquired first mode information 52 does not indicate virtual PLP drive mode (step S1203, No), that is, if it indicates normal drive mode, CPU 12 terminates the startup process. If the first mode information 52 indicates normal drive mode, CPU 12 determines that no user data was written due to abnormal termination or unintended restart of storage system 3 immediately prior to this startup. Therefore, CPU 12 terminates the startup process and accepts access to storage system 3 from host 2.

[0342] If the acquired first mode information 52 indicates the virtual PLP drive mode (step S1203, YES), the CPU 12 determines whether a first mode release command has been received from the host 2 (step S1204). The first mode release command is a command for shifting the storage system 3 from the virtual PLP drive mode to the normal drive mode.

[0343] Upon receiving a command to terminate the first mode from the host 2 (step S1204, YES), the CPU 12 causes the storage system 3 to transition from the virtual PLP drive mode to the normal drive mode (step S1205). The CPU 12 then deletes the virtual PLP host ID 51 stored in the NAND flash memory 5 (step S1206), terminating the boot process. Thus, in the normal drive mode, the CPU 12 accepts access from the host 2 to the storage system 3.

[0344] If the first mode release command has not been received from the host 2 (step S1204, No), the CPU 12 determines whether a second mode transition command has been received from the host 2 (step S1207). The second mode transition command is a command for causing the storage system 3 to transition from the normal write mode to the recovery write mode. When the storage system 3 transitions to the recovery write mode, the CPU 12 processes the write commands received from the host 2 (i.e., the write commands received from the commit queue 243) in the order in which they were received. In other words, the CPU 12 ensures that the write processing corresponding to the write commands is executed in the order in which they were received.

[0345] If the second mode transition command is not received from the host 2 (No in step S1207), the CPU 12 terminates the startup process. For example, if the storage system 3 abnormally terminates or is unintentionally restarted immediately before the current startup, but there is no unwritten user data to the NAND flash memory 5, the CPU 12 terminates the startup process. Therefore, in the storage system 3 operating in the virtual PLP drive mode, the CPU 12 accepts access to the storage system 3 from the host 2.

[0346] When the second mode transition instruction is received from the host 2 (step S1207, yes), the CPU 12 causes the storage system 3 to transition from the normal write mode to the recovery write mode (step S1208). Then, the CPU 12 performs a write control process (step S1209). In the write control process, the CPU 12 accepts a write instruction from the host 2 and controls the writing of user data corresponding to the accepted write instruction. For specific steps of the write control process, refer to Figure 20 As described.

[0347] Next, the CPU 12 determines whether or not a second mode release instruction has been received from the host computer 2 (step S1210 ).

[0348] If the second mode release command is not received from the host 2 (step S1210, No), the CPU 12 returns to step 1209. That is, the CPU 21 continues the write control process until the second mode release command is received from the host 2.

[0349] If the CPU 12 receives a command to release the second mode from the host 2 (step S1210: Yes), the CPU 12 causes the storage system 3 to transition from the recovery write mode to the normal write mode (step S1211), and terminates the boot process. Thus, in the normal write mode, the CPU 12 accepts access to the storage system 3 from the host 2.

[0350] Through the above startup process, if the writing of user data cannot be completed due to abnormal termination or unintentional restart of the storage system 3 immediately before the current startup, the CPU 12 can resume the writing of the user data.

[0351] Here, the recovery write request processing and write control processing are described when the storage system 3 is not provided with a structure for operating in the recovery write mode. In this case, if the storage system 3 receives multiple write commands from the host 2, it may not be possible to ensure that the write processing corresponding to the write commands will be executed in the order in which they were received.

[0352] Therefore, when host 2 sends multiple write commands that specify overlapping LBAs (or LBA ranges) to storage system 3, for example, after storing one of these multiple write commands in commit queue 243, host 2 repeatedly stores the flash memory command in commit queue 243. Specifically, host 2 repeatedly waits for completion of the flash memory command and stores the next write command in commit queue 243. Storage system 3 then proceeds to write data from write commands received before the flash memory command to NAND flash memory 5 in the order in which the flash memory commands were returned. This ensures that the write processing corresponding to multiple write commands specifying the same LBA is executed in the order in which the write commands were received.

[0353] The storage system 3 of this embodiment supports the recovery write mode, so the host 2 can perform recovery processing at high speed simply by loading write commands into the commit queue 243 in the order in which they are to be processed.

[0354] Figure 29 This is a flowchart showing an example of the steps of the recovery write request processing executed by the CPU 21 of the host 2 when the flash memory command is used. Figure 27 The above-described recovery write request processing follows the same procedures as steps S1101 to S1105. Specifically, the CPU 21 retrieves n entries from the locked data list 245 in ascending order of completion, each of which indicates that the first completion has been received. Based on the i-th entry, the CPU 21 locks the user data in the corresponding data buffer 242, issues the corresponding write command (i-th write command), and stores it in the commit queue 243.

[0355] Next, the CPU 21 refers to the n entries and determines whether another write command that specifies the same LBA (or LBA range) as the i-th write command has been issued after the i-th write command (step S1306). Specifically, the CPU 21 determines, for example, whether the n entries include an entry that has a higher completion order than the i-th entry and includes SQ entry information corresponding to a write command that specifies the same LBA as the i-th write command.

[0356] After the i-th write instruction, if another write instruction is issued whose designated LBA overlaps with the i-th write instruction (step S1306, yes), CPU 21 issues a flash memory instruction and saves it to submission queue 243 (step S1307), and CPU 21 proceeds to step S1308. In submission queue 243, a flash memory instruction is stored after the i-th write instruction. Thus, in storage system 3, the write processing of user data corresponding to the i-th write instruction can be completed based on the subsequent flash memory instruction. Therefore, in storage system 3, it is possible to ensure that the write processing corresponding to multiple write instructions specifying the same LBA is executed in the order in which the write instructions were accepted.

[0357] After the i-th write command, if another write command whose designated LBA overlaps with that of the i-th write command has not been issued (step S1306 , No), the CPU 21 proceeds to step S1308 .

[0358] The subsequent steps S1308 to S1310 and reference Figure 27 The steps S1106 and S1108 of the recovery write request processing are the same.

[0359] Through the above-described recovery write request processing, when multiple write commands with duplicate designated LBAs are sent to the storage system 3, the CPU 21 saves one of the multiple write commands in the commit queue 243 and then saves the flash memory command in the commit queue 243. This ensures that the storage system 3 executes the write processing corresponding to the multiple write commands that specify the same LBA in the order in which the write commands were received.

[0360] Figure 30 This is a flowchart showing an example of a write control process executed by the CPU 12 of the storage system 3 when using a flash memory command. For ease of explanation, the case where only write commands and flash memory commands are stored in the commit queue 243 is illustrated.

[0361] First, the CPU 12 obtains a command from the commit queue 243 (step S1401 ). The CPU 12 then determines whether the obtained command is a write command or a flash memory command (step S1402 ).

[0362] If the acquired command is a write command (a write command in step S1402), the CPU 12 executes the steps from step S1403 to step S1412 and ends the write control process. Figure 20 The steps from step S402 to step S411 of the write control process are the same.

[0363] If the command received is a flash memory command (flash memory command in step S1402), the CPU 12 transfers the unwritten user data corresponding to the received write command from the data buffer 242 of the host 2 to the NAND flash memory 5 of the storage system 3 (step S1413). The CPU 12 fills the transferred user data band with the NAND flash memory 5 (step S1414). Then, the CPU 12 executes the steps from step S1408 to step S1412 to end the write control process. The steps from step S1408 to step S1412 are the same as those in the reference step. Figure 20 The steps from step S407 to step S411 of the write control process are the same.

[0364] Through the above write control processing, CPU 12 accepts a write command from host 2 and, while performing write processing corresponding to the accepted write command, if a flash memory command is accepted, the unwritten user data band stored in host 2's data buffer 242 is filled and written to NAND flash memory 5. When host 2 sends multiple write commands with duplicate specified LBAs to the storage system, it saves the flash memory command in submit queue 243 immediately after saving one of the multiple write commands in submit queue 243. Thus, CPU 12 can complete write processing corresponding to multiple write commands specifying the same LBA based on subsequent flash memory commands. Therefore, in storage system 3, it is possible to ensure that write processing corresponding to multiple write commands specifying the same LBA is executed in the order in which the write commands were accepted.

[0365] As described above, according to this embodiment, it is possible to recover incomplete writes to the storage system 3 in response to an abnormal termination or unintentional restart. The write management unit 212 stores the first data in the NVRAM 24. The write management unit 212 and the command issuing unit 211 send a first write request (e.g., a write command) associated with the first data to the storage system 3 for the first time. The write management unit 212 stores first management data (e.g., an entry in the lock data list 245) including information corresponding to the first write request in the NVRAM 24. Upon receiving a first response to the first write request sent for the first time from the storage system 3, the write management unit 212 appends information indicating that the first response to the first write request sent for the first time has been received to the first management data. After receiving the first response, the write management unit 212 deletes the first data and the first management data from the NVRAM 24 upon receiving a second response to the first write request sent for the first time from the storage system 3.

[0366] In this way, the host 2 stores the first data to be written to the NAND flash memory 5 and the first management data for managing the processing status of the first write command sent from the host 2 to the storage system 3 in the NVRAM 24. Therefore, for example, if the storage system 3 does not have a buffer capable of protecting the first data using the PLP function, even if an abnormal termination or an unintended restart occurs, the first data and the first management data stored in the NVRAM 24 can be used to recover the incomplete writing.

[0367] The various functions described in the description of this embodiment may also be implemented by circuits (processing circuits) respectively. In the example of a processing circuit, a programmable processor such as a central processing unit (CPU) is included. The processor performs the functions described in the description of this embodiment respectively by executing a computer program (command group) stored in a memory. The processor may also be a microprocessor including a circuit. In the example of a processing circuit, a digital signal processor (DSP), an integrated circuit (ASIC) for a specific purpose, a microcontroller, a controller, and other electrical circuit components are also included. Other components other than the CPU described in the description of this embodiment may also be implemented by processing circuits.

[0368] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments may be implemented in various other ways, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their variations are intended to be within the scope and spirit of the invention and are encompassed by the invention set forth in the claims and their equivalents.

Claims

1. An information processing device capable of being connected to a storage system, comprising a non-volatile memory and a processor, The processor is configured as follows: storing first data in the non-volatile memory; Sending a first write request associated with the first data to the storage system for the first time; storing first management data in the nonvolatile memory, wherein the first management data includes information corresponding to the first write request; In response to receiving a first response to the first write request sent for the first time from the storage system, adding information indicating that the first response to the first write request sent for the first time has been received to the first management data; as well as After receiving the first response, the first data and the first management data are deleted from the nonvolatile memory in response to receiving a second response from the storage system to the first write request sent for the first time.

2. The information processing device according to claim 1, wherein The processor is further configured to: The first write request is sent to the storage system for the second time based on the fact that the storage system has been activated after the first write request is sent to the storage system for the first time and when the first management data is stored in the nonvolatile memory.

3. The information processing device according to claim 2, wherein: The processor is further configured to: The first data and the first management data are deleted from the nonvolatile memory in response to a first response and a second response to the second transmitted first write request being received from the storage system.

4. The information processing device according to any one of claims 1 to 3, wherein: The processor is further configured to: sending a first mode transfer request to the storage system; as well as When the storage system transitions from the first system mode to the second system mode according to the first mode transition request, storing identification information of the storage system in the non-volatile memory, Sending the first write request to the storage system for the first time, storing the first management data associated with the identification information in the nonvolatile memory, In response to receiving the first response to the first write request sent for the first time from the storage system, information indicating that the first response has been received is added to the first management data; After receiving the first response, the first data and the first management data associated with the identification information are deleted from the nonvolatile memory in response to receiving the second response to the first write request sent for the first time from the storage system.

5. The information processing apparatus according to claim 4, wherein: The processor is further configured to: Based on the fact that the storage system has been activated and the identification information of the storage system and the first management data associated with the identification information are stored in the nonvolatile memory, the first write request is sent to the storage system for the second time. The information processing apparatus according to claim 4 , wherein: The processor is further configured to: sending a first mode release instruction to the storage system operating in the second system mode; as well as The identification information of the storage system stored in the nonvolatile memory is deleted in response to the storage system shifting from the second system mode to the first system mode in response to the first mode release command.

7. The information processing apparatus according to claim 1, wherein: The processor is further configured to: storing second data in the non-volatile memory; sending a second write request associated with the second data to the storage system for the first time; storing second management data in the nonvolatile memory, the second management data including information corresponding to the second write request; in response to receipt of a third response to the second write request sent for the first time from the storage system, adding information indicating receipt of the third response to the second write request sent for the first time to the second management data; as well as After receiving the third response, the second data and the second management data are deleted from the nonvolatile memory in response to receiving a fourth response from the storage system to the second write request that was sent for the first time.

8. The information processing apparatus according to claim 7, wherein: The processor is further configured to: Information indicating an order in which the first response and the third response are received is stored in the nonvolatile memory, wherein the first response is a response to the first write request sent for the first time, and the third response is a response to the second write request sent for the first time.

9. The information processing apparatus according to claim 8, wherein: The processor is further configured to: Based on the fact that the storage system has been started, the first management data and the second management data are stored in the non-volatile memory, and the first write request is sent to the storage system for the second time and the second write request is sent to the storage system for the second time in the order in which the first response and the third response are received.

10. The information processing apparatus according to claim 9, wherein: The processor is further configured to, when the first management data and the second management data are stored in the nonvolatile memory in response to the storage system being activated, sending a second mode transfer request to the storage system; as well as When the storage system transitions from the first write mode to the second write mode according to the second mode transition request, the first write request is sent to the storage system for the second time and the second write request is sent to the storage system for the second time in the order in which the first response and the third response are received. The first write request sent for the second time and the second write request sent for the second time are processed by the storage system that has shifted to the second write mode in the order in which they are accepted. The information processing apparatus according to claim 10 , wherein: The processor is further configured to: When the first response and the second response to the first write request sent for the second time, and the third response and the fourth response to the second write request sent for the second time are received from the storage system, a second mode release request is sent to the storage system, and the second mode release request causes the storage system operating in the second write mode to be transferred to the first write mode.

12. The information processing apparatus according to claim 9, wherein: The processor is further configured to: In a case where the first write request and the second write request specify the same logical address, after one of the first write request is sent to the storage system for the second time and the second write request is sent to the storage system for the second time, a flash memory request is sent to the storage system, and the flash memory request enables the storage system to complete the data writing corresponding to the accepted write request.

13. The information processing apparatus according to claim 1, wherein: The processor is further configured to, when the first data and the first management data are stored in the nonvolatile memory before the operation of the storage system ends, sending a flash request to the storage system, the flash request causing the storage system to complete writing data corresponding to the accepted write request; as well as After receiving the first response and the second response to the first write request sent for the first time from the storage system, a request to terminate the operation of the storage system is sent to the storage system.

14. The information processing apparatus according to claim 1, wherein: The processor is further configured to: After locking the first data so that a storage area in the nonvolatile memory storing the first data is not released, sending the first write request to the storage system for the first time; as well as The first data is unlocked in response to receipt of the second response from the storage system to the first write request sent for the first time.

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