Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, wherein the semiconductor structure comprises: a channel structure, comprising a first channel structure which is spaced and suspended above the first protruding part, the first channel structure comprising one or more first channel layers which are sequentially and spaced, the first channel layers are stacked in a direction perpendicular to the substrate surface; and along the arrangement direction of the first protruding part, the first channel layer is a wave-shaped structure with a <111> crystal plane, in the semiconductor field, the hole mobility of the channel of the PMOS device in the <111> crystal plane is greater than that in the <100> crystal plane, so that the embodiment of the present application can provide the PMOS device with a channel with a <111> crystal plane, which is conducive to improving the channel mobility of the PMOS device, and the first channel layer is a wave-shaped structure, which is also conducive to increasing the effective channel width of the PMOS device; in summary, the embodiment of the present application is conducive to improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration, and semiconductor process nodes are continuously shrinking in accordance with Moore's Law. Transistors, as the most basic semiconductor devices, are currently widely used. Therefore, as the component density and integration of semiconductor devices increase, the channel length of transistors must be continuously shortened to adapt to the shrinking process nodes.

[0003] To better adapt to the requirements of proportionally shrinking device dimensions, semiconductor manufacturing processes are gradually transitioning from planar transistors to more efficient three-dimensional transistors, such as gate-all-around (GAA) transistors, nanosheet field-effect transistors (NSFETs), forksheet transistors, and complementary field-effect transistors (CFETs). Among these, in GAA transistors, the gate surrounds the channel region from all sides. Compared to planar transistors, GAA transistors offer stronger control over the channel and better suppress short-channel effects.

[0004] However, the performance of the device still needs to be improved. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate including a PMOS region for forming a PMOS device; a plurality of first protrusions disposed on the substrate of the PMOS region; an isolation layer located on the substrate and surrounding the first protrusions, the isolation layer exposing the top surface of the first protrusions; a channel structure including a first channel structure spaced apart and suspended above the first protrusions, the first channel structure including one or more first channel layers spaced apart sequentially, the first channel layers being stacked in a direction perpendicular to the substrate surface; and the first channel layers having a [missing information - likely a specific feature or characteristic] along the arrangement direction of the first protrusions. <111> A wavy crystal structure; a gate structure including a first gate structure located on the isolation layer in the PMOS region and spanning the first channel structure, the first gate structure surrounding the first channel layer; source / drain doped regions located within the channel structures on both sides of the gate structure; the source / drain doped regions including first source / drain doped regions located on both sides of the first gate structure and contacting the end of each first channel layer in the first channel structure along the extension direction.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a PMOS region for forming a PMOS device, wherein a plurality of discrete first protrusions are formed on the substrate of the PMOS region; forming an isolation layer surrounding the first protrusions on the substrate, wherein the top surface of the isolation layer is lower than the top surface of the first protrusions; removing a portion of the thickness of the first protrusions, and forming a groove within the first protrusions; forming a first stacked structure within the groove, the first stacked structure being located on the first protrusions, the first stacked structure including one or more first channel stacks stacked sequentially from bottom to top, each first channel stack including a first sacrificial layer and a first channel layer located on the first sacrificial layer; and, along the arrangement direction of the first protrusions, the first channel layer having... <111> A wavy structure on the crystal plane; a pseudo-gate structure is formed on the isolation layer, spanning the first stacked structure, the pseudo-gate structure covering part of the top and part of the sidewalls of the first stacked structure; first source / drain doped regions are formed in the first stacked structures on both sides of the pseudo-gate structure; after forming the first source / drain doped regions, the pseudo-gate structure is removed to form a gate opening, the gate opening exposing the first channel stack; through the gate opening, a first sacrificial layer in the first channel stack is removed to form a first through-slot, the first through-slot being surrounded by a first protrusion and a first channel layer adjacent to the first protrusion, or by an adjacent first channel layer; a first gate structure is filled in the first through-slot and the gate opening of the PMOS region, the first gate structure surrounding the first channel layer.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] In the semiconductor structure provided by the embodiments of the present invention, along the arrangement direction of the first protrusion, the first channel layer has <111> The wavy structure of the crystal plane, in the semiconductor field, is the channel of PMOS devices. <111> The hole mobility on the crystal plane is greater than that on the crystal plane. <100> The hole mobility of the crystal plane, thus the embodiments of the present invention can provide PMOS devices with <111> The channel on the crystal plane is beneficial to improving the channel mobility of the PMOS device. Furthermore, the first channel layer has a wavy structure, which is also beneficial to increasing the effective channel width of the PMOS device. In summary, the embodiments of the present invention are beneficial to improving the performance of the semiconductor structure.

[0010] In the semiconductor structure formation method provided by the embodiments of the present invention, in the step of forming the first stacked structure, along the arrangement direction of the first protrusions, the first channel layer is having <111> The wavy structure of the crystal plane, in the semiconductor field, is the channel of PMOS devices. <111> The hole mobility on the crystal plane is greater than that on the crystal plane. <100> The hole mobility of the crystal plane, thus the embodiments of the present invention can provide PMOS devices with <111> The channel on the crystal plane is beneficial to improving the channel mobility of the PMOS device. Furthermore, the first channel layer has a wavy structure, which is also beneficial to increasing the effective channel width of the PMOS device. In summary, the embodiments of the present invention are beneficial to improving the performance of the semiconductor structure. Attached Figure Description

[0011] Figures 1 to 2 This is a schematic diagram of a semiconductor structure.

[0012] Figures 3 to 5 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0013] Figures 6 to 26 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0014] As can be seen from the background technology, the performance of current devices needs to be improved.

[0015] Taking the fully enclosed gate transistor as an example, we will analyze the reasons why the performance of the device needs to be improved by combining a semiconductor structure. Figures 1 to 2 This is a schematic diagram of a semiconductor structure. Figure 1 It is a cross-sectional view along the direction perpendicular to the conductive channel. Figure 2 yes Figure 1 A sectional view along the 1-1 direction.

[0016] like Figures 1 to 2As shown, the semiconductor structure includes: a substrate 1; a plurality of protrusions 2, disposed on the substrate 1; a channel structure 4, including one or more channel layers 3 disposed sequentially at intervals, the channel layers 3 being stacked in a direction perpendicular to the surface of the substrate 1; an isolation layer 5, located on the substrate 1 and surrounding the protrusions 2 and exposing the channel structure 4; a gate structure 6, located on the isolation layer 5 and spanning the channel structure 4 and surrounding the channel layers 3; a gate dielectric layer 7, located between the gate structure 6 and the channel layers 3; and source / drain doped regions 8, located in the channel structures 4 on both sides of the gate structure 6 and in contact with the end of each channel layer 3 in the channel structure 4 along the extension direction.

[0017] Taking the semiconductor structure as an example of a fully enclosed gate transistor (or nanosheet field-effect transistor), the gate structure 6 surrounds the channel layer 3, that is, the gate structure 6 surrounds the area where the channel is located from all sides.

[0018] In the semiconductor field, the conductive channel of NMOS devices is... <100> The crystal plane has high electron mobility, and the conductive channel of the PMOS device is in... <110> The hole mobility of the crystal plane is relatively high, while the conductive channel of the PMOS device is... <100> The hole mobility of the crystal plane is low. In the semiconductor structure, for both NMOS and PMOS devices, the channel layer 3 is a cuboid structure, and the crystal plane of the channel layer 3 includes... <100> Crystal planes (e.g.) Figure 1 (as shown) and <110> Crystal planes (e.g.) Figure 1 As shown), and, the channel layer 3 is in <110> The area of ​​the crystal plane is smaller than that in <110> The area of ​​the crystal plane results in a low hole mobility in PMOS devices, leading to poor performance.

[0019] To address the aforementioned technical problem, embodiments of the present invention provide a semiconductor structure in which the first channel layer has a [missing information - likely a specific feature or characteristic] along the arrangement direction of the first protrusions. <111> The wavy structure of the crystal plane, in the semiconductor field, is the channel of PMOS devices. <111> The hole mobility on the crystal plane is greater than that on the crystal plane. <100> The hole mobility of the crystal plane, in the semiconductor field, thus the embodiments of the present invention can provide PMOS devices with... <111> The channel on the crystal plane is beneficial to improving the channel mobility of the PMOS device. Furthermore, the first channel layer has a wavy structure, which is also beneficial to increasing the effective channel width of the PMOS device. In summary, the embodiments of the present invention are beneficial to improving the performance of the semiconductor structure.

[0020] To address the aforementioned technical problem, embodiments of the present invention also provide a method for forming a semiconductor structure. In the step of forming the first stacked structure, along the arrangement direction of the first protrusions, the first channel layer is a layer having… <111> The wavy structure of the crystal plane, in the semiconductor field, is the channel of PMOS devices. <111> The hole mobility on the crystal plane is greater than that on the crystal plane. <100> The hole mobility of the crystal plane, in the semiconductor field, thus the embodiments of the present invention can provide PMOS devices with... <111> The channel on the crystal plane is beneficial to improving the channel mobility of the PMOS device. Furthermore, the first channel layer has a wavy structure, which is also beneficial to increasing the effective channel width of the PMOS device. In summary, the embodiments of the present invention are beneficial to improving the performance of the semiconductor structure.

[0021] To make the above-mentioned objects, features, and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (Reference) Figures 3 to 5 , Figure 3 This is a top view. Figure 4 for Figure 3 Cross-sectional view along the xx direction. Figure 5 for Figure 3 A cross-sectional view along the yy direction shows a schematic diagram of an embodiment of the semiconductor structure of the present invention.

[0022] like Figures 3 to 5 As shown, in this embodiment, the semiconductor structure includes: a substrate 100, including a PMOS region 100P for forming a PMOS device; a plurality of first protrusions 110, disposed on the substrate 100 of the PMOS region 100P; an isolation layer 120, located on the substrate 100 and surrounding the first protrusions 110, the isolation layer 120 exposing the top surface of the first protrusions 110; a channel structure, including a first channel structure 300 suspended above the first protrusions 100 of the PMOS region at intervals, the first channel structure 300 including one or more first channel layers 20 arranged sequentially at intervals, the first channel layers 20 being stacked in a direction perpendicular to the surface of the substrate 100; along the arrangement direction of the first protrusions 110, the first channel layers 20 having <111> The crystal plane has a wavy structure; a gate structure including a first gate structure 240 located on the isolation layer 120 of the PMOS region 100P and spanning the first channel structure 300, the first gate structure 240 surrounding the first channel layer 20; source / drain doped regions located within the channel structures on both sides of the gate structure; the source / drain doped regions include first source / drain doped regions 170 located on both sides of the first gate structure 240 and contacting the end of each first channel layer 20 in the first channel structure 300 along the extension direction.

[0023] The substrate 100 serves as a process platform for the formation of field-effect transistors. In this embodiment, the substrate 100 serves as a process platform for forming a gate-all-around (GAA) transistor or a nanosheet field-effect transistor (NSFET). In other embodiments, the substrate can also serve as a process platform for forming other types of transistors, such as forksheet transistors and complementary field-effect transistors (CFETs).

[0024] The substrate 100 includes a PMOS region 100P for forming a PMOS device.

[0025] It should be noted that, in this embodiment, the substrate 100 further includes an NMOS region (not shown) for forming an NMOS device.

[0026] In this embodiment, the substrate 100 is a silicon substrate, that is, the material of the substrate 100 is single-crystal silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, and gallium arsenide, and the substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0027] The first protrusion 110 serves to support the gate structure and the channel structure located above the first protrusion 110. The first protrusion 110 also serves to provide space for forming the isolation layer 120 so that the isolation layer 120 can surround the first protrusion 110 and expose the channel structure, and the isolation layer 120 can isolate the substrate 100 and the gate structure.

[0028] In this embodiment, the first protrusion 110 and the substrate 100 are an integral structure, and the first protrusion 110 and the substrate 100 are made of the same material, silicon. In other embodiments, the material of the first protrusion may be different from the material of the substrate. The material of the first protrusion may be other suitable materials, such as one or more of germanium, silicon germanide, silicon carbide, gallium nitride, and gallium arsenide.

[0029] In this embodiment, the first protrusion 110 is along the X direction (e.g., Figure 3 As shown), the first protrusion 110 extends in the Y direction (e.g., as shown). Figure 3 As shown in the figure, the X direction is perpendicular to the Y direction.

[0030] In this embodiment, a discrete second protrusion (not shown) is also formed on the substrate 100 of the NMOS region. The second protrusion is used to support the gate structure and the channel structure located above the second protrusion. The second protrusion is also used to provide space for the formation of the isolation layer 120 so that the isolation layer 120 can surround the second protrusion and expose the channel structure, thereby enabling the isolation layer 120 to isolate the substrate 100 and the gate structure.

[0031] In this embodiment, the second protrusion and the substrate 100 are an integral structure, and the second protrusion and the substrate 100 are made of the same material, silicon. In other embodiments, the material of the second protrusion may be different from the material of the substrate. The material of the second protrusion may be other suitable materials, such as one or more of germanium, silicon germanide, silicon carbide, gallium nitride, and gallium arsenide.

[0032] In this embodiment, the second protrusion extends along the X direction, and the arrangement direction of the second protrusion is the Y direction, wherein the X direction is perpendicular to the Y direction.

[0033] The isolation layer 120 is used to isolate adjacent first protrusions 110, and also to isolate the substrate 100 from the gate structure. In this embodiment, the isolation layer 120 is also used to isolate adjacent second protrusions and to isolate the first protrusion from the second protrusion.

[0034] In this embodiment, the material of the insulating layer 120 is silicon oxide. The material of the insulating layer 120 can also be other insulating materials, such as one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, germanium silicon oxide, boron nitride, and boron carbonitride.

[0035] Channel structures are used to provide conductive channels for field-effect transistors.

[0036] Specifically, the first channel structure 300 is used to provide a conductive channel for the PMOS device. One or more first channel layers 20 are stacked in a direction perpendicular to the surface of the substrate 100. More specifically, the first channel layer 20 is used to provide a conductive channel for the PMOS device.

[0037] Along the arrangement direction of the first protrusions 110, the first channel layer 20 has <111> The wavy structure of the crystal plane, in the semiconductor field, is the channel of PMOS devices. <111> The hole mobility on the crystal plane is greater than that on the crystal plane. <100> The hole mobility of the crystal plane, thus this embodiment can provide PMOS devices with <111> The channel on the crystal plane is beneficial to improving the channel mobility of the PMOS device. Furthermore, compared with the first channel layer 20 having a linear structure, the first channel layer 20 has a wavy structure, which is also beneficial to increasing the effective channel width of the PMOS device. In summary, this embodiment is beneficial to improving the performance of the semiconductor structure.

[0038] Specifically, in the semiconductor field, for PMOS devices, the channel is... <111> The hole mobility on the crystal plane is greater than that on the crystal plane. <100> The hole mobility of the crystal plane, and to make the first channel layer 20 have <110> Crystal facets and <110> Compared to a larger crystal plane area, by making the first channel layer 20 a wavy structure, the first channel layer 20 thus possesses... <111> Crystal planes are easier to obtain, and larger crystals are also easier to obtain in wavy structures. <111> Crystal plane area is beneficial for improving the carrier mobility of PMOS devices while reducing the difficulty of the process and making it easier to achieve mass production.

[0039] In this embodiment, the material of the first channel layer 20 includes Si; or, the material of the first channel layer 20 includes SiGe, and the Ge concentration in the first channel layer 20 is 0% to 30%. As an example, the material of the first channel layer 20 is SiGe.

[0040] In other embodiments, the material of the first channel layer includes one or more of monocrystalline silicon, germanium, silicon germanide, silicon carbide, gallium nitride, and gallium arsenide.

[0041] As one embodiment, along the arrangement direction (i.e., the Y direction) of the first protrusions 110, a plurality of adjacent first protrusions 110 form a protrusion group 140, and each first channel layer 20 on the protrusion group 140 is connected to each other, thereby increasing the width of the first channel layer 20 along the arrangement direction of the first protrusions 110, and thus increasing the effective channel width of the PMOS device.

[0042] Specifically, in this embodiment, each first channel layer 20 is an integral structure along the arrangement direction of the first protrusion 110.

[0043] In this embodiment, a protrusion group 140 is formed by four adjacent first protrusions 110, and the first channel structures 300 on the protrusion group 140 are connected to each other as an example. In other embodiments, other numbers of first protrusions may be used to form the protrusion group, such as two, three, or five first protrusions.

[0044] In other embodiments, the first channel structures located on a single first protrusion may also be independent of each other along the arrangement direction of the first protrusion.

[0045] In this embodiment, the example given is that the first channel structure 300 has multiple first channel layers 20, and the stacking direction of the multiple first channel layers 20 is perpendicular to the surface of the substrate 100. As an example, the number of first channel layers 20 is three. In other embodiments, the number of first channel layers in the first channel structure can also be other, such as two, four, five, etc.

[0046] In this embodiment, the channel structure further includes a second channel structure (not shown), which is suspended above the second protrusion at intervals. The second channel structure includes one or more second channel layers that are spaced apart in sequence, and the second channel layers are stacked in a direction perpendicular to the surface of the substrate 100.

[0047] Specifically, the second channel layer is used to provide a conductive channel for the NMOS device.

[0048] In this embodiment, the second channel layer has a cuboid structure, that is, the second channel layer has a linear structure, and the surface of the second channel layer has <100> Crystal planes are beneficial for NMOS devices to have higher electron mobility, thereby improving the performance of NMOS devices.

[0049] In this embodiment, the NMOS region is used to form an NMOS transistor, and the material of the second channel layer is Si, which is beneficial to improving the performance of the NMOS device.

[0050] In this embodiment, the second channel layer is made of the same material as the first protrusion 110. In other embodiments, the second channel layer and the first protrusion may be made of different materials.

[0051] In other embodiments, the material of the second channel layer may also be one or more of silicon germanide, germanium, silicon carbide, gallium nitride, and gallium arsenide.

[0052] When the device is in operation, the gate structure is used to control the opening and closing of the conductive channel of the device.

[0053] Specifically, when the device is in operation, the first gate structure 240 is used to control the opening and closing of the conductive channel of the PMOS device.

[0054] In this embodiment, the first gate structure 240 filling between each first protrusion 110 and the first channel layer 20 adjacent to the first protrusion 110 is a first portion 240(1), and the first portion 240(1) is a Sigma-type structure, thereby the surface of the first channel layer 20 adjacent to the first protrusion 110 has a corresponding... <111> Crystal facets.

[0055] When there are multiple first channel layers 20 in the first channel structure 300, the first gate structure 240 filling the spaces between adjacent first channel layers 20 is a second portion 240 (2); the first channel layers 20 and the second portion 240 (2) are sequentially and conformally stacked on the first portion 240 (1), so that the surfaces of the multiple first channel layers 20 in the first channel structure 300 all have <111> Crystal facets.

[0056] In this embodiment, the first gate structure 240 spanning the first channel structure 300 is a third part 240(3), and the third part 240(3), the second part, and the first part constitute the first gate structure 240.

[0057] In this embodiment, the first gate structure 240 is a metal gate structure.

[0058] In this embodiment, the first gate structure 240 includes a first gate dielectric layer 41 and a first gate electrode layer 42 located on the first gate dielectric layer 41.

[0059] The first gate dielectric layer 41 is used to achieve electrical insulation between the first gate electrode layer 41 and the conductive channel.

[0060] The material of the first gate dielectric layer 41 includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3.

[0061] In this embodiment, the first gate dielectric layer 41 includes a high-k gate dielectric layer (not shown), and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3. In other embodiments, the first gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the first gate dielectric layer may only include a gate oxide layer.

[0062] The first gate electrode layer 42 is used as an external electrode for electrically connecting the first gate structure 240 to an external circuit. The material of the first gate electrode layer 42 includes one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0063] In a specific embodiment, the first gate electrode layer 42 may include: a cover layer (not shown), a work function layer (not shown), a barrier layer (not shown), and a metal electrode layer stacked sequentially on the gate dielectric layer 41.

[0064] It should be noted that, in this embodiment, the gate structure further includes a second gate structure (not shown), which surrounds the second channel layer.

[0065] The second gate structure is used to enable and disable the conductive channel of the NMOS device. In this embodiment, the second gate structure is a metal gate structure.

[0066] As an example, the second gate structure includes a second gate dielectric layer and a second gate electrode layer located on the second gate dielectric layer.

[0067] For a detailed description of the second gate structure, please refer to the corresponding description of the first gate structure 240 above, which will not be repeated here.

[0068] In this embodiment, along the extension direction perpendicular to the gate structure, the end of the gate structure is recessed relative to the end on the same side of the channel structure; the gate structure spanning the channel structure is a gate spanning portion (not shown), the first gate structure located between the first protrusion 110 and the first channel layer 20 or between adjacent first channel layers 20, and the second gate structure located between the second protrusion and the second channel layer or between adjacent second channel layers are a gate interlayer portion (not shown).

[0069] In this embodiment, the semiconductor structure further includes: a gate sidewall 160 located on the sidewall of the gate span portion and exposing the end of the channel structure along the extension direction; and an inner sidewall 180 located on the sidewall of the gate interlayer portion and exposing the end of the channel structure along the extension direction.

[0070] The gate sidewall 160 is used to define the formation location of the source and drain doped regions, and the gate sidewall 160 is also used to protect the sidewall of the gate structure.

[0071] In this embodiment, the material of the gate sidewall 160 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material, or ultra-low-k dielectric material, and the gate sidewall 160 is a single-layer or multi-layer structure. As an example, the gate sidewall 160 is a single-layer structure, and the material of the gate sidewall 160 is silicon nitride.

[0072] The inner wall 180 is used to isolate the source / drain doped regions from the gate structure, and also increases the distance between the gate structure and the source / drain doped regions, which helps to reduce the parasitic capacitance between the gate structure and the source / drain doped regions.

[0073] In this embodiment, the inner sidewall 180 is made of an insulating material to achieve isolation between the gate structure and the source / drain doped regions. In this embodiment, the material of the inner sidewall 180 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material, or ultra-low-k dielectric material. As an example, the material of the inner sidewall 180 is silicon nitride.

[0074] The source and drain doped regions are used as the source or drain of a field-effect transistor.

[0075] The first source / drain doped region 170 is used as the source or drain of the PMOS field-effect transistor. When the field-effect transistor is working, the first source / drain doped region 170 is used to provide a carrier source for the PMOS device.

[0076] In this embodiment, the first source / drain doped region 170 includes a stress layer doped with ions. The stress layer is used to provide stress to the channel region, thereby improving the carrier mobility. Specifically, the first source / drain doped region 170 is used as the source or drain of a PMOS field-effect transistor. The first source / drain doped region 170 includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe.

[0077] In this embodiment, the source / drain doped region further includes: a second source / drain doped region (not shown), located on both sides of the second gate structure, and in contact with the end of each second channel layer in the second channel structure along the extension direction.

[0078] The second source-drain doped region is used as the source or drain of the NMOS field-effect transistor. When the field-effect transistor is working, the second source-drain doping is used to provide a carrier source for the NMOS device.

[0079] In this embodiment, the second source / drain doped region includes a stress layer doped with ions. The stress layer is used to provide stress to the channel region, thereby improving the carrier mobility. Specifically, the second source / drain doped region is used as the source or drain of an NMOS field-effect transistor. The second source / drain doped region includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe.

[0080] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 190, which is located on the exposed isolation layer 120 of the gate structure and covers the source and drain doped regions.

[0081] The interlayer dielectric layer 190 covers the sidewall of the gate sidewall 160 and the first source / drain doped region 170. In this embodiment, the interlayer dielectric layer 190 also covers the second source / drain doped region.

[0082] The interlayer dielectric layer 190 is used to isolate adjacent devices. In this embodiment, the material of the interlayer dielectric layer 190 is silicon oxide. The material of the interlayer dielectric layer 190 can also be other insulating materials.

[0083] In this embodiment, for ease of illustration and explanation, only the interlayer dielectric layer 190 and the isolation layer 120 are shown in the cross-sectional view.

[0084] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 6 to 26 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0085] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0086] refer to Figures 6 to 7 , Figure 6 This is a top view. Figure 7 for Figure 6 A cross-sectional view along the yy direction shows a substrate 100, which includes a PMOS region 100P for forming a PMOS device, and a plurality of discrete first protrusions 110 are formed on the substrate 100 of the PMOS region 100P.

[0087] The substrate 100 serves as a process platform for subsequent fabrication processes. In this embodiment, the substrate 100 serves as a process platform for forming a gate-all-around (GAA) transistor or a nanosheet field-effect transistor (NSFET). In other embodiments, the substrate can also serve as a process platform for forming other types of transistors, such as forksheet transistors and complementary field-effect transistors (CFETs).

[0088] The substrate 100 includes a PMOS region 100P for forming a PMOS device.

[0089] In this embodiment, the substrate 100 is a silicon substrate, that is, the material of the substrate 100 is single-crystal silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, and gallium arsenide, and the substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0090] The first protrusion 110 is used to support the subsequent stacked structure. The first protrusion 110 is also used to provide space for forming an isolation layer so that the subsequent isolation layer can surround the first protrusion 110 and expose the stacked structure, and the isolation layer can isolate the substrate 100 and the gate structure.

[0091] In this embodiment, the first protrusion 110 and the substrate 100 are an integral structure, and the first protrusion 110 and the substrate 100 are made of the same material, silicon. In other embodiments, the material of the first protrusion may be different from the material of the substrate. The material of the first protrusion may be other suitable materials, such as one or more of germanium, silicon germanide, silicon carbide, gallium nitride, and gallium arsenide.

[0092] In this embodiment, the first protrusion 110 is along the X direction (e.g., Figure 6 As shown), the first protrusion 110 extends in the Y direction (e.g., as shown). Figure 6 As shown in the figure, the X direction is perpendicular to the Y direction.

[0093] It should be noted that, in this embodiment, the substrate 100 further includes an NMOS region (not shown) for forming an NMOS device. During the step of providing the substrate, discrete second protrusions (not shown) are also formed on the substrate of the NMOS region. A second stacked structure (not shown) is also formed on the second protrusion. The second stacked structure includes one or more second channel stacks (not shown) stacked sequentially from bottom to top. Each second channel stack includes a second sacrificial layer and a second channel layer located on the second sacrificial layer.

[0094] The second protrusion serves to support the gate structure and channel structure located above the second protrusion. The second protrusion also provides space for forming the isolation layer 120 so that the isolation layer 120 can surround the second protrusion and expose the channel structure, and the isolation layer 120 can isolate the substrate 100 and the gate structure.

[0095] In this embodiment, the second protrusion and the substrate 100 are an integral structure, and the second protrusion and the substrate 100 are made of the same material, silicon. In other embodiments, the material of the second protrusion may be different from the material of the substrate. The material of the second protrusion may be other suitable materials, such as one or more of germanium, silicon germanide, silicon carbide, gallium nitride, and gallium arsenide.

[0096] In this embodiment, the second protrusion extends along the X direction, and the arrangement direction of the second protrusion is the Y direction, wherein the X direction is perpendicular to the Y direction.

[0097] The second channel stack provides a process basis for the subsequent formation of a second channel layer with suspended space partitions.

[0098] Specifically, the second channel layer is used to provide a conductive channel for the NMOS device, and the second sacrificial layer is used to support the second channel layer, thereby providing a process basis for the subsequent implementation of the spaced floating arrangement of the second channel layer. The second sacrificial layer is also used to occupy space for the subsequent formation of the second gate structure.

[0099] In this embodiment, the second channel layer has a cuboid structure, that is, the second channel layer has a linear structure, and the surface of the second channel layer has <100> Crystal planes are beneficial for NMOS devices to have higher electron mobility, thereby improving the performance of NMOS devices.

[0100] In this embodiment, the NMOS region is used to form an NMOS transistor. The material of the second channel layer is Si, and the material of the second sacrificial layer is SiGe. During the subsequent removal of the second sacrificial layer, the etching selectivity of SiGe and Si is relatively high. Therefore, by setting the material of the second sacrificial layer to SiGe and the material of the second channel layer to Si, the impact of the removal process of the second sacrificial layer on the second channel layer can be effectively reduced, thereby improving the quality of the second channel layer and thus contributing to improved NMOS device performance.

[0101] In this embodiment, the second channel layer is made of the same material as the first protrusion 110. In other embodiments, the second channel layer and the first protrusion may be made of different materials.

[0102] In other embodiments, the material of the second channel layer may also be one or more of silicon germanide, germanium, silicon carbide, gallium nitride, and gallium arsenide.

[0103] In this embodiment, the top surface of the second protrusion is lower than the top surface of the first protrusion 110, thereby preventing the top surface of the second stacked structure from being too high, which in turn helps to make the formed NMOS device have a smaller thickness.

[0104] refer to Figure 8An isolation layer 120 is formed on the substrate 100 surrounding the first protrusion 110, the top surface of the isolation layer 120 being lower than the top surface of the first protrusion 110.

[0105] The isolation layer 120 is used to isolate adjacent first protrusions 110, and also to isolate the substrate 100 from the subsequent dummy gate structure, and from the gate structure. In this embodiment, the isolation layer 120 also surrounds the second protrusion and exposes the second stacked structure.

[0106] In this embodiment, the material of the insulating layer 120 is silicon oxide. The material of the insulating layer 120 can also be other insulating materials, such as one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon germanium silicon oxide, boron nitride, boron carbonitride, and silicon germanium silicon oxide.

[0107] refer to Figure 9 This shows that based on Figure 8 A cross-sectional view shows that a portion of the thickness of the first protrusion 110 located in the PMOS region 100P is removed, and a groove 130 is formed in the first protrusion 110 of the PMOS region 100P.

[0108] The groove 130 is used to provide a spatial location for forming the first stacked structure.

[0109] By removing a portion of the thickness of the first protrusion 110 of the PMOS region 100P, thereby reducing the top surface height of the first protrusion 110 of the PMOS region 100P, the top surface height of the first stacked structure located on the first protrusion 110 is correspondingly reduced in the subsequent step of forming a first stacked structure in the groove 130.

[0110] Specifically, a dry etching process can be used to remove a portion of the first protrusion 110 located in the PMOS region 100P. The dry etching process has high process controllability and etching precision, which is beneficial for precise control of the removal thickness of the first protrusion 110 in the PMOS region 100P.

[0111] refer to Figures 10 to 14 A first stacked structure 200 is formed within the groove 130. The first stacked structure 200 is located on the first protrusion 110 of the PMOS region 100P. The first stacked structure 200 includes one or more first channel stacks 210 stacked sequentially from bottom to top. Each first channel stack 210 includes a first sacrificial layer 10 and a first channel layer 20 located on the first sacrificial layer 10. Along the arrangement direction of the first protrusion 110, the first channel layer 20 has... <111> The wavy structure of the crystal facets.

[0112] Along the arrangement direction of the first protrusions 110, the first channel layer 20 has <111> The wavy structure of the crystal plane, in the semiconductor field, is the channel of PMOS devices. <111> The hole mobility on the crystal plane is greater than that on the crystal plane. <100> The hole mobility of the crystal plane, thus this embodiment can provide PMOS devices with <111> The channel on the crystal plane is beneficial to improving the channel mobility of the PMOS device. Furthermore, compared with the first channel layer having a linear structure, the first channel layer 20 provided in this embodiment has a wavy structure, which is also beneficial to increasing the effective channel width of the PMOS device. In summary, this embodiment is beneficial to improving the performance of the semiconductor structure.

[0113] Specifically, in the semiconductor field, for PMOS devices, the channel is... <111> The hole mobility on the crystal plane is greater than that on the crystal plane. <100> The hole mobility of the crystal plane, and to make the first channel layer 20 have <110> Crystal facets and <110> Compared to a larger crystal plane area, by making the first channel layer 20 a wavy structure, the first channel layer 20 thus possesses... <111> Crystal planes are easier to obtain, and larger crystals are also easier to obtain in wavy structures. <111> Crystal plane area is beneficial for improving the carrier mobility of PMOS devices while reducing the difficulty of the process and making it easier to achieve mass production.

[0114] The first channel stack 210 provides a process basis for the subsequent formation of the first channel layer 20 with suspended space partition.

[0115] Specifically, the first channel layer 20 is used to provide a conductive channel for the PMOS device, and the first sacrificial layer 10 is used to support the first channel layer 20, thereby providing a process basis for the subsequent implementation of the spaced floating arrangement of the first channel layer 20. The first sacrificial layer 10 is also used to occupy space for the subsequent formation of the gate structure.

[0116] In this embodiment, the material of the first sacrificial layer 10 includes SiGe; the material of the first channel layer 20 includes Si; or, the material of the first channel layer 20 includes SiGe, and the Ge concentration in the first channel layer 20 is different from the Ge concentration in the first sacrificial layer 10.

[0117] Specifically, when the material of the first channel layer 20 is Si, there is a high etching selectivity between Si and SiGe, which correspondingly results in a high etching selectivity ratio between the first sacrificial layer 10 and the first channel layer 20, so as to prevent the first channel layer 20 from being damaged during the subsequent removal of the sacrificial layer 10. When the material of the first channel layer 20 is SiGe, the Ge concentration in the first channel layer 20 is different from the Ge concentration in the first sacrificial layer 10. There is etching selectivity between SiGe materials with different Ge concentrations, which results in an etching selectivity ratio between the first sacrificial layer 10 and the first channel layer 20, reducing the probability of damage to the first channel layer 20 during the subsequent removal of the first sacrificial layer 10.

[0118] Specifically, when the material of the first channel layer 20 includes SiGe, the Ge concentration in the first channel layer 20 is lower than the Ge concentration in the first sacrificial layer 10. That is, the lower Ge concentration in the first channel layer 20 is beneficial for improving the hole mobility of the PMOS channel; the higher Ge concentration in the first sacrificial layer 10 is beneficial for further improving the etching selectivity between the first sacrificial layer 10 and the first channel layer 20, and further reducing the probability of damage to the first channel layer 20.

[0119] As an example, the material of the first channel layer 20 is SiGe.

[0120] The Ge concentration in the first channel layer 20 should not be too high; otherwise, the difference in Ge concentration between the first channel layer 20 and the first sacrificial layer 10 will make it difficult to meet the requirement of a high etching selectivity between the first sacrificial layer 10 and the first channel layer 20. Therefore, in this embodiment, the Ge concentration in the first channel layer 20 is 0% to 30%.

[0121] The Ge concentration in the first sacrificial layer 10 should not be too low; otherwise, the difference in Ge concentration between the first sacrificial layer 10 and the first channel layer 20 will not be sufficient to give the first sacrificial layer 10 and the first channel layer 20 a high etching selectivity, which will increase the likelihood of damage to the first channel layer 20 during the subsequent removal of the first sacrificial layer 10. Therefore, in this embodiment, the Ge concentration in the first sacrificial layer 10 is greater than or equal to 50%.

[0122] In this embodiment, in the step of forming the first stacked structure 200 in the groove 130, the first channel stack 210 closest to the first protrusion 110 is the bottom channel stack 210(a), the first sacrificial layer 10 in the bottom channel stack 210(a) is a sigma-type structure, and the first channel layer 20 in the bottom channel stack 210(a) conformally covers the first sacrificial layer 10.

[0123] The first sacrificial layer 10 in the bottom channel stack 210(a) has a Sigma-type structure, thus the surface of the first sacrificial layer 10 in the bottom channel stack 210(a) has <111> The crystal plane, and the surface of the first channel layer 20 conformally covering the first sacrificial layer 10, also have corresponding crystal planes. <111> Crystal facets.

[0124] When there are multiple first channel stacks 210, the first channel stack 210 located above the bottom channel stack 210(a) is the top channel stack 210(b), and the top channel stack 210(b) conformally covers the bottom channel stack 210(a).

[0125] The surface of the first channel layer 20 of the bottom channel stack 210(a) has <111> The surface of the first channel layer 20 in the top channel layer 210(b), which conformally covers the bottom channel layer 210(a), also has a crystal plane. <111> Crystal facets.

[0126] As one embodiment, in the step of forming the first stacked structure 200, along the arrangement direction (i.e., the Y direction) of the first protrusions 110, a plurality of adjacent first protrusions 110 form a protrusion group 140, and the first stacked structures 200 located on the protrusion group 140 are connected to each other, thereby increasing the width of the first stacked structure 200 along the arrangement direction of the first protrusions 110, correspondingly increasing the width of the first channel layer 20 along the arrangement direction of the first protrusions 110, and thus increasing the effective channel width of the PMOS device.

[0127] Specifically, the connection between the first stacked structures 200 on the protrusion group 140 means that, along the arrangement direction of the first protrusion 110, each first channel layer 20 on the protrusion group 140 is correspondingly connected to each other, and each first sacrificial layer 10 on the protrusion group 140 is correspondingly connected to each other.

[0128] In this embodiment, a protrusion group 140 is formed by four adjacent first protrusions 110, and the first stacked structures 200 on the protrusion group 140 are connected to each other as an example. In other embodiments, the protrusion group may be formed by other numbers of first protrusions, such as two, three, or five first protrusions.

[0129] In other embodiments, the first stacked structures located on a single first protrusion may also be independent of each other along the arrangement direction of the first protrusion.

[0130] In this embodiment, the example is taken where the number of first channel stacks 10 in the first stacked structure 200 is multiple, and the stacking direction of the multiple first channel stacks 210 is perpendicular to the surface of the substrate 100. As an example, the number of first channel stacks 210 is three. In other embodiments, the number of first channel stacks can also be other, such as two, four, five, etc.

[0131] In this embodiment, the steps for forming the first stacked structure 200 include:

[0132] like Figure 10 As shown, it illustrates the basis Figure 9 The cross-sectional view shows that a bottom sacrificial layer 10(a) is formed in the groove 130, and the bottom sacrificial layer 10(a) has a sigma-type structure; a bottom channel layer 20(a) is formed on the bottom sacrificial layer 10(a) and conformally covers the bottom sacrificial layer 10(a), and the bottom sacrificial layer 10(a) and the bottom channel layer 20(a) located on the bottom sacrificial layer 10(a) constitute a bottom channel stack 210(a).

[0133] In this embodiment, the process for forming the bottom sacrificial layer 10(a) and the bottom channel layer 20(a) includes an epitaxial process.

[0134] Specifically, in the step of forming the bottom sacrificial layer 10(a), by controlling the process parameters of the epitaxial process, the bottom sacrificial layer 10(a) is made into a sigma-type structure, thereby giving the surface of the bottom sacrificial layer 10(a) a certain shape. <111> Crystal facets.

[0135] After the bottom sacrificial layer 10(a) is formed, the bottom channel layer 20(a) is epitaxially grown on the bottom sacrificial layer 10(a) using the bottom sacrificial layer 10(a) as the growth base. Accordingly, the bottom channel layer 20(a) can conformally cover the bottom sacrificial layer 10(a) and has <111> Crystal facets.

[0136] When the number of the first channel stack 210 is multiple, such as Figures 11 to 14 As shown, the step of forming the first stacked structure 200 further includes forming one or more conformally covered top channel stacks 210(b) on the bottom channel stack 210(a).

[0137] The top channel stack 210(b) conformally covers the bottom channel stack 210(a), thereby enabling the channel layer 20 in the top channel stack 210(b) to have <111> Crystal facets.

[0138] Specifically, as an example, the steps for forming the top channel stack 210(b) include: Figure 11As shown, a top sacrificial layer 10(b) is formed; as Figure 13 As shown, a top channel layer 20(b) is formed on the top sacrificial layer 10(b).

[0139] In this embodiment, an epitaxial process is used to form a top sacrificial layer 10(b); an epitaxial process is used to form a top channel layer 20(b) on the top sacrificial layer 10(b).

[0140] It should be noted that, in this embodiment, the step of forming the top channel stack 210(b) further includes: after forming the top sacrificial layer 10(b) and before forming the top channel layer 20(b) on the top sacrificial layer 10(b), such as Figure 12 As shown, the top sacrificial layer 10(b) is subjected to a first corner rounding treatment, which is suitable for increasing the smoothness of the surface corners of the top sacrificial layer 10(b).

[0141] Performing a first corner rounding treatment on the top sacrificial layer 10(b) is suitable for increasing the smoothness of the surface corners of the top sacrificial layer 10(b), which is beneficial for forming a smooth surface of the top channel layer 20(b) on the top sacrificial layer 10(b), reducing the probability of forming sharp corners in the top channel layer 20(b), and correspondingly improving the corner smoothness of the surface of the top channel layer 20(b), thereby improving the reliability of the device.

[0142] As one embodiment, an isotropic etching process is used to perform a first corner rounding treatment on the top sacrificial layer 10(b). The isotropic etching process has the characteristics of isotropic etching, and the etching rate for corners is greater than the etching rate for planar surfaces, thereby achieving the effect of increasing the smoothness of the surface corners of the top sacrificial layer 10(b).

[0143] In this embodiment, the isotropic etching process includes plasma etching or wet etching. The plasma etching process can use H-based, Cl-based, F-based, or N-based plasma; the wet etching process can use HCl, HF, or NH3 to isotropically etch the top sacrificial layer 10(a).

[0144] In other embodiments, the first corner rounding process may be omitted based on actual process requirements.

[0145] refer to Figure 15 and Figure 16 , Figure 15 This is a top view. Figure 16 for Figure 15In a cross-sectional view along the yy direction, a pseudo-gate structure 150 is formed on the isolation layer 120, spanning the first stacked structure 200. The pseudo-gate structure 150 covers a portion of the top and a portion of the sidewalls of the first stacked structure 200. The extending direction (i.e., the Y direction) of the pseudo-gate structure 150 is perpendicular to the extending direction (i.e., the X direction) of the first protrusion 110.

[0146] The pseudo-gate structure 150 is used to pre-occupy space for the subsequent formation of the gate structure.

[0147] In this embodiment, during the step of forming the pseudo-gate structure 150, the pseudo-gate structure 150 also spans the second stacked structure and covers part of the top and part of the sidewalls of the second stacked structure.

[0148] The dummy gate structure 150 can be a stacked or single-layer structure. In this embodiment, the dummy gate structure 150 is a stacked structure, including a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) located on the dummy gate oxide layer. Specifically, the dummy gate structure 150 is a polysilicon gate structure or an amorphous silicon gate structure, the material of the dummy gate oxide layer can be silicon oxide or silicon oxynitride, and the material of the dummy gate layer can be polysilicon or amorphous silicon.

[0149] In this embodiment, after forming the dummy gate structure 150, the method for forming the semiconductor structure further includes forming a gate sidewall 160 on the sidewall of the dummy gate structure 150.

[0150] The gate sidewall 160 is used together with the dummy gate structure 150 as an etching mask for the subsequent etching process to form a groove, so as to define the formation position of the source and drain doped regions. The gate sidewall 160 is also used to protect the dummy gate structure 150 and the sidewalls of the subsequent gate structure.

[0151] In this embodiment, the material of the gate sidewall 160 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material, or ultra-low-k dielectric material, and the gate sidewall 160 is a single-layer or multi-layer structure. As an example, the gate sidewall 160 is a single-layer structure, and the material of the gate sidewall 160 is silicon nitride.

[0152] refer to Figures 17 to 18 , Figure 17 This is a top view. Figure 18 for Figure 17 A cross-sectional view along the x-direction shows first source / drain doped regions 170 formed in the first stacked structures 200 on both sides of the dummy gate structure 150. The first source / drain doped regions 170 are in contact with the ends of each first channel layer 20 in the first channel stack 210 along the extending direction. Specifically, the first source / drain doped regions 170 are located within the first stacked structures 200 on both sides of the dummy gate structure 150 and the gate sidewall 160.

[0153] The first source-drain doped region 170 is used as the source or drain of the PMOS field-effect transistor. When the field-effect transistor is working, the first source-drain doped region 170 is used to provide a carrier source for the PMOS device.

[0154] In this embodiment, the first source / drain doped region 170 includes a stress layer doped with ions. The stress layer is used to provide stress to the channel region, thereby improving the carrier mobility. Specifically, the first source / drain doped region 170 is used as the source or drain of a PMOS field-effect transistor. The first source / drain doped region 170 includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe.

[0155] Specifically, the step of forming the first source / drain doped region 170 includes: forming source / drain grooves (not shown) in the first stacked structure 200 on both sides of the pseudo-gate structure 150; and forming the first source / drain doped region 170 in the source / drain grooves.

[0156] It should be noted that, in this embodiment, after forming the source / drain trench and before forming the first source / drain doped region 170 in the source / drain trench, the method for forming the semiconductor structure further includes: etching the first sacrificial layer 10 exposed on the sidewall of the source / drain trench along the channel direction, so that the first sacrificial layer 10 and the adjacent first channel layer 20 form an inner trench (not shown), or so that the first sacrificial layer 10, the first protrusion 110, and the first channel layer 20 adjacent to the first protrusion 110 form an inner trench; and forming an inner sidewall 180 in the inner trench.

[0157] The inner wall 180 is used to isolate the first source / drain doped region 170 from the gate structure, and also increases the distance between the gate structure and the first source / drain doped region 170, which helps to reduce the parasitic capacitance between the gate structure and the first source / drain doped region 170.

[0158] In this embodiment, the inner sidewall 180 is made of an insulating material to achieve isolation between the gate structure and the first source / drain doped region 170. In this embodiment, the material of the inner sidewall 180 includes silicon nitride, silicon oxide, silicon oxynitride, a low-k dielectric material, or an ultra-low-k dielectric material. As an example, the material of the inner sidewall 180 is silicon nitride.

[0159] It should be noted that, in this embodiment, after forming the dummy gate structure 150, the method for forming the semiconductor structure further includes: forming a second source / drain doped region (not shown) in the second stacked structure on both sides of the dummy gate structure 150.

[0160] The second source / drain doped region is used as the source or drain of the NMOS field-effect transistor. When the field-effect transistor is operating, the second source / drain doping provides a carrier source for the NMOS device. In this embodiment, the second source / drain doping is located in the second stacked structure on both sides of the dummy gate structure 150 and the gate sidewall 160.

[0161] In this embodiment, the second source / drain doped region includes a stress layer doped with ions. The stress layer is used to provide stress to the channel region, thereby improving the carrier mobility. Specifically, the second source / drain doped region is used as the source or drain of an NMOS field-effect transistor. The second source / drain doped region includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe.

[0162] It should be noted that, along the extension direction perpendicular to the pseudo-gate structure, an inner wall is also formed between the second source / drain doped region and the second sacrificial layer. The specific description of the formation steps and materials of the inner wall will not be repeated here.

[0163] refer to Figure 19 This indicates that based on Figure 18 The cross-sectional view shows that, in this embodiment, the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer 190 on the isolation layer 120 exposed on the dummy gate structure 150.

[0164] The interlayer dielectric layer 190 covers the sidewall of the gate sidewall 160 and the first source / drain doped region 170. In this embodiment, the interlayer dielectric layer 190 also covers the second source / drain doped region.

[0165] The interlayer dielectric layer 190 is used to isolate adjacent devices. In this embodiment, the material of the interlayer dielectric layer 190 is silicon oxide. The material of the interlayer dielectric layer 190 can also be other insulating materials. In this embodiment, for ease of illustration and explanation, only the interlayer dielectric layer 190 and the isolation layer 120 are shown in a cross-sectional view.

[0166] refer to Figures 20 to 22 , Figure 20 This is a top view. Figure 21 for Figure 20 Cross-sectional view along the xx direction. Figure 22 for Figure 20 In the cross-sectional view along the yy direction, after the first source / drain doped region 170 is formed, the pseudo-gate structure 150 is removed to form a gate opening 220, which exposes the first channel stack 210.

[0167] The gate opening 220 provides spatial location for forming the gate structure. The gate opening 220 exposes the first channel stack 210 so that the first sacrificial layer 10 in the first channel stack 210 can be subsequently removed through the gate opening 220.

[0168] In this embodiment, the bottom of the gate opening 220 also exposes the isolation layer 10.

[0169] Specifically, in the step of removing the pseudo-gate structure 150, the gate opening 220 is formed in the interlayer dielectric layer 190, and the gate opening 220 is surrounded by the gate sidewall 160.

[0170] Continue to refer to Figures 20 to 22 , Figure 20 This is a top view. Figure 21 for Figure 20 Cross-sectional view along the xx direction. Figure 22 for Figure 20 In the cross-sectional view along the yy direction, the first sacrificial layer 10 in the first channel stack 210 is removed through the gate opening 220 to form a through groove 230. The through groove 30 is surrounded by the first protrusion 110 and the first channel layer 20 adjacent to the first protrusion 110, or by the adjacent first channel layer 20.

[0171] The through-slot 230 and the gate opening 220 together provide space for forming the gate structure. The through-slot 230 is connected to the gate opening 220.

[0172] In the step of removing the first sacrificial layer 10 to form the first through groove 230, along the arrangement direction (i.e., the Y direction) of the first protrusions 110, the first channel layer 20 located on the protrusion group 140 has a wavy structure, so that the first channel layer 20 has a wavy structure along the arrangement direction (i.e., the Y direction) of the first protrusions 110. <111> Crystal planes in the direction of orientation.

[0173] It should be noted that, in this embodiment, since the first channel layer 20 has a wavy structure along the arrangement direction of the first protrusions 110, the process of removing the first sacrificial layer 10 within the irregular slits is more difficult. In this embodiment, in order to ensure that the first sacrificial layer 10 can be completely removed and to prevent the first sacrificial layer 10 from leaving residue, in the step of removing the first sacrificial layer 10 from the first channel stack 210, the etching selectivity ratio of the first sacrificial layer 10 to the first channel layer 20 is at least 20:1.

[0174] In this embodiment, the material of the first sacrificial layer 10 includes SiGe, and the process for removing the first sacrificial layer 10 includes a wet etching process. The wet etching process has the characteristic of isotropic etching, which facilitates the complete removal of each of the first sacrificial layers 10 located within the irregular slits. Specifically, in this embodiment, the etching solution used in the wet etching process is an APM etching solution (SC1, standard clean 1), which can achieve a high etching selectivity for SiGe and Si. The APM etching solution refers to a mixed solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water.

[0175] In other embodiments, the etching solution or etching vapor in the wet etching process is HCl, which can also achieve a high etching selectivity for SiGe and Si.

[0176] In this embodiment, after removing the first sacrificial layer 10, the first channel layer 20 and the first protrusion 110 are spaced apart, and adjacent first channel layers 20 are suspended at intervals. The one or more suspended first channel layers 20 are used to form the channel structure 300.

[0177] It should be noted that in the step of removing the first sacrificial layer 10 in the first channel stack 210 through the gate opening 220, the second sacrificial layer in the second channel stack is also removed to form a second through slot (not shown). The second through slot is surrounded by the second protrusion and the second channel layer adjacent to the second protrusion, or by the adjacent second channel layer. The second through slot is connected to the gate opening of the NMOS region.

[0178] The second through slot and the gate opening of the NMOS region are used to provide space for forming the second gate structure.

[0179] For a detailed description of removing the second sacrificial layer, please refer to the aforementioned description of removing the first sacrificial layer; it will not be repeated here.

[0180] It should also be noted that the reference Figure 23 This shows that based on Figure 22 The cross-sectional view shows that after forming the first channel 230, in this embodiment, the method for forming the semiconductor structure further includes: performing a second corner rounding treatment on the first channel layer 20, which is suitable for increasing the smoothness of the corners on the surface of the first channel layer 20.

[0181] The first channel layer 20 is subjected to a second corner rounding treatment, which is suitable for increasing the smoothness of the corners on the surface of the first channel layer 20, thereby transforming the sharp corners in the first channel layer 20 into smooth corners, reducing the probability of forming sharp corners in the PMOS device, and helping to improve the reliability of the PMOS device.

[0182] Specifically, in this embodiment, the first channel layer 20 is subjected to a second corner rounding treatment, which is suitable for increasing the smoothness of the corners on the surface of the first channel layer 20, and also helps to provide a smooth surface for the subsequent formation of the first gate structure, thereby improving the formation quality of the first gate structure.

[0183] As one embodiment, an isotropic etching process is used to perform a second corner rounding treatment on the first channel layer 20. The isotropic etching process has the characteristics of isotropic etching, and the etching rate for corners is greater than the etching rate for planar surfaces, thereby achieving the effect of increasing the smoothness of the surface corners of the first channel layer 20.

[0184] In this embodiment, the isotropic etching process includes plasma etching or wet etching. The plasma used in the plasma etching process can be H-based, Cl-based, F-based, or N-based plasma; the wet etching process can use HCl, HF, or NH3 to perform isotropic etching on the first channel layer.

[0185] In other embodiments, other methods can be used to smooth the second corner. For example, the first channel layer can be oxidized. The oxidation rate at sharp corners is greater than that on planar surfaces, thereby consuming more material from the first channel layer at sharp corners and increasing the smoothness of the corners on the surface of the first channel layer.

[0186] In other embodiments, the second corner rounding process may be omitted based on actual process requirements.

[0187] refer to Figures 24 to 26 , Figure 24 This is a top view. Figure 25 for Figure 24 Cross-sectional view along the xx direction. Figure 26 for Figure 24 A cross-sectional view along the yy direction shows that a first gate structure 240 is filled in the first through-slot 230 and the gate opening 220 of the PMOS region 100P, and the first gate structure 240 surrounds the first channel layer 20.

[0188] When the device is operating, the first gate structure 240 is used to control the opening and closing of the conductive channel of the PMOS device. In this embodiment, the first gate structure 240 is a metal gate structure.

[0189] In this embodiment, the first gate structure 240 includes a first gate dielectric layer 41 and a first gate electrode layer 42 located on the first gate dielectric layer 41.

[0190] The first gate dielectric layer 41 is used to achieve electrical insulation between the first gate electrode layer 41 and the conductive channel.

[0191] The material of the first gate dielectric layer 41 includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3.

[0192] In this embodiment, the first gate dielectric layer 41 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3. In other embodiments, the first gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the first gate dielectric layer may only include a gate oxide layer.

[0193] The gate electrode layer 42 is used as an external electrode for electrically connecting the first gate structure 240 to an external circuit. The material of the gate electrode layer 42 includes one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0194] In a specific embodiment, the gate electrode layer 42 may include: a capping layer (not shown), a work function layer (not shown), a barrier layer (not shown), and a metal electrode layer stacked sequentially on the gate dielectric layer 41.

[0195] It should be noted that, in this embodiment, the method for forming the semiconductor structure further includes: filling the second through-slot 230 and the gate opening 220 of the NMOS region with a second gate structure (not shown), the second gate structure surrounding the second channel layer.

[0196] The second gate structure is used to enable and disable the conductive channel of the NMOS device. In this embodiment, the second gate structure is a metal gate structure.

[0197] As an example, the second gate structure includes a second gate dielectric layer and a second gate electrode layer located on the second gate dielectric layer. A detailed description of the second gate structure can be found in conjunction with the foregoing description of the first gate structure 240, and will not be repeated here.

[0198] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes the PMOS region used to form the PMOS device; Multiple first protrusions are disposed on the substrate of the PMOS region; An isolation layer is located on the substrate and surrounds the first protrusion, the isolation layer being exposed above the top surface of the first protrusion; The channel structure includes a first channel structure suspended above the first protrusion at intervals. The first channel structure includes one or more first channel layers arranged at intervals in sequence. The first channel layers are stacked in a direction perpendicular to the substrate surface. Along the arrangement direction of the first protrusion, the first channel layers have... <111> The wavy structure of the crystal facets; The gate structure includes a first gate structure located on the isolation layer of the PMOS region and spanning the first channel structure, the first gate structure surrounding the first channel layer. The source and drain doped regions are located within the channel structures on both sides of the gate structure; the source and drain doped regions include first source and drain doped regions located on both sides of the first gate structure and in contact with the end of each first channel layer in the first channel structure along the extension direction.

2. The semiconductor structure as described in claim 1, characterized in that, The first gate structure filling the space between each of the first protrusions and the first channel layer adjacent to the first protrusion is a first portion, and the first portion is a sigma-type structure; When there are multiple first channel layers in the first channel structure, the first gate structure filling the spaces between adjacent first channel layers is the second part; The first channel layer and the second portion are conformally stacked alternately on the first portion.

3. The semiconductor structure as described in claim 1, characterized in that, Along the arrangement direction of the first protrusions, multiple adjacent first protrusions form a protrusion group, and each first channel layer on the protrusion group is connected to the other.

4. The semiconductor structure as described in claim 1, characterized in that, The material of the first channel layer includes one or more of silicon, germanium, silicon germanide, silicon carbide, gallium nitride, and gallium arsenide.

5. The semiconductor structure as described in claim 1 or 4, characterized in that, The material of the first channel layer includes Si; or, the material of the first channel layer includes SiGe, and the Ge concentration in the first channel layer is 0% to 30%.

6. The semiconductor structure as described in claim 1, characterized in that, The substrate also includes an NMOS region for forming an NMOS device; discrete second protrusions are also formed on the substrate of the NMOS region; The channel structure further includes: a second channel structure, which is suspended above the second protrusion at intervals. The second channel structure includes one or more second channel layers that are spaced apart in sequence, and the second channel layers are stacked in a direction perpendicular to the substrate surface. The gate structure further includes: a second gate structure located on the isolation layer of the NMOS region and spanning the second channel structure and surrounding the second channel layer; The source / drain doped region further includes: a second source / drain doped region, located on both sides of the second gate structure, and in contact with the end of each second channel layer in the second channel structure along the extension direction.

7. The semiconductor structure as described in claim 6, characterized in that, The material of the second channel layer includes one or more of silicon, germanium, silicon germanide, silicon carbide, gallium nitride, and gallium arsenide.

8. The semiconductor structure as described in claim 1, characterized in that, The substrate material includes one or more of single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, and gallium arsenide; The material of the first protrusion includes one or more of single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, and gallium arsenide; The material of the isolation layer includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon germanium oxide, boron nitride, and boron carbonitride.

9. The semiconductor structure as described in claim 1, characterized in that, The first gate structure includes a first gate dielectric layer and a first gate electrode layer located on the first gate dielectric layer.

10. The semiconductor structure as described in claim 9, characterized in that, The material of the first gate dielectric layer includes one or more of the following: silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3; The material of the gate electrode layer includes one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

11. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a PMOS region for forming a PMOS device, wherein a plurality of discrete first protrusions are formed on the substrate of the PMOS region; An isolation layer is formed on the substrate surrounding the first protrusion, wherein the top surface of the isolation layer is lower than the top surface of the first protrusion; Remove a portion of the thickness from the first protrusion, and form a groove within the first protrusion; A first stacked structure is formed within the groove, the first stacked structure being located on a first protrusion of the PMOS region. The first stacked structure includes one or more first channel stacks stacked sequentially from bottom to top, each first channel stack including a first sacrificial layer and a first channel layer located on the first sacrificial layer; along the arrangement direction of the first protrusion, the first channel layer has... <111> The wavy structure of the crystal facets; A pseudo-gate structure is formed on the isolation layer, spanning the first stacked structure, the pseudo-gate structure covering part of the top and part of the sidewalls of the first stacked structure; A first source / drain doped region is formed in the first stacked structure on both sides of the pseudo-gate structure; After forming the first source / drain doped region, the dummy gate structure is removed to form a gate opening that exposes the first channel stack. The first sacrificial layer in the first channel stack is removed through the gate opening to form a first through-slot. The first through-slot is surrounded by the first protrusion and the first channel layer adjacent to the first protrusion, or by the adjacent first channel layer. A first gate structure is filled within the first through-slot and the gate opening of the PMOS region, and the first gate structure surrounds the first channel layer.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of forming the first stacked structure in the groove, the first channel stack closest to the first protrusion is the bottom channel stack, the first sacrificial layer in the bottom channel stack is a sigma-type structure, and the first channel layer in the bottom channel stack conformally covers the first sacrificial layer. When there are multiple first channel stacks, the first channel stack located above the bottom channel stack is the top channel stack, and the top channel stack conformally covers the bottom channel stack.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, The step of forming the first stacked structure includes: forming a bottom sacrificial layer in the groove, the sacrificial layer being a sigma-type structure; forming a conformally covering bottom channel layer on the bottom sacrificial layer, the bottom sacrificial layer and the bottom channel layer on the bottom sacrificial layer constituting a bottom channel stack; When there are multiple first channel stacks, the step of forming the stack structure further includes: forming one or more conformally covered top channel stacks on the bottom channel stacks; the step of forming the top channel stacks includes: forming a top sacrificial layer; and forming a top channel layer on the top sacrificial layer.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The step of forming the top channel stack further includes: after forming the top sacrificial layer and before forming the top channel layer on the top sacrificial layer, performing a first corner rounding treatment on the top sacrificial layer to increase the smoothness of the surface corners of the top sacrificial layer.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, An isotropic etching process is used to smooth the first corner of the top sacrificial layer.

16. The method for forming a semiconductor structure as described in claim 11, characterized in that, The process for forming the first sacrificial layer and the first trench layer includes an epitaxial process.

17. The method for forming a semiconductor structure as described in claim 11, characterized in that, The material of the first sacrificial layer includes SiGe; The material of the first channel layer includes Si; or, the material of the first channel layer includes SiGe, and the Ge concentration in the first channel layer is different from the Ge concentration in the first sacrificial layer.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The material of the first channel layer includes SiGe, and the Ge concentration in the first channel layer is lower than the Ge concentration in the first sacrificial layer.

19. The method for forming a semiconductor structure as described in claim 17 or 18, characterized in that, The Ge concentration in the first sacrificial layer is greater than or equal to 50%; The Ge concentration in the first channel layer is 0% to 30%.

20. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of forming the first stacked structure, along the arrangement direction of the first protrusions, a plurality of adjacent first protrusions form a protrusion group, and the first stacked structures located on the protrusion group are connected to each other. In the step of removing the first sacrificial layer to form the first through groove, the first channel layer located on the protrusion group has a wave-shaped structure along the arrangement direction of the first protrusion.

21. The method for forming a semiconductor structure as described in claim 11, characterized in that, After forming the first through-slot and before filling the first gate structure into the first through-slot and the gate opening of the PMOS region, the method for forming the semiconductor structure further includes: performing a second corner rounding treatment on the first channel layer, which is adapted to increase the smoothness of the corners on the surface of the first channel layer.

22. The method for forming a semiconductor structure as described in claim 21, characterized in that, An isotropic etching process is used to smooth the second corner of the first trench layer.

23. The method for forming a semiconductor structure as described in claim 15 or 22, characterized in that, The isotropic etching process includes plasma etching or wet etching.

24. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of removing the first sacrificial layer in the first channel stack, the etching selectivity ratio of the first sacrificial layer to the first channel layer is at least 20:

1.

25. The method for forming a semiconductor structure as described in claim 11, characterized in that, The substrate also includes an NMOS region for forming an NMOS device; The method for forming the semiconductor structure further includes: in the step of providing a substrate, a discrete second protrusion is formed on the substrate of the NMOS region, and a second stacked structure is formed on the second protrusion. The second stacked structure includes one or more second channel stacks stacked sequentially from bottom to top, and each second channel stack includes a second sacrificial layer and a second channel layer located on the second sacrificial layer. In the step of forming the isolation layer, the isolation layer also surrounds the second protrusion and exposes the second stacked structure; In the step of forming the pseudo-gate structure, the pseudo-gate structure also spans the second stacked structure and covers part of the top and part of the sidewalls of the second stacked structure; After the pseudo-gate structure is formed and before the pseudo-gate structure is removed, a second source / drain doped region is formed in the second stacked structure on both sides of the pseudo-gate structure. In the step of removing the first sacrificial layer in the first channel stack through the gate opening, the second sacrificial layer in the second channel stack is also removed to form a second through slot. The second through slot is surrounded by the second protrusion and the second channel layer adjacent to the second protrusion, or surrounded by the adjacent second channel layer. The second through slot is connected to the gate opening of the NMOS region. The method for forming the semiconductor structure further includes: filling a second gate structure within the second through-channel and the gate opening of the NMOS region, wherein the second gate structure surrounds the second channel layer.

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