Field-effect transistor device

Abstract

The present invention discloses a field effect transistor device for solving the problem of short channel effect of field effect transistors in the prior art, which includes: an active layer including a source region, a drain region, and a channel region located between the source region and the drain region; a gate disposed around the channel region; a gate insulating layer disposed between the gate and the channel region; wherein, when the device is turned on, an effective channel, an equivalent source and / or an equivalent drain far from the effective channel are formed in the channel region, and the field effect transistor device connects the source region and the drain region through the effective channel and the equivalent source and / or the equivalent drain to form a working current.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and specifically relates to a field effect transistor device. Background Art

[0002] With the development of integrated circuit technology, the gate length (corresponding to the channel length) of field effect transistors is continuously shrinking. Currently, VLSI chips based on sub-micron or even gate lengths below 10 nanometers have been mass-produced. For such small-sized devices, how to cope with their short-channel effects is an important challenge in device technology. The short-channel effects cause the threshold voltage and sub-threshold characteristics of small-sized devices to deteriorate comprehensively. Specifically, the threshold voltage of the device is no longer a constant, but decreases as the channel length decreases and also decreases as the drain terminal voltage of the device increases; the sub-threshold swing of the device transfer characteristics also deteriorates simultaneously.

[0003] Currently, one method to improve the short-channel effects of field effect transistor devices is the gate-all-around transistor GAAFET. By setting a surrounding gate to wrap the channel region, the control of the gate over the channel is enhanced. However, there is still room for improvement in the short-channel effects of this type of transistor.

[0004] The information disclosed in this background art section is only intended to enhance the overall understanding of the present invention and should not be regarded as an admission or any form of implication that this information constitutes prior art already known to those of ordinary skill in the art. Summary of the Invention

[0005] The purpose of the present invention is to provide a field effect transistor device, which is used to solve the problem of the short-channel effects of the device.

[0006] To achieve the above purpose, the present invention provides a field effect transistor device, including:

[0007] An active layer, including a source region, a drain region, and a channel region located between the source region and the drain region;

[0008] A gate, disposed around the channel region;

[0009] A gate insulating layer, disposed between the gate and the channel region;

[0010] Wherein, when the device is turned on, an effective channel and an equivalent source and / or equivalent drain away from the effective channel are formed in the channel region, and the field effect transistor device connects the source region and the drain region through the effective channel and the equivalent source and / or equivalent drain to form a working current.

[0011] In one embodiment, a conductive region that does not connect the source region and the drain region is formed in the channel region; wherein,

[0012] When the conductive region is in communication with the source region, the conductive region forms the equivalent source; and / or,

[0013] When the conductive region is in communication with the drain region, the conductive region forms the equivalent drain.

[0014] In one embodiment, a perpendicular projection of the gate and the conductive region on a reference plane overlaps. The gate can control the channel region and form a channel therein. A non-overlapping portion between the channel and a perpendicular projection of the conductive region on the reference plane forms the effective channel, where the reference plane is a plane passing through a central axis in the length direction of the channel region.

[0015] In one embodiment, when the device is turned on, the conductance of the conductive region is greater than the conductance of the remaining portion of the channel other than the effective channel, so that at least one of the conductive region and the effective channel can inject carriers into the other; preferably,

[0016] The conductance of the conductive region is at least three times greater than the conductance of the remaining portion of the channel other than the effective channel.

[0017] In one embodiment, when the device is turned on, the conductance per unit length of the effective channel in the channel is greater than the conductance per unit length of the remaining portion of the channel other than the effective channel; preferably,

[0018] When the device is turned on, the conductance per unit length of the effective channel in the channel is at least three times greater than the conductance per unit length of the remaining portion of the channel other than the effective channel.

[0019] In one embodiment, a thickness of a portion of the gate insulating layer corresponding to the effective channel is less than a thickness of the remaining portion of the gate insulating layer; and / or,

[0020] The portion of the gate insulating layer corresponding to the effective channel and the remaining portion of the gate insulating layer are made of materials with different dielectric constants; and / or,

[0021] The portion of the gate corresponding to the effective channel and the remaining portion are made of materials with different work functions.

[0022] In one embodiment, the equivalent source and / or the equivalent drain extend along a central axis in the length direction of the channel region.

[0023] In one embodiment, the active layer includes at least two semiconductor materials that vary along its axial or radial direction.

[0024] In one embodiment, the conductive region is formed by carriers introduced by doping in the channel region.

[0025] In one embodiment, an insulating structure is provided in the channel region, and the conductive region is composed of carriers generated by the injected charges in the insulating structure through electrostatic induction near the insulating structure in the channel region.

[0026] In one embodiment, a semiconductor structure is provided in the channel region. The semiconductor structure and the channel region form a heterostructure, and the conductive region is composed of a two-dimensional electron gas channel or a two-dimensional hole gas channel distributed in the heterostructure.

[0027] In one embodiment, the active layer is configured as a nanowire, a nanosheet, or a nanoring.

[0028] Compared with the prior art, the field-effect transistor device according to the present invention can form an effective channel, as well as an equivalent source and an equivalent drain far from the effective channel in the channel region, so as to connect the source region and the drain region to form a working current. In this way, the equivalent drain (source) connected to the drain (source) region is structurally far from the effective channel, which can reduce the influence of the drain-end voltage on the effective channel and suppress the short-channel effect of the device. At the same time, the peak electric field in the drain-end depletion region when the device operates in saturation is reduced, thereby improving the output characteristics of the device. Description of the Drawings

[0029] Figure 1 is a schematic structural diagram of a field-effect transistor device according to an embodiment of the present application;

[0030] Figure 2 is a cross-sectional view when the field-effect transistor according to an embodiment of the present application is turned on;

[0031] Figure 3 is a schematic diagram of forming a conductive region of a field-effect transistor according to an embodiment of the present application;

[0032] Figures 4 to 9 is a schematic structural diagram of a field-effect transistor device according to various embodiments of the present invention;

[0033] Figures 10 to 14 is a schematic diagram of the principle of manufacturing a conductive region in various embodiments of the present invention;

[0034] Figures 15 to 16 is a comparison diagram of transfer curves of a GAA device using the field-effect transistor device structure of the present invention and a conventional GAA device in the present invention under different V D under;

[0035] Figures 17 to 18 is a comparison diagram of output characteristics of a GAA device using the field-effect transistor device structure of the present invention and a conventional GAA device in the present invention in one embodiment;

[0036] Figures 19 to 20In one embodiment of the present invention, it is a comparison diagram of the transfer curves of the GAA device using the field-effect transistor device structure of the present invention and a conventional GAA device in the linear region and the saturation region, respectively. Detailed implementation manners

[0037] The following will describe in detail the specific implementation manners of the present invention with reference to the accompanying drawings. It should be understood that the protection scope of the present invention is not limited by the specific implementation manners.

[0038] Unless otherwise clearly stated, in the whole specification and claims, the term "comprise" or its variations such as "comprises" or "including" etc. will be understood to include the stated elements or components, without excluding other elements or other components.

[0039] Refer Figure 1 and Figure 2 To introduce a specific implementation manner of the field-effect transistor device 100 of the present application. In this embodiment, the field-effect transistor device 100 includes an active layer 10, a gate 20, and a gate insulating layer 30.

[0040] The active layer 10 includes a source region 101, a drain region 102, and a channel region 103 located between the source region 101 and the drain region 102. The gate 20 is disposed around the channel region 103, and the gate insulating layer 30 is located between the gate 20 and the channel region 103. In this embodiment, the gate 20 entirely and completely wraps the channel region 103, that is, it is a fully surrounding gate 20.

[0041] Cooperate Figure 2 With the schematic diagram when the device is turned on as shown, an effective channel 1041, an equivalent source 1051, and an equivalent drain 1052 far from the effective channel 1041 are formed in the channel region 103 of the field-effect transistor device 100. The field-effect transistor device 100 connects the source region 101 and the drain region 102 through the effective channel 1041, the equivalent source 1051, and the equivalent drain 1052 to form a working current. That is, the effective channel 1041, the equivalent source 1051, and the equivalent drain 1052 together constitute the path of the working current when the device is turned on.

[0042] In this embodiment, the length direction in which the channel region 103 extends between the source region 101 and the drain region 102 is referred to as the axial direction of the channel region 103, and the linear extension direction on the plane perpendicular to the axial direction of the channel region 103 is referred to as the radial direction of the channel region 103. On this basis, the "far from" between the effective channel 1041 and the equivalent source 1051, the equivalent drain 1052 mentioned in the present application may mean having a gap in the radial direction of the channel region 103, or having gaps both in the radial direction of the channel region 103 and in the axial direction of the channel region 103.

[0043] In a typical field-effect transistor device 100, the source region 101 in the active region 10 is used to provide carriers when the device is turned on, and the drain region 102 is used to collect the carriers provided by the source region 101. Correspondingly, in the present application, the equivalent source 1051 mentioned refers to a structure that directly injects the carriers provided by the source region 101 into the effective channel 1041, and the equivalent drain 1052 refers to a structure that directly receives carriers from the effective channel 1041 and injects them into the drain region 102.

[0044] With reference to Figure 2 , the "effective channel 1041" mentioned in the present application refers to the channel that contributes the main carrier path when the device is turned on. Taking this embodiment as an example, when a gate bias is applied to the gate 20 to turn on the device, a channel 104 can be controlled to be formed under the gate 20, and this channel 104 is structurally connected to the source region 101 and the drain region 102. However, from a functional perspective, only a part of this channel 104 can be used to transmit the working circuit; specifically, if the plane passing through the central axis of the channel region 103 is defined as the reference plane, then only the part of the channel 104 that does not overlap with the vertical projections of the equivalent source 1051 and the equivalent drain 1052 on the reference plane participates in transmitting the working current, and therefore only this part of the channel will be referred to as the "effective channel 1041" here.

[0045] The settings of the equivalent source 1051 and the equivalent drain 1052 are equivalent to shortening the length of the part in the channel 104 that can conduct the working current, that is, there is a gap between the effective channel 1041 and the source region 101 and the drain region 102. Moreover, the equivalent drain 1052 connected to the drain region 102 is structurally far from the effective channel 1041, reducing the influence of the drain-end potential on the effective channel 1041, and the equivalent source 1051 connected to the source region 101 is structurally far from the effective channel 1041, also reducing the influence of the drain-end potential on the effective channel 1041, so as to improve the short-channel effect of the device.

[0046] In the embodiment of the present application, the equivalent source 1051 and the equivalent drain 1052 can preferably both extend along the central axis in the length direction of the channel region 103. In this way, both the equivalent source 1051 and the equivalent drain 1052 can have a relatively reasonable distance from the overall surrounding gate 20, so as to minimize the influence of the source-end potential and the drain-end potential on the effective channel 1041.

[0047] With reference to Figure 3, in the specific preparation of the equivalent source 1051 and the equivalent drain 1052, a conductive region A that does not connect the source region 101 and the drain region 102 can be formed in the channel region 103. When the conductive region A is connected to the source region 101, this part of the conductive region A constitutes the equivalent source 1051; when the conductive region A is connected to the drain region 102, this part of the conductive region constitutes the equivalent drain 1052. In this embodiment, the conductive region A is divided into two parts, one part of which is connected to the source region 101 and the other part of which is connected to the drain region 102. Therefore, the equivalent source 1051 and the equivalent drain 1052 are simultaneously formed in the channel region 103.

[0048] When the device is turned on, the conductance of the conductive region A is set to be greater than the conductance of the rest of the channel except the effective channel 1041, so that carriers can be injected between the conductive region A and the effective channel 1041. In this way, the carriers in the source region 101 will be attracted by the equivalent source 1051 with a greater conductance and will not be directly injected into the rest 1042 of the channel 104 that is directly connected to the source region 101; similarly, the carriers transmitted in the effective channel 1041 will also be attracted by the equivalent drain 1052 and will not continue to be transmitted through the rest 1042 of the channel 104. As Figure 2 shown by the dotted arrow indicating the carrier flow direction, in the formation of the working current of the device in this embodiment, the carriers provided by the source region 101 enter the equivalent source 1051 and are injected into the effective channel 1041 from the end of the equivalent source 1051 far from the source region 101; the carriers flowing through the effective channel 1041 will be injected into the equivalent drain 1052 at the end near the equivalent drain 1052 and finally injected into the drain region 102.

[0049] In order to achieve the carrier injection setting between the equivalent source 1051, the equivalent drain 1052, and the effective channel 1041 here, the conductance of the conductive region A can be set to be at least three times greater than the conductance of the rest 1042 of the channel 104 except the effective channel 1041. And, since the carriers flow in the radial direction of the channel region 103 during the above "injection" process, the interval between the conductive region A and the effective channel 1041 in the radial direction of the channel region 103 can be set to 1 nm to 10 μm, or more preferably 3 nm to 1 μm, or more preferably 5 nm to 100 nm according to the specific design of different devices to ensure the normal injection of carriers and the performance of the device.

[0050] It should be noted that the "carriers" mentioned in this application refer to the charged particles that can move freely in the corresponding polar channel / conductive region A. Generally, we refer to the electrons in the N-type channel or the holes in the P-type channel as the "carriers" here. Correspondingly, the holes in the N-type channel or the electrons in the P-type channel are not referred to as the "carriers" here. Therefore, in this application, the polarities of the effective channel 1041 and the conductive region A are set to be the same, so that the carrier interaction between the effective channel 1041 and the conductive region A can ultimately substantially contribute to the working current of the device.

[0051] Refer Figure 4 , and introduce another embodiment of the field effect transistor device 200 of this application.

[0052] Different from the above embodiment, in this embodiment, when the device is turned on, an equivalent drain is not formed in the channel region 103 at this time. The field effect transistor device 200 connects the source region 101 and the drain region 102 through the effective channel 1041 and the equivalent source 1051 to form a working current.

[0053] In this embodiment, it is equivalent to only weakening the influence of the drain terminal potential on the potential near the source end of the channel region 103 through the setting of the equivalent source 1051, thereby improving the short-channel effect of the device. Correspondingly, the effective channel 1041 is directly connected to the drain region 102.

[0054] In carrier transmission, the carriers provided by the source region 101 enter the equivalent source 1051 and are injected into the effective channel 1041 from the end of the equivalent source 1051 far from the source region 101; the carriers flowing through the effective channel 1041 are then injected back into the drain region 102. That is, in this embodiment, only the conductive region injects carriers into the effective channel 1041 unidirectionally.

[0055] Refer Figure 5 , and introduce another embodiment of the field effect transistor device 300 of this application.

[0056] Different from the above embodiment, in this embodiment, when the device is turned on, an equivalent source 1051 is not formed in the channel region 103 at this time. The field effect transistor device 300 connects the source region 101 and the drain region 102 through the effective channel 1041 and the equivalent drain 1052 to form a working current.

[0057] In this embodiment, it is equivalent to only weakening the influence of the drain terminal potential on the effective channel 1041 through the setting of the equivalent drain 1052, thereby improving the short-channel effect of the device. Correspondingly, the effective channel 1041 is directly connected to the source region 101.

[0058] In carrier transport, carriers provided by the source region 101 enter the effective channel 1041, are injected from one end of the effective channel 1041 away from the source region 101 into the equivalent drain 1052, and then injected back into the drain region 102. That is, in this embodiment, only the effective channel 1041 injects carriers into the conductive region unidirectionally.

[0059] In the above embodiment, a structure in which a part of the channel 104 formed by the control of the gate 20 constitutes the effective channel 1041 has been shown. In such a structure, in order to further improve the short-channel effect of the device, the unit length conductance of the effective channel 1041 in the channel 104 can be set to be greater than the unit length conductance of the remaining part 1042 in the channel 104 except the effective channel 1041. The following introduces some corresponding embodiments.

[0060] Refer Figure 6 , and introduce another embodiment of the field effect transistor device 400 of the present application.

[0061] The field effect transistor device 400 includes an active layer 10, and the active layer 10 includes a source region 101, a drain region 102, and a channel region 103. The source region 101 and the drain region 102 are respectively located on both sides of the active layer 10, and the channel region 103 is located between the source region 101 and the drain region 102.

[0062] The gate 20 is disposed around the channel region 103, and a gate insulating layer 30 is disposed between the gate 20 and the channel region 103. The thickness of the portion 302 of the gate insulating layer 30 corresponding to the effective channel 1041 is less than the thickness of the remaining portion 301. That is, the gate insulating layer corresponding to the equivalent source 1051 and the equivalent drain 1052 is relatively thickened. In this way, the modulation ability of the gate 20 corresponding to the remaining part 1042 of the channel 104 outside the effective channel 1041 to the corresponding part 1042 of the channel 104 can be weakened, so that the unit length conductance of the corresponding part 1042 of the channel 104 is reduced.

[0063] Cooperatively, the unit length conductance of the effective channel 1041 in the channel can also be made greater than that of the remaining part by adjusting the materials (dielectric constants) of the portion of the gate insulating layer 30 corresponding to the effective channel 1041 and the remaining part of the gate insulating layer.

[0064] Refer Figure 7 , and introduce another embodiment of the field effect transistor device 500 of the present application.

[0065] The field effect transistor device 500 includes an active layer 10, which includes a source region 101, a drain region 102, and a channel region 103. The source region 101 and the drain region 102 are respectively located on both sides of the active layer 10, and the channel region 103 is located between the source region 101 and the drain region 102.

[0066] The gate 20 is disposed around the channel region 103, and a gate insulating layer 30 is disposed between the gate 20 and the channel region 103. The part 201 of the gate 20 corresponding to the effective channel 1041 and the remaining part 202 are made of different materials, so that the part 201 of the gate 20 corresponding to the effective channel 1041 and the remaining part 202 have different modulation capabilities for the corresponding formed channel, and the unit length conductance of the effective channel 1041 is greater than the unit length conductance of the remaining part 1042 of the channel 104 except the effective channel 1041.

[0067] Specifically, if it is an N-type device, the part 201 of the gate 20 corresponding to the effective channel 1041 can use a metal with a smaller work function such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or Ru-Hf, WN, HfN, TiN, TaN, TaSiN, etc. with a smaller work function obtained by adjusting the compound composition as the gate material; the remaining part 202 can use a metal with a larger work function such as gold, platinum, or P-type doped (P+) polysilicon, or ITO, RuO2, WN, MoN, etc. with a larger work function obtained by adjusting the compound composition as the gate 20 material. If it is a P-type device, the part 201 of the gate 20 corresponding to the effective channel 1041 can use a metal with a larger work function such as gold, platinum, or P-type doped (P+) polysilicon, or ITO, RuO2, WN, MoN, etc. with a larger work function obtained by adjusting the compound composition as the gate material; the remaining part 202 can use a metal with a smaller work function such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or Ru-Hf, WN, HfN, TiN, TaN, TaSiN, etc. with a smaller work function obtained by adjusting the compound composition as the gate material.

[0068] See Figure 8 , in some alternative embodiments, the field effect transistor device 600 may also only have a surrounding gate 20 disposed on a partial surface of the channel region 103 between the equivalent source 1051 and the equivalent drain 1052, and the gate 20 is not integrally connected to at least one of the equivalent source 1051 and the equivalent drain 1052. In this way, even when a bias voltage that can turn on the device is applied to the gate 20, no channel that structurally connects the source region 101 and the drain region 102 will be formed under the gate 20 (such as Figure 8As shown, the channel 104 formed under the control of the gate 20 at this time does not connect the source region 101 and the drain region 102). That is, the channel 104 formed in the channel region 103 under the control of the gate 20 is the above-mentioned "effective channel".

[0069] In the above embodiments, the active layers mainly shown are all cylindrical, and can also be called "nanowires". The cross-sectional shape of such nanowires can be set differently according to needs, for example Figure 9 The nanowire with a square cross-section (active layer 10) is shown. And, in some alternative embodiments, the active layer can also be constructed as a nanosheet or a nanoring, and an equivalent source, an equivalent drain, and an effective channel are similarly arranged in the channel region of the nanosheet or nanoring-shaped active layer to achieve the above similar functions, which will not be elaborated here.

[0070] At the same time, in the field effect transistor devices of the above embodiments, the gates all surround and completely wrap the channel region; while in some other embodiments, the gates can also incompletely wrap the channel region, and a typical example is a fin field effect transistor (FinFET, Fin Field-Effect Transistor).

[0071] In a fin field effect transistor, the gate surrounds the channel region on three sides, and the equivalent source and the equivalent drain can be arranged at positions farther away from the top surface part of the gate, so as to reduce the influence of the source end potential and the drain end potential on the effective channel.

[0072] The following introduces the formation method of the conductive region in this application with some specific embodiments:

[0073] Embodiment 1

[0074] The conductive region A is formed by carriers introduced by local doping in the channel region 103A.

[0075] Correspondingly, referring to Figure 10 , if it is an N-type silicon-based device 100A, the doping concentration of the corresponding part in the channel region 103A can be changed by doping donor atoms such as phosphorus and arsenic in the channel region 103A; referring to Figure 11 , if it is a P-type silicon-based device 100A, the doping concentration of the corresponding part in the channel region 103A can be changed by doping acceptor atoms such as boron in the channel region 103A.

[0076] Embodiment 2

[0077] Cooperate with reference to Figure 12 and Figure 13, the field effect transistor device 100B further includes an insulating structure 40B disposed in the channel region 103B, and the conductive region A is formed in the channel region 103B by electrostatic induction of the implanted charges in the insulating structure 40B.

[0078] Correspondingly, Figure 12 , if it is an N-type device, it can be achieved by implanting positive charges, such as H+, holes, into the insulating structure 40B; Figure 13 , if it is a P-type device, it can be achieved by implanting negative charges, such as - F - , Cl

[0079] , electrons, etc. into the insulating structure 40B. In this way, a high density of fixed charges is formed in the insulating structure 40B, and carriers of the conductive region A are generated in the channel region 103B by electrostatic induction.

[0080] Embodiment 3

[0081] Refer to Figure 14 , the field effect transistor device 100C includes a semiconductor structure 40C disposed in the channel region 103C. The semiconductor structure 40C and the channel region 103C form a heterostructure, and the conductive region A is formed by a two-dimensional electron gas channel or a two-dimensional hole gas channel distributed in the heterostructure.

[0082] Specifically, the semiconductor structure 40C and the channel region 103C have different bandgap widths. The semiconductor structure 40C can be divided into two parts respectively connected to the source region 101C and the drain region 102C, so that the formed two-dimensional electron gas channel does not conduct the source and drain regions.

[0083] Of course, in some alternative embodiments, for example, by processing corresponding parts in the channel region 103C to form a two-dimensional electron gas channel or a two-dimensional hole gas channel, these alternative embodiments of forming a two-dimensional electron gas channel or a two-dimensional hole gas channel well-known to those skilled in the art should all fall within the protection scope of this application. And the semiconductor structure 40C mentioned here can be a barrier layer structure, and the barrier layer structure can be doped or intrinsic.

[0084] In each of the above embodiments, the active layer of the device may be composed of a single semiconductor material, or may include at least two semiconductor materials that vary axially or radially to form a composite channel, thereby improving the carrier injection effect between the equivalent source, equivalent drain, and effective channel, and / or reducing the influence of the drain-end potential on the effective channel, thereby further improving the short-channel effect of the device.

[0085] It should be noted that the different semiconductor materials mentioned here may include semiconductor materials with different elemental composition ratios. Taking semiconductor materials Si x Ge 1-x as an example, when the value of x is different, they can be considered as different semiconductor materials here.

[0086] Taking the GAA device as an example below, Silvaco TCAD is used to simulate and compare the transistor device of the present invention and the conventional (GAA) device in terms of the short-channel effect of the device and the characteristics of the device output curve.

[0087] The specific parameters of the devices involved in the simulation are as follows:

[0088] ① The material of the channel region is Si, cylindrical, with a radius of 50 nm;

[0089] ② The P-type doping concentration in the channel region is 10 17 cm -3 ;

[0090] ③ The material of the gate insulating layer is SiO2, with a thickness of 5 nm;

[0091] ④ For the conventional GAA device, the channel length L = 0.1 μm;

[0092] ⑤ The apparent gate length L of the GAA device of the present invention G = 0.2 μm;

[0093] ⑥ The effective channel length L of the GAA device of the present invention eff = 0.1 μm;

[0094] ⑦ The lengths of the equivalent source and equivalent drain of the GAA device of the present invention are both 50 nm;

[0095] ⑧ The N-type doping concentration in the source and drain regions is 2×10 19 cm -3 ;

[0096] ⑨ The fixed positive charge surface density at the back interface of the channel forming the equivalent source and drain of the GAA device of the present invention is 10 14 cm -2 .

[0097] Figure Figure 15 and Figure 16 are the comparison diagrams of the transfer curves of the GAA device and the conventional GAA device of the present invention at different V D values. It can be observed from the transfer curves at different V D values that the short-channel effect of the GAA device of the present invention is significantly improved compared with that of the conventional GAA device. When V D = 3V, the subthreshold swing SS of the conventional GAA device is 119.1 mV / dec, while the subthreshold swing of the GAA device of the present invention is 65.8 mV / dec. Due to the short-channel effect of the conventional GAA device, when V D = 3V, the threshold voltage of the device decreases significantly (when V D = 3V, the threshold voltage is 0.33V, which is 0.38V lower than the threshold voltage of 0.71V when V D = 0.1V). In contrast, the change in the threshold voltage of the GAA device of the present invention is smaller (when V D = 3V, the threshold voltage is 0.73V, which is 0.04V lower than the threshold voltage of 0.77V when V D = 0.1V). As shown in the figure, the threshold voltage is extracted using the constant current method.

[0098] Figure Figure 17 and Figure 18 are the comparison diagrams of the output characteristics of the GAA device of the present invention and the conventional GAA device. It can be seen from the figure that whether V G = 2V or 4V, the output characteristic curve of the GAA device of the present invention is flatter, the working range is wider, and the output impedance is larger. The V D value corresponding to the significant occurrence of the kink current in the output characteristics is V kink . The larger V kink is, the weaker the carrier impact ionization effect in the drain depletion region of the device is, and the more difficult it is for the device to generate the kink current effect. Taking V G = 4V as an example ( Figure 18 ), the V kink of the conventional GAA device is 1.40V, and the output impedance is 26.5 kΩ, while the V kink of the GAA device of the present invention is 1.70V, and the output impedance is 38.1 kΩ. It shows that the GAA device of the present invention can effectively reduce the carrier impact ionization effect during device operation, suppress the kink current, increase the output resistance, and improve the output characteristics of the device.

[0099] Figure Figure 19 and Figure 20 are the GAA device of the present invention and the conventional GAA device in the linear region (V D = 0.1V) and the saturation region (V D= 3V), transfer curve comparison diagram. In the linear region, for the GAA device of the present invention at V D = 0.1V, the on-state region transconductance of 46.7 μA / V is lower (by about 35%) compared to that of the conventional GAA device at 71.9 μA / V. In the saturation region, for the GAA device of the present invention at V D = 3V, the on-state region transconductance is 175.4 μA / V, which is almost the same as that of the conventional GAA device at 184.1 μA / V (only a decrease of about 4.7%). Therefore, for each of the embodiments / examples provided in this application, in the saturation region where V D is relatively large, the short-channel effect of the device can be effectively improved without substantially sacrificing the original conduction performance of the device.

[0100] The foregoing description of specific exemplary embodiments of the present invention is for purposes of illustration and exemplification. These descriptions are not intended to limit the present invention to the precise forms disclosed, and obviously, many changes and variations are possible in light of the above teachings. The purpose of selecting and describing the exemplary embodiments is to explain the specific principles of the present invention and its practical applications, so that those skilled in the art can implement and utilize the various different exemplary embodiments of the present invention, as well as various different selections and changes. The scope of the present invention is intended to be defined by the claims and their equivalents.

Claims

1. A field effect transistor device, characterized in that, Comprising: An active layer, including a source region, a drain region, and a channel region located between the source region and the drain region, wherein a conductive region that does not connect the source region and the drain region is formed in the channel region; wherein, when the conductive region is connected to the source region, the conductive region constitutes an equivalent source, and / or, when the conductive region is connected to the drain region, the conductive region constitutes an equivalent drain; A gate, disposed surrounding the channel region; A gate insulating layer, disposed between the gate and the channel region; Wherein, when the device is turned on, an effective channel, and an equivalent source and / or equivalent drain away from the effective channel are formed in the channel region, and the field effect transistor device forms a working current by connecting the source region and the drain region through the effective channel, and the equivalent source and / or equivalent drain.

2. The field effect transistor device according to claim 1, characterized in that, The vertical projections of the gate and the conductive region on a reference plane overlap, the gate can control the channel region and form a channel therein, and the non-overlapping part between the channel and the vertical projection of the conductive region on the reference plane constitutes the effective channel, wherein the reference plane is a plane passing through the central axis in the length direction of the channel region.

3. The field effect transistor device according to claim 2, characterized in that, When the device is turned on, the conductivity of the conductive region is greater than the conductivity of the remaining part of the channel except the effective channel, so that at least one of the conductive region and the effective channel can inject carriers into the other.

4. The field effect transistor device according to claim 3, characterized in that, The conductivity of the conductive region is at least three times greater than the conductivity of the remaining part of the channel except the effective channel.

5. The field effect transistor device according to claim 2, characterized in that, When the device is turned on, the unit length conductivity of the effective channel in the channel is greater than the unit length conductivity of the remaining part of the channel except the effective channel.

6. The field effect transistor device according to claim 5, characterized in that, When the device is turned on, the unit length conductivity of the effective channel in the channel is at least three times greater than the unit length conductivity of the remaining part of the channel except the effective channel.

7. The field effect transistor device according to claim 5, characterized in that, The thickness of the part of the gate insulating layer corresponding to the effective channel is less than the thickness of the remaining part of the gate insulating layer; and / or, The part of the gate insulating layer corresponding to the effective channel and the remaining part of the gate insulating layer are made of materials with different dielectric constants; and / or, The part of the gate corresponding to the effective channel and the remaining part are made of materials with different work functions.

8. The field effect transistor device according to claim 1, characterized in that, The equivalent source and / or equivalent drain extend along the central axis in the length direction of the channel region.

9. The field effect transistor device according to any one of claims 1 to 8, characterized in that, The conductive region is formed by carriers introduced by doping in the channel region; and / or, The active layer includes at least two semiconductor materials that vary axially or radially along it.

10. The field effect transistor device according to any one of claims 1 to 8, characterized in that, An insulating structure is disposed in the channel region, and the conductive region is composed of carriers generated by electrostatic induction of the injected charges in the insulating structure near the channel region in the channel region.

11. The field effect transistor device according to any one of claims 1 to 8, characterized in that, A semiconductor structure is disposed in the channel region, the semiconductor structure forms a heterostructure with the channel region, and the conductive region is composed of a two-dimensional electron gas channel or a two-dimensional hole gas channel distributed in the heterostructure.

12. The field effect transistor device according to any one of claims 1 to 8, characterized in that, The active layer is configured as a nanowire, a nanosheet, or a nanoring.

Images