Capacitor amplifier circuit and its signal generation method

Abstract

This invention discloses a capacitive amplifier circuit and its signal generation method. The capacitive amplifier circuit includes a sampling circuit, a first-stage amplification unit, a second-stage amplification unit, a set of feedback capacitors, and a control unit. The control unit is used to control the on / off states between the first-stage amplification unit and the feedback capacitor, between the first-stage amplification unit and the second-stage amplification unit, and between the feedback capacitor and the second-stage amplification unit, respectively. According to the capacitive amplifier circuit and its signal generation method of this invention, by controlling the on / off states between the first-stage amplification unit, the feedback capacitor, and the second-stage amplification unit, as well as between the feedback capacitor and the second-stage amplification unit, the feedback capacitor can be pre-charged after the sampling circuit finishes sampling and before the capacitive amplifier circuit enters the amplification state. This reduces the operational amplifier switching time and lowers the bandwidth requirements for establishing a high-precision signal.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a capacitor amplifier circuit and a method for generating signals therefrom. Background Technology

[0002] For a capacitor operational amplifier, its time constant is related to the bandwidth of the operational amplifier, and the bandwidth is related to the current. In high-speed operational amplifiers, to establish a high-precision signal, the bandwidth requirement of the operational amplifier is very high, which requires a large current consumption.

[0003] The output signal of the capacitive operational amplifier is Vout:

[0004] Vout = -Vstep * Cs / CF * (1 - e) -t / τ (1)

[0005] Where Vstep is the step signal generated by the sampling and amplification of the capacitive operational amplifier, Cs / CF is the amplification factor, t is the settling time of the capacitive operational amplifier, and τ is the time constant of the capacitive operational amplifier. Assuming Cs / CF = 1, we can obtain from formula (1):

[0006]

[0007] The settling error of a capacitive operational amplifier can be obtained from the accuracy N of the capacitive operational amplifier:

[0008]

[0009] Combining formula (2) and formula (1), we can obtain: Since the traditional capacitive operational amplifier has Vstep≈Vout, meaning the output signal Vout is built up from 0 each time, we can obtain: t=τ*ln(2 N ).

[0010] As can be seen from the above, if the step signal Vstep is reduced to one-thousandth or less of the output signal Vout (Vstep≈0.001Vout), then τ will increase accordingly given a fixed settling time, thereby greatly reducing the bandwidth requirement GBW of the capacitive operational amplifier.

[0011] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0012] The purpose of this invention is to provide a capacitor amplifier circuit that can reduce the bandwidth requirements for establishing a high-precision signal.

[0013] To achieve the above objectives, embodiments of the present invention provide a capacitor amplifier circuit, including: a first-stage amplifier unit, a second-stage amplifier unit, a sampling circuit, a set of feedback capacitors, and a control unit.

[0014] The first-stage amplification unit has a set of first input terminals and a set of first output terminals, and the second-stage amplification unit has a set of second input terminals and a set of second output terminals. The first output terminal of the first-stage amplification unit is connected to the second input terminal of the second-stage amplification unit.

[0015] The sampling circuit is used to sample the input signal and output the sampled signal to the first input terminal of the first-stage amplification unit; the first terminal of the feedback capacitor is connected to the first input terminal of the first-stage amplification unit, and the second terminal of the feedback capacitor is connected to the first output terminal of the first-stage amplification unit and the second output terminal of the second-stage amplification unit.

[0016] The control unit is used to control the connection and disconnection between the first terminal of the feedback capacitor and the first input terminal of the first-stage amplifier unit and the sampling circuit, and / or the connection and disconnection between the first output terminal of the first-stage amplifier unit and the second terminal of the feedback capacitor. The control unit also controls the connection and disconnection between the first output terminal of the first-stage amplifier unit and the second input terminal of the second-stage amplifier unit, and the connection and disconnection between the second terminal of the feedback capacitor and the second output terminal of the second-stage amplifier unit.

[0017] In one or more embodiments of the present invention, the control unit includes a set of first switches, a first terminal of the first switch being connected to a second terminal of a feedback capacitor, and a second terminal of the first switch being connected to a first output terminal of a first-stage amplification unit.

[0018] In one or more embodiments of the present invention, the control unit includes a set of second switches, the first end of the second switches being connected to the first output terminal of the first stage amplification unit, and the second end of the second switches being connected to the second input terminal of the second stage amplification unit.

[0019] In one or more embodiments of the present invention, the control unit includes a set of third switches, the first end of the third switches being connected to the second end of the feedback capacitor, and the second end of the third switches being connected to the second output terminal of the secondary amplification unit.

[0020] In one or more embodiments of the present invention, the first-stage amplification unit includes a first operational amplifier, and / or the second-stage amplification unit includes a second operational amplifier and a set of Miller capacitors, wherein a first terminal of the Miller capacitor is connected to the input terminal of the second operational amplifier to form a first input terminal of the second-stage amplification unit, and a second terminal of the Miller capacitor is connected to the output terminal of the second operational amplifier to form a second output terminal of the second-stage amplification unit.

[0021] In one or more embodiments of the present invention, the sampling circuit includes a set of sampling capacitors, a set of fourth switches, a set of fifth switches, and a sixth switch; the first end of the sampling capacitor is connected to the signal input terminal through the fourth switch to receive the input signal, and the first end of the set of sampling capacitors is connected through the sixth switch, the second end of the sampling capacitor is connected to the common-mode signal through the fifth switch, and the second end of the sampling capacitor is connected to the first input terminal of the first-stage amplification unit and the first end of the feedback capacitor.

[0022] In one or more embodiments of the present invention, the capacitive amplifier circuit further includes a set of seventh switches, the first terminal of the seventh switches being connected to the second terminal of the feedback capacitor, and the second terminal of the seventh switches being connected to a common-mode signal.

[0023] The present invention also discloses a signal generation method, comprising: an alternating first stage and a second stage, wherein the second stage includes a pre-charging stage and an amplification stage, wherein...

[0024] In the first stage, the input signal is sampled by the sampling circuit and the sampled signal is output.

[0025] During the pre-charging stage, the feedback capacitor is pre-charged based on the sampled signal through a first-stage amplification unit;

[0026] During the amplification stage, the sampled signal is amplified by cascaded primary and secondary amplification units based on the signal holding of the feedback capacitor.

[0027] In one or more embodiments of the present invention, the pre-charging of the feedback capacitor based on the sampling signal by the first-stage amplification unit includes: connecting the second terminal of the feedback capacitor to the first output terminal of the first-stage amplification unit by the control unit, disconnecting the connection between the first output terminal of the first-stage amplification unit and the second input terminal of the second-stage amplification unit, and disconnecting the connection between the second terminal of the feedback capacitor and the second output terminal of the second-stage amplification unit.

[0028] In one or more embodiments of the present invention, the amplification of the sampled signal by means of a cascaded primary amplification unit and a secondary amplification unit based on the signal holding of a feedback capacitor includes: connecting the first output terminal of the primary amplification unit to the second input terminal of the secondary amplification unit through a control unit, disconnecting the connection between the second terminal of the feedback capacitor and the first output terminal of the primary amplification unit, and connecting the second terminal of the feedback capacitor to the second output terminal of the secondary amplification unit.

[0029] Compared with the prior art, the capacitive amplifier circuit and signal generation method of the present invention, by controlling the switching between the first-stage amplification unit, the feedback capacitor, and the second-stage amplification unit through the control unit, can pre-charge the feedback capacitor before the capacitive amplifier circuit enters the amplification state after the sampling circuit finishes sampling. This reduces the switching time of the capacitive amplifier circuit and thus shortens the settling time. At the same time, combined with the fact that the second-stage amplification unit has stored charge before sampling, the bandwidth requirement for establishing a high-precision signal can be reduced even under different settling time requirements, thereby greatly reducing power consumption, especially in high-speed applications, which can significantly reduce the power consumption of the chip. Attached Figure Description

[0030] Figure 1 This is a circuit diagram of a capacitor amplifier circuit according to an embodiment of the present invention.

[0031] Figure 2 This is a timing diagram of the control signals for a capacitor amplifier circuit according to an embodiment of the present invention.

[0032] Figure 3 This is a flowchart of a signal generation method according to an embodiment of the present invention. Detailed Implementation

[0033] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0034] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0035] The terms "coupled," "connected," or "linked" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in this invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0036] like Figure 1As shown, a capacitor amplifier circuit includes: a sampling circuit 10, a first-stage amplifier unit 20, a second-stage amplifier unit 30, a set of feedback capacitors CF, and a control unit.

[0037] In this embodiment, the first-stage amplification unit 20 and the second-stage amplification unit 30 are cascaded together. The first-stage amplification unit 20 includes a first operational amplifier G1, and the second-stage amplification unit 30 includes a second operational amplifier G2 and a set of Miller capacitors Cc. In this embodiment, the first operational amplifier G1 is used to improve signal gain, and the second operational amplifier G2 employs a class AB structure to improve the output of large-swing signals and reduce distortion. In other embodiments, the first operational amplifier G1 and the second operational amplifier G2 can employ operational amplifiers with other structures.

[0038] The first operational amplifier G1 has a set of first input terminals and a set of first output terminals, and the second operational amplifier G2 has a set of second input terminals and a set of second output terminals. The first output terminal of the first operational amplifier G1 is connected to the corresponding second input terminal of the second operational amplifier G2. In this embodiment, there are two sets.

[0039] The first and second ends of each Miller capacitor Cc are connected to a second input terminal and a second output terminal of the second operational amplifier G2, respectively, forming a second input node i (i.e., the second input terminal of the secondary amplification unit 30) and a second output node o (i.e., the second output terminal of the secondary amplification unit 30). A set of Miller capacitors Cc corresponds to two second input nodes i and two second output nodes o. The first ends of the two feedback capacitors CF are respectively connected to the two first input terminals of the first operational amplifier G1, and the second ends of the two feedback capacitors CF are respectively connected to the two first output terminals of the first operational amplifier G1. The second ends of the two feedback capacitors CF are also simultaneously connected to the two second output terminals of the second operational amplifier G2.

[0040] In this embodiment, the control unit controls the switching between the first output terminal of the first operational amplifier G1 and the second terminal of the corresponding feedback capacitor CF, as well as the switching between the output terminal of the first operational amplifier G1 and the corresponding second input node i, and also controls the switching between the second terminal of the corresponding feedback capacitor CF and the second output node o.

[0041] like Figure 1 As shown, the control unit includes a set of first switches S1, a set of second switches S2, and a set of third switches S3.

[0042] The first terminal of each first switch S1 is connected to the second terminal of the corresponding feedback capacitor CF, and the second terminal of each first switch S1 is connected to the first output terminal of the first operational amplifier G1.

[0043] The first terminal of each second switch S2 is connected to the first output terminal of the first operational amplifier G1 and the second terminal of the corresponding first switch S1, and the second terminal of the second switch S2 is connected to the corresponding second input node i.

[0044] The first terminal of each third switch S3 is connected to the second terminal of the corresponding feedback capacitor CF and the first terminal of the first switch S1, and the second terminal of each third switch S3 is connected to the corresponding second output node o.

[0045] In addition, the capacitor amplifier circuit also includes a set of seventh switches S7. The first terminal of each seventh switch S7 is connected to the second terminal of the corresponding feedback capacitor CF, the first terminal of the first switch S1, and the first terminal of the third switch S3. The second terminal of the seventh switch S7 is connected to the common-mode signal VCM.

[0046] In this embodiment, the sampling circuit 10 is used to sample the input signal and output the sampled signal to the first-stage amplification unit 20.

[0047] like Figure 1 As shown, the sampling circuit 10 includes a set of sampling capacitors CS, a set of fourth switches S4, a set of fifth switches S5 and a sixth switch S6.

[0048] The first terminal of the sampling capacitor CS is connected to the signal input terminal VIP via the corresponding fourth switch S4 to receive the input signal. The first terminal of another sampling capacitor CS is connected to the signal input terminal VIN via the corresponding fourth switch S4 to receive the input signal. The first terminals of this set of sampling capacitors CS are connected via the sixth switch S6. The second terminals of each set of sampling capacitors CS are connected to the common-mode signal VCM via a fifth switch S3. The second terminals of the two sampling capacitors CS are also connected to the two first input terminals of the first operational amplifier G1 and the first terminals of the two corresponding feedback capacitors CF, respectively.

[0049] like Figure 2 As shown, in this embodiment, a set of fourth switches S4, fifth switches S5 and seventh switches S7 are synchronously controlled by a first control signal φ1, a sixth switch S6 is controlled by a second control signal φ2, a set of first switches S1 is synchronously controlled by a third control signal φ21, and a set of second switches S2 and third switches S3 are synchronously controlled by a fourth control signal φ22.

[0050] like Figure 3As shown, based on the above-described capacitor amplifier circuit, this embodiment also discloses a signal generation method, including: an alternating first phase (phase 1) and a second phase (phase 2). In this embodiment, the first phase (phase 1) and the second phase (phase 2) form a cycle, and there is a non-overlapping time Td between the first phase (phase 1) and the second phase (phase 2). The non-overlapping time Td ensures the conservation of charge at the high-resistance node of the second end of the sampling capacitor CS. The second phase (phase 2) includes a pre-charging phase (phase 21) and an amplification phase (phase 22), wherein...

[0051] In the first phase (phase 1), the input signal is sampled by the sampling circuit 10 and a sampled signal is output.

[0052] Specifically, in the first phase (phase 1), the first control signal φ1 is a high-level signal, while the third control signal φ21, the fourth control signal φ22, and the second control signal φ2 are all low-level signals. The sixth switch S6, a set of first switches S1, a set of second switches S2, and a set of fifth switches S3 are all open. Correspondingly, a set of fourth switches S4, a set of fifth switches S5, and a set of seventh switches S7 are all closed. The first terminals of the two sampling capacitors CS are connected to the signal input terminals VIP and VIN, respectively, while the second terminals of the two sampling capacitors CS are connected to the common-mode signal VCM. At this time, the input signal is sampled through a set of sampling capacitors CS.

[0053] In the pre-charging phase 21, the feedback capacitor CF is pre-charged based on the sampled signal by the first-stage amplification unit 20.

[0054] In this embodiment, the control unit connects the second terminals of the two feedback capacitors CF to the two first output terminals of the first-stage amplifier unit 20, respectively. The control unit disconnects the connection between the two first output terminals of the first-stage amplifier unit 20 and the two corresponding second input terminals of the second-stage amplifier unit 30, respectively. The control unit also disconnects the connection between the second terminals of the two feedback capacitors CF and the two corresponding second output terminals of the second-stage amplifier unit 30, respectively.

[0055] Specifically, in the pre-charging phase 21, the first control signal φ1 and the fourth control signal φ22 are low-level signals, while the third control signal φ21 and the second control signal φ2 are high-level signals. Correspondingly, a set of fourth switches S4, a set of fifth switches S5, and a set of seventh switches S7 are all open; a set of second switches S2 and a set of fifth switches S3 are also open; the sixth switch S6 is closed; and a set of first switches S1 is closed. The first terminals of the two sampling capacitors CS are closed. At this time, the feedback capacitor CF is only connected to the first input and first output terminals of the first operational amplifier G1 and the sampling capacitors CS. The first operational amplifier G1 is configured for amplification. Based on the sampling signal output from the sampling capacitors CS, the first operational amplifier G1 rapidly pre-charges the feedback capacitor CF. Because the first operational amplifier G1 has a large bandwidth, the feedback capacitor CF can be charged to the expected value in a shorter time, thereby improving the subsequent setup speed of the capacitive amplifier circuit and shortening the setup time.

[0056] In the amplification phase 22, the sampled signal is amplified by the cascaded primary amplification unit 20 and secondary amplification unit 30 based on the signal holding of the feedback capacitor CF.

[0057] In this embodiment, the control unit connects the first output terminal of the first-stage amplification unit 20 to the second input terminal of the second-stage amplification unit 30, disconnects the connection between the second terminals of the two feedback capacitors CF and the two first output terminals of the first-stage amplification unit 20, and connects the second terminals of the two feedback capacitors CF to the two second output terminals of the second-stage amplification unit 30.

[0058] Specifically, during the amplification phase 22, the first control signal φ1 and the third control signal φ21 are low-level signals, while the fourth control signal φ22 and the second control signal φ2 are high-level signals. Correspondingly, a set of fourth switches S4, a set of fifth switches S5, and a set of seventh switches S7 are all open, a set of first switches S1 is open, and a set of sixth switches S6, a set of second switches S2, and a set of fifth switches S3 are closed. At this time, the second end of the feedback capacitor CF is connected to the second output node o of the secondary amplification unit 30, and the primary amplification unit 20 and the secondary amplification unit 30 are also connected, thereby amplifying the sampled signal based on the signal held by the feedback capacitor CF.

[0059] Furthermore, since the Miller capacitor Cc has been fully established before the first phase (phase 1), i.e. during the previous cycle (or initial cycle), the Miller capacitor Cc has already stored its charge. At the same time, during the pre-charging phase (phase 21) of the next cycle, the charge pre-charged to the feedback capacitor CF and the charge stored in the Miller capacitor Cc are close to their respective charges at the end of the previous cycle (or initial cycle). Therefore, during the amplification phase (phase 22) of the next cycle, the speed at which the feedback capacitor CF and the Miller capacitor Cc are recharged to the expected charge can be reduced, thereby shortening the setup time. This reduces the time it takes for the capacitor amplifier circuit to amplify the signal to the expected value and lowers the bandwidth requirements of the capacitor amplifier circuit.

[0060] Because the Miller capacitor Cc has already stored charge in the previous cycle (or the initial cycle), in the pre-charge phase 21 of the next cycle, the second operational amplifier G2 can maintain unity gain output based on the Miller capacitor Cc, and the charge on the Miller capacitor Cc is in a latched state. The charge held by the Miller capacitor Cc drives the subsequent load capacitor CL to the desired value relatively quickly through the second operational amplifier G2.

[0061] In the amplification phase 22, the first-stage amplification unit 20 and the second-stage amplification unit 30 are connected to form a complete capacitor amplifier mode, thereby relying on the loop bandwidth of the system to establish a signal with small error to sufficient accuracy.

[0062] In the amplification phase 22, the feedback capacitor CF and the Miller capacitor Cc are connected, and the first operational amplifier G1 and the second operational amplifier G2 are connected to reduce the differential jitter to the level of a few mV. The smaller the value of the step signal Vstep, the smaller the bandwidth requirement of the system. In this way, the system can reduce the bandwidth requirement of the two-stage operational amplifiers and achieve the purpose of reducing power consumption.

[0063] The present invention also discloses a chip including the above-described capacitor amplifier circuit.

[0064] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings; the invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments and various different choices and modifications of the invention without departing from the scope and spirit of the invention. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A capacitor amplifier circuit, characterized in that, include: A primary amplification unit and a secondary amplification unit, wherein the primary amplification unit has a set of first input terminals and a set of first output terminals, and the secondary amplification unit has a set of second input terminals and a set of second output terminals, and the first output terminal of the primary amplification unit is connected to the second input terminal of the secondary amplification unit; The sampling circuit is used to sample the input signal and output the sampled signal to the first input terminal of the first-stage amplifier unit; A set of feedback capacitors, wherein the first terminal of the feedback capacitor is connected to the first input terminal of the first-stage amplification unit, and the second terminal of the feedback capacitor is connected to the first output terminal of the first-stage amplification unit and the second output terminal of the second-stage amplification unit; and The control unit is used to control the connection and disconnection between the first output terminal of the first-stage amplifier unit and the second terminal of the feedback capacitor. The control unit also controls the connection and disconnection between the first output terminal of the first-stage amplifier unit and the second input terminal of the second-stage amplifier unit, as well as the connection and disconnection between the second terminal of the feedback capacitor and the second output terminal of the second-stage amplifier unit. The control unit includes a set of first switches, the first end of which is connected to the second end of the feedback capacitor, and the second end of which is connected to the first output terminal of the first stage amplification unit.

2. The capacitor amplifier circuit as described in claim 1, characterized in that, The control unit includes a set of second switches, the first end of which is connected to the first output terminal of the first-stage amplifier unit, and the second end of which is connected to the second input terminal of the second-stage amplifier unit.

3. The capacitor amplifier circuit as described in claim 1, characterized in that, The control unit includes a set of third switches, the first end of which is connected to the second end of the feedback capacitor, and the second end of which is connected to the second output end of the secondary amplifier unit.

4. The capacitor amplifier circuit as described in claim 1, characterized in that, The first-stage amplification unit includes a first operational amplifier, and / or the second-stage amplification unit includes a second operational amplifier and a set of Miller capacitors, wherein the first end of the Miller capacitor is connected to the input end of the second operational amplifier to form the first input end of the second-stage amplification unit, and the second end of the Miller capacitor is connected to the output end of the second operational amplifier to form the second output end of the second-stage amplification unit.

5. The capacitor amplifier circuit as described in claim 1, characterized in that, The sampling circuit includes a set of sampling capacitors, a set of fourth switches, a set of fifth switches, and a sixth switch. The first end of the sampling capacitor is connected to the signal input terminal through the fourth switch to receive the input signal, and the first end of the set of sampling capacitors is connected through the sixth switch. The second end of the sampling capacitor is connected to the common-mode signal through the fifth switch. The second end of the sampling capacitor is connected to the first input terminal of the first-stage amplification unit and the first end of the feedback capacitor.

6. The capacitor amplifier circuit as described in claim 1, characterized in that, The capacitor amplifier circuit also includes a seventh switch, the first end of which is connected to the second end of the feedback capacitor, and the second end of which is connected to the common-mode signal.

7. A signal generation method, characterized in that, The signal generation method is based on the capacitor amplifier circuit as described in any one of claims 1 to 6, and the signal generation method includes: an alternating first stage and a second stage, wherein the second stage includes a pre-charging stage and an amplification stage, wherein... In the first stage, the input signal is sampled by the sampling circuit and the sampled signal is output. During the pre-charging stage, the feedback capacitor is pre-charged based on the sampled signal through a first-stage amplification unit; During the amplification stage, the sampled signal is amplified by cascaded primary and secondary amplification units based on the signal holding of the feedback capacitor; The pre-charging of the feedback capacitor based on the sampled signal by the first-stage amplification unit includes: connecting the second terminal of the feedback capacitor to the first output terminal of the first-stage amplification unit through the control unit, disconnecting the connection between the first output terminal of the first-stage amplification unit and the second input terminal of the second-stage amplification unit, and disconnecting the connection between the second terminal of the feedback capacitor and the second output terminal of the second-stage amplification unit.

8. The signal generation method as described in claim 7, characterized in that, The amplification of the sampled signal by means of a cascaded primary amplification unit and a secondary amplification unit based on the signal holding of a feedback capacitor includes: connecting the first output terminal of the primary amplification unit to the second input terminal of the secondary amplification unit through a control unit, disconnecting the connection between the second terminal of the feedback capacitor and the first output terminal of the primary amplification unit, and connecting the second terminal of the feedback capacitor to the second output terminal of the secondary amplification unit.

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